drm/amd/display: Add support for extended DSC DPCD caps

[why]
A few of the new DSC DPCD caps were introduced by a DP 1.4a SCR in order
to give DSC branch decoders a chance to expose their maximum throughput
and maximum line width limitations.
Signed-off-by: Nikola Cornij <nikola.cornij@amd.com>
Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c

@@ -2383,8 +2383,8 @@ static bool retrieve_link_cap(struct dc_link *link)
 	int i;
 	struct dp_sink_hw_fw_revision dp_hw_fw_revision;
 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
-	uint8_t dsc_data[16];
-	struct dsc_dec_dpcd_caps *dsc_caps;
+	uint8_t dsc_data[16]; /* DP_DSC_BITS_PER_PIXEL_INC - DP_DSC_SUPPORT + 1 == 16 */
+	struct dsc_dec_dpcd_caps *dsc_dec_caps;
 #endif
 
 	memset(dpcd_data, '\0', sizeof(dpcd_data));
@@ -2558,8 +2558,8 @@ static bool retrieve_link_cap(struct dc_link *link)
 		sizeof(dp_hw_fw_revision.ieee_fw_rev));
 
 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
-	dsc_caps = &link->dpcd_caps.dsc_sink_caps;
-	memset(dsc_caps, '\0', sizeof(*dsc_caps));
+	dsc_dec_caps = &link->dpcd_caps.dsc_sink_caps;
+	memset(dsc_dec_caps, '\0', sizeof(*dsc_dec_caps));
 	memset(&link->dpcd_caps.dsc_sink_caps, '\0',
 			sizeof(link->dpcd_caps.dsc_sink_caps));
 	memset(&link->dpcd_caps.fec_cap, '\0', sizeof(link->dpcd_caps.fec_cap));
@@ -2571,7 +2571,7 @@ static bool retrieve_link_cap(struct dc_link *link)
 				dsc_data,
 				sizeof(dsc_data));
 		if (status == DC_OK) {
-			DC_LOG_DSC("DSC capability read at link %d:",
+			DC_LOG_DSC("DSC DPCD capability read at link %d:",
 					link->link_index);
 			DC_LOG_DSC("\t%02x %02x %02x %02x",
 					dsc_data[0], dsc_data[1],
@@ -2590,37 +2590,43 @@ static bool retrieve_link_cap(struct dc_link *link)
 			return false;
 		}
 
-		if (dc_dsc_parse_dsc_dpcd(dsc_data,
-				dsc_caps)) {
-			DC_LOG_DSC("DSC capability parsed at link %d:",
+		if (dc_dsc_parse_dsc_dpcd(dsc_data, NULL,
+				dsc_dec_caps)) {
+			DC_LOG_DSC("DSC DPCD capabilities parsed at link %d:",
 					link->link_index);
 			DC_LOG_DSC("\tis_dsc_supported:\t%d",
-					dsc_caps->is_dsc_supported);
-			DC_LOG_DSC("\tdsc_version:\t%d", dsc_caps->dsc_version);
+					dsc_dec_caps->is_dsc_supported);
+			DC_LOG_DSC("\tdsc_version:\t%d", dsc_dec_caps->dsc_version);
 			DC_LOG_DSC("\trc_buffer_size:\t%d",
-					dsc_caps->rc_buffer_size);
+					dsc_dec_caps->rc_buffer_size);
 			DC_LOG_DSC("\tslice_caps1:\t0x%x20",
-					dsc_caps->slice_caps1.raw);
+					dsc_dec_caps->slice_caps1.raw);
 			DC_LOG_DSC("\tslice_caps2:\t0x%x20",
-					dsc_caps->slice_caps2.raw);
+					dsc_dec_caps->slice_caps2.raw);
 			DC_LOG_DSC("\tlb_bit_depth:\t%d",
-					dsc_caps->lb_bit_depth);
+					dsc_dec_caps->lb_bit_depth);
 			DC_LOG_DSC("\tis_block_pred_supported:\t%d",
-					dsc_caps->is_block_pred_supported);
+					dsc_dec_caps->is_block_pred_supported);
 			DC_LOG_DSC("\tedp_max_bits_per_pixel:\t%d",
-					dsc_caps->edp_max_bits_per_pixel);
+					dsc_dec_caps->edp_max_bits_per_pixel);
 			DC_LOG_DSC("\tcolor_formats:\t%d",
-					dsc_caps->color_formats.raw);
+					dsc_dec_caps->color_formats.raw);
 			DC_LOG_DSC("\tcolor_depth:\t%d",
-					dsc_caps->color_depth.raw);
+					dsc_dec_caps->color_depth.raw);
 			DC_LOG_DSC("\tthroughput_mode_0_mps:\t%d",
-					dsc_caps->throughput_mode_0_mps);
+					dsc_dec_caps->throughput_mode_0_mps);
 			DC_LOG_DSC("\tthroughput_mode_1_mps:\t%d",
-					dsc_caps->throughput_mode_1_mps);
+					dsc_dec_caps->throughput_mode_1_mps);
 			DC_LOG_DSC("\tmax_slice_width:\t%d",
-					dsc_caps->max_slice_width);
+					dsc_dec_caps->max_slice_width);
 			DC_LOG_DSC("\tbpp_increment_div:\t%d",
-					dsc_caps->bpp_increment_div);
+					dsc_dec_caps->bpp_increment_div);
+			DC_LOG_DSC("\tbranch_overall_throughput_0_mps:\t%d",
+					dsc_dec_caps->branch_overall_throughput_0_mps);
+			DC_LOG_DSC("\tbranch_overall_throughput_1_mps:\t%d",
+					dsc_dec_caps->branch_overall_throughput_1_mps);
+			DC_LOG_DSC("\tbranch_max_line_width:\t%d",
+					dsc_dec_caps->branch_max_line_width);
 		} else {
 			/* Some sinks return bogus DSC DPCD data
 			 * when they don't support DSC.

drivers/gpu/drm/amd/display/dc/dc_dsc.h

@@ -34,7 +34,8 @@ struct dc_dsc_bw_range {
 };
 
 
-bool dc_dsc_parse_dsc_dpcd(const uint8_t *dpcd_dsc_data,
+bool dc_dsc_parse_dsc_dpcd(const uint8_t *dpcd_dsc_basic_data,
+		const uint8_t *dpcd_dsc_ext_data,
 		struct dsc_dec_dpcd_caps *dsc_sink_caps);
 
 bool dc_dsc_compute_bandwidth_range(

drivers/gpu/drm/amd/display/dc/dc_types.h

@@ -773,6 +773,11 @@ struct dsc_dec_dpcd_caps {
 	int32_t throughput_mode_1_mps; /* In MPs */
 	int32_t max_slice_width;
 	uint32_t bpp_increment_div; /* bpp increment divisor, e.g. if 16, it's 1/16th of a bit */
+
+	/* Extended DSC caps */
+	uint32_t branch_overall_throughput_0_mps; /* In MPs */
+	uint32_t branch_overall_throughput_1_mps; /* In MPs */
+	uint32_t branch_max_line_width;
 };
 #endif
 #endif /* DC_TYPES_H_ */

drivers/gpu/drm/amd/display/include/dpcd_structs.h

+/*
+ * dpcd_structs.h
+ *
+ *  Created on: Oct 31, 2018
+ *      Author: jlei
+ */
+
+#ifndef DAL_INCLUDE_DPCD_STRUCTS_H_
+#define DAL_INCLUDE_DPCD_STRUCTS_H_
+
+struct dpcd_receive_port0_cap01 {
+	union {
+		struct {
+			// Byte 0
+			unsigned char reserved0				:1; // Bit0
+			unsigned char local_edid_present		:1;
+			unsigned char associated_to_preceding_port	:1;
+			unsigned char hblank_expansion_capable		:1;
+			unsigned char buffer_size_unit			:1; // Bit4
+			unsigned char buffer_size_per_port		:1;
+			unsigned char reserved1				:2;
+
+			// Byte 1
+			unsigned char buffer_size			:8;
+		} fields;
+		unsigned char raw[2];
+	};
+};
+
+#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+
+struct dpcd_dsc_basic_capabilities {
+	union {
+		struct {
+			// Byte 0
+			struct {
+
+				unsigned char dsc_support				:1; // Bit0
+				unsigned char reserved					:7;
+			} dsc_support;
+
+			// Byte 1
+			struct {
+				unsigned char dsc_version_major	:4;
+				unsigned char dsc_version_minor	:4;
+			} dsc_algorithm_revision;
+
+			// Byte 2
+			struct {
+				unsigned char rc_block_buffer_size	:2;
+				unsigned char reserved	:6;
+			} dsc_rc_buffer_block_size;
+
+			// Byte 3
+			unsigned char dsc_rc_buffer_size;
+
+			// Byte 4
+			struct {
+				unsigned char one_slice_per_dp_dsc_sink_device		:1; // Bit0
+				unsigned char two_slices_per_dp_dsc_sink_device		:1;
+				unsigned char reserved					:1;
+				unsigned char four_slices_per_dp_dsc_sink_device	:1;
+				unsigned char six_slices_per_dp_dsc_sink_device		:1; // Bit 4
+				unsigned char eight_slices_per_dp_dsc_sink_device	:1;
+				unsigned char ten_slices_per_dp_dsc_sink_device		:1;
+				unsigned char twelve_slices_per_dp_dsc_sink_device	:1;
+			} dsc_slice_capabilities_1;
+
+			// Byte 5
+			struct {
+				unsigned char line_buffer_bit_depth	:4;
+				unsigned char reserved			:4;
+			} dsc_line_buffer_bit_depth;
+
+			// Byte 6
+			struct {
+				unsigned char block_prediction_support	:1;
+				unsigned char reserved			:7;
+			} dsc_block_prediction_support;
+
+			// Byte 7,8
+			struct {
+				unsigned char maximum_bits_per_pixel_supported_by_the_decompressor_low	:7;
+				unsigned char maximum_bits_per_pixel_supported_by_the_decompressor_high	:7;
+			} maximum_bits_per_pixel_supported_by_the_decompressor;
+
+			// Byte 9
+			struct {
+				unsigned char rgb_support			:1; // Bit0
+				unsigned char y_cb_cr_444_support		:1;
+				unsigned char y_cb_cr_simple_422_support	:1;
+				unsigned char y_cb_cr_native_422_support	:1;
+				unsigned char y_cb_cr_native_420_support	:1; // Bit 4
+				unsigned char reserved				:3;
+			} dsc_decoder_color_format_capabilities;
+
+			// Byte 10
+			struct {
+				unsigned char reserved0				:1; // Bit0
+				unsigned char eight_bits_per_color_support	:1;
+				unsigned char ten_bits_per_color_support	:1;
+				unsigned char twelve_bits_per_color_support	:1;
+				unsigned char reserved1				:4; // Bit 4
+			} dsc_decoder_color_depth_capabilities;
+
+			// Byte 11
+			struct {
+				unsigned char throughput_mode_0			:4;
+				unsigned char throughput_mode_1			:4;
+			} peak_dsc_throughput_dsc_sink;
+
+			// Byte 12
+			unsigned char dsc_maximum_slice_width;
+
+			// Byte 13
+			struct {
+				unsigned char sixteen_slices_per_dsc_sink_device	:1;
+				unsigned char twenty_slices_per_dsc_sink_device		:1;
+				unsigned char twentyfour_slices_per_dsc_sink_device	:1;
+				unsigned char reserved					:5;
+			} dsc_slice_capabilities_2;
+
+			// Byte 14
+			unsigned char reserved;
+
+			// Byte 15
+			struct {
+				unsigned char increment_of_bits_per_pixel_supported	:3;
+				unsigned char reserved					:5;
+			} bits_per_pixel_increment;
+		} fields;
+		unsigned char raw[16];
+	};
+};
+
+struct dpcd_dsc_ext_capabilities {
+	union {
+		struct {
+			unsigned char branch_overall_throughput_0; // Byte 0
+			unsigned char branch_overall_throughput_1; // Byte 1
+			unsigned char branch_max_line_width; // Byte 2
+		} fields;
+		unsigned char raw[3];
+	};
+};
+
+struct dpcd_dsc_capabilities {
+	struct dpcd_dsc_basic_capabilities dsc_basic_caps;
+	struct dpcd_dsc_ext_capabilities dsc_ext_caps;
+};
+
+struct dpcd_fec_capability {
+	union {
+		struct {
+			// Byte 0
+			unsigned char fec_capable				:1; // Bit0
+			unsigned char uncorrected_block_error_count_capable	:1;
+			unsigned char corrected_block_error_count_capable	:1;
+			unsigned char bit_error_count_capable			:1;
+			unsigned char reserved					:4; // Bit4
+		} fields;
+		unsigned char raw[1];
+	};
+};
+
+#endif
+
+#endif /* DAL_INCLUDE_DPCD_STRUCTS_H_ */

include/drm/drm_dp_helper.h

@@ -356,6 +356,11 @@
 # define DP_FEC_CORR_BLK_ERROR_COUNT_CAP    (1 << 2)
 # define DP_FEC_BIT_ERROR_COUNT_CAP	    (1 << 3)
 
+/* DP Extended DSC Capabilities */
+#define DP_DSC_BRANCH_OVERALL_THROUGHPUT_0  0x0a0   /* DP 1.4a SCR */
+#define DP_DSC_BRANCH_OVERALL_THROUGHPUT_1  0x0a1
+#define DP_DSC_BRANCH_MAX_LINE_WIDTH        0x0a2
+
 /* link configuration */
 #define	DP_LINK_BW_SET		            0x100
 # define DP_LINK_RATE_TABLE		    0x00    /* eDP 1.4 */