Commit f52cf14b authored by Anton Blanchard's avatar Anton Blanchard Committed by Linus Torvalds

[PATCH] ppc64: Remove flush_instruction_cache

Remove flush_instruction_cache, we cant touch HID bits on LPAR machines.
Signed-off-by: default avatarAnton Blanchard <anton@samba.org>
Signed-off-by: default avatarAndrew Morton <akpm@osdl.org>
Signed-off-by: default avatarLinus Torvalds <torvalds@osdl.org>
parent 0ca63a2a
......@@ -168,26 +168,6 @@ _GLOBAL(call_with_mmu_off)
mtspr SPRN_SRR1,r0
rfid
/*
* Flush instruction cache.
*/
_GLOBAL(flush_instruction_cache)
/*
* This is called by kgdb code
* and should probably go away
* to be replaced by invalidating
* the cache lines that are actually
* modified
*/
/* use invalidate-all bit in HID0
* - is this consistent across all 64-bit cpus? -- paulus */
mfspr r3,HID0
ori r3,r3,HID0_ICFI
mtspr HID0,r3
sync
isync
blr
.section ".toc","aw"
PPC64_CACHES:
......
......@@ -114,7 +114,6 @@ EXPORT_SYMBOL(iounmap);
EXPORT_SYMBOL(start_thread);
EXPORT_SYMBOL(kernel_thread);
EXPORT_SYMBOL(flush_instruction_cache);
EXPORT_SYMBOL(giveup_fpu);
#ifdef CONFIG_ALTIVEC
EXPORT_SYMBOL(giveup_altivec);
......
......@@ -108,7 +108,6 @@ extern void show_regs(struct pt_regs * regs);
extern void low_hash_fault(struct pt_regs *regs, unsigned long address);
extern int die(const char *str, struct pt_regs *regs, long err);
extern void flush_instruction_cache(void);
extern int _get_PVR(void);
extern void giveup_fpu(struct task_struct *);
extern void disable_kernel_fp(void);
......
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