Commit f5f06e21 authored by Tao Zhou's avatar Tao Zhou Committed by Alex Deucher

drm/amdgpu: update parameter of ras_ih_cb

change struct ras_err_data *err_data to void *err_data, align with
umc code and the callback's declaration in each ras block could
pay no attention to the structure type
Signed-off-by: default avatarTao Zhou <tao.zhou1@amd.com>
Reviewed-by: default avatarGuchun Chen <guchun.chen@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent e7da754b
...@@ -362,7 +362,7 @@ struct ras_err_handler_data { ...@@ -362,7 +362,7 @@ struct ras_err_handler_data {
}; };
typedef int (*ras_ih_cb)(struct amdgpu_device *adev, typedef int (*ras_ih_cb)(struct amdgpu_device *adev,
struct ras_err_data *err_data, void *err_data,
struct amdgpu_iv_entry *entry); struct amdgpu_iv_entry *entry);
struct ras_ih_data { struct ras_ih_data {
......
...@@ -4204,7 +4204,7 @@ static int gfx_v9_0_early_init(void *handle) ...@@ -4204,7 +4204,7 @@ static int gfx_v9_0_early_init(void *handle)
} }
static int gfx_v9_0_process_ras_data_cb(struct amdgpu_device *adev, static int gfx_v9_0_process_ras_data_cb(struct amdgpu_device *adev,
struct ras_err_data *err_data, void *err_data,
struct amdgpu_iv_entry *entry); struct amdgpu_iv_entry *entry);
static int gfx_v9_0_ecc_late_init(void *handle) static int gfx_v9_0_ecc_late_init(void *handle)
...@@ -5457,7 +5457,7 @@ static int gfx_v9_0_priv_inst_irq(struct amdgpu_device *adev, ...@@ -5457,7 +5457,7 @@ static int gfx_v9_0_priv_inst_irq(struct amdgpu_device *adev,
} }
static int gfx_v9_0_process_ras_data_cb(struct amdgpu_device *adev, static int gfx_v9_0_process_ras_data_cb(struct amdgpu_device *adev,
struct ras_err_data *err_data, void *err_data,
struct amdgpu_iv_entry *entry) struct amdgpu_iv_entry *entry)
{ {
/* TODO ue will trigger an interrupt. */ /* TODO ue will trigger an interrupt. */
......
...@@ -246,16 +246,18 @@ static int gmc_v9_0_ecc_interrupt_state(struct amdgpu_device *adev, ...@@ -246,16 +246,18 @@ static int gmc_v9_0_ecc_interrupt_state(struct amdgpu_device *adev,
} }
static int gmc_v9_0_process_ras_data_cb(struct amdgpu_device *adev, static int gmc_v9_0_process_ras_data_cb(struct amdgpu_device *adev,
struct ras_err_data *err_data, void *ras_error_status,
struct amdgpu_iv_entry *entry) struct amdgpu_iv_entry *entry)
{ {
struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status;
if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX)) if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX))
return AMDGPU_RAS_SUCCESS; return AMDGPU_RAS_SUCCESS;
kgd2kfd_set_sram_ecc_flag(adev->kfd.dev); kgd2kfd_set_sram_ecc_flag(adev->kfd.dev);
if (adev->umc.funcs && if (adev->umc.funcs &&
adev->umc.funcs->query_ras_error_count) adev->umc.funcs->query_ras_error_count)
adev->umc.funcs->query_ras_error_count(adev, err_data); adev->umc.funcs->query_ras_error_count(adev, ras_error_status);
if (adev->umc.funcs && if (adev->umc.funcs &&
adev->umc.funcs->query_ras_error_address && adev->umc.funcs->query_ras_error_address &&
......
...@@ -1690,7 +1690,7 @@ static int sdma_v4_0_early_init(void *handle) ...@@ -1690,7 +1690,7 @@ static int sdma_v4_0_early_init(void *handle)
} }
static int sdma_v4_0_process_ras_data_cb(struct amdgpu_device *adev, static int sdma_v4_0_process_ras_data_cb(struct amdgpu_device *adev,
struct ras_err_data *err_data, void *err_data,
struct amdgpu_iv_entry *entry); struct amdgpu_iv_entry *entry);
static int sdma_v4_0_late_init(void *handle) static int sdma_v4_0_late_init(void *handle)
...@@ -1939,7 +1939,7 @@ static int sdma_v4_0_process_trap_irq(struct amdgpu_device *adev, ...@@ -1939,7 +1939,7 @@ static int sdma_v4_0_process_trap_irq(struct amdgpu_device *adev,
} }
static int sdma_v4_0_process_ras_data_cb(struct amdgpu_device *adev, static int sdma_v4_0_process_ras_data_cb(struct amdgpu_device *adev,
struct ras_err_data *err_data, void *err_data,
struct amdgpu_iv_entry *entry) struct amdgpu_iv_entry *entry)
{ {
uint32_t err_source; uint32_t err_source;
......
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