Commit f63837f0 authored by Benjamin Herrenschmidt's avatar Benjamin Herrenschmidt Committed by Paul Mackerras

powerpc/mm: Remove flush_HPTE()

The function flush_HPTE() is used in only one place, the implementation
of DEBUG_PAGEALLOC on ppc32.

It's actually a dup of flush_tlb_page() though it's -slightly- more
efficient on hash based processors.  We remove it and replace it by
a direct call to the hash flush code on those processors and to
flush_tlb_page() for everybody else.
Signed-off-by: default avatarBenjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: default avatarPaul Mackerras <paulus@samba.org>
parent e41e811a
...@@ -58,17 +58,14 @@ extern phys_addr_t lowmem_end_addr; ...@@ -58,17 +58,14 @@ extern phys_addr_t lowmem_end_addr;
* architectures. -- Dan * architectures. -- Dan
*/ */
#if defined(CONFIG_8xx) #if defined(CONFIG_8xx)
#define flush_HPTE(X, va, pg) _tlbie(va, 0 /* 8xx doesn't care about PID */)
#define MMU_init_hw() do { } while(0) #define MMU_init_hw() do { } while(0)
#define mmu_mapin_ram() (0UL) #define mmu_mapin_ram() (0UL)
#elif defined(CONFIG_4xx) #elif defined(CONFIG_4xx)
#define flush_HPTE(pid, va, pg) _tlbie(va, pid)
extern void MMU_init_hw(void); extern void MMU_init_hw(void);
extern unsigned long mmu_mapin_ram(void); extern unsigned long mmu_mapin_ram(void);
#elif defined(CONFIG_FSL_BOOKE) #elif defined(CONFIG_FSL_BOOKE)
#define flush_HPTE(pid, va, pg) _tlbie(va, pid)
extern void MMU_init_hw(void); extern void MMU_init_hw(void);
extern unsigned long mmu_mapin_ram(void); extern unsigned long mmu_mapin_ram(void);
extern void adjust_total_lowmem(void); extern void adjust_total_lowmem(void);
...@@ -77,18 +74,4 @@ extern void adjust_total_lowmem(void); ...@@ -77,18 +74,4 @@ extern void adjust_total_lowmem(void);
/* anything 32-bit except 4xx or 8xx */ /* anything 32-bit except 4xx or 8xx */
extern void MMU_init_hw(void); extern void MMU_init_hw(void);
extern unsigned long mmu_mapin_ram(void); extern unsigned long mmu_mapin_ram(void);
/* Be careful....this needs to be updated if we ever encounter 603 SMPs,
* which includes all new 82xx processors. We need tlbie/tlbsync here
* in that case (I think). -- Dan.
*/
static inline void flush_HPTE(unsigned context, unsigned long va,
unsigned long pdval)
{
if ((Hash != 0) &&
cpu_has_feature(CPU_FTR_HPTE_TABLE))
flush_hash_pages(0, va, pdval, 1);
else
_tlbie(va);
}
#endif #endif
...@@ -342,7 +342,11 @@ static int __change_page_attr(struct page *page, pgprot_t prot) ...@@ -342,7 +342,11 @@ static int __change_page_attr(struct page *page, pgprot_t prot)
return -EINVAL; return -EINVAL;
set_pte_at(&init_mm, address, kpte, mk_pte(page, prot)); set_pte_at(&init_mm, address, kpte, mk_pte(page, prot));
wmb(); wmb();
flush_HPTE(0, address, pmd_val(*kpmd)); #ifdef CONFIG_PPC_STD_MMU
flush_hash_pages(0, address, pmd_val(*kpmd), 1);
#else
flush_tlb_page(NULL, address);
#endif
pte_unmap(kpte); pte_unmap(kpte);
return 0; return 0;
......
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