Commit f7de96ee authored by Harry Wentland's avatar Harry Wentland Committed by Alex Deucher

drm/amd/display: Add DCN2 DPP

Add support to program the DCN2 DPP (Multiple pipe and plane combine)

HW Blocks:

    +--------+
    |  DPP   |
    +--------+
        |
        v
    +--------+
    |  MPC   |
    +--------+
        |
        v
    +-------+
    |  OPP  |
    +-------+
        |
        v
    +--------+
    |  OPTC  |
    +--------+
        |
        v
    +--------+       +--------+
    |  DIO   |       |  DCCG  |
    +--------+       +--------+
Signed-off-by: default avatarHarry Wentland <harry.wentland@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent f789b0b8
......@@ -290,7 +290,12 @@ void dpp1_cnv_setup (
enum surface_pixel_format format,
enum expansion_mode mode,
struct dc_csc_transform input_csc_color_matrix,
#ifdef CONFIG_DRM_AMD_DC_DCN2_0
enum dc_color_space input_color_space,
struct cnv_alpha_2bit_lut *alpha_2bit_lut)
#else
enum dc_color_space input_color_space)
#endif
{
uint32_t pixel_format;
uint32_t alpha_en;
......@@ -523,6 +528,11 @@ static const struct dpp_funcs dcn10_dpp_funcs = {
.set_optional_cursor_attributes = dpp1_cnv_set_optional_cursor_attributes,
.dpp_dppclk_control = dpp1_dppclk_control,
.dpp_set_hdr_multiplier = dpp1_set_hdr_multiplier,
#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
.dpp_program_blnd_lut = NULL,
.dpp_program_shaper_lut = NULL,
.dpp_program_3dlut = NULL
#endif
};
static struct dpp_caps dcn10_dpp_cap = {
......
......@@ -1486,7 +1486,12 @@ void dpp1_cnv_setup (
enum surface_pixel_format format,
enum expansion_mode mode,
struct dc_csc_transform input_csc_color_matrix,
#ifdef CONFIG_DRM_AMD_DC_DCN2_0
enum dc_color_space input_color_space,
struct cnv_alpha_2bit_lut *alpha_2bit_lut);
#else
enum dc_color_space input_color_space);
#endif
void dpp1_full_bypass(struct dpp *dpp_base);
......
......@@ -731,6 +731,10 @@ void dpp1_full_bypass(struct dpp *dpp_base)
/* COLOR_KEYER_CONTROL.COLOR_KEYER_EN = 0 this should be default */
if (dpp->tf_mask->CM_BYPASS_EN)
REG_SET(CM_CONTROL, 0, CM_BYPASS_EN, 1);
#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
else
REG_SET(CM_CONTROL, 0, CM_BYPASS, 1);
#endif
/* Setting degamma bypass for now */
REG_SET(CM_DGAM_CONTROL, 0, CM_DGAM_LUT_MODE, 0);
......
......@@ -218,6 +218,14 @@ static void dpp1_dscl_set_lb(
INTERLEAVE_EN, lb_params->interleave_en, /* Interleave source enable */
LB_DATA_FORMAT__ALPHA_EN, lb_params->alpha_en); /* Alpha enable */
}
#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
else {
/* DSCL caps: pixel data processed in float format */
REG_SET_2(LB_DATA_FORMAT, 0,
INTERLEAVE_EN, lb_params->interleave_en, /* Interleave source enable */
LB_DATA_FORMAT__ALPHA_EN, lb_params->alpha_en); /* Alpha enable */
}
#endif
REG_SET_2(LB_MEMORY_CTRL, 0,
MEMORY_CONFIG, mem_size_config,
......
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......@@ -36,7 +36,13 @@ struct dpp {
struct dpp_caps *caps;
struct pwl_params regamma_params;
struct pwl_params degamma_params;
#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
struct dpp_cursor_attributes cur_attr;
#endif
#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
struct pwl_params shaper_params;
#endif
};
struct dpp_input_csc_matrix {
......@@ -49,6 +55,34 @@ struct dpp_grph_csc_adjustment {
enum graphics_gamut_adjust_type gamut_adjust_type;
};
#ifdef CONFIG_DRM_AMD_DC_DCN2_0
struct cnv_color_keyer_params {
int color_keyer_en;
int color_keyer_mode;
int color_keyer_alpha_low;
int color_keyer_alpha_high;
int color_keyer_red_low;
int color_keyer_red_high;
int color_keyer_green_low;
int color_keyer_green_high;
int color_keyer_blue_low;
int color_keyer_blue_high;
};
/* new for dcn2: set the 8bit alpha values based on the 2 bit alpha
*ALPHA_2BIT_LUT. ALPHA_2BIT_LUT0 default: 0b00000000
*ALPHA_2BIT_LUT. ALPHA_2BIT_LUT1 default: 0b01010101
*ALPHA_2BIT_LUT. ALPHA_2BIT_LUT2 default: 0b10101010
*ALPHA_2BIT_LUT. ALPHA_2BIT_LUT3 default: 0b11111111
*/
struct cnv_alpha_2bit_lut {
int lut0;
int lut1;
int lut2;
int lut3;
};
#endif
struct dcn_dpp_state {
uint32_t is_enabled;
uint32_t igam_lut_mode;
......@@ -155,7 +189,12 @@ struct dpp_funcs {
enum surface_pixel_format format,
enum expansion_mode mode,
struct dc_csc_transform input_csc_color_matrix,
#ifdef CONFIG_DRM_AMD_DC_DCN2_0
enum dc_color_space input_color_space,
struct cnv_alpha_2bit_lut *alpha_2bit_lut);
#else
enum dc_color_space input_color_space);
#endif
void (*dpp_full_bypass)(struct dpp *dpp_base);
......@@ -184,6 +223,20 @@ struct dpp_funcs {
bool dppclk_div,
bool enable);
#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
bool (*dpp_program_blnd_lut)(
struct dpp *dpp,
const struct pwl_params *params);
bool (*dpp_program_shaper_lut)(
struct dpp *dpp,
const struct pwl_params *params);
bool (*dpp_program_3dlut)(
struct dpp *dpp,
struct tetrahedral_params *params);
void (*dpp_cnv_set_alpha_keyer)(
struct dpp *dpp_base,
struct cnv_color_keyer_params *color_keyer);
#endif
};
......
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