Commit f9201325 authored by Jitao Shi's avatar Jitao Shi Committed by CK Hu

dt-bindings: display: mediatek: update dsi supported chips

Update device tree binding documentation for the dsi for
Mediatek MT8183 SoCs.
Signed-off-by: default avatarJitao Shi <jitao.shi@mediatek.com>
Acked-by: default avatarRob Herring <robh@kernel.org>
Signed-off-by: default avatarCK Hu <ck.hu@mediatek.com>
parent 54ecb8f7
...@@ -7,7 +7,7 @@ channel output. ...@@ -7,7 +7,7 @@ channel output.
Required properties: Required properties:
- compatible: "mediatek,<chip>-dsi" - compatible: "mediatek,<chip>-dsi"
the supported chips are mt2701 and mt8173. the supported chips are mt2701, mt8173 and mt8183.
- reg: Physical base address and length of the controller's registers - reg: Physical base address and length of the controller's registers
- interrupts: The interrupt signal from the function block. - interrupts: The interrupt signal from the function block.
- clocks: device clocks - clocks: device clocks
...@@ -26,7 +26,7 @@ The MIPI TX configuration module controls the MIPI D-PHY. ...@@ -26,7 +26,7 @@ The MIPI TX configuration module controls the MIPI D-PHY.
Required properties: Required properties:
- compatible: "mediatek,<chip>-mipi-tx" - compatible: "mediatek,<chip>-mipi-tx"
the supported chips are mt2701 and mt8173. the supported chips are mt2701, mt8173 and mt8183.
- reg: Physical base address and length of the controller's registers - reg: Physical base address and length of the controller's registers
- clocks: PLL reference clock - clocks: PLL reference clock
- clock-output-names: name of the output clock line to the DSI encoder - clock-output-names: name of the output clock line to the DSI encoder
......
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