Commit f9e75922 authored by Andrew Lunn's avatar Andrew Lunn Committed by Jason Cooper

ARM: Kirkwood: Make use of mvebu pincltl and gpio drivers

Select the generic mvebu kirkwood pincltr driver and generic mvebu
gpio driver. This requires minor changes to the DT, and the calls to
configure plat-orion gpio driver are removed.
Signed-off-by: default avatarAndrew Lunn <andrew@lunn.ch>
Tested-by: default avatarMichael Walle <michael@walle.cc>
Tested-by: default avatarSimon Baatz <gmbnomis@gmail.com>
Tested-by: default avatarJamie Lentin <jm@lentin.co.uk>
Tested-by: default avatarJoshua Coombs <josh.coombs@gmail.com>
Signed-off-by: default avatarJason Cooper <jason@lakedaemon.net>
parent 49e928d6
...@@ -549,6 +549,8 @@ config ARCH_KIRKWOOD ...@@ -549,6 +549,8 @@ config ARCH_KIRKWOOD
select CPU_FEROCEON select CPU_FEROCEON
select GENERIC_CLOCKEVENTS select GENERIC_CLOCKEVENTS
select PCI select PCI
select PINCTRL
select PINCTRL_KIRKWOOD
select PLAT_ORION_LEGACY select PLAT_ORION_LEGACY
help help
Support for the following Marvell Kirkwood series SoCs: Support for the following Marvell Kirkwood series SoCs:
......
...@@ -4,6 +4,10 @@ / { ...@@ -4,6 +4,10 @@ / {
compatible = "marvell,kirkwood"; compatible = "marvell,kirkwood";
interrupt-parent = <&intc>; interrupt-parent = <&intc>;
aliases {
gpio0 = &gpio0;
gpio1 = &gpio1;
};
intc: interrupt-controller { intc: interrupt-controller {
compatible = "marvell,orion-intc", "marvell,intc"; compatible = "marvell,orion-intc", "marvell,intc";
interrupt-controller; interrupt-controller;
...@@ -24,7 +28,8 @@ gpio0: gpio@10100 { ...@@ -24,7 +28,8 @@ gpio0: gpio@10100 {
#gpio-cells = <2>; #gpio-cells = <2>;
gpio-controller; gpio-controller;
reg = <0x10100 0x40>; reg = <0x10100 0x40>;
ngpio = <32>; ngpios = <32>;
interrupt-controller;
interrupts = <35>, <36>, <37>, <38>; interrupts = <35>, <36>, <37>, <38>;
}; };
...@@ -33,7 +38,8 @@ gpio1: gpio@10140 { ...@@ -33,7 +38,8 @@ gpio1: gpio@10140 {
#gpio-cells = <2>; #gpio-cells = <2>;
gpio-controller; gpio-controller;
reg = <0x10140 0x40>; reg = <0x10140 0x40>;
ngpio = <18>; ngpios = <18>;
interrupt-controller;
interrupts = <39>, <40>, <41>; interrupts = <39>, <40>, <41>;
}; };
......
...@@ -41,7 +41,7 @@ void __init orion_irq_init(unsigned int irq_start, void __iomem *maskaddr) ...@@ -41,7 +41,7 @@ void __init orion_irq_init(unsigned int irq_start, void __iomem *maskaddr)
static int __init orion_add_irq_domain(struct device_node *np, static int __init orion_add_irq_domain(struct device_node *np,
struct device_node *interrupt_parent) struct device_node *interrupt_parent)
{ {
int i = 0, irq_gpio; int i = 0;
void __iomem *base; void __iomem *base;
do { do {
...@@ -54,10 +54,6 @@ static int __init orion_add_irq_domain(struct device_node *np, ...@@ -54,10 +54,6 @@ static int __init orion_add_irq_domain(struct device_node *np,
irq_domain_add_legacy(np, i * 32, 0, 0, irq_domain_add_legacy(np, i * 32, 0, 0,
&irq_domain_simple_ops, NULL); &irq_domain_simple_ops, NULL);
irq_gpio = i * 32;
orion_gpio_of_init(irq_gpio);
return 0; return 0;
} }
......
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