Commit fa6749d4 authored by Dmitry Osipenko's avatar Dmitry Osipenko Committed by Thierry Reding

memory: tegra: Don't set EMC rate to maximum on probe for Tegra20

The memory frequency scaling will be managed by tegra20-devfreq driver
and PM QoS once all the prerequisite patches will get upstreamed.
The parent clock is now managed by the clock driver and we also should
assume that PLLM rate can't be changed on some devices (Galaxy Tab 10.1
for example). Altogether there is no point in touching of clock's rate
from the EMC driver.
Acked-by: default avatarPeter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: default avatarDmitry Osipenko <digetx@gmail.com>
Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
parent 63a613fd
...@@ -137,9 +137,6 @@ struct tegra_emc { ...@@ -137,9 +137,6 @@ struct tegra_emc {
struct device *dev; struct device *dev;
struct completion clk_handshake_complete; struct completion clk_handshake_complete;
struct notifier_block clk_nb; struct notifier_block clk_nb;
struct clk *backup_clk;
struct clk *emc_mux;
struct clk *pll_m;
struct clk *clk; struct clk *clk;
void __iomem *regs; void __iomem *regs;
...@@ -424,41 +421,6 @@ static int emc_setup_hw(struct tegra_emc *emc) ...@@ -424,41 +421,6 @@ static int emc_setup_hw(struct tegra_emc *emc)
return 0; return 0;
} }
static int emc_init(struct tegra_emc *emc, unsigned long rate)
{
int err;
err = clk_set_parent(emc->emc_mux, emc->backup_clk);
if (err) {
dev_err(emc->dev,
"failed to reparent to backup source: %d\n", err);
return err;
}
err = clk_set_rate(emc->pll_m, rate);
if (err) {
dev_err(emc->dev,
"failed to change pll_m rate: %d\n", err);
return err;
}
err = clk_set_parent(emc->emc_mux, emc->pll_m);
if (err) {
dev_err(emc->dev,
"failed to reparent to pll_m: %d\n", err);
return err;
}
err = clk_set_rate(emc->clk, rate);
if (err) {
dev_err(emc->dev,
"failed to change emc rate: %d\n", err);
return err;
}
return 0;
}
static int tegra_emc_probe(struct platform_device *pdev) static int tegra_emc_probe(struct platform_device *pdev)
{ {
struct device_node *np; struct device_node *np;
...@@ -522,52 +484,14 @@ static int tegra_emc_probe(struct platform_device *pdev) ...@@ -522,52 +484,14 @@ static int tegra_emc_probe(struct platform_device *pdev)
return err; return err;
} }
emc->pll_m = clk_get_sys(NULL, "pll_m");
if (IS_ERR(emc->pll_m)) {
err = PTR_ERR(emc->pll_m);
dev_err(&pdev->dev, "failed to get pll_m clock: %d\n", err);
return err;
}
emc->backup_clk = clk_get_sys(NULL, "pll_p");
if (IS_ERR(emc->backup_clk)) {
err = PTR_ERR(emc->backup_clk);
dev_err(&pdev->dev, "failed to get pll_p clock: %d\n", err);
goto put_pll_m;
}
emc->emc_mux = clk_get_parent(emc->clk);
if (IS_ERR(emc->emc_mux)) {
err = PTR_ERR(emc->emc_mux);
dev_err(&pdev->dev, "failed to get emc_mux clock: %d\n", err);
goto put_backup;
}
err = clk_notifier_register(emc->clk, &emc->clk_nb); err = clk_notifier_register(emc->clk, &emc->clk_nb);
if (err) { if (err) {
dev_err(&pdev->dev, "failed to register clk notifier: %d\n", dev_err(&pdev->dev, "failed to register clk notifier: %d\n",
err); err);
goto put_backup; return err;
}
/* set DRAM clock rate to maximum */
err = emc_init(emc, emc->timings[emc->num_timings - 1].rate);
if (err) {
dev_err(&pdev->dev, "failed to initialize EMC clock rate: %d\n",
err);
goto unreg_notifier;
} }
return 0; return 0;
unreg_notifier:
clk_notifier_unregister(emc->clk, &emc->clk_nb);
put_backup:
clk_put(emc->backup_clk);
put_pll_m:
clk_put(emc->pll_m);
return err;
} }
static const struct of_device_id tegra_emc_of_match[] = { static const struct of_device_id tegra_emc_of_match[] = {
......
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