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Commit fa7cccc7 authored by Linus Torvalds's avatar Linus Torvalds
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DRI CVS merge: radeon driver update 

This cleans up the PCI vs AGP GART handling, and turning the
PCI GART hardware on and off.
parent 2219fb8e
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Showing with 111 additions and 235 deletions
drivers/char/drm/radeon.h
View file @ fa7cccc7
......@@ -68,19 +68,19 @@
* 1.5 - Add r200 packets to cmdbuf ioctl
* - Add r200 function to init ioctl
* - Add 'scalar2' instruction to cmdbuf
* 1.6 - Add static agp memory manager
* 1.6 - Add static GART memory manager
* Add irq handler (won't be turned on unless X server knows to)
* Add irq ioctls and irq_active getparam.
* Add wait command for cmdbuf ioctl
* Add agp offset query for getparam
* Add GART offset query for getparam
* 1.7 - Add support for cube map registers: R200_PP_CUBIC_FACES_[0..5]
* and R200_PP_CUBIC_OFFSET_F1_[0..5].
* Added packets R200_EMIT_PP_CUBIC_FACES_[0..5] and
* R200_EMIT_PP_CUBIC_OFFSETS_[0..5]. (brian)
* 1.8 - Remove need to call cleanup ioctls on last client exit (keith)
* Add 'GET' queries for starting additional clients on different VT's.
* Add DRM_IOCTL_RADEON_CP_RESUME ioctl.
* 1.9 - Add texture rectangle support for r100.
* 1.9 - Add DRM_IOCTL_RADEON_CP_RESUME ioctl.
* Add texture rectangle support for r100.
*/
#define DRIVER_IOCTLS \
[DRM_IOCTL_NR(DRM_IOCTL_DMA)] = { radeon_cp_buffers, 1, 0 }, \
......@@ -113,7 +113,7 @@
/* When a client dies:
* - Check for and clean up flipped page state
* - Free any alloced agp memory.
* - Free any alloced GART memory.
*
* DRM infrastructure takes care of reclaiming dma buffers.
*/
......@@ -124,7 +124,7 @@ do { \
if ( dev_priv->page_flipping ) { \
radeon_do_cleanup_pageflip( dev ); \
} \
radeon_mem_release( filp, dev_priv->agp_heap ); \
radeon_mem_release( filp, dev_priv->gart_heap ); \
radeon_mem_release( filp, dev_priv->fb_heap ); \
} \
} while (0)
......
drivers/char/drm/radeon_cp.c
View file @ fa7cccc7
......@@ -855,25 +855,23 @@ static void radeon_cp_init_ring_buffer( drm_device_t *dev,
/* Initialize the memory controller */
RADEON_WRITE( RADEON_MC_FB_LOCATION,
(dev_priv->agp_vm_start - 1) & 0xffff0000 );
(dev_priv->gart_vm_start - 1) & 0xffff0000 );
#if __REALLY_HAVE_AGP
if ( !dev_priv->is_pci ) {
RADEON_WRITE( RADEON_MC_AGP_LOCATION,
(((dev_priv->agp_vm_start - 1 +
dev_priv->agp_size) & 0xffff0000) |
(dev_priv->agp_vm_start >> 16)) );
}
(((dev_priv->gart_vm_start - 1 +
dev_priv->gart_size) & 0xffff0000) |
(dev_priv->gart_vm_start >> 16)) );
#if __REALLY_HAVE_AGP
if ( !dev_priv->is_pci )
ring_start = (dev_priv->cp_ring->offset
- dev->agp->base
+ dev_priv->agp_vm_start);
else
+ dev_priv->gart_vm_start);
} else
#endif
ring_start = (dev_priv->cp_ring->offset
- dev->sg->handle
+ dev_priv->agp_vm_start);
+ dev_priv->gart_vm_start);
RADEON_WRITE( RADEON_CP_RB_BASE, ring_start );
......@@ -891,7 +889,7 @@ static void radeon_cp_init_ring_buffer( drm_device_t *dev,
RADEON_WRITE( RADEON_CP_RB_RPTR_ADDR,
dev_priv->ring_rptr->offset
- dev->agp->base
+ dev_priv->agp_vm_start);
+ dev_priv->gart_vm_start);
} else
#endif
{
......@@ -975,10 +973,36 @@ static void radeon_cp_init_ring_buffer( drm_device_t *dev,
RADEON_ISYNC_CPSCRATCH_IDLEGUI) );
}
/* Enable or disable PCI GART on the chip */
static void radeon_set_pcigart( drm_radeon_private_t *dev_priv, int on )
{
u32 tmp = RADEON_READ( RADEON_AIC_CNTL );
if ( on ) {
RADEON_WRITE( RADEON_AIC_CNTL, tmp | RADEON_PCIGART_TRANSLATE_EN );
/* set PCI GART page-table base address
*/
RADEON_WRITE( RADEON_AIC_PT_BASE, dev_priv->bus_pci_gart );
/* set address range for PCI address translate
*/
RADEON_WRITE( RADEON_AIC_LO_ADDR, dev_priv->gart_vm_start );
RADEON_WRITE( RADEON_AIC_HI_ADDR, dev_priv->gart_vm_start
+ dev_priv->gart_size - 1);
/* Turn off AGP aperture -- is this required for PCI GART?
*/
RADEON_WRITE( RADEON_MC_AGP_LOCATION, 0xffffffc0 ); /* ?? */
RADEON_WRITE( RADEON_AGP_COMMAND, 0 ); /* clear AGP_COMMAND */
} else {
RADEON_WRITE( RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN );
}
}
static int radeon_do_init_cp( drm_device_t *dev, drm_radeon_init_t *init )
{
drm_radeon_private_t *dev_priv;
u32 tmp;
DRM_DEBUG( "\n" );
dev_priv = DRM(alloc)( sizeof(drm_radeon_private_t), DRM_MEM_DRIVER );
......@@ -1091,7 +1115,7 @@ static int radeon_do_init_cp( drm_device_t *dev, drm_radeon_init_t *init )
dev_priv->ring_offset = init->ring_offset;
dev_priv->ring_rptr_offset = init->ring_rptr_offset;
dev_priv->buffers_offset = init->buffers_offset;
dev_priv->agp_textures_offset = init->agp_textures_offset;
dev_priv->gart_textures_offset = init->gart_textures_offset;
if(!dev_priv->sarea) {
DRM_ERROR("could not find sarea!\n");
......@@ -1136,11 +1160,10 @@ static int radeon_do_init_cp( drm_device_t *dev, drm_radeon_init_t *init )
return DRM_ERR(EINVAL);
}
if ( !dev_priv->is_pci ) {
DRM_FIND_MAP( dev_priv->agp_textures,
init->agp_textures_offset );
if(!dev_priv->agp_textures) {
DRM_ERROR("could not find agp texture region!\n");
if ( init->gart_textures_offset ) {
DRM_FIND_MAP( dev_priv->gart_textures, init->gart_textures_offset );
if ( !dev_priv->gart_textures ) {
DRM_ERROR("could not find GART texture region!\n");
dev->dev_private = (void *)dev_priv;
radeon_do_cleanup_cp(dev);
return DRM_ERR(EINVAL);
......@@ -1182,25 +1205,25 @@ static int radeon_do_init_cp( drm_device_t *dev, drm_radeon_init_t *init )
}
dev_priv->agp_size = init->agp_size;
dev_priv->agp_vm_start = RADEON_READ( RADEON_CONFIG_APER_SIZE );
dev_priv->gart_size = init->gart_size;
dev_priv->gart_vm_start = RADEON_READ( RADEON_CONFIG_APER_SIZE );
#if __REALLY_HAVE_AGP
if ( !dev_priv->is_pci )
dev_priv->agp_buffers_offset = (dev_priv->buffers->offset
dev_priv->gart_buffers_offset = (dev_priv->buffers->offset
- dev->agp->base
+ dev_priv->agp_vm_start);
+ dev_priv->gart_vm_start);
else
#endif
dev_priv->agp_buffers_offset = (dev_priv->buffers->offset
dev_priv->gart_buffers_offset = (dev_priv->buffers->offset
- dev->sg->handle
+ dev_priv->agp_vm_start);
+ dev_priv->gart_vm_start);
DRM_DEBUG( "dev_priv->agp_size %d\n",
dev_priv->agp_size );
DRM_DEBUG( "dev_priv->agp_vm_start 0x%x\n",
dev_priv->agp_vm_start );
DRM_DEBUG( "dev_priv->agp_buffers_offset 0x%lx\n",
dev_priv->agp_buffers_offset );
DRM_DEBUG( "dev_priv->gart_size %d\n",
dev_priv->gart_size );
DRM_DEBUG( "dev_priv->gart_vm_start 0x%x\n",
dev_priv->gart_vm_start );
DRM_DEBUG( "dev_priv->gart_buffers_offset 0x%lx\n",
dev_priv->gart_buffers_offset );
dev_priv->ring.start = (u32 *)dev_priv->cp_ring->handle;
dev_priv->ring.end = ((u32 *)dev_priv->cp_ring->handle
......@@ -1213,7 +1236,13 @@ static int radeon_do_init_cp( drm_device_t *dev, drm_radeon_init_t *init )
dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK;
if ( dev_priv->is_pci ) {
#if __REALLY_HAVE_AGP
if ( !dev_priv->is_pci ) {
/* Turn off PCI GART */
radeon_set_pcigart( dev_priv, 0 );
} else
#endif
{
if (!DRM(ati_pcigart_init)( dev, &dev_priv->phys_pci_gart,
&dev_priv->bus_pci_gart)) {
DRM_ERROR( "failed to init PCI GART!\n" );
......@@ -1221,32 +1250,9 @@ static int radeon_do_init_cp( drm_device_t *dev, drm_radeon_init_t *init )
radeon_do_cleanup_cp(dev);
return DRM_ERR(ENOMEM);
}
/* Turn on PCI GART
*/
tmp = RADEON_READ( RADEON_AIC_CNTL )
| RADEON_PCIGART_TRANSLATE_EN;
RADEON_WRITE( RADEON_AIC_CNTL, tmp );
/* set PCI GART page-table base address
*/
RADEON_WRITE( RADEON_AIC_PT_BASE, dev_priv->bus_pci_gart );
/* set address range for PCI address translate
*/
RADEON_WRITE( RADEON_AIC_LO_ADDR, dev_priv->agp_vm_start );
RADEON_WRITE( RADEON_AIC_HI_ADDR, dev_priv->agp_vm_start
+ dev_priv->agp_size - 1);
/* Turn off AGP aperture -- is this required for PCIGART?
*/
RADEON_WRITE( RADEON_MC_AGP_LOCATION, 0xffffffc0 ); /* ?? */
RADEON_WRITE( RADEON_AGP_COMMAND, 0 ); /* clear AGP_COMMAND */
} else {
/* Turn off PCI GART
*/
tmp = RADEON_READ( RADEON_AIC_CNTL )
& ~RADEON_PCIGART_TRANSLATE_EN;
RADEON_WRITE( RADEON_AIC_CNTL, tmp );
/* Turn on PCI GART */
radeon_set_pcigart( dev_priv, 1 );
}
radeon_cp_load_microcode( dev_priv );
......@@ -1304,162 +1310,30 @@ int radeon_do_cleanup_cp( drm_device_t *dev )
/* This code will reinit the Radeon CP hardware after a resume from disc.
* AFAIK, it would be very difficult to pickle the state at suspend time, so
* here we make sure that all Radeon hardware initialisation is re-done without
* affecting running applications. This function is called radeon_do_resume_cp()
* as it was derived from radeon_init_cp, where most of the initialisation takes
* place during DRI init.
*
* This patch is NOT to be confused with my and Michel Daenzer's earlier DRI
* reinit work, which de- and re-initialised the complete DRI at every VT
* switch.
* affecting running applications.
*
* Charl P. Botha <http://cpbotha.net>
*/
static int radeon_do_resume_cp( drm_device_t *dev)
static int radeon_do_resume_cp( drm_device_t *dev )
{
drm_radeon_private_t *dev_priv;
u32 tmp;
DRM_DEBUG( "\n" );
DRM_DEBUG("Starting radeon_do_resume_cp()\n");
/* get the existing dev_private */
dev_priv = dev->dev_private;
#if !defined(PCIGART_ENABLED)
/* PCI support is not 100% working, so we disable it here.
*/
if ( dev_priv->is_pci ) {
DRM_ERROR( "PCI GART not yet supported for Radeon!\n" );
radeon_do_cleanup_cp(dev);
return DRM_ERR(EINVAL);
}
#endif
if ( dev_priv->is_pci && !dev->sg ) {
DRM_ERROR( "PCI GART memory not allocated!\n" );
radeon_do_cleanup_cp(dev);
return DRM_ERR(EINVAL);
}
if ( dev_priv->usec_timeout < 1 ||
dev_priv->usec_timeout > RADEON_MAX_USEC_TIMEOUT ) {
DRM_DEBUG( "TIMEOUT problem!\n" );
radeon_do_cleanup_cp(dev);
return DRM_ERR(EINVAL);
}
if ( ( dev_priv->cp_mode != RADEON_CSQ_PRIBM_INDDIS ) &&
( dev_priv->cp_mode != RADEON_CSQ_PRIBM_INDBM ) ) {
DRM_DEBUG( "BAD cp_mode (%x)!\n", dev_priv->cp_mode );
radeon_do_cleanup_cp(dev);
return DRM_ERR(EINVAL);
}
if(!dev_priv->sarea) {
DRM_ERROR("could not find sarea!\n");
radeon_do_cleanup_cp(dev);
return DRM_ERR(EINVAL);
}
if(!dev_priv->fb) {
DRM_ERROR("could not find framebuffer!\n");
radeon_do_cleanup_cp(dev);
return DRM_ERR(EINVAL);
}
if(!dev_priv->mmio) {
DRM_ERROR("could not find mmio region!\n");
radeon_do_cleanup_cp(dev);
return DRM_ERR(EINVAL);
}
if(!dev_priv->cp_ring) {
DRM_ERROR("could not find cp ring region!\n");
radeon_do_cleanup_cp(dev);
return DRM_ERR(EINVAL);
}
if(!dev_priv->ring_rptr) {
DRM_ERROR("could not find ring read pointer!\n");
radeon_do_cleanup_cp(dev);
return DRM_ERR(EINVAL);
}
if(!dev_priv->buffers) {
DRM_ERROR("could not find dma buffer region!\n");
radeon_do_cleanup_cp(dev);
return DRM_ERR(EINVAL);
}
if ( !dev_priv->is_pci ) {
if(!dev_priv->agp_textures) {
DRM_ERROR("could not find agp texture region!\n");
radeon_do_cleanup_cp(dev);
return DRM_ERR(EINVAL);
}
}
drm_radeon_private_t *dev_priv = dev->dev_private;
if ( !dev_priv->is_pci ) {
if(!dev_priv->cp_ring->handle ||
!dev_priv->ring_rptr->handle ||
!dev_priv->buffers->handle) {
DRM_ERROR("could not find ioremap agp regions!\n");
radeon_do_cleanup_cp(dev);
return DRM_ERR(EINVAL);
}
} else {
DRM_DEBUG( "dev_priv->cp_ring->handle %p\n",
dev_priv->cp_ring->handle );
DRM_DEBUG( "dev_priv->ring_rptr->handle %p\n",
dev_priv->ring_rptr->handle );
DRM_DEBUG( "dev_priv->buffers->handle %p\n",
dev_priv->buffers->handle );
if ( !dev_priv ) {
DRM_ERROR( "Called with no initialization\n" );
return DRM_ERR( EINVAL );
}
DRM_DEBUG( "dev_priv->agp_size %d\n",
dev_priv->agp_size );
DRM_DEBUG( "dev_priv->agp_vm_start 0x%x\n",
dev_priv->agp_vm_start );
DRM_DEBUG( "dev_priv->agp_buffers_offset 0x%lx\n",
dev_priv->agp_buffers_offset );
DRM_DEBUG("Starting radeon_do_resume_cp()\n");
#if __REALLY_HAVE_AGP
if ( !dev_priv->is_pci ) {
/* Turn off PCI GART
*/
tmp = RADEON_READ( RADEON_AIC_CNTL )
& ~RADEON_PCIGART_TRANSLATE_EN;
RADEON_WRITE( RADEON_AIC_CNTL, tmp );
/* Turn off PCI GART */
radeon_set_pcigart( dev_priv, 0 );
} else
#endif
{
/* I'm not so sure about this ati_picgart_init after at resume-time... */
if (!DRM(ati_pcigart_init)( dev, &dev_priv->phys_pci_gart,
&dev_priv->bus_pci_gart)) {
DRM_ERROR( "failed to init PCI GART!\n" );
radeon_do_cleanup_cp(dev);
return DRM_ERR(ENOMEM);
}
tmp = RADEON_READ( RADEON_AIC_CNTL )
| RADEON_PCIGART_TRANSLATE_EN;
RADEON_WRITE( RADEON_AIC_CNTL, tmp );
/* set PCI GART page-table base address
*/
RADEON_WRITE( RADEON_AIC_PT_BASE, dev_priv->bus_pci_gart );
/* set address range for PCI address translate
*/
RADEON_WRITE( RADEON_AIC_LO_ADDR, dev_priv->agp_vm_start );
RADEON_WRITE( RADEON_AIC_HI_ADDR, dev_priv->agp_vm_start
+ dev_priv->agp_size - 1);
/* Turn off AGP aperture -- is this required for PCIGART?
*/
RADEON_WRITE( RADEON_MC_AGP_LOCATION, 0xffffffc0 ); /* ?? */
RADEON_WRITE( RADEON_AGP_COMMAND, 0 ); /* clear AGP_COMMAND */
/* Turn on PCI GART */
radeon_set_pcigart( dev_priv, 1 );
}
radeon_cp_load_microcode( dev_priv );
......@@ -1467,6 +1341,8 @@ static int radeon_do_resume_cp( drm_device_t *dev)
radeon_do_engine_reset( dev );
DRM_DEBUG("radeon_do_resume_cp() complete\n");
return 0;
}
......@@ -1584,7 +1460,7 @@ void radeon_do_release( drm_device_t *dev )
RADEON_WRITE( RADEON_GEN_INT_CNTL, 0 );
/* Free memory heap structures */
radeon_mem_takedown( &(dev_priv->agp_heap) );
radeon_mem_takedown( &(dev_priv->gart_heap) );
radeon_mem_takedown( &(dev_priv->fb_heap) );
/* deallocate kernel resources */
......
drivers/char/drm/radeon_drm.h
View file @ fa7cccc7
......@@ -214,11 +214,11 @@ typedef union {
#define RADEON_NR_SAREA_CLIPRECTS 12
/* There are 2 heaps (local/AGP). Each region within a heap is a
/* There are 2 heaps (local/GART). Each region within a heap is a
* minimum of 64k, and there are at most 64 of them per heap.
*/
#define RADEON_LOCAL_TEX_HEAP 0
#define RADEON_AGP_TEX_HEAP 1
#define RADEON_GART_TEX_HEAP 1
#define RADEON_NR_TEX_HEAPS 2
#define RADEON_NR_TEX_REGIONS 64
#define RADEON_LOG_TEX_GRANULARITY 16
......@@ -400,7 +400,7 @@ typedef struct drm_radeon_init {
unsigned long sarea_priv_offset;
int is_pci;
int cp_mode;
int agp_size;
int gart_size;
int ring_size;
int usec_timeout;
......@@ -415,7 +415,7 @@ typedef struct drm_radeon_init {
unsigned long ring_offset;
unsigned long ring_rptr_offset;
unsigned long buffers_offset;
unsigned long agp_textures_offset;
unsigned long gart_textures_offset;
} drm_radeon_init_t;
typedef struct drm_radeon_cp_stop {
......@@ -525,18 +525,18 @@ typedef struct drm_radeon_indirect {
/* 1.3: An ioctl to get parameters that aren't available to the 3d
* client any other way.
*/
#define RADEON_PARAM_AGP_BUFFER_OFFSET 1 /* card offset of 1st agp buffer */
#define RADEON_PARAM_GART_BUFFER_OFFSET 1 /* card offset of 1st GART buffer */
#define RADEON_PARAM_LAST_FRAME 2
#define RADEON_PARAM_LAST_DISPATCH 3
#define RADEON_PARAM_LAST_CLEAR 4
/* Added with DRM version 1.6. */
#define RADEON_PARAM_IRQ_NR 5
#define RADEON_PARAM_AGP_BASE 6 /* card offset of agp base */
#define RADEON_PARAM_GART_BASE 6 /* card offset of GART base */
/* Added with DRM version 1.8. */
#define RADEON_PARAM_REGISTER_HANDLE 7 /* for drmMap() */
#define RADEON_PARAM_STATUS_HANDLE 8
#define RADEON_PARAM_SAREA_HANDLE 9
#define RADEON_PARAM_AGP_TEX_HANDLE 10
#define RADEON_PARAM_GART_TEX_HANDLE 10
typedef struct drm_radeon_getparam {
int param;
......@@ -545,14 +545,14 @@ typedef struct drm_radeon_getparam {
/* 1.6: Set up a memory manager for regions of shared memory:
*/
#define RADEON_MEM_REGION_AGP 1
#define RADEON_MEM_REGION_FB 2
#define RADEON_MEM_REGION_GART 1
#define RADEON_MEM_REGION_FB 2
typedef struct drm_radeon_mem_alloc {
int region;
int alignment;
int size;
int *region_offset; /* offset from start of fb or agp */
int *region_offset; /* offset from start of fb or GART */
} drm_radeon_mem_alloc_t;
typedef struct drm_radeon_mem_free {
......
drivers/char/drm/radeon_drv.h
View file @ fa7cccc7
......@@ -73,9 +73,9 @@ typedef struct drm_radeon_private {
drm_radeon_ring_buffer_t ring;
drm_radeon_sarea_t *sarea_priv;
int agp_size;
u32 agp_vm_start;
unsigned long agp_buffers_offset;
int gart_size;
u32 gart_vm_start;
unsigned long gart_buffers_offset;
int cp_mode;
int cp_running;
......@@ -130,7 +130,7 @@ typedef struct drm_radeon_private {
unsigned long ring_offset;
unsigned long ring_rptr_offset;
unsigned long buffers_offset;
unsigned long agp_textures_offset;
unsigned long gart_textures_offset;
drm_local_map_t *sarea;
drm_local_map_t *fb;
......@@ -138,9 +138,9 @@ typedef struct drm_radeon_private {
drm_local_map_t *cp_ring;
drm_local_map_t *ring_rptr;
drm_local_map_t *buffers;
drm_local_map_t *agp_textures;
drm_local_map_t *gart_textures;
struct mem_block *agp_heap;
struct mem_block *gart_heap;
struct mem_block *fb_heap;
/* SW interrupt */
......
drivers/char/drm/radeon_mem.c
View file @ fa7cccc7
/* radeon_mem.c -- Simple agp/fb memory manager for radeon -*- linux-c -*-
/* radeon_mem.c -- Simple GART/fb memory manager for radeon -*- linux-c -*-
*
* Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
*
......@@ -35,7 +35,7 @@
#include "radeon_drm.h"
#include "radeon_drv.h"
/* Very simple allocator for agp memory, working on a static range
/* Very simple allocator for GART memory, working on a static range
* already mapped into each client's address space.
*/
......@@ -212,8 +212,8 @@ static struct mem_block **get_heap( drm_radeon_private_t *dev_priv,
int region )
{
switch( region ) {
case RADEON_MEM_REGION_AGP:
return &dev_priv->agp_heap;
case RADEON_MEM_REGION_GART:
return &dev_priv->gart_heap;
case RADEON_MEM_REGION_FB:
return &dev_priv->fb_heap;
default:
......
drivers/char/drm/radeon_state.c
View file @ fa7cccc7
......@@ -893,7 +893,7 @@ static void radeon_cp_dispatch_vertex( drm_device_t *dev,
{
drm_radeon_private_t *dev_priv = dev->dev_private;
drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
int offset = dev_priv->agp_buffers_offset + buf->offset + prim->start;
int offset = dev_priv->gart_buffers_offset + buf->offset + prim->start;
int numverts = (int)prim->numverts;
int nbox = sarea_priv->nbox;
int i = 0;
......@@ -966,7 +966,7 @@ static void radeon_cp_dispatch_indirect( drm_device_t *dev,
buf->idx, start, end );
if ( start != end ) {
int offset = (dev_priv->agp_buffers_offset
int offset = (dev_priv->gart_buffers_offset
+ buf->offset + start);
int dwords = (end - start + 3) / sizeof(u32);
......@@ -999,7 +999,7 @@ static void radeon_cp_dispatch_indices( drm_device_t *dev,
{
drm_radeon_private_t *dev_priv = dev->dev_private;
drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
int offset = dev_priv->agp_buffers_offset + prim->offset;
int offset = dev_priv->gart_buffers_offset + prim->offset;
u32 *data;
int dwords;
int i = 0;
......@@ -2159,8 +2159,8 @@ int radeon_cp_getparam( DRM_IOCTL_ARGS )
DRM_DEBUG( "pid=%d\n", DRM_CURRENTPID );
switch( param.param ) {
case RADEON_PARAM_AGP_BUFFER_OFFSET:
value = dev_priv->agp_buffers_offset;
case RADEON_PARAM_GART_BUFFER_OFFSET:
value = dev_priv->gart_buffers_offset;
break;
case RADEON_PARAM_LAST_FRAME:
dev_priv->stats.last_frame_reads++;
......@@ -2176,8 +2176,8 @@ int radeon_cp_getparam( DRM_IOCTL_ARGS )
case RADEON_PARAM_IRQ_NR:
value = dev->irq;
break;
case RADEON_PARAM_AGP_BASE:
value = dev_priv->agp_vm_start;
case RADEON_PARAM_GART_BASE:
value = dev_priv->gart_vm_start;
break;
case RADEON_PARAM_REGISTER_HANDLE:
value = dev_priv->mmio_offset;
......@@ -2189,8 +2189,8 @@ int radeon_cp_getparam( DRM_IOCTL_ARGS )
/* The lock is the first dword in the sarea. */
value = (int)dev->lock.hw_lock;
break;
case RADEON_PARAM_AGP_TEX_HANDLE:
value = dev_priv->agp_textures_offset;
case RADEON_PARAM_GART_TEX_HANDLE:
value = dev_priv->gart_textures_offset;
break;
default:
return DRM_ERR(EINVAL);
......
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