DRI CVS merge: radeon driver update

This cleans up the PCI vs AGP GART handling, and turning the
PCI GART hardware on and off.

drivers/char/drm/radeon.h

@@ -68,19 +68,19 @@
  * 1.5 - Add r200 packets to cmdbuf ioctl
  *     - Add r200 function to init ioctl
  *     - Add 'scalar2' instruction to cmdbuf
- * 1.6 - Add static agp memory manager
+ * 1.6 - Add static GART memory manager
  *       Add irq handler (won't be turned on unless X server knows to)
  *       Add irq ioctls and irq_active getparam.
  *       Add wait command for cmdbuf ioctl
- *       Add agp offset query for getparam
+ *       Add GART offset query for getparam
  * 1.7 - Add support for cube map registers: R200_PP_CUBIC_FACES_[0..5]
  *       and R200_PP_CUBIC_OFFSET_F1_[0..5].
  *       Added packets R200_EMIT_PP_CUBIC_FACES_[0..5] and
  *       R200_EMIT_PP_CUBIC_OFFSETS_[0..5].  (brian)
  * 1.8 - Remove need to call cleanup ioctls on last client exit (keith)
  *       Add 'GET' queries for starting additional clients on different VT's.
- *       Add DRM_IOCTL_RADEON_CP_RESUME ioctl.
- * 1.9 - Add texture rectangle support for r100.
+ * 1.9 - Add DRM_IOCTL_RADEON_CP_RESUME ioctl.
+ *       Add texture rectangle support for r100.
  */
 #define DRIVER_IOCTLS							     \
  [DRM_IOCTL_NR(DRM_IOCTL_DMA)]               = { radeon_cp_buffers,  1, 0 }, \
@@ -113,7 +113,7 @@
 
 /* When a client dies:
  *    - Check for and clean up flipped page state
- *    - Free any alloced agp memory.
+ *    - Free any alloced GART memory.
  *
  * DRM infrastructure takes care of reclaiming dma buffers.
  */
@@ -124,7 +124,7 @@ do {									\
 		if ( dev_priv->page_flipping ) {			\
 			radeon_do_cleanup_pageflip( dev );		\
 		}							\
-                radeon_mem_release( filp, dev_priv->agp_heap );		\
+		radeon_mem_release( filp, dev_priv->gart_heap );	\
                 radeon_mem_release( filp, dev_priv->fb_heap );		\
 	}								\
 } while (0)

drivers/char/drm/radeon_drm.h

@@ -214,11 +214,11 @@ typedef union {
 
 #define RADEON_NR_SAREA_CLIPRECTS	12
 
-/* There are 2 heaps (local/AGP).  Each region within a heap is a
+/* There are 2 heaps (local/GART).  Each region within a heap is a
  * minimum of 64k, and there are at most 64 of them per heap.
  */
 #define RADEON_LOCAL_TEX_HEAP		0
-#define RADEON_AGP_TEX_HEAP		1
+#define RADEON_GART_TEX_HEAP		1
 #define RADEON_NR_TEX_HEAPS		2
 #define RADEON_NR_TEX_REGIONS		64
 #define RADEON_LOG_TEX_GRANULARITY	16
@@ -400,7 +400,7 @@ typedef struct drm_radeon_init {
 	unsigned long sarea_priv_offset;
 	int is_pci;
 	int cp_mode;
-	int agp_size;
+	int gart_size;
 	int ring_size;
 	int usec_timeout;
 
@@ -415,7 +415,7 @@ typedef struct drm_radeon_init {
 	unsigned long ring_offset;
 	unsigned long ring_rptr_offset;
 	unsigned long buffers_offset;
-	unsigned long agp_textures_offset;
+	unsigned long gart_textures_offset;
 } drm_radeon_init_t;
 
 typedef struct drm_radeon_cp_stop {
@@ -525,18 +525,18 @@ typedef struct drm_radeon_indirect {
 /* 1.3: An ioctl to get parameters that aren't available to the 3d
  * client any other way.  
  */
-#define RADEON_PARAM_AGP_BUFFER_OFFSET     1 /* card offset of 1st agp buffer */
+#define RADEON_PARAM_GART_BUFFER_OFFSET    1 /* card offset of 1st GART buffer */
 #define RADEON_PARAM_LAST_FRAME            2
 #define RADEON_PARAM_LAST_DISPATCH         3
 #define RADEON_PARAM_LAST_CLEAR            4
 /* Added with DRM version 1.6. */
 #define RADEON_PARAM_IRQ_NR                5
-#define RADEON_PARAM_AGP_BASE              6 /* card offset of agp base */
+#define RADEON_PARAM_GART_BASE             6 /* card offset of GART base */
 /* Added with DRM version 1.8. */
 #define RADEON_PARAM_REGISTER_HANDLE       7 /* for drmMap() */
 #define RADEON_PARAM_STATUS_HANDLE         8
 #define RADEON_PARAM_SAREA_HANDLE          9
-#define RADEON_PARAM_AGP_TEX_HANDLE        10
+#define RADEON_PARAM_GART_TEX_HANDLE       10
 
 typedef struct drm_radeon_getparam {
 	int param;
@@ -545,14 +545,14 @@ typedef struct drm_radeon_getparam {
 
 /* 1.6: Set up a memory manager for regions of shared memory:
  */
-#define RADEON_MEM_REGION_AGP 1
+#define RADEON_MEM_REGION_GART 1
 #define RADEON_MEM_REGION_FB   2
 
 typedef struct drm_radeon_mem_alloc {
 	int region;
 	int alignment;
 	int size;
-	int *region_offset;	/* offset from start of fb or agp */
+	int *region_offset;	/* offset from start of fb or GART */
 } drm_radeon_mem_alloc_t;
 
 typedef struct drm_radeon_mem_free {

drivers/char/drm/radeon_drv.h

@@ -73,9 +73,9 @@ typedef struct drm_radeon_private {
 	drm_radeon_ring_buffer_t ring;
 	drm_radeon_sarea_t *sarea_priv;
 
-	int agp_size;
-	u32 agp_vm_start;
-	unsigned long agp_buffers_offset;
+	int gart_size;
+	u32 gart_vm_start;
+	unsigned long gart_buffers_offset;
 
 	int cp_mode;
 	int cp_running;
@@ -130,7 +130,7 @@ typedef struct drm_radeon_private {
 	unsigned long ring_offset;
 	unsigned long ring_rptr_offset;
 	unsigned long buffers_offset;
-	unsigned long agp_textures_offset;
+	unsigned long gart_textures_offset;
 
 	drm_local_map_t *sarea;
 	drm_local_map_t *fb;
@@ -138,9 +138,9 @@ typedef struct drm_radeon_private {
 	drm_local_map_t *cp_ring;
 	drm_local_map_t *ring_rptr;
 	drm_local_map_t *buffers;
-	drm_local_map_t *agp_textures;
+	drm_local_map_t *gart_textures;
 
-	struct mem_block *agp_heap;
+	struct mem_block *gart_heap;
 	struct mem_block *fb_heap;
 
 	/* SW interrupt */

drivers/char/drm/radeon_mem.c

-/* radeon_mem.c -- Simple agp/fb memory manager for radeon -*- linux-c -*-
+/* radeon_mem.c -- Simple GART/fb memory manager for radeon -*- linux-c -*-
  *
  * Copyright (C) The Weather Channel, Inc.  2002.  All Rights Reserved.
  * 
@@ -35,7 +35,7 @@
 #include "radeon_drm.h"
 #include "radeon_drv.h"
 
-/* Very simple allocator for agp memory, working on a static range
+/* Very simple allocator for GART memory, working on a static range
  * already mapped into each client's address space.  
  */
 
@@ -212,8 +212,8 @@ static struct mem_block **get_heap( drm_radeon_private_t *dev_priv,
 				   int region )
 {
 	switch( region ) {
-	case RADEON_MEM_REGION_AGP:
- 		return &dev_priv->agp_heap; 
+	case RADEON_MEM_REGION_GART:
+ 		return &dev_priv->gart_heap; 
 	case RADEON_MEM_REGION_FB:
 		return &dev_priv->fb_heap;
 	default:

drivers/char/drm/radeon_state.c

@@ -893,7 +893,7 @@ static void radeon_cp_dispatch_vertex( drm_device_t *dev,
 {
 	drm_radeon_private_t *dev_priv = dev->dev_private;
 	drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
-	int offset = dev_priv->agp_buffers_offset + buf->offset + prim->start;
+	int offset = dev_priv->gart_buffers_offset + buf->offset + prim->start;
 	int numverts = (int)prim->numverts;
 	int nbox = sarea_priv->nbox;
 	int i = 0;
@@ -966,7 +966,7 @@ static void radeon_cp_dispatch_indirect( drm_device_t *dev,
 		   buf->idx, start, end );
 
 	if ( start != end ) {
-		int offset = (dev_priv->agp_buffers_offset
+		int offset = (dev_priv->gart_buffers_offset
 			      + buf->offset + start);
 		int dwords = (end - start + 3) / sizeof(u32);
 
@@ -999,7 +999,7 @@ static void radeon_cp_dispatch_indices( drm_device_t *dev,
 {
 	drm_radeon_private_t *dev_priv = dev->dev_private;
 	drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
-	int offset = dev_priv->agp_buffers_offset + prim->offset;
+	int offset = dev_priv->gart_buffers_offset + prim->offset;
 	u32 *data;
 	int dwords;
 	int i = 0;
@@ -2159,8 +2159,8 @@ int radeon_cp_getparam( DRM_IOCTL_ARGS )
 	DRM_DEBUG( "pid=%d\n", DRM_CURRENTPID );
 
 	switch( param.param ) {
-	case RADEON_PARAM_AGP_BUFFER_OFFSET:
-		value = dev_priv->agp_buffers_offset;
+	case RADEON_PARAM_GART_BUFFER_OFFSET:
+		value = dev_priv->gart_buffers_offset;
 		break;
 	case RADEON_PARAM_LAST_FRAME:
 		dev_priv->stats.last_frame_reads++;
@@ -2176,8 +2176,8 @@ int radeon_cp_getparam( DRM_IOCTL_ARGS )
 	case RADEON_PARAM_IRQ_NR:
 		value = dev->irq;
 		break;
-	case RADEON_PARAM_AGP_BASE:
-		value = dev_priv->agp_vm_start;
+	case RADEON_PARAM_GART_BASE:
+		value = dev_priv->gart_vm_start;
 		break;
 	case RADEON_PARAM_REGISTER_HANDLE:
 		value = dev_priv->mmio_offset;
@@ -2189,8 +2189,8 @@ int radeon_cp_getparam( DRM_IOCTL_ARGS )
 		/* The lock is the first dword in the sarea. */
 		value = (int)dev->lock.hw_lock; 
 		break;	
-	case RADEON_PARAM_AGP_TEX_HANDLE:
-		value = dev_priv->agp_textures_offset;
+	case RADEON_PARAM_GART_TEX_HANDLE:
+		value = dev_priv->gart_textures_offset;
 		break;
 	default:
 		return DRM_ERR(EINVAL);