Commit fbd1cec5 authored by Eugeniy Paltsev's avatar Eugeniy Paltsev Committed by Vineet Gupta

ARC: [plat-axs103]: Set initial core pll output frequency

Set initial core pll output frequency specified in device tree to
100MHz for SMP configuration and 90MHz for UP configuration.
It will be applied at the core pll driver probing.

Update platform quirk for decreasing core frequency for quad core
configuration.
Acked-by: default avatarStephen Boyd <sboyd@codeaurora.org>
Signed-off-by: default avatarEugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: default avatarVineet Gupta <vgupta@synopsys.com>
parent 7bde846d
...@@ -35,6 +35,14 @@ core_clk: core-clk@80 { ...@@ -35,6 +35,14 @@ core_clk: core-clk@80 {
reg = <0x80 0x10>, <0x100 0x10>; reg = <0x80 0x10>, <0x100 0x10>;
#clock-cells = <0>; #clock-cells = <0>;
clocks = <&input_clk>; clocks = <&input_clk>;
/*
* Set initial core pll output frequency to 90MHz.
* It will be applied at the core pll driver probing
* on early boot.
*/
assigned-clocks = <&core_clk>;
assigned-clock-rates = <90000000>;
}; };
core_intc: archs-intc@cpu { core_intc: archs-intc@cpu {
......
...@@ -35,6 +35,14 @@ core_clk: core-clk@80 { ...@@ -35,6 +35,14 @@ core_clk: core-clk@80 {
reg = <0x80 0x10>, <0x100 0x10>; reg = <0x80 0x10>, <0x100 0x10>;
#clock-cells = <0>; #clock-cells = <0>;
clocks = <&input_clk>; clocks = <&input_clk>;
/*
* Set initial core pll output frequency to 100MHz.
* It will be applied at the core pll driver probing
* on early boot.
*/
assigned-clocks = <&core_clk>;
assigned-clock-rates = <100000000>;
}; };
core_intc: archs-intc@cpu { core_intc: archs-intc@cpu {
......
...@@ -320,22 +320,18 @@ static void __init axs103_early_init(void) ...@@ -320,22 +320,18 @@ static void __init axs103_early_init(void)
unsigned int num_cores = (read_aux_reg(ARC_REG_MCIP_BCR) >> 16) & 0x3F; unsigned int num_cores = (read_aux_reg(ARC_REG_MCIP_BCR) >> 16) & 0x3F;
if (num_cores > 2) { if (num_cores > 2) {
u32 freq = 50, orig; u32 freq = 50, orig;
/*
* TODO: use cpu node "cpu-freq" param instead of platform-specific
* "/cpu_card/core_clk" as it works only if we use fixed-clock for cpu.
*/
int off = fdt_path_offset(initial_boot_params, "/cpu_card/core_clk"); int off = fdt_path_offset(initial_boot_params, "/cpu_card/core_clk");
const struct fdt_property *prop; const struct fdt_property *prop;
prop = fdt_get_property(initial_boot_params, off, prop = fdt_get_property(initial_boot_params, off,
"clock-frequency", NULL); "assigned-clock-rates", NULL);
orig = be32_to_cpu(*(u32*)(prop->data)) / 1000000; orig = be32_to_cpu(*(u32*)(prop->data)) / 1000000;
/* Patching .dtb in-place with new core clock value */ /* Patching .dtb in-place with new core clock value */
if (freq != orig ) { if (freq != orig ) {
freq = cpu_to_be32(freq * 1000000); freq = cpu_to_be32(freq * 1000000);
fdt_setprop_inplace(initial_boot_params, off, fdt_setprop_inplace(initial_boot_params, off,
"clock-frequency", &freq, sizeof(freq)); "assigned-clock-rates", &freq, sizeof(freq));
} }
} }
#endif #endif
......
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