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Commit fbefc532 authored by Arnd Bergmann's avatar Arnd Bergmann
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Merge tag 'sti-dt-for-v4.17-round1' of... 

Merge tag 'sti-dt-for-v4.17-round1' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/pchotard/sti into next/dt

Pull "STi dts update" from Patrice Chotard:

Fix all DT dtc warnings when building with W=1
For most of implicated node, the addition of a fake reg property
fixes these warnings.
For others nodes, their location in device tree
have been updated.

* tag 'sti-dt-for-v4.17-round1' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/pchotard/sti:
  ARM: dts: STi: Remove unused clk_ext2f_a9 clock
  ARM: dts: STi: Update clocks node location
  ARM: dts: STi: Update sound related nodes location
  ARM: dts: STi: Add fake reg property for usb2_picophyX nodes
  ARM: dts: STi: Add fake reg for restart, powerdown and picophy/softreset
  ARM: dts: STi: Add fake reg property for remote processors
  ARM: dts: STi: Add fake reg property for irq-syscfg
  ARM: dts: STi: Add fake reg property for miphy28lp_phy
  ARM: dts: STi: Add fake reg property for sti-display-subsystem
  ARM: dts: STi: Move leds node outside soc node
  ARM: dts: STi: Fix bindings notation
parents d6bdd009 0e04ce02
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arch/arm/boot/dts/stih407-b2120.dts
View file @ fbefc532
......@@ -18,7 +18,7 @@ chosen {
linux,stdout-path = &sbc_serial0;
};
memory {
memory@40000000 {
device_type = "memory";
reg = <0x40000000 0x80000000>;
};
......
arch/arm/boot/dts/stih407-clock.dtsi
View file @ fbefc532
......@@ -7,11 +7,6 @@
*/
#include <dt-bindings/clock/stih407-clks.h>
/ {
clocks {
#address-cells = <1>;
#size-cells = <1>;
ranges;
/*
* Fixed 30MHz oscillator inputs to SoC
*/
......@@ -21,18 +16,17 @@ clk_sysin: clk-sysin {
clock-frequency = <30000000>;
};
/*
* ARM Peripheral clock for timers
*/
arm_periph_clk: clk-m-a9-periphs {
clk_tmdsout_hdmi: clk-tmdsout-hdmi {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&clk_m_a9>;
clock-div = <2>;
clock-mult = <1>;
compatible = "fixed-clock";
clock-frequency = <0>;
};
clocks {
#address-cells = <1>;
#size-cells = <1>;
ranges;
/*
* A9 PLL.
*/
......@@ -62,32 +56,19 @@ clk_m_a9: clk-m-a9@92b0000 {
<&clockgen_a9_pll 0>,
<&clk_s_c0_flexgen 13>,
<&clk_m_a9_ext2f_div2>;
};
/*
* ARM Peripheral clock for timers
*/
clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2s {
arm_periph_clk: clk-m-a9-periphs {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&clk_s_c0_flexgen 13>;
clock-output-names = "clk-m-a9-ext2f-div2";
clocks = <&clk_m_a9>;
clock-div = <2>;
clock-mult = <1>;
};
/*
* Bootloader initialized system infrastructure clock for
* serial devices.
*/
clk_ext2f_a9: clockgen-c0@13 {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <200000000>;
clock-output-names = "clk-s-icn-reg-0";
};
clockgen-a@90ff000 {
......@@ -204,6 +185,21 @@ clk_s_c0_flexgen: clk-s-c0-flexgen {
<CLK_EXT2F_A9>,
<CLK_ICN_LMI>,
<CLK_ICN_SBC>;
/*
* ARM Peripheral clock for timers
*/
clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2s {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&clk_s_c0_flexgen 13>;
clock-output-names = "clk-m-a9-ext2f-div2";
clock-div = <2>;
clock-mult = <1>;
};
};
};
......@@ -254,13 +250,7 @@ clk_s_d2_quadfs: clk-s-d2-quadfs@9106000 {
"clk-s-d2-fs0-ch3";
};
clk_tmdsout_hdmi: clk-tmdsout-hdmi {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <0>;
};
clockgen-d2@x9106000 {
clockgen-d2@9106000 {
compatible = "st,clkgen-c32";
reg = <0x9106000 0x1000>;
......
arch/arm/boot/dts/stih407-family.dtsi
View file @ fbefc532
......@@ -92,7 +92,7 @@ timer@8760200 {
clocks = <&arm_periph_clk>;
};
l2: cache-controller {
l2: cache-controller@8762000 {
compatible = "arm,pl310-cache";
reg = <0x08762000 0x1000>;
arm,data-latency = <3 3 3>;
......@@ -125,24 +125,28 @@ soc {
ranges;
compatible = "simple-bus";
restart {
restart: restart-controller@0 {
compatible = "st,stih407-restart";
reg = <0 0>;
st,syscfg = <&syscfg_sbc_reg>;
status = "okay";
};
powerdown: powerdown-controller {
powerdown: powerdown-controller@0 {
compatible = "st,stih407-powerdown";
reg = <0 0>;
#reset-cells = <1>;
};
softreset: softreset-controller {
softreset: softreset-controller@0 {
compatible = "st,stih407-softreset";
reg = <0 0>;
#reset-cells = <1>;
};
picophyreset: picophyreset-controller {
picophyreset: picophyreset-controller@0 {
compatible = "st,stih407-picophyreset";
reg = <0 0>;
#reset-cells = <1>;
};
......@@ -174,6 +178,13 @@ syscfg_sbc_reg: fvdp-lite-syscfg@9600000 {
syscfg_core: core-syscfg@92b0000 {
compatible = "st,stih407-core-syscfg", "syscon";
reg = <0x92b0000 0x1000>;
sti_sasg_codec: sti-sasg-codec {
compatible = "st,stih407-sas-codec";
#sound-dai-cells = <1>;
status = "disabled";
st,syscfg = <&syscfg_core>;
};
};
syscfg_lpm: lpm-syscfg@94b5100 {
......@@ -181,8 +192,9 @@ syscfg_lpm: lpm-syscfg@94b5100 {
reg = <0x94b5100 0x1000>;
};
irq-syscfg {
irq-syscfg@0 {
compatible = "st,stih407-irq-syscfg";
reg = <0 0>;
st,syscfg = <&syscfg_core>;
st,irq-device = <ST_IRQ_SYSCFG_PMU_0>,
<ST_IRQ_SYSCFG_PMU_1>;
......@@ -380,8 +392,9 @@ i2c@9541000 {
status = "disabled";
};
usb2_picophy0: phy1 {
usb2_picophy0: phy1@0 {
compatible = "st,stih407-usb2-phy";
reg = <0 0>;
#phy-cells = <0>;
st,syscfg = <&syscfg_core 0x100 0xf4>;
resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
......@@ -389,12 +402,13 @@ usb2_picophy0: phy1 {
reset-names = "global", "port";
};
miphy28lp_phy: miphy28lp@9b22000 {
miphy28lp_phy: miphy28lp@0 {
compatible = "st,miphy28lp-phy";
st,syscfg = <&syscfg_core>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
reg = <0 0>;
phy_port0: port@9b22000 {
reg = <0x9b22000 0xff>,
......@@ -805,6 +819,7 @@ mailbox3: mailbox@8f03000 {
st231_gp0: st231-gp0@0 {
compatible = "st,st231-rproc";
reg = <0 0>;
memory-region = <&gp0_reserved>;
resets = <&softreset STIH407_ST231_GP0_SOFTRESET>;
reset-names = "sw_reset";
......@@ -818,6 +833,7 @@ st231_gp0: st231-gp0@0 {
st231_delta: st231-delta@0 {
compatible = "st,st231-rproc";
reg = <0 0>;
memory-region = <&delta_reserved>;
resets = <&softreset STIH407_ST231_DMU_SOFTRESET>;
reset-names = "sw_reset";
......@@ -885,13 +901,6 @@ fdma2: dma-controller@8e60000 {
status = "disabled";
};
sti_sasg_codec: sti-sasg-codec {
compatible = "st,stih407-sas-codec";
#sound-dai-cells = <1>;
status = "disabled";
st,syscfg = <&syscfg_core>;
};
sti_uni_player0: sti-uni-player@8d80000 {
compatible = "st,stih407-uni-player-hdmi";
#sound-dai-cells = <0>;
......@@ -980,8 +989,9 @@ sti_uni_reader1: sti-uni-reader@8d84000 {
status = "disabled";
};
delta0 {
delta0@0 {
compatible = "st,st-delta";
reg = <0 0>;
clock-names = "delta",
"delta-st231",
"delta-flash-promip";
......
arch/arm/boot/dts/stih407-pinctrl.dtsi
View file @ fbefc532
......@@ -45,7 +45,7 @@ aliases {
};
soc {
pin-controller-sbc {
pin-controller-sbc@961f080 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "st,stih407-sbc-pinctrl";
......@@ -369,7 +369,7 @@ st,pins {
};
};
pin-controller-front0 {
pin-controller-front0@920f080 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "st,stih407-front-pinctrl";
......@@ -929,7 +929,7 @@ st,pins {
};
};
pin-controller-front1 {
pin-controller-front1@921f080 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "st,stih407-front-pinctrl";
......@@ -962,7 +962,7 @@ st,pins {
};
};
pin-controller-rear {
pin-controller-rear@922f080 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "st,stih407-rear-pinctrl";
......@@ -1157,7 +1157,7 @@ st,pins {
};
};
pin-controller-flash {
pin-controller-flash@923f080 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "st,stih407-flash-pinctrl";
......
arch/arm/boot/dts/stih407.dtsi
View file @ fbefc532
......@@ -11,11 +11,11 @@
#include <dt-bindings/gpio/gpio.h>
/ {
soc {
sti-display-subsystem {
sti-display-subsystem@0 {
compatible = "st,sti-display-subsystem";
#address-cells = <1>;
#size-cells = <1>;
reg = <0 0>;
assigned-clocks = <&clk_s_d2_quadfs 0>,
<&clk_s_d2_quadfs 1>,
<&clk_s_c0_pll1 0>,
......
arch/arm/boot/dts/stih410-b2120.dts
View file @ fbefc532
......@@ -18,7 +18,7 @@ chosen {
linux,stdout-path = &sbc_serial0;
};
memory {
memory@40000000 {
device_type = "memory";
reg = <0x40000000 0x80000000>;
};
......@@ -37,11 +37,11 @@ mmc0: sdhci@9060000 {
sd-uhs-ddr50;
};
usb2_picophy1: phy2 {
usb2_picophy1: phy2@0 {
status = "okay";
};
usb2_picophy2: phy3 {
usb2_picophy2: phy3@0 {
status = "okay";
};
......@@ -61,7 +61,7 @@ ehci1: usb@9a83e00 {
status = "okay";
};
sti-display-subsystem {
sti-display-subsystem@0 {
sti-hda@8d02000 {
status = "okay";
};
......
arch/arm/boot/dts/stih410-b2260.dts
View file @ fbefc532
......@@ -19,7 +19,7 @@ chosen {
linux,stdout-path = &uart1;
};
memory {
memory@40000000 {
device_type = "memory";
reg = <0x40000000 0x40000000>;
};
......@@ -29,8 +29,6 @@ aliases {
ethernet0 = &ethernet0;
};
soc {
leds {
compatible = "gpio-leds";
user_green_1 {
......@@ -59,6 +57,26 @@ user_green_4 {
};
};
sound: sound {
compatible = "simple-audio-card";
simple-audio-card,name = "STI-B2260";
status = "okay";
simple-audio-card,dai-link0 {
/* DAC */
format = "i2s";
mclk-fs = <128>;
cpu {
sound-dai = <&sti_uni_player0>;
};
codec {
sound-dai = <&sti_hdmi>;
};
};
};
soc {
/* Low speed expansion connector */
uart0: serial@9830000 {
label = "LS-UART0";
......@@ -128,11 +146,11 @@ pwm1: pwm@9510000 {
status = "okay";
};
usb2_picophy1: phy2 {
usb2_picophy1: phy2@0 {
status = "okay";
};
usb2_picophy2: phy3 {
usb2_picophy2: phy3@0 {
status = "okay";
};
......@@ -182,26 +200,7 @@ hdmiddc: i2c@9541000 {
status = "okay";
};
sound {
compatible = "simple-audio-card";
simple-audio-card,name = "STI-B2260";
status = "okay";
simple-audio-card,dai-link@0 {
/* DAC */
format = "i2s";
mclk-fs = <128>;
cpu {
sound-dai = <&sti_uni_player0>;
};
codec {
sound-dai = <&sti_hdmi>;
};
};
};
miphy28lp_phy: miphy28lp@9b22000 {
miphy28lp_phy: miphy28lp@0 {
phy_port1: port@9b2a000 {
st,osc-force-ext;
......
arch/arm/boot/dts/stih410-clock.dtsi
View file @ fbefc532
......@@ -7,13 +7,6 @@
*/
#include <dt-bindings/clock/stih410-clks.h>
/ {
clocks {
#address-cells = <1>;
#size-cells = <1>;
ranges;
compatible = "st,stih410-clk", "simple-bus";
/*
* Fixed 30MHz oscillator inputs to SoC
*/
......@@ -24,17 +17,19 @@ clk_sysin: clk-sysin {
clock-output-names = "CLK_SYSIN";
};
/*
* ARM Peripheral clock for timers
*/
arm_periph_clk: clk-m-a9-periphs {
clk_tmdsout_hdmi: clk-tmdsout-hdmi {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&clk_m_a9>;
clock-div = <2>;
clock-mult = <1>;
compatible = "fixed-clock";
clock-frequency = <0>;
};
clocks {
#address-cells = <1>;
#size-cells = <1>;
ranges;
compatible = "st,stih410-clk", "simple-bus";
/*
* A9 PLL.
*/
......@@ -64,32 +59,16 @@ clk_m_a9: clk-m-a9@92b0000 {
<&clockgen_a9_pll 0>,
<&clk_s_c0_flexgen 13>,
<&clk_m_a9_ext2f_div2>;
};
/*
* ARM Peripheral clock for timers
*/
clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2s {
arm_periph_clk: clk-m-a9-periphs {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&clk_s_c0_flexgen 13>;
clock-output-names = "clk-m-a9-ext2f-div2";
clocks = <&clk_m_a9>;
clock-div = <2>;
clock-mult = <1>;
};
/*
* Bootloader initialized system infrastructure clock for
* serial devices.
*/
clk_ext2f_a9: clockgen-c0@13 {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <200000000>;
clock-output-names = "clk-s-icn-reg-0";
};
clockgen-a@90ff000 {
......@@ -214,6 +193,21 @@ clk_s_c0_flexgen: clk-s-c0-flexgen {
<CLK_EXT2F_A9>,
<CLK_ICN_LMI>,
<CLK_ICN_SBC>;
/*
* ARM Peripheral clock for timers
*/
clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2s {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&clk_s_c0_flexgen 13>;
clock-output-names = "clk-m-a9-ext2f-div2";
clock-div = <2>;
clock-mult = <1>;
};
};
};
......@@ -266,13 +260,7 @@ clk_s_d2_quadfs: clk-s-d2-quadfs@9106000 {
"clk-s-d2-fs0-ch3";
};
clk_tmdsout_hdmi: clk-tmdsout-hdmi {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <0>;
};
clockgen-d2@x9106000 {
clockgen-d2@9106000 {
compatible = "st,clkgen-c32";
reg = <0x9106000 0x1000>;
......
arch/arm/boot/dts/stih410-pinctrl.dtsi
View file @ fbefc532
......@@ -10,7 +10,7 @@
/ {
soc {
pin-controller-rear {
pin-controller-rear@922f080 {
usb0 {
pinctrl_usb0: usb2-0 {
......
arch/arm/boot/dts/stih410.dtsi
View file @ fbefc532
......@@ -16,8 +16,9 @@ aliases {
};
soc {
usb2_picophy1: phy2 {
usb2_picophy1: phy2@0 {
compatible = "st,stih407-usb2-phy";
reg = <0 0>;
#phy-cells = <0>;
st,syscfg = <&syscfg_core 0xf8 0xf4>;
resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
......@@ -27,8 +28,9 @@ usb2_picophy1: phy2 {
status = "disabled";
};
usb2_picophy2: phy3 {
usb2_picophy2: phy3@0 {
compatible = "st,stih407-usb2-phy";
reg = <0 0>;
#phy-cells = <0>;
st,syscfg = <&syscfg_core 0xfc 0xf4>;
resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
......@@ -102,11 +104,12 @@ ehci1: usb@9a83e00 {
status = "disabled";
};
sti-display-subsystem {
sti-display-subsystem@0 {
compatible = "st,sti-display-subsystem";
#address-cells = <1>;
#size-cells = <1>;
reg = <0 0>;
assigned-clocks = <&clk_s_d2_quadfs 0>,
<&clk_s_d2_quadfs 1>,
<&clk_s_c0_pll1 0>,
......@@ -235,7 +238,7 @@ sti-hda@8d02000 {
<&clk_s_d2_quadfs 1>;
};
sti-hqvdp@9c000000 {
sti-hqvdp@9c00000 {
compatible = "st,stih407-hqvdp";
reg = <0x9C00000 0x100000>;
clock-names = "hqvdp", "pix_main";
......@@ -273,7 +276,7 @@ thermal@91a0000 {
interrupts = <GIC_SPI 205 IRQ_TYPE_EDGE_RISING>;
};
delta0 {
delta0@0 {
compatible = "st,st-delta";
clock-names = "delta",
"delta-st231",
......
arch/arm/boot/dts/stih418-b2199.dts
View file @ fbefc532
......@@ -18,7 +18,7 @@ chosen {
linux,stdout-path = &sbc_serial0;
};
memory {
memory@40000000 {
device_type = "memory";
reg = <0x40000000 0xc0000000>;
};
......@@ -28,11 +28,6 @@ aliases {
ethernet0 = &ethernet0;
};
soc {
sbc_serial0: serial@9530000 {
status = "okay";
};
leds {
compatible = "gpio-leds";
red {
......@@ -46,6 +41,11 @@ green {
};
};
soc {
sbc_serial0: serial@9530000 {
status = "okay";
};
i2c@9842000 {
status = "okay";
};
......@@ -88,7 +88,7 @@ mmc0: sdhci@9060000 {
non-removable;
};
miphy28lp_phy: miphy28lp@9b22000 {
miphy28lp_phy: miphy28lp@0 {
phy_port0: port@9b22000 {
st,osc-rdy;
......
arch/arm/boot/dts/stih418-clock.dtsi
View file @ fbefc532
......@@ -7,13 +7,6 @@
*/
#include <dt-bindings/clock/stih418-clks.h>
/ {
clocks {
#address-cells = <1>;
#size-cells = <1>;
ranges;
compatible = "st,stih418-clk", "simple-bus";
/*
* Fixed 30MHz oscillator inputs to SoC
*/
......@@ -24,17 +17,19 @@ clk_sysin: clk-sysin {
clock-output-names = "CLK_SYSIN";
};
/*
* ARM Peripheral clock for timers
*/
arm_periph_clk: clk-m-a9-periphs {
clk_tmdsout_hdmi: clk-tmdsout-hdmi {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&clk_m_a9>;
clock-div = <2>;
clock-mult = <1>;
compatible = "fixed-clock";
clock-frequency = <0>;
};
clocks {
#address-cells = <1>;
#size-cells = <1>;
ranges;
compatible = "st,stih418-clk", "simple-bus";
/*
* A9 PLL.
*/
......@@ -64,32 +59,17 @@ clk_m_a9: clk-m-a9@92b0000 {
<&clockgen_a9_pll 0>,
<&clk_s_c0_flexgen 13>,
<&clk_m_a9_ext2f_div2>;
};
/*
* ARM Peripheral clock for timers
*/
clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2s {
arm_periph_clk: clk-m-a9-periphs {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&clk_s_c0_flexgen 13>;
clock-output-names = "clk-m-a9-ext2f-div2";
clocks = <&clk_m_a9>;
clock-div = <2>;
clock-mult = <1>;
};
/*
* Bootloader initialized system infrastructure clock for
* serial devices.
*/
clk_ext2f_a9: clockgen-c0@13 {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <200000000>;
clock-output-names = "clk-s-icn-reg-0";
};
clockgen-a@90ff000 {
......@@ -207,6 +187,21 @@ clk_s_c0_flexgen: clk-s-c0-flexgen {
"clk-proc-mixer",
"clk-proc-sc",
"clk-avsp-hevc";
/*
* ARM Peripheral clock for timers
*/
clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2s {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&clk_s_c0_flexgen 13>;
clock-output-names = "clk-m-a9-ext2f-div2";
clock-div = <2>;
clock-mult = <1>;
};
};
};
......@@ -259,13 +254,7 @@ clk_s_d2_quadfs: clk-s-d2-quadfs@9106000 {
"clk-s-d2-fs0-ch3";
};
clk_tmdsout_hdmi: clk-tmdsout-hdmi {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <0>;
};
clockgen-d2@x9106000 {
clockgen-d2@9106000 {
compatible = "st,clkgen-c32";
reg = <0x9106000 0x1000>;
......
arch/arm/boot/dts/stih418.dtsi
View file @ fbefc532
......@@ -30,8 +30,9 @@ cpu@3 {
};
soc {
usb2_picophy1: phy2 {
usb2_picophy1: phy2@0 {
compatible = "st,stih407-usb2-phy";
reg = <0 0>;
#phy-cells = <0>;
st,syscfg = <&syscfg_core 0xf8 0xf4>;
resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
......@@ -39,8 +40,9 @@ usb2_picophy1: phy2 {
reset-names = "global", "port";
};
usb2_picophy2: phy3 {
usb2_picophy2: phy3@0 {
compatible = "st,stih407-usb2-phy";
reg = <0 0>;
#phy-cells = <0>;
st,syscfg = <&syscfg_core 0xfc 0xf4>;
resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
......
arch/arm/boot/dts/stihxxx-b2120.dtsi
View file @ fbefc532
......@@ -10,11 +10,6 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/media/c8sectpfe.h>
/ {
soc {
sbc_serial0: serial@9530000 {
status = "okay";
};
leds {
compatible = "gpio-leds";
red {
......@@ -28,6 +23,57 @@ green {
};
};
sound: sound {
compatible = "simple-audio-card";
simple-audio-card,name = "STI-B2120";
status = "okay";
simple-audio-card,dai-link0 {
/* HDMI */
format = "i2s";
mclk-fs = <128>;
cpu {
sound-dai = <&sti_uni_player0>;
};
codec {
sound-dai = <&sti_hdmi>;
};
};
simple-audio-card,dai-link1 {
/* DAC */
format = "i2s";
mclk-fs = <256>;
frame-inversion = <1>;
cpu {
sound-dai = <&sti_uni_player2>;
};
codec {
sound-dai = <&sti_sasg_codec 1>;
};
};
simple-audio-card,dai-link2 {
/* SPDIF */
format = "left_j";
mclk-fs = <128>;
cpu {
sound-dai = <&sti_uni_player3>;
};
codec {
sound-dai = <&sti_sasg_codec 0>;
};
};
};
soc {
sbc_serial0: serial@9530000 {
status = "okay";
};
pwm0: pwm@9810000 {
status = "okay";
};
......@@ -80,7 +126,7 @@ hdmiddc: i2c@9541000 {
st,i2c-min-sda-pulse-width-us = <5>;
};
miphy28lp_phy: miphy28lp@9b22000 {
miphy28lp_phy: miphy28lp@0 {
phy_port0: port@9b22000 {
st,osc-rdy;
......@@ -126,7 +172,7 @@ demux@8a20000 {
clock-names = "c8sectpfe";
/* tsin0 is TSA on NIMA */
tsin0: port@0 {
tsin0: port {
tsin-num = <0>;
serial-not-parallel;
i2c-bus = <&ssc2>;
......@@ -147,54 +193,12 @@ sti_uni_player3: sti-uni-player@8d85000 {
status = "okay";
};
syscfg_core: core-syscfg@92b0000 {
sti_sasg_codec: sti-sasg-codec {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spdif_out>;
};
sound {
compatible = "simple-audio-card";
simple-audio-card,name = "STI-B2120";
status = "okay";
simple-audio-card,dai-link@0 {
/* HDMI */
format = "i2s";
mclk-fs = <128>;
cpu {
sound-dai = <&sti_uni_player0>;
};
codec {
sound-dai = <&sti_hdmi>;
};
};
simple-audio-card,dai-link@1 {
/* DAC */
format = "i2s";
mclk-fs = <256>;
frame-inversion = <1>;
cpu {
sound-dai = <&sti_uni_player2>;
};
codec {
sound-dai = <&sti_sasg_codec 1>;
};
};
simple-audio-card,dai-link@2 {
/* SPDIF */
format = "left_j";
mclk-fs = <128>;
cpu {
sound-dai = <&sti_uni_player3>;
};
codec {
sound-dai = <&sti_sasg_codec 0>;
};
};
};
};
};
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