- 21 Dec, 2015 2 commits
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Alex Deucher authored
Need to properly handle the max link rate in the dpcd. This prevents some cases where 5.4 Ghz is selected when it shouldn't be. v2: simplify logic, add array bounds check Reviewed-by:
Tom St Denis <tom.stdenis@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
Need to properly handle the max link rate in the dpcd. This prevents some cases where 5.4 Ghz is selected when it shouldn't be. v2: simplify logic, add array bounds check Reviewed-by:
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- 18 Dec, 2015 10 commits
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Nicolai Hähnle authored
In the rare situation where the kmalloc fails we're probably screwed anyway, but let's try to be more robust about it. Reviewed-by:
Michel Dänzer <michel.daenzer@amd.com> Signed-off-by:
Nicolai Hähnle <Nicolai.Haehnle@amd.com> Signed-off-by:
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Nicolai Hähnle authored
v2: agd: clarify commit message, fix "an" as spotted by Michel. Reviewed-by:
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Nicolai Hähnle authored
Previously, the comment was inconsistent. EDEADLK is what the ww_mutex mechanism really returns. Signed-off-by:
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Thierry Reding authored
Commit 88e72717 ("drm/irq: Use unsigned int pipe in public API") updated the prototype of this function but not the implementation. This wasn't noticed even through compile tests because the prototype is part of the source file that uses it and hence the compiler won't know the prototype when it compiles the implementation. The right thing would've been to move the prototype to a header that's included in radeon_kms.c so that the implementation signature could be checked against it, but the closest thing would've been radeon_drv.h and including that results in a lot of build errors, so we'll leave it as is for now. Cc: Christian König <christian.koenig@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
Thierry Reding <treding@nvidia.com> Signed-off-by:
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Mario Kleiner authored
commit 4dfd6486 "drm: Use vblank timestamps to guesstimate how many vblanks were missed" introduced in Linux 4.4-rc1 makes the drm core more fragile to drivers which don't update hw vblank counters and vblank timestamps in sync with firing of the vblank irq and essentially at leading edge of vblank. This exposed a problem with radeon-kms/amdgpu-kms which do not satisfy above requirements: The vblank irq fires a few scanlines before start of vblank, but programmed pageflips complete at start of vblank and vblank timestamps update at start of vblank, whereas the hw vblank counter increments only later, at start of vsync. This leads to problems like off by one errors for vblank counter updates, vblank counters apparently going backwards or vblank timestamps apparently having time going backwards. The net result is stuttering of graphics in games, or little hangs, as well as total failure of timing sensitive applications. See bug #93147 for an example of the regression on Linux 4.4-rc: https://bugs.freedesktop.org/show_bug.cgi?id=93147 This patch tries to align all above events better from the viewpoint of the drm core / of external callers to fix the problem: 1. The apparent start of vblank is shifted a few scanlines earlier, so the vblank irq now always happens after start of this extended vblank interval and thereby drm_update_vblank_count() always samples the updated vblank count and timestamp of the new vblank interval. To achieve this, the reporting of scanout positions by radeon_get_crtc_scanoutpos() now operates as if the vblank starts radeon_crtc->lb_vblank_lead_lines before the real start of the hw vblank interval. This means that the vblank timestamps which are based on these scanout positions will now update at this earlier start of vblank. 2. The driver->get_vblank_counter() function will bump the returned vblank count as read from the hw by +1 if the query happens after the shifted earlier start of the vblank, but before the real hw increment at start of vsync, so the counter appears to increment at start of vblank in sync with the timestamp update. 3. Calls from vblank irq-context and regular non-irq calls are now treated identical, always simulating the shifted vblank start, to avoid inconsistent results for queries happening from vblank irq vs. happening from drm_vblank_enable() or vblank_disable_fn(). 4. The radeon_flip_work_func will delay mmio programming a pageflip until the start of the real vblank iff it happens to execute inside the shifted earlier start of the vblank, so pageflips now also appear to execute at start of the shifted vblank, in sync with vblank counter and timestamp updates. This to avoid some races between updates of vblank count and timestamps that are used for swap scheduling and pageflip execution which could cause pageflips to execute before the scheduled target vblank. The lb_vblank_lead_lines "fudge" value is calculated as the size of the display controllers line buffer in scanlines for the given video mode: Vblank irq's are triggered by the line buffer logic when the line buffer refill for a video frame ends, ie. when the line buffer source read position enters the hw vblank. This means that a vblank irq could fire at most as many scanlines before the current reported scanout position of the crtc timing generator as the number of scanlines the line buffer can maximally hold for a given video mode. This patch has been successfully tested on a RV730 card with DCE-3 display engine and on a evergreen card with DCE-4 display engine, in single-display and dual-display configuration, with different video modes. A similar patch is needed for amdgpu-kms to fix the same problem. Limitations: - Line buffer sizes in pixels are hard-coded on < DCE-4 to a value i just guessed to be high enough to work ok, lacking info on the true sizes atm. Fixes: fdo#93147 Signed-off-by:
Mario Kleiner <mario.kleiner.de@gmail.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Michel Dänzer <michel.daenzer@amd.com> Cc: Harry Wentland <Harry.Wentland@amd.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> (v1) Tested-by: Dave Witbrodt <dawitbro@sbcglobal.net> (v2) Refine radeon_flip_work_func() for better efficiency: In radeon_flip_work_func, replace the busy waiting udelay(5) with event lock held by a more performance and energy efficient usleep_range() until at least predicted true start of hw vblank, with some slack for scheduler happiness. Release the event lock during waits to not delay other outputs in doing their stuff, as the waiting can last up to 200 usecs in some cases. Retested on DCE-3 and DCE-4 to verify it still works nicely. (v2) Signed-off-by: Mario Kleiner <mario.kleiner.de@gmail.com> Signed-off-by:
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Slava Grigorev authored
DP audio is derived from the dfs clock. Signed-off-by:
Slava Grigorev <slava.grigorev@amd.com> Reviewed-by:
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Christian König authored
This avoids allocating it on the fly. v2: fix grammar in comment Signed-off-by:
Chunming Zhou <david1.zhou@amd.com>
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Christian König authored
This way we avoid the extra allocation for the page directory entry. Signed-off-by:
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Christian König authored
They share the reservation object with the page directory anyway. Signed-off-by:
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Chunming Zhou authored
Signed-off-by:
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- 17 Dec, 2015 1 commit
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Alex Deucher authored
In some cases the amount of vram may be less than the BAR size, if so, limit visible vram to the amount of actual vram, not the BAR size. Reviewed-by:
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- 15 Dec, 2015 4 commits
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Chunming Zhou authored
Change the default scheduler queue size from 16 to 32. Signed-off-by:
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Chunming Zhou authored
Signed-off-by:
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Chunming Zhou authored
Properly handle ctx init failure. Signed-off-by:
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Chunming Zhou authored
umd somtimes will create a context for every ring, that means some entities wouldn't be used at all. Signed-off-by:
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- 11 Dec, 2015 4 commits
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Alex Deucher authored
Add more fine grained debugging output for init/fini/suspend/ resume failures. Signed-off-by: -
Flora Cui authored
Change-Id: I2ae9bb4a929f7c0c8783e0be563ae04be77596e2 Signed-off-by:
Flora Cui <Flora.Cui@amd.com> Reviewed-by:
Jammy Zhou <Jammy.Zhou@amd.com> Reviewed-by:
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Flora Cui authored
Use default value as a base. Signed-off-by:
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Flora Cui authored
Otherwise FW cannot see the RLC ACK for the memory clean request It's for Stoney. Signed-off-by:
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- 04 Dec, 2015 7 commits
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jimqu authored
there is a protection fault about freed list when OCL test. add a spin lock to protect it. v2: drop changes in vm_fini Signed-off-by:
JimQu <jim.qu@amd.com> Reviewed-by:
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Tom St Denis authored
Signed-off-by:
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Nicolai Hähnle authored
As soon as we leave the spinlock after the job has been added to the job queue, we can no longer rely on the job's data to be available. I have seen a null-pointer dereference due to sched == NULL in amd_sched_wakeup via amd_sched_entity_push_job and amd_sched_ib_submit_kernel_helper. Since the latter initializes sched_job->sched with the address of the ring scheduler, which is guaranteed to be non-NULL, this race appears to be a likely culprit. Signed-off-by:
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Chunming Zhou authored
Missing error check if the operation failed. Signed-off-by:
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Tom St Denis authored
Simplified the function by folding the two paths into one. Signed-off-by:
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Tom St Denis authored
Simplification of the function gfx_v8_0_create_bitmask(). Signed-off-by:
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Tom St Denis authored
Simplification and LOC reduction of function gfx_v8_0_tiling_mode_table_init() v2: remove spurious break bug: https://bugs.freedesktop.org/show_bug.cgi?id=93236Signed-off-by:
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- 02 Dec, 2015 12 commits
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Tom St Denis authored
Signed-off-by:
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Chunming Zhou authored
Allows us to set priorities in the scheduler. Signed-off-by:
Junwei Zhang <Jerry.Zhang@amd.com>
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Alex Deucher authored
This adds EDC support for CZ. EDC = Error Correction and Detection This code properly initializes the EDC hardware and resets the error counts. This is done in late_init since it requires the IB pool which is not initialized during hw_init. v2: fix the IB size as noted by Felix, fix shader pgm register programming v3: use the IB for the shaders as suggested by Christian Reviewed-by:
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Alex Deucher authored
EDC is a RAS feature for on chip memory. Reviewed-by:
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Daniel Vetter authored
For drm_gem_object_unreference callers are required to hold dev->struct_mutex, which these paths don't. Enforcing this requirement has become a bit more strict with commit ef4c6270 Author: Daniel Vetter <daniel.vetter@ffwll.ch> Date: Thu Oct 15 09:36:25 2015 +0200 drm/gem: Check locking in drm_gem_object_unreference Cc: Alex Deucher <alexander.deucher@amd.com> Reviewed-by:
Daniel Vetter <daniel.vetter@intel.com> Signed-off-by:
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Daniel Vetter authored
For drm_gem_object_unreference callers are required to hold dev->struct_mutex, which these paths don't. Enforcing this requirement has become a bit more strict with commit ef4c6270 Author: Daniel Vetter <daniel.vetter@ffwll.ch> Date: Thu Oct 15 09:36:25 2015 +0200 drm/gem: Check locking in drm_gem_object_unreference Cc: Alex Deucher <alexander.deucher@amd.com> Reviewed-by:
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monk.liu authored
Read the vbios directly from the rom. In some cases, e.g., virtualization, the rom is not available via the BAR or other means. Access it directly. This is an updated version of Monks original patch which uses family specific callbacks and unifies some of the validation checking. Reviewed-by:
Monk Liu <Monk.Liu@amd.com> Signed-off-by:
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Alex Deucher authored
Read the vbios image directly from the rom. Reviewed-by:
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Alex Deucher authored
Read the vbios image directly from the rom. Reviewed-by:
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Alex Deucher authored
This is necessary when the vbios image is not directly accessible via the rom BAR or legacy vga location. Reviewed-by:
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Julia Lawall authored
The radeon_asic_ring structures are never modified, so declare them as const. Done with the help of Coccinelle. Reviewed-by:
Julia Lawall <Julia.Lawall@lip6.fr> Signed-off-by:
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Jammy Zhou authored
This can solve the path problem when compile amdgpu with DKMS. v2: agd: rebase on current drm-next Signed-off-by:
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