- 17 Dec, 2018 40 commits
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Linus Walleij authored
This adds GPIO descriptor look-up tables for a whole bunch of PXA boards with MMC card detect (CD) and write protect (WP) GPIO lines, so we can move away from the hard-coded GPIO numberspace. In some cases the platforms were compulsively including the <linux/gpio.h> header even if they weren't actually using it, and in these cases I simply replaced that inclusion with the more appropriate <linux/gpio/machine.h> which is what board files should be including most of the time. Cc: Daniel Mack <daniel@zonque.org> Cc: Robert Jarzmik <robert.jarzmik@free.fr> Cc: Bartosz Golaszewski <brgl@bgdev.pl> Cc: Andrea Adami <andrea.adami@gmail.com> Signed-off-by:
Linus Walleij <linus.walleij@linaro.org> Acked-by:
Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by:
Ulf Hansson <ulf.hansson@linaro.org>
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Linus Walleij authored
Instead of using the name directly from the I2C client to name the gpio_chip, use dev_name() on the client->dev, so we get the sometimes more unique device name, as I2C has a mechanism for naming its devices explicitly in e.g. board data. This is a prerequisite for being able to reference uniquely any I2C GPIO expander defined in a board file when setting up GPIO descriptor tables. Reviewed-by:
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Linus Walleij authored
Simplify things by making the S3CMCI driver just use slot GPIO with descriptors instead of passing around the global GPIO numbers that we want to get rid of. Getting the names of the GPIO chips into the machine descriptor tables was a bit of a challenge but I think I have them right. The platform data supports passing in inversion flags, but no platform is using them, and it is highly unlikely that we will add more, so drop them. The long term plan is to let the inversion flags on the GPIO machine descriptor do the job. The lines are flagged as GPIO_ACTIVE_[LOW|HIGH] as that is what they are, and since we can now rely on the descriptors to have the right polarity, we set the "override_active_level" to false in mmc_gpiod_request_cd() and mmc_gpiod_request_ro(). Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Sylwester Nawrocki <s.nawrocki@samsung.com> Cc: Sergio Prado <sergio.prado@e-labworks.com> Reviewed-by:
Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by:
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Linus Walleij authored
The TMIO MMC driver was passing global GPIO numbers around for card detect. It turns out only one single board in the kernel was actually making use of this feature so it is pretty easy to convert the driver to use only GPIO descriptors. The lines are flagged as GPIO_ACTIVE_[LOW|HIGH] as that is what they are, and since we can now rely on the descriptors to have the right polarity, we set the "override_active_level" to false in mmc_gpiod_request_cd() and mmc_gpiod_request_ro(). Reviewed-by:
Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Acked-by:
Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by:
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Linus Walleij authored
Switch the SPI MMC driver to use GPIO descriptors internally and just look those up using the standard slot GPIO functions mmc_gpiod_request_cd() and mmc_gpiod_request_ro(). Make sure to request index 0 and 1 in accordance with the SPI MMC DT binding, and add the same GPIOs in machine descriptor tables on all boards that use SPI MMC in board files. The lines are flagged as GPIO_ACTIVE_[LOW|HIGH] as that is what they are, and since we can now rely on the descriptors to have the right polarity, we set the "override_active_level" to false in mmc_gpiod_request_cd() and mmc_gpiod_request_ro(). Cc: Hartley Sweeten <hsweeten@visionengravers.com> # Vision EP9307 Cc: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Reviewed-by:
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Nicholas Mc Guire authored
devm_kasprintf() may return NULL on failure of internal allocation thus the assignments to init.name are not safe if not checked. On error meson_mx_mmc_register_clks() returns negative values so -ENOMEM in the (unlikely) failure case of devm_kasprintf() should be fine here. Signed-off-by:
Nicholas Mc Guire <hofrat@osadl.org> Fixes: ed80a13b ("mmc: meson-mx-sdio: Add a driver for the Amlogic Meson8 and Meson8b SoCs") Acked-by:
Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by:
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Yangbo Lu authored
This was a SoC issue on LX2160A Rev1.0. eSDHC_DLLCFG1[DLL_PD_PULSE_STRETCH_SEL] must be set to 0 to get 4 delay cells in the pulse width detection logic for eMMC HS400 mode. Otherwise it would cause unexpected HS400 issue. This patch is to clear this bit always for affected SoC when reset for all, since this bit doesn't affect other speed modes. Signed-off-by:
Yangbo Lu <yangbo.lu@nxp.com> Signed-off-by:
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Yangbo Lu authored
Currently only LX2160A eSDHC supports eMMC HS400. According to a large number of tests, eMMC HS400 failed to work at 150MHz, and for a few boards failed to work at 175MHz. But eMMC HS400 worked fine on 200MHz. We hadn't found the root cause but setting eSDHC_DLLCFG0[DLL_FREQ_SEL] = 0 using slow delay chain seemed to resovle this issue. Let's use this as fixup for now. Signed-off-by:
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Yangbo Lu authored
There are timing violations in case of few division ratio options are selected for card clock frequency. prescaler*divisor options /3,/5,/6,/7,/9,/10,/11,/13,/14 and /15 are not available in LX2 Rev1.0. prescaler*divisor options /4,/8 and /12 only available in LX2 Rev1.0. Applicable only for HS400 mode. so by add the erratum A011334 support to limit the prescaler*divisor in LX2 REV1.0 Signed-off-by:
Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by:
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Yangbo Lu authored
1. Perform the Tuning Process at the HS400 target operating frequency. Latched the clock division value. 2. if read transaction, then set the SDTIMNGCTL[FLW_CTL_BG]. 3. Switch to High Speed mode and then set the card clock frequency to a value not greater than 52Mhz 4. Clear TBCTL[TB_EN],tuning block enable bit. 5. Change to 8 bit DDR Mode 6. Switch the card to HS400 mode. 7. Set TBCTL[TB_EN], tuning block enable bit. 8. Clear SYSCTL[SDCLKEN] 9. Wait for PRSSTAT[SDSTB] to be set 10. Change the clock division to latched value.Set TBCTL[HS 400 mode] and Set SDCLKCTL[CMD_CLK_CTRL] 11. Set SYSCTL[SDCLKEN] 12. Wait for PRSSTAT[SDSTB] to be set 13. Set DLLCFG0[DLL_ENABLE] and DLLCFG0[DLL_FREQ_SEL]. 14. Wait for delay chain to lock. 15. Set TBCTL[HS400_WNDW_ADJUST] 16. Again clear SYSCTL[SDCLKEN] 17. Wait for PRSSTAT[SDSTB] to be set 18. Set ESDHCCTL[FAF] 19. Wait for ESDHCCTL[FAF] to be cleared 20. Set SYSCTL[SDCLKEN] 21. Wait for PRSSTAT[SDSTB] to be set. Signed-off-by: -
Yinbo Zhu authored
Some eMMC controllers need specific settings for HS400 mode before the speed mode can be switched to DDR mode, during the HS400 initialization sequence. For that reason, let's introduce a new host callback, ->hs400_prepare_ddr() and invoked it just before switching to DDR mode. Signed-off-by:
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Faiz Abbas authored
The sdhci_execute_tuning() function has assignment of private pointers multiple times. Remove the redundant assignment. Acked-by:
Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by:
Faiz Abbas <faiz_abbas@ti.com> Acked-by:
Adrian Hunter <adrian.hunter@intel.com> Signed-off-by:
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Faiz Abbas authored
The TRM (SPRUIC2C - January 2017 - Revised May 2018 [1]) forbids assertion of data reset while tuning is happening. Implement a platform specific callback that takes care of this condition. [1] http://www.ti.com/lit/pdf/spruic2 Section 25.5.1.2.4 Acked-by:
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Ezequiel Garcia authored
As reported by Aaro, the JZ4740 MMC driver throws a warning when the kernel is built without preemption (CONFIG_PREEMPT_NONE=y). [ 16.461094] jz4740-mmc 13450000.mmc: [jz4740_mmc_prepare_dma_data] invalid cookie: data->host_cookie 567 host->next_data.cookie 568 [ 16.473120] jz4740-mmc 13450000.mmc: [jz4740_mmc_prepare_dma_data] invalid cookie: data->host_cookie 568 host->next_data.cookie 569 [ 16.485144] jz4740-mmc 13450000.mmc: [jz4740_mmc_prepare_dma_data] invalid cookie: data->host_cookie 569 host->next_data.cookie 570 [ 16.497170] jz4740-mmc 13450000.mmc: [jz4740_mmc_prepare_dma_data] invalid cookie: data->host_cookie 570 host->next_data.cookie 571 The problem seems to be related to how pre_req/post_req is implemented. Currently, it seems the driver expects jz4740_mmc_prepare_dma_data() to be called with monotonically increasing host_cookie values, which is wrong. Moreover, the implementation is overly complicated, keeping track of unneeded "next cookie" state. So, instead of attempting to fix the current pre_req/post_req implementation, this commit refactors the driver, dropping the state, following other drivers such as dw_mmc and sdhci. Cc: Paul Cercueil <paul@crapouillou.net> Cc: Mathieu Malaterre <malat@debian.org> Reported-by:
Aaro Koskinen <aaro.koskinen@iki.fi> Signed-off-by:
Ezequiel Garcia <ezequiel@collabora.com> Tested-by:
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Ludovic Barre authored
Refer to "4.15 set block count command" of sd specification: Host needs to issue CMD12 if any error is detected in the CMD18 and CMD25 operations. In sbc case, the data->stop is fill by framework. Signed-off-by:
Ludovic Barre <ludovic.barre@st.com> Tested-by:
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Wolfram Sang authored
If we use it this way, people should know about it. Also, replace true/false with nonzero/zero because the flag is not strictly a bool anymore. Signed-off-by:
Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by:
Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by:
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Wolfram Sang authored
Some variants (namely Renesas SDHI) have bits in the STATS and IRQ_MASK registers which are 'always 1' and should be written as such. Introduce a seperate mask for this and apply it whenever such a register is written. Signed-off-by:
Simon Horman <horms+renesas@verge.net.au> Reviewed-by:
Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Signed-off-by:
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Niklas Söderlund authored
The Renesas BSP confirms that H3 ES1.x and M3-W ES1.[012] do not properly support HS400. Add a quirk to indicate this and disable HS400 in the MMC capabilities if the quirk is set. Signed-off-by:
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Niklas Söderlund authored
It was though all ES revisions of H3 and M3-W SoCs required the TMIO_MMC_HAVE_4TAP_HS400 flag. Recent datasheet updates tells us this is not true, only early ES revisions of the SoC do. Since quirk matching based on ES revisions is now used to handle the flag it's possible to align all Gen3 compatibility properties. This will allow later ES revisions of H3 and M3-W to use the correct 8-tap HS400 mode. Signed-off-by:
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Niklas Söderlund authored
Latest datasheet makes it clear that not all ES revisions of the H3 and M3-W have the 4-tap HS400 mode quirk, currently the quirk is set unconditionally for these two SoCs. Prepare to handle the quirk based on SoC revision instead of compatibility value by using soc_device_match() and set the TMIO_MMC_HAVE_4TAP_HS400 flag explicitly. The reason for adding a new quirks struct instead of just a flag is that looking ahead it seems more quirks needs to be handled in a SoC revision basis. Signed-off-by:
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Niklas Söderlund authored
The initial value of the interrupt mask register may be different from the H/W manual at the startup of the kernel by setting from the bootloader. Since the error interrupts may be unmasked, the driver sets initial value. The initial value is only known for R-Car Gen2 and Gen3 platforms so limit the initialization to those platforms. Based on work from Masaharu Hayakawa. Signed-off-by:
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Niklas Söderlund authored
SD / MMC did not operate properly when suspend transition failed. Because the SCC was not reset at resume, issue of the command failed. Call the host specific reset function and reset the hardware in order to add reset of SCC. This change also fixes tuning on some stubborn cards on Gen2. Based on work from Masaharu Hayakawa. Signed-off-by:
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Niklas Söderlund authored
On runtime power management resume, the host clock needs to be enabled before calling tmio_mmc_reset. If the mmc device has a power domain entry, the host clock is enabled via genpd_runtime_resume, running before tmio_mmc_host_runtime_resume. If the mmc device has no power domain entry, however, genpd_runtime_resume is not called. This patch changes tmio_mmc_host_runtime_resume to enable the host clock before calling tmio_mmc_reset. Based on work from Masaharu Hayakawa. Signed-off-by:
Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by:
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Wolfram Sang authored
The only user was converted to fill a sbc command which is the proper way to do it because of AutoCMD23 feature of some hosts. Signed-off-by:
Clément Péron <peron.clem@gmail.com> Reviewed-by:
Avri Altman <avri.altman@wdc.com> Reviewed-by:
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Stefan Wahren authored
In case dmaengine_prep_slave_sg fails we need to call dma_unmap_sg. Signed-off-by:
Stefan Wahren <stefan.wahren@i2se.com> Acked-by:
Eric Anholt <eric@anholt.net> Signed-off-by:
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Stefan Wahren authored
There are two variables len within bcm2835_prepare_dma. So rename the result of dma_map_sg to sg_len. While we are at this add a bail out to simplify the following change. Signed-off-by:
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Stefan Wahren authored
It's better to make sure that the timeout work is really terminated before calling mmc_request_done. Signed-off-by:
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Stefan Wahren authored
There are two accesses on the data requests which are not protected by the mutex. So fix this accordingly. Signed-off-by:
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Stefan Wahren authored
We need to release the slave DMA channel during driver unload. Signed-off-by:
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Phil Elwell authored
If the user issues an "mmc extcsd read", the SD controller receives what it thinks is a SEND_IF_COND command with an unexpected data block. The resulting operations leave the FSM stuck in READWAIT, a state which persists until the MMC framework resets the controller, by which point the root filesystem is likely to have been unmounted. A less heavyweight solution is to detect the condition and nudge the FSM by asserting the (self-clearing) FORCE_DATA_MODE bit. Link: https://github.com/raspberrypi/linux/issues/2728Signed-off-by:
Phil Elwell <phil@raspberrypi.org> Signed-off-by:
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Michal Suchanek authored
The bcm2835 mmc host tends to lock up for unknown reason so reset it on timeout. The upper mmc block layer tries retransimitting with single blocks which tends to work out after a long wait. This is better than giving up and leaving the machine broken for no obvious reason. Fixes: 660fc733 ("mmc: bcm2835: Add new driver for the sdhost controller.") Signed-off-by:
Michal Suchanek <msuchanek@suse.de> Signed-off-by:
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Linus Walleij authored
Simplify things by making the i.MX SDHCI driver just use slot GPIO with descriptors instead of passing around the global GPIO numbers that we want to get rid of. As it turns out, just one single board is using the platform data to pass in GPIOs numbers for CD and WP, so we augment this to use a machine descriptor table instead. Cc: Shawn Guo <shawnguo@kernel.org> Cc: Sascha Hauer <s.hauer@pengutronix.de> Cc: Pengutronix Kernel Team <kernel@pengutronix.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: NXP Linux Team <linux-imx@nxp.com> Cc: Bartosz Golaszewski <brgl@bgdev.pl> Signed-off-by:
Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by:
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Linus Walleij authored
The power GPIO line is passed with inversion flags and all from the platform data. Switch to using an optional GPIO descriptor and use this to switch the power. Augment the only boardfile to pass in the proper "power" descriptor in the GPIO descriptor machine table instead. As the GPIO handling is now much simpler, we can cut down on some overhead code. Cc: Paul Cercueil <paul@crapouillou.net> Cc: linux-mips@linux-mips.org Signed-off-by:
Paul Burton <paul.burton@mips.com> Signed-off-by:
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Linus Walleij authored
Modifty the JZ4740 driver to retrieve card detect and write protect GPIO pins from GPIO descriptors instead of hard-coded global numbers. Augment the only board file using this in the process and cut down on passed in platform data. Preserve the code setting the caps2 flags for CD and WP as active low or high since the slot GPIO code currently ignores the gpiolib polarity inversion semantice and uses the raw accessors to read the GPIO lines, but set the right polarity flags in the descriptor table for jz4740. Cc: Paul Cercueil <paul@crapouillou.net> Cc: linux-mips@linux-mips.org Signed-off-by:
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Linus Walleij authored
The use of string pointers in the MMC slot GPIO context is pretty dubious, allocating some 2*len extra bytes for each label of the ro and wp pins. Tidy this up using kasprintf() with dynamic allocation of labels for these strings. Signed-off-by:
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Veerabhadrarao Badiganti authored
On few SDHCI-MSM controllers, the host controller's clock tuning circuit may go out of sync if controller clocks are gated which eventually will result in data CRC, command CRC/timeout errors. To overcome this h/w limitation, the DLL needs to be re-initialized and restored with its old settings once clocks are ungated. Signed-off-by:
Veerabhadrarao Badiganti <vbadigan@codeaurora.org> Reviewed-by:
Evan Green <evgreen@chromium.org> Signed-off-by:
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Veerabhadrarao Badiganti authored
Add SoC-specific compatible strings for qcom-sdhci controller. Signed-off-by:
Rob Herring <robh@kernel.org> Signed-off-by:
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Adrian Hunter authored
If the host controller supports auto-commands then enable the auto-command error interrupt and handle it. In the case of auto-CMD23, the error is treated the same as manual CMD23 error. In the case of auto-CMD12, commands-during-transfer are not permitted, so the error handling is treated the same as a data error. Signed-off-by:
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Adrian Hunter authored
The SDHCI_ACMD12_ERR register is used for auto-CMD23 and auto-CMD12 errors, as is the SDHCI_INT_ACMD12ERR interrupt bit. Rename them to SDHCI_AUTO_CMD_STATUS and SDHCI_INT_AUTO_CMD_ERR respectively. Signed-off-by:
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Adrian Hunter authored
Existing data command CRC error handling is non-standard and does not work with some Intel host controllers. Specifically, the assumption that the host controller will continue operating normally after the error interrupt, is not valid. Change the driver to handle the error in the same manner as a data CRC error, taking care to ensure that the data line reset is done for single or multi-block transfers, and it is done before unmapping DMA. Signed-off-by:
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