- 04 Oct, 2017 21 commits
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Chris Wilson authored
Move the re-enabling of MI arbitration from a per-bb w/a buffer to the emission of the batch buffer itself. Signed-off-by:
Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by:
Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20171003203453.15692-5-chris@chris-wilson.co.uk
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Chris Wilson authored
Add another perma-pinned context for using for preemption at any time. We cannot just reuse the existing kernel context, as first and foremost we need to ensure that we can preempt the kernel context itself, so require a distinct context id. Similar to the kernel context, we may want to interrupt execution and switch to the preempt context at any time, and so it needs to be permanently pinned and available. To compensate for yet another permanent allocation, we shrink the existing context and the new context by reducing their ringbuffer to the minimum. v2: Assert that we never allocate a request from the preemption context. v3: Limit perma-pin to engines that may preempt. v4: Onion cleanup for early driver death v5: Onion ordering in main driver cleanup as well. Signed-off-by:
Michał Winiarski <michal.winiarski@intel.com> Reviewed-by:
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Chris Wilson authored
Let the listener know that the context we just scheduled out was not complete, and will be scheduled back in at a later point. v2: Handle CONTEXT_STATUS_PREEMPTED in gvt by aliasing it to CONTEXT_STATUS_OUT for the moment, gvt can expand upon the difference later. Signed-off-by:
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Michał Winiarski authored
Supporting fine-granularity preemption levels may require changes in userspace batch buffer programming. Therefore, we need to fallback to safe default values, rather that use hardware defaults. Userspace is still able to enable fine-granularity, since we're whitelisting the register controlling it in WaEnablePreemptionGranularityControlByUMD. v2: Extend w/a to cover Cannonlake v3: Fix commentary to include both fake w/a names. Signed-off-by:
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Jeff McGee authored
The WA applies to all production Gen9 and requires both enabling and whitelisting of the per-context preemption control register. v2: Extend to Cannonlake. Signed-off-by:
Jeff McGee <jeff.mcgee@intel.com> Signed-off-by:
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Michal Wajdeczko authored
We don't want to make aggregate uc functions to be too detailed. This will also make future patch easier. Signed-off-by:
Michal Wajdeczko <michal.wajdeczko@intel.com> Cc: Sagar Arun Kamble <sagar.a.kamble@intel.com> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Reviewed-by:
Sagar Arun Kamble <sagar.a.kamble@intel.com> Reviewed-by:
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Michal Wajdeczko authored
We want to keep each uC specific code in separate files. Signed-off-by:
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Michal Wajdeczko authored
This is a prerequisite to unblock next steps. v2: correct include order (Joonas) v3: use common function prefix (Joonas) add kerneldoc (Michal) Signed-off-by: -
Sagar Arun Kamble authored
This patch adds new function intel_uc_init_mmio which will initialize MMIO access related variables prior to uc load/init. v2: Removed unnecessary export of guc_send_init_regs. Created intel_uc_init_mmio that currently wraps guc_init_send_regs. (Michal) v3 (Michal): add kerneldoc (Joonas) Signed-off-by:
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Michal Wajdeczko authored
We don't need it here. Signed-off-by:
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Michal Wajdeczko authored
We're trying to resolve inter-header dependencies. Signed-off-by:
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Chris Wilson authored
trace_i915_gem_evict_everything and trace_i915_gem_ring_flush stopped being used when their parent functions were removed. Signed-off-by:
Tvrtko Ursulin <tvrtko.ursulin@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20171003125055.11370-2-chris@chris-wilson.co.uk
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Chris Wilson authored
The tracepoints need some tlc, in particular we've neglected to update them for the 64b era. v2: Prefix hexadecimal output with 0x. Signed-off-by:
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Chris Wilson authored
These macros are of dubious merit when coupled with the per-context w/a set. Instead of tweaking the value in the context, they tweak the value based on the mmio at the time of recording; they are almost by definition not per-context! Having removed the last users, remove the macros to avoid temptation in the future. v2: Kill WA_WRITE as well (now also unused). Signed-off-by:
Mika Kuoppala <mika.kuoppala@linux.intel.com>
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Chris Wilson authored
Looking at gem_workarounds shows us that MMCD_MISC_CTRL is not restored following a suspend-resume cycle. This implies that MMCD_MISC_CTRL is not stored in the context, but is an ordinary register w/a that we need to restore during init_hw. Signed-off-by:
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Oscar Mateo authored
RING_FORCE_TO_NONPRIV registers do not live in the logical context. They are simply global privileged MMIO registers that happen to be powercontext saved and restored (meaning only they can survive RC6). Therefore, there is absolutely no need to save them so that they can be restored everytime we create a new logical context. Suggested-by:
Oscar Mateo <oscar.mateo@intel.com> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/1506638439-6903-1-git-send-email-oscar.mateo@intel.comAcked-by:
Michel Thierry <michel.thierry@intel.com> Tested-by: Chris Wilson <chris@chris-wilson.co.uk> #bxt Reviewed-by:
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Maarten Lankhorst authored
This has been unused since commit afa8ce5b ("drm/i915: Nuke legacy flip queueing code"). Changes since v1: - Rebase on top of all the changes to modparams. Cc: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by:
Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Reviewed-by:
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Imre Deak authored
According to BSpec GLK like BXT needs to ignore the idle state of cores before starting the DMC firmware's DC state handler. Fixes: dbb28b5c ("drm/i915/DMC/GLK: Load DMC on GLK") Cc: Anusha Srivatsa <anusha.srivatsa@intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by:
Imre Deak <imre.deak@intel.com> Reviewed-by:
Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20171003095159.711-2-imre.deak@intel.com
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Imre Deak authored
The DMC firmware program memory is lost after S3/S4 system suspend, so we need to reprogram it during resume. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103070 Fixes: cebfcead ("drm/i915/DMC/CNL: Load DMC on CNL") Cc: Anusha Srivatsa <anusha.srivatsa@intel.com> Cc: Animesh Manna <animesh.manna@intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by:
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Maarten Lankhorst authored
In legacy cursor updates we need the extra vblank waits if we update watermarks, and then we cannot skip the vblank for cursors. This is why for < gen9 we disabled the cursor fastpath, but we can skip the wait when post vblank watermarks are untouched. Signed-off-by:
Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20170919121419.13708-2-maarten.lankhorst@linux.intel.com
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Maarten Lankhorst authored
Commit b44d5c0c ("drm/i915: Always wait for flip_done, v2.") removed the call to wait_for_vblanks and replaced it with flip_done. Unfortunately legacy_cursor_update was unset too late, and the replacement call drm_atomic_helper_wait_for_flip_done() was a noop. Make sure that its unset before setup_commit() is called to fix this issue. Changes since v1: - Force vblank wait for watermarks not yet converted to atomic too. (Ville) - Use for_each_new_intel_crtc_in_state. (Ville) Changes since v2: - Move the optimization to a separate commit. (Ville) Signed-off-by:
Marta Löfstedt <marta.lofstedt@intel.com> Cc: Marta Löfstedt <marta.lofstedt@intel.com> Tested-by:
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- 03 Oct, 2017 5 commits
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Rodrigo Vivi authored
Let's organize this in a way that it gets more obvious when looking to the platform colors and in a easier way to get inherited. v2: Add comma at the end (Jani), when possible. Cc: Jani Nikula <jani.nikula@intel.com> Signed-off-by:
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Rodrigo Vivi authored
As Chris noticed the current organization is confusing and inheritance is not clear. So, let's split it in GEN<n>_FEATURES <cdn>_PLATFORM where new GEN inherit features from previous gens and Platforms only use gen features plus what ever is specific for that platform and shouldn't be passed on. Cc: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by:
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Rodrigo Vivi authored
According to Spec for SKL+: "Isochronous Priority Control. If enabled, Display sends demoted requests once the transition watermark is reached. If transition watermark is not enabled, Display sends demoted requests when the display buffer is full." The commit 'e57f1c02 ("drm/i915/gen9+: Add has_ipc flag in device info structure")' introduced that as gen9+ but missing many SKL Skus. I believe the reason for that is Spec also mentions workarounds for SKL-ALL: "IPC (Isoch Priority Control) may cause underflows WA: Do not enable IPC in register ARB_CTL2" It seems lame to add the feature and forever disable it, but it will avoid a mistake of enabling it when we are reorganizing the feature definitions on i915_pci.c later. It will also allow us to probably extend that workaround for other platforms. Cc: Mahesh Kumar <mahesh1.kumar@intel.com> Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by:
Mahesh Kumar <mahesh1.kumar@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20171003063652.17248-1-rodrigo.vivi@intel.com
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Imre Deak authored
The common lane power down flag of a DPIO PHY has a funky semantic: after the initial enabling of the PHY (so from a disabled state) this flag will be clear. It will be set only after the PHY will be used for the first time (for instance due to enabling the corresponding pipe) and then become unused (due to disabling the pipe). During the initial PHY enablement we don't know which of the above phases we are in, so move the check for the flag where this is known, the HW readout code. This is where the rest of lane power down status checks are done anyway. This fixes at least a problem on GLK where after module reloading, the common lane power down flag of PHY1 is set, but the PHY is actually powered-on and properly set up. The GRC readout code for other PHYs will hence think that PHY1 is not powered initially and disable it after the GRC readout. This will cause the AUX power well related to PHY1 to get disabled in a stuck state, timing out when we try to enable it later. Cc: Ville Syrjala <ville.syrjala@linux.intel.com> Fixes: e93da0a0 ("drm/i915/bxt: Sanitiy check the PHY lane power down status") Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102777Signed-off-by:
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Imre Deak authored
On GLK and CNL enabling a pipe with its pipe scaler enabled will result in a FIFO underrun. This happens only once after driver loading or system/runtime resume, more specifically after power well 1 gets enabled; subsequent modesets seem to be free of underruns. The BSpec workaround for this is to disable the pipe scaler clock gating for the duration of modeset. Based on my tests disabling clock gating must be done before enabling pipe scaling and we can re-enable it after the pipe is enabled and one vblank has passed. For consistency I also checked if plane scaling would cause the same problem, but that doesn't seem to trigger this problem. The patch is based on an earlier version from Ander. v2 (Rodrigo): - Set also CLKGATE_DIS_PSL bits 8 and 9. - Add also the BSpec workaround ID. Cc: Ander Conselvan de Oliveira <conselvan2@gmail.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=100302Signed-off-by:
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- 02 Oct, 2017 3 commits
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David Weinehall authored
While testing Jim Bride's latest batch of PSR patches I noticed that gen9lp doesn't include the has_psr flag, and that our GLK system thus reported PSR as unsupported. This patch simply adds has_psr. Signed-off-by:
David Weinehall <david.weinehall@linux.intel.com> Acked-by:
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Imre Deak authored
Only init / reset the display interrupts during power well enabling / disabling if the i915 interrupts are enabled. So far we did the init / reset during driver loading / resuming too, where initialization / enabling of the i915 interrupts happens only at a later point. This didn't cause a problem due to GEN8_MASTER_IRQ_CONTROL being cleared, but triggered gen3_assert_iir_is_zero() in GEN8_IRQ_INIT_NDX(). References: https://bugs.freedesktop.org/show_bug.cgi?id=102988 Cc: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by:
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Imre Deak authored
Atm, on GEN9 big core platforms before saving the hibernation image we uninitialize the display, disabling power wells manually, while before restoring the image we keep things powered (letting HW/DMC power down things as needed). The state mismatch will trigger the following error: DC state mismatch (0x0 -> 0x2) While the restore handler knows how to initialize the display from an unknown state (due to a different loader kernel or not having i915 loaded in the loader kernel) we should still use the same state for consistency before image saving and restoring. Do this by uniniting the display before restoring the image too. Bugzilla: https://bugs.freedesktop.org/attachment.cgi?id=133376Reported-and-tested-by:
Wang Wendy <wendy.wang@intel.com> Reported-and-tested-by:
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- 29 Sep, 2017 6 commits
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Michał Winiarski authored
Avoid the repeated rbtree lookup for each request as we unwind them by tracking the last priolist. v2: Fix up my unhelpful suggestion of using default_priolist. Signed-off-by:
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Chris Wilson authored
We use INT_MIN to denote the priority of a request that has not been submitted to the scheduler; we treat INT_MIN as an invalid priority and initialise the request to it. Give the value a name so it stands out. Signed-off-by:
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Chris Wilson authored
In the future, we will want to unwind requests following a preemption point. This requires the same steps as for unwinding upon a reset, so extract the existing code to a separate function for later use. Signed-off-by:
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Sagar Arun Kamble authored
i915_gem_restore_fences is GEM resumption task hence it is moved to i915_gem_resume from i915_restore_state. Signed-off-by:
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Chris Wilson authored
Currently, we are being fairly lazy and only using a wmb() following an update to an active batch. Previously, we have found that to be insufficient to ensure that a write from the CPU reaches memory in a timely fashion, and in some caches we may need to flush a chipset cache. To that end, we have i915_gem_chipset_flush() so use it. Suggested-by:
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Jani Nikula authored
Signed-off-by:Jani Nikula <jani.nikula@intel.com>
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- 28 Sep, 2017 5 commits
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Chris Wilson authored
Take advantage of optimised memset64() instead of open coding it to prefill the GTT pages. Signed-off-by:
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Rodrigo Vivi authored
One of the differences I spotted for GEN8+ platforms when compared to older platforms is that spec for BDW+ includes this sentence: "The first CRC done indication after CRC is first enabled is from only a partial frame, so it will not have the expected CRC result." This is an indication that on BDW+ platforms, by the time we receive the interrupt the CRC is not accurate yet for the full frame. That would be ok, because we are already skipping the first CRC for all platforms. However the comment on the code state that it is for some unknown reason. Also, on CHV (gen8 lp) we were already discarding the second CRC as well to make sure we have a reliable CRC on hand. So based on all ou tests and bugs it seems that it is not on CHV that needs to discard 2 first CRCs, but all BDW+ platforms. Starting on SKL we have this CRC done bit (24), but the experiments around the use of this bit wasn't that stable as just discarding the second CRC. So, let's for now just move with CHV solution for all gen8+ platforms and make our CI a bit more stable. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102374 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101309 Cc: Mika Kahola <mika.kahola@intel.com> Signed-off-by:
Mika Kahola <mika.kahola@intel.com> Reviewed-by:
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vathsala nagaraju authored
Set frames before SU entry value for max resync frame count of dpcd register 2009, bit field 0:3. v2 : - add macro EDP_PSR2_FRAME_BEFORE_SU (Rodrigo) - remove EDP_FRAMES_BEFORE_SU_ENTRY (Rodrigo) - add check ==1 for dpcd_read call (ville) v3 : (Rodrigo) - move macro EDP_PSR2_FRAME_BEFORE_SU after EDP_PSR2_FRAME_BEFORE_SU - replace with &= v4 : - change the macro to shift value (jani) - updated register names Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> CC: Puthikorn Voravootivat <puthik@chromium.org> Reviewed-by:
Vathsala Nagaraju <vathsala.nagaraju@intel.com> Signed-off-by:
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vathsala nagaraju authored
Add defines for dpcd register 2009 (synchronization latency in sink). v2: - add spec version (Daniel) - use register name as is in spec,only drop excess from end (jani) - add the full register contents (jani) [Rodrigo fixed spec version when merging] Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> CC: Puthikorn Voravootivat <puthik@chromium.org> Reviewed-by:
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Jani Nikula authored
Need MST sideband message transaction to power up/down nodes. Signed-off-by:
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