- 07 Jul, 2019 4 commits
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Chris Packham authored
Add an implementation of the _is_locked operation for concatenated mtd devices. This doesn't handle getting the lock status of a range that spans chips, which is consistent with cfi_ppb_is_locked and cfi_intelext_is_locked which only look at the first block in the range. Signed-off-by:
Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by:
Richard Weinberger <richard@nod.at>
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Chris Packham authored
concat_lock() and concat_unlock() only differed in terms of the mtd_xx operation they called. Refactor them to use a common helper function and pass a boolean flag to indicate whether lock or unlock is needed. Signed-off-by:
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Masahiro Yamada authored
Linux kernel tolerates C++ style comments these days. Actually, the SPDX License tags for .c files start with //. On the other hand, uapi headers are written in more strict C, where the C++ comment style is forbidden. Signed-off-by:
Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by:
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Ding Xiang authored
NULL check before kfree is unneeded, so remove it. Signed-off-by:
Ding Xiang <dingxiang@cmss.chinamobile.com> Signed-off-by:
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- 06 Jul, 2019 1 commit
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git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linuxRichard Weinberger authored
NAND core changes: - use longest matching pattern in ->exec_op() default parser - export NAND operation tracer - add flag to indicate panic_write in MTD - use kzalloc() instead of kmalloc() and memset() Raw NAND controller drivers changes: - brcmnand: * fix BCH ECC layout for large page NAND parts * fallback to detected ecc-strength, ecc-step-size * when oops in progress use pio and interrupt polling * code refactor code to introduce helper functions * add support for v7.3 controller - FSMC: * use nand_op_trace for operation tracing - GPMI: * move all driver code into single file * various cleanups (including dmaengine changes) * use runtime PM to manage clocks * implement exec_op - MTK: * correct low level time calculation of r/w cycle * improve data sampling timing for read cycle * add validity check for CE# pin setting * fix wrongly assigned OOB buffer pointer issue * re-license MTK NAND driver as Dual MIT/GPL - STM32: * manage the get_irq error case * increase DMA completion timeouts Raw NAND chips drivers changes: - Macronix: add read-retry support Onenand driver changes: - add support for 8Gb datasize chips - avoid fall-through warnings SPI-NAND changes: - define macros for page-read ops with three-byte addresses - add support for two-byte device IDs and then for GigaDevice GD5F1GQ4UFxxG - add initial support for Paragon PN26G0xA - handle the case where the last page read has bitflips
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- 28 Jun, 2019 4 commits
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Amelie Delaunay authored
When the system is overloaded, DMA data transfer completion occurs after 100ms. Increase the timeouts to let it the time to complete. Signed-off-by:
Amelie Delaunay <amelie.delaunay@st.com> Signed-off-by:
Christophe Kerello <christophe.kerello@st.com> Signed-off-by:
Miquel Raynal <miquel.raynal@bootlin.com>
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Fuqian Huang authored
Replace kmalloc() by a memset() followed with a kzalloc(). There is a recommendation to use zeroing allocator rather than allocator followed by memset(0) in ./scripts/coccinelle/api/alloc/zalloc-simple.cocci Signed-off-by:
Fuqian Huang <huangfq.daxian@gmail.com> Signed-off-by:
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Vignesh Raghavendra authored
Add driver for HyperBus memory controller on TI's AM654 SoC. Programming IP is pretty simple and provides direct memory mapped access to connected Flash devices. Add basic support for the IP without DMA. Second chip-select is not supported for now. Signed-off-by:
Vignesh Raghavendra <vigneshr@ti.com> Signed-off-by:
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liaoweixiong authored
In case of the last page containing bitflips (ret > 0), spinand_mtd_read() will return that number of bitflips for the last page while it should instead return max_bitflips like it does when the last page read returns with 0. Signed-off-by:
Weixiong Liao <liaoweixiong@allwinnertech.com> Reviewed-by:
Boris Brezillon <boris.brezillon@collabora.com> Reviewed-by:
Frieder Schrempf <frieder.schrempf@kontron.de> Cc: stable@vger.kernel.org Fixes: 7529df46 ("mtd: nand: Add core infrastructure to support SPI NANDs") Signed-off-by:
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- 27 Jun, 2019 31 commits
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Jeff Kletsky authored
Add initial support for Paragon Technology PN26G01Axxxxx and PN26G02Axxxxx SPI NAND Datasheets available at http://www.xtxtech.com/upfile/2016082517274590.pdf http://www.xtxtech.com/upfile/2016082517282329.pdfSigned-off-by:
Jeff Kletsky <git-commits@allycomm.com> Reviewed-by:
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Xiaolei Li authored
It is wanted to use MTK NAND driver with GPL-2.0 or MIT license. But now it is only licensed as GPL-2.0, so re-license it as dual MIT/GPL. Signed-off-by:
Xiaolei Li <xiaolei.li@mediatek.com> Acked-by:
Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org> Acked-by:
Ryder Lee <ryder.lee@mediatek.com> Acked-by:
Rafał Miłecki <rafal@milecki.pl> Acked-by:
Wen Yang <yellowriver2010@hotmail.com> Acked-by:
Dan Carpenter <dan.carpenter@oracle.com> Acked-by:
Arnd Bergmann <arnd@arndb.de> Acked-by:
RogerCC Lin <rogercc.lin@mediatek.com> Reviewed-by:
Matthias Brugger <matthias.bgg@gmail.com> Signed-off-by:
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Colin Ian King authored
The variable block_size is being assigned to itself and to geo->ecc_chunk_size. Clean up the double assignment by removing the assignment to itself. Addresses-Coverity: ("Evaluation order violation") Signed-off-by:Colin Ian King <colin.king@canonical.com> Signed-off-by:
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Kamal Dasu authored
Added brcm,brcmnand-v7.3 as possible compatible string to support brcmnand controller v7.3. Signed-off-by:
Kamal Dasu <kdasu.kdev@gmail.com> Reviewed-by:
Rob Herring <robh@kernel.org> Signed-off-by:
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Kamal Dasu authored
This change adds support for brcm NAND v7.3 controller. This controller uses a newer version of flash_dma engine and change mostly implements these differences. Signed-off-by:
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Kamal Dasu authored
Refactored NAND ECC and CMD address configuration code to use helper functions. Signed-off-by:
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Kamal Dasu authored
If mtd_oops is in progress, switch to polling during NAND command completion instead of relying on DMA/interrupts so that the mtd_oops buffer can be completely written in the assigned NAND partition. Signed-off-by:
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Kamal Dasu authored
Added a flag to indicate a panic_write so that low level drivers can use it to take required action where applicable, to ensure oops data gets written to assigned mtd device. Signed-off-by:
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Mason Yang authored
Add support for Macronix NAND read retry. Macronix NANDs support specific read operation for data recovery, which can be enabled with a SET_FEATURE. Driver checks byte 167 of Vendor Blocks in ONFI parameter page table to see if this high-reliability function is supported. Signed-off-by:
Mason Yang <masonccyang@mxic.com.tw> Signed-off-by:
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Gustavo A. R. Silva authored
NOTICE THAT: "...we don't know whether we need fallthroughs or breaks here and this is just a change to avoid having new warnings when switching to -Wimplicit-fallthrough but this change might be entirely wrong."[1] See the original thread of discussion here: https://lore.kernel.org/patchwork/patch/1036251/ So, in preparation to enabling -Wimplicit-fallthrough, this patch silences the following warnings: drivers/mtd/nand/onenand/onenand_base.c: In function ‘onenand_check_features’: drivers/mtd/nand/onenand/onenand_base.c:3264:6: warning: this statement may fall through [-Wimplicit-fallthrough=] if (ONENAND_IS_DDP(this)) ^ drivers/mtd/nand/onenand/onenand_base.c:3284:2: note: here case ONENAND_DEVICE_DENSITY_2Gb: ^~~~ drivers/mtd/nand/onenand/onenand_base.c:3288:17: warning: this statement may fall through [-Wimplicit-fallthrough=] this->options |= ONENAND_HAS_UNLOCK_ALL; drivers/mtd/nand/onenand/onenand_base.c:3290:2: note: here case ONENAND_DEVICE_DENSITY_1Gb: ^~~~ Warning level 3 was used: -Wimplicit-fallthrough=3 Also, notice that this patch doesn't change any functionality. See the most recent thread of discussion here: https://lore.kernel.org/patchwork/patch/1077395/ This patch is part of the ongoing efforts to enable -Wimplicit-fallthrough. [1] https://lore.kernel.org/lkml/20190509085318.34a9d4be@xps13/ Cc: Miquel Raynal <miquel.raynal@bootlin.com> Suggested-by:
Kees Cook <keescook@chromium.org> Signed-off-by:
Gustavo A. R. Silva <gustavo@embeddedor.com> Reviewed-by:
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Jeff Kletsky authored
The GigaDevice GD5F1GQ4UFxxG SPI NAND is in current production devices and, while it has the same logical layout as the E-series devices, it differs in the SPI interfacing in significant ways. This support is contingent on previous commits to: * Add support for two-byte device IDs * Define macros for page-read ops with three-byte addresses http://www.gigadevice.com/datasheet/gd5f1gq4xfxxg/Signed-off-by:
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Jeff Kletsky authored
The GigaDevice GD5F1GQ4UFxxG SPI NAND utilizes two-byte device IDs. http://www.gigadevice.com/datasheet/gd5f1gq4xfxxg/Signed-off-by:
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Jeff Kletsky authored
The GigaDevice GD5F1GQ4UFxxG SPI NAND utilizes three-byte addresses for its page-read ops. http://www.gigadevice.com/datasheet/gd5f1gq4xfxxg/Signed-off-by:
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Kamal Dasu authored
This change supports nand-ecc-step-size and nand-ecc-strength fields in brcmnand DT node to be optional. see: Documentation/devicetree/bindings/mtd/brcm,brcmnand.txt If both nand-ecc-strength and nand-ecc-step-size are not specified in device tree node for NAND, raw NAND layer does detect ECC information by reading ONFI extended parameter page for parts using ONFI >= 2.1. In case of non-ONFI NAND parts there could be a nand_id table entry with ECC information. If there is valid device tree entry for nand-ecc-strength and nand-ecc-step-size fields it still shall override the detected values. Signed-off-by:
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Kamal Dasu authored
nand-ecc-strength and nand-ecc-step-size can be made optional as brcmnand driver can support using raw NAND layer detected values. Signed-off-by:
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Sascha Hauer authored
The gpmi driver performance suffers from NAND operations being split in multiple small DMA transfers. This has been forced by the NAND layer in the former days, but now with exec_op we can use the controller as intended. With this patch gpmi_nfc_exec_op becomes the main entry point to NAND operations. Here all instructions are collected and chained as separate DMA transfers. In the end whole chain is fired and waited to be finished. gpmi_nfc_exec_op only does the hardware operations, bad block marker swapping and buffer scrambling is done by the callers. It's worth noting that the nand_*_op functions always take the buffer lengths for the data that the NAND chip actually transfers. When doing BCH we have to calculate the net data size from the raw data size in some places. This patch has been tested with 2048/64 and 2048/128 byte NAND on i.MX6q. mtd_oobtest, mtd_subpagetest and mtd_speedtest run without errors. nandbiterrs, nandpagetest and nandsubpagetest userspace tests from mtdutils run without errors and UBIFS can successfully be mounted. Signed-off-by:
Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by:
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Sascha Hauer authored
The mxs dma driver uses the flags parameter in dmaengine_prep_slave_sg() for custom flags, but still uses the dmaengine specific names of the flags. Do a little bit better and at least give the flag a custom name. Signed-off-by:
Vinod Koul <vkoul@kernel.org> Signed-off-by:
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Sascha Hauer authored
The mxs dma driver can do PIO transfers. A pointer to the PIO words to transfer is passed in the struct scatterlist * argument of dmaengine_prep_slave_sg(). It's quite ugly and non obvious to cast u32 * to struct scatterlist * each time when calling dmaengine_prep_slave_sg(), so add a static inline wrapper function to be called by the user along with a description what is going on. Signed-off-by:
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Sascha Hauer authored
The DMA_PREP_INTERRUPT flag is no longer needed by the mxs DMA driver, drop it. Signed-off-by:
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Sascha Hauer authored
The mxs dma driver insists on having the DMA_PREP_INTERRUPT flag set on all but the first transfer. There's no need to let the user set this flag, the driver can do it internally whenever it needs it. Drop handling of this flag from the driver. Signed-off-by:
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Sascha Hauer authored
The gpmi driver aggressively en/disables the clocks between operations which has significant performance cost. Use runtime PM to get rid of this bottleneck. Signed-off-by:
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Sascha Hauer authored
The i.MX23 specific option read code is called right after nand_scan. We can rely on the NAND core having disabled the chipselect, so there's no point in restoring the original chip select after NAND operations. Drop it. Signed-off-by:
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Sascha Hauer authored
gpmi_ecc_read_page_data uses the page parameter only for a debug printf, so we can drop the parameter and the debug printf. Moving the oob delivery from gpmi_ecc_read_page_data to gpmi_ecc_read_page makes the oob_required parameter unnecessary aswell. Signed-off-by:
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Sascha Hauer authored
The driver calls nand_read_page_op without a buffer passed and then calls chip->legacy.read_buf to read the buffer afterwards which is the same as passing the buffer nand_read_page_op in the first place. Signed-off-by:
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Sascha Hauer authored
this->page_buffer_virt and this->payload_virt are always set to the same value, so drop the former and just use the latter. Same for this->page_buffer_virt and this->payload_virt. Signed-off-by:
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Sascha Hauer authored
The "private" member of struct gpmi_nand_data isn't used anywhere. Remove it. Signed-off-by:
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Sascha Hauer authored
This moves the whole driver into a single C file. The filename gpmi-lib implies that it implements library functions, but in fact there are several cases where functions in gpmi-lib.c call back into functions in gpmi-nand.c. With this one has to constantly jump between those two files, so moving it into a single file improves readability, even when the file gets quite large. Signed-off-by:
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Sascha Hauer authored
Replace the different operation tracing functions with a call to nand_op_trace. Signed-off-by:
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Sascha Hauer authored
The NAND core has a NAND operation tracing function, but it can only be used by drivers using the generic option parser from the NAND core. Export the tracing function as a static inline function in rawnand.h so that drivers implementing exec_op directly do not have to write their own operation tracing. Signed-off-by:
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Xiaolei Li authored
One main goal of the function mtk_nfc_update_ecc_stats is to check whether sectors are all empty. If they are empty, set these sectors's data buffer and OOB buffer as 0xff. But now, the sector OOB buffer pointer is wrongly assigned. We always do memset from sector 0. To fix this issue, pass start sector number to make OOB buffer pointer be properly assigned. Fixes: 1d6b1e46 ("mtd: mediatek: driver for MTK Smart Device") Signed-off-by:
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Xiaolei Li authored
Currently, we only check how many CE# pins are set in device tree. But it should be necessary to check whether CE# pin setting is duplicated or if CE# pin index exceeds the maximum CE# number that controller supports. So, add validity check to avoid these invalid settings. Signed-off-by:
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