- 13 Jan, 2014 40 commits
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Alexandre Belloni authored
Other MMC hosts handle a regulator named vmmc-supply that allows to power the MMC card or SDIO device before communicating on the bus. Signed-off-by:
Alexandre Belloni <alexandre.belloni@free-electrons.com> Acked-by:
Ulf Hansson <ulf.hansson@linaro.org> Acked-by:
Ludovic Desroches <ludovic.desroches@atmel.com> Signed-off-by:
Chris Ball <chris@printf.net>
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David Cohen authored
Due to unknown hw issue so far, Merrifield is unable to enable HS200 support. This patch adds quirk to avoid SDHCI to initialize with error below: [ 53.850132] CPU: 0 PID: 0 Comm: swapper/0 Tainted: G W 3.12.0-rc6-00037-g3d7c8d9-dirty #36 [ 53.850150] Hardware name: Intel Corporation Merrifield/SALT BAY, BIOS 397 2013.09.12:11.51.40 [ 53.850167] 00000000 00000000 ee409e48 c18816d2 00000000 ee409e78 c123e254 c1acc9b0 [ 53.850227] 00000000 00000000 c1b14148 000003de c16c03bf c16c03bf ee75b480 ed97c54c [ 53.850282] ee75b480 ee409e88 c123e292 00000009 00000000 ee409ef8 c16c03bf c1207fac [ 53.850339] Call Trace: [ 53.850376] [<c18816d2>] dump_stack+0x4b/0x79 [ 53.850408] [<c123e254>] warn_slowpath_common+0x84/0xa0 [ 53.850436] [<c16c03bf>] ? sdhci_send_command+0xb4f/0xc50 [ 53.850462] [<c16c03bf>] ? sdhci_send_command+0xb4f/0xc50 [ 53.850490] [<c123e292>] warn_slowpath_null+0x22/0x30 [ 53.850516] [<c16c03bf>] sdhci_send_command+0xb4f/0xc50 [ 53.850545] [<c1207fac>] ? native_sched_clock+0x2c/0xb0 [ 53.850575] [<c14c1f93>] ? delay_tsc+0x73/0xb0 [ 53.850601] [<c14c1ebe>] ? __const_udelay+0x1e/0x20 [ 53.850626] [<c16bdeb3>] ? sdhci_reset+0x93/0x190 [ 53.850654] [<c16c05b0>] sdhci_finish_data+0xf0/0x2e0 [ 53.850683] [<c16c130f>] sdhci_irq+0x31f/0x930 [ 53.850713] [<c12cb080>] ? __buffer_unlock_commit+0x10/0x20 [ 53.850740] [<c12cbcd7>] ? trace_buffer_unlock_commit+0x37/0x50 [ 53.850773] [<c1288f3c>] handle_irq_event_percpu+0x5c/0x220 [ 53.850800] [<c128bc96>] ? handle_fasteoi_irq+0x16/0xd0 [ 53.850827] [<c128913a>] handle_irq_event+0x3a/0x60 [ 53.850852] [<c128bc80>] ? unmask_irq+0x30/0x30 [ 53.850878] [<c128bcce>] handle_fasteoi_irq+0x4e/0xd0 [ 53.850895] <IRQ> [<c1890b52>] ? do_IRQ+0x42/0xb0 [ 53.850943] [<c1890a31>] ? common_interrupt+0x31/0x38 [ 53.850973] [<c12b00d8>] ? cgroup_mkdir+0x4e8/0x580 [ 53.851001] [<c1208d32>] ? default_idle+0x22/0xf0 [ 53.851029] [<c1209576>] ? arch_cpu_idle+0x26/0x30 [ 53.851054] [<c1288505>] ? cpu_startup_entry+0x65/0x240 [ 53.851082] [<c18793d5>] ? rest_init+0xb5/0xc0 [ 53.851108] [<c1879320>] ? __read_lock_failed+0x18/0x18 [ 53.851138] [<c1bf6a15>] ? start_kernel+0x31b/0x321 [ 53.851164] [<c1bf652f>] ? repair_env_string+0x51/0x51 [ 53.851190] [<c1bf6363>] ? i386_start_kernel+0x139/0x13c [ 53.851209] ---[ end trace 92777f5fe48d33f2 ]--- [ 53.853449] mmcblk0: error -84 transferring data, sector 11142162, nr 304, cmd response 0x0, card status 0x0 [ 53.853476] mmcblk0: retrying using single block read [ 55.937863] sdhci: Timeout waiting for Buffer Read Ready interrupt during tuning procedure, falling back to fixed sampling clock [ 56.207951] sdhci: Timeout waiting for Buffer Read Ready interrupt during tuning procedure, falling back to fixed sampling clock [ 66.228785] mmc0: Timeout waiting for hardware interrupt. [ 66.230855] ------------[ cut here ]------------ Signed-off-by:
David Cohen <david.a.cohen@linux.intel.com> Reviewed-by:
Chuanxiao Dong <chuanxiao.dong@intel.com> Acked-by:
Dong Aisheng <b29396@freescale.com> Cc: stable <stable@vger.kernel.org> # [3.13] Signed-off-by:
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David Cohen authored
This patch defines a quirk for platforms unable to enable HS200 support. Signed-off-by:
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Soren Brinkmann authored
Add a driver for Arasan's SDHCI controller core. Signed-off-by:
Soren Brinkmann <soren.brinkmann@xilinx.com> Acked-by: Rob Herring <rob.herring@calxeda.com> [binding] Acked-by:
Michal Simek <monstr@monstr.eu> Signed-off-by:
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Zhangfei Gao authored
Add dw_mmc-k3.c for k3v2, support sd/emmc Signed-off-by:
Zhangfei Gao <zhangfei.gao@linaro.org> Signed-off-by:
Zhigang Wang <brooke.wangzhigang@huawei.com> Acked-by:
Arnd Bergmann <arnd@arndb.de> Signed-off-by:
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Zhangfei Gao authored
Suggested by Jaehoon: Use slot-gpio to handle cd-gpio Add function dw_mci_of_get_cd_gpio to check "cd-gpios" from dts. mmc_gpio_request_cd and mmc_gpio_get_cd are used to handle cd pin Signed-off-by:
Jaehoon Chung <jh80.chung@samsung.com> Acked-by:
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Adam Lee authored
Add O2Micro/BayHubTech SD Host DeviceId 8520 support. Add O2Micro/BayHubTech SD Host DeviceId 8420 & 8421 support. Add O2Micro/BayHubTech SD Host DeviceId 8620 & 8621 support. These card readers are used in laptops like Lenovo ThinkPad W540, Dell Latitude E5440, Dell Latitude E6540. Signed-off-by:
Peter Guo <peter.guo@bayhubtech.com> Signed-off-by:
Adam Lee <adam.lee@canonical.com> Signed-off-by:
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Adam Lee authored
Break out definitions in sdhci-pci.c to sdhci-pci.h, for introducing module files like sdhci-pci-xxx.c Signed-off-by:
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Kuninori Morimoto authored
This patch fixes the below compile error: ${LINUX}/drivers/mmc/host/tmio_mmc.c: In function 'tmio_mmc_probe': ${LINUX}/drivers/mmc/host/tmio_mmc.c:93:35: \ error: 'res_ctl' undeclared (first use in this function) ${LINUX}/drivers/mmc/host/tmio_mmc.c:93:35: \ note: each undeclared identifier is reported only \ once for each function it appears in Reported-by:Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Acked-by:
Simon Horman <horms+renesas@verge.net.au> Signed-off-by:
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Chris Ball authored
I'm no longer at OLPC. (The old email address still works for now.) Signed-off-by: -
Laurent Pinchart authored
This helps increasing build testing coverage. Signed-off-by:
Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Acked-by:
Simon Horman <horms@verge.net.au> Signed-off-by:
Chris Ball <cjb@laptop.org>
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Laurent Pinchart authored
This helps increasing build testing coverage. The driver doesn't compile on (at least) x86 due (possibly among others) to missing readsw/writesw I/O accessors, restrict compilation to SUPERH or ARM. Whether the CTL_DMA_ENABLE register is part of the standard TMIO controller or is Renesas-specific is unknown and impossible to test as we have no current or planned TMIO DMA users other than SUPERH and ARCH_SHMOBILE. Writing to the register is thus conditionally compiled for SUPERH and ARCH_SHMOBILE only. Adding ARCH_SHMOBILE_MULTI to the list would extend this to multiarch kernels, but would break the driver for non-shmobile platforms if the register is Renesas-specific. We can thus get rid of the conditional compilation completely without introducing any further issue, and let future non-Renesas users deal with the situation if it turns out to be a the problem. Signed-off-by:
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Stephen Warren authored
Tegra124's MMC controller is very similar to earlier SoC generations, and can be supported by the same driver. However, there are some non-backwards-compatible HW differences, and hence a new DT compatible value must be used to describe the HW. This patch updates the driver to support that new compatible value. That said, the HW differences are only relevant when enabling certain high-performance transfer modes. Since the driver is currently very simple and doesn't enable those modes, we don't actually need to address any of these HW differences in the code yet, hence the simple nature of this patch. Signed-off-by:
Stephen Warren <swarren@nvidia.com> Reviewed-by:
Thierry Reding <treding@nvidia.com> Signed-off-by:
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Laurent Pinchart authored
Casting an integer to a void * generates a "cast to pointer from integer of different size" warning. Cast the integer to an unsigned long first to fix it. Signed-off-by:
Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by:
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Laurent Pinchart authored
The channel request and configuration code is duplicated for the rx and tx channels. Create a function that requests a single channel and call it twice instead. Signed-off-by:
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Kuninori Morimoto authored
One of Renesas SDHI chip needs workaround to use it, and, we can judge it based on chip version. This patch adds very quick-hack workaround method, since we still don't know how many chips need workaround in the future. Signed-off-by:
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Kuninori Morimoto authored
The accessibility checking method to the higher register was added by 69d1fe18 (mmc: tmio: only access registers above 0xff, if available) But, it doesn't care 32bit register. It is impossible to calculate it from the resource size, since there is 16/32 bit register IP (e.g. VERSION is located on 0xe2 if 16bit register, but it is located on 0x1c4 if 32bit register). This patch adds new TMIO_MMC_HAVE_HIGH_REG flags, tmio_mmc driver has it, and sh_mobile_sdhi doesn't have it today. Signed-off-by:
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Kuninori Morimoto authored
.bus_shift is used to 16/32bit register access offset calculation on tmio driver. tmio_mmc_xxx is used from Toshiba/Renesas now, but this bus_shift value depends on HW IP. This patch moves .bus_shift to tmio_mmc_data member and sets it on each driver. Signed-off-by:
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Kuninori Morimoto authored
Current tmio driver tries to use default ocr_avail if 1) it couldn't find regulator and 2) if platform data doesn't have ocr_mask. But, there is no guarantee that regulator driver probe is faster than TMIO driver probe. TMIO driver will not use regulator in such case. By this patch, TMIO driver returns -EPROBE_DEFER if it couldn't find regulator and if platform doesn't have ocr_mask. Because, there is a possibility that regulator has not been probed, but the user expects it. This patch changes tmio_mmc_host_probe() behavior, but there is no user who has conflict. Signed-off-by:
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Sascha Hauer authored
Use generic helper function. This also adds support for the cd-gpios and max-frequency devicetree properties. Signed-off-by:
Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by:
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Sascha Hauer authored
This also fixes that the read-only gpio was used without being requested. Signed-off-by:
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Sascha Hauer authored
We have a MMC_CAP2_CD_ACTIVE_HIGH flag, so use it rather than a custom driver specific flag. Signed-off-by:
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Sascha Hauer authored
Use the standard MMC_CAP_NEEDS_POLL flag rather than a custom broken_cd flag. The original code used to just return true in the card detection function for broken card detection. The MMC_CAP_NEEDS_POLL works different, but was introduced for the same purpose, so assume the code works correct now. Signed-off-by:
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Sascha Hauer authored
The standard caps already have a MMC_CAP_NONREMOVABLE flag. Use it rather than a custom non_removable flag. Signed-off-by:
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Sascha Hauer authored
Non removable cards are always present, so do not call get_cd for them. Signed-off-by:
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Mika Westerberg authored
Newer Intel PCHs with LPSS have the same SDHCI controller than Haswell but ACPI ID is different. Add this ID to the driver list. Signed-off-by:
Mika Westerberg <mika.westerberg@linux.intel.com> Acked-by:
Adrian Hunter <adrian.hunter@intel.com> Signed-off-by:
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Laurent Pinchart authored
Turn clk_enable() and clk_disable() calls into clk_prepare_enable() and clk_disable_unprepare() to get ready for the migration to the common clock framework. Signed-off-by:
Guennadi Liakhovetski <g.liakhovetski@gmx.de> Signed-off-by:
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Fabio Estevam authored
Fix the following sparse warning: drivers/mmc/host/sdhci-esdhc-imx.c:617:35: warning: Using plain integer as NULL pointer Signed-off-by:
Fabio Estevam <fabio.estevam@freescale.com> Cc: Shawn Guo <shawn.guo@linaro.org> Signed-off-by:
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Chuansheng Liu authored
In function sdhci_request(), it is possible to do the tuning execution like below: sdhci_request() { spin_lock_irqsave(&host->lock, flags); host->mrq = mrq; ... spin_unlock_irqrestore(&host->lock, flags); <=== Here it is possible one pending finish_tasklet get running and it will operate the original mrq, and notified the mrq is done, and causes memory corruption. sdhci_execute_tuning(mmc, tuning_opcode); spin_lock_irqsave(&host->lock, flags); host->mrq = mrq; ... } In the above race place, the original mrq should not be finished wrongly, so here before unlock the spinlock, we need to set the host->mrq to NULL to avoid this case. Signed-off-by:Liu, Chuansheng <chuansheng.liu@intel.com> Signed-off-by:
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Guennadi Liakhovetski authored
Since I'm currently unable to dedicate sufficient time to driver maintainership, remove myself from the maintainers list. Signed-off-by:
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Ludovic Desroches authored
With some SDIO devices, timeout errors can happen when reading data. To solve this issue, the DMA transfer has to be activated before sending the command to the device. This order is incorrect in PDC mode. So we have to take care if we are using DMA or PDC to know when to send the MMC command. Cc: stable <stable@vger.kernel.org> # 3.2+ Signed-off-by:
Nicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by:
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Kuninori Morimoto authored
02cb3221 ("mmc: tmio: support caps2 flags") added caps2 support on tmio, but it overwrites mmc_of_parse() settings. This patch fixes it. Signed-off-by:
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Ray Jui authored
Under function mmc_blk_issue_rq, after an MMC discard operation, the MMC request data structure may be freed in memory. Later in the same function, the check of req->cmd_flags & MMC_REQ_SPECIAL_MASK is dangerous and invalid. It causes the MMC host not to be released when it should. This patch fixes the issue by marking the special request down before the discard/flush operation. Reported by: Harold (SoonYeal) Yang <haroldsy@broadcom.com> Signed-off-by:
Ray Jui <rjui@broadcom.com> Reviewed-by:
Seungwon Jeon <tgih.jun@samsung.com> Acked-by:
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Dong Aisheng authored
The root clock will be disabled in runtime pm to save power. Signed-off-by:
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Dong Aisheng authored
Since we're using common esdhc_send_command for tuning commands and the core code will call pm_runtime_put after command is finished. So we add a pm_runtime_get_sync here to get the balance. Signed-off-by:
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Dong Aisheng authored
Current code will clear all turning related bits like ESDHC_STD_TUNING_EN and ESDHC_MIX_CTRL_FBCLK_SEL when clear SDHCI_CTRL_EXEC_TUNING. This may cause the card which has already passed the turning to become unwork since the turning status lost. We observed this failure when enable runtime pm. BTW, imx needs to enable ESDHC_MIX_CTRL_FBCLK_SEL bit for turned clock. The FBCLK_SEL will be cleared when SDHCI_CTRL_TUNED_CLK is cleared and SDHCI_CTRL_EXEC_TUNING is not set. This is used in case we change to another normal card from a UHS card in the same slot. FBCLK_SEL is not needed for normal card. After that, SDHCI_CTRL_EXEC_TUNING will only affect ESDHC_MIX_CTRL_EXE_TUNE. Clearing it does not affect the turned card to remain working on UHS mode. Signed-off-by:
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Dong Aisheng authored
We should not clear tuning bits during reset or the SD3.0/eMMC4.5 card working on UHS mode may not work after reset since the former tuning settings was lost. Signed-off-by:
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Dong Aisheng authored
It is helpful for platform code to use to eliminate duplicated code. Signed-off-by:
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Dong Aisheng authored
Add support for eMMC 4.5 cards to work on hs200 mode. Signed-off-by:
Shawn Guo <shawn.guo@linaro.org> Signed-off-by:
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Dong Aisheng authored
The MMC_CAP_UHS_DDR50 must work on 1.8v. However, the eMMC DDR mode can work on either 1.8v or 3.3v and should not depend on UHS_DDR50. So get rid of this limitation to let controller without 1.8v signal voltage support can also work for eMMC DDR mode if it claims. Signed-off-by:
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