- 26 Jun, 2013 2 commits
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Alex Deucher authored
v2: further updates Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
v2: update to latest driver changes v3: properly tear down vm on suspend v4: fix up irq init ordering v5: remove outdated comment Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com>
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- 25 Jun, 2013 20 commits
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Alex Deucher authored
Async page table updates using the sDMA engine. sDMA has a special packet for updating entries for contiguous pages that reduces overhead. v2: add support for and use the CP for now. v3: update for 2 level PTs v4: rebase, fix DMA packet v5: switch to using an IB Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
Update the page table base address and flush the VM TLB using the sDMA. V2: update for 2 level PTs V3: update vm flush V4: update SH_MEM* regs V5: switch back to old style VM TLB invalidate V6: fix packet formatting Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
CIK has new asynchronous DMA engines called sDMA (system DMA). Each engine supports 1 ring buffer for kernel and gfx and 2 userspace queues for compute. TODO: fill in the compute setup. v2: update to the latest reset code v3: remove ib_parse v4: fix copy_dma() v5: drop WIP compute sDMA queues v6: rebase v7: endian fixes for IB v8: cleanup for release Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
Todo: - handle interrupts for compute queues v2: add documentation v3: update to latest reset code v4: update to latest illegal CP handling v5: fix missing break in interrupt handler switch statement Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
RLC handles the interrupt controller and other tasks on the GPU. v2: add documentation v3: update programming sequence v4: additional setup Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
Update the page table base address and flush the VM TLB using the CP. v2: update for 2 level PTs v3: use new packet for invalidate v4: update SH_MEM* regs when flushing the VM v5: add pfp sync, go back to old style vm TLB invalidate v6: fix hdp flush packet count v7: use old style HDP flush Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
v2: add documenation v3: update the latest ib changes Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
For gfx ring only. Compute is still todo. v2: add documentation v3: update to latest reset changes, integrate emit update patch. v4: fix count on wait_reg_mem for HDP flush v5: use old hdp flush method for fence v6: set valid bit for IB v7: cleanup for release Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
Sets up the GFX ring and loads ucode for GFX and Compute. Todo: - handle compute queue setup. v2: add documentation v3: integrate with latest reset changes v4: additional init fixes v5: scratch reg write back no longer supported on CIK v6: properly set CP_RB0_BASE_HI v7: rebase Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
Load the GDDR5 ucode and train the links. v2: update ucode Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
Currently the driver required 6 sets of ucode: 1. pfp - pre-fetch parser, part of the GFX CP 2. me - micro engine, part of the GFX CP 3. ce - constant engine, part of the GFX CP 4. rlc - interrupt, etc. controller 5. mc - memory controller (discrete cards only) 6. mec - compute engines, part of Compute CP V2: add documentation V3: update MC ucode V4: rebase V5: update mc ucode Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
Redirect invalid memory accesses to the default page instead of locking up the memory controller. v2: rebase on top of 2 level PTs Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
The vm callbacks are the same as the SI ones right now (same regs and bits). We could share the SI variants, and I may yet do that, but I figured I would add CIK specific ones for now in case we need to change anything. V2: add documentation, minor fixes. V3: integrate vram offset fixes for APUs V4: enable 2 level VM PTs V5: index SH_MEM_* regs properly V6: add ib_parse() Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
v2: split soft reset into compute and gfx. Still need to make reset more fine grained, but this should be a start. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
v2: tiling fixes v3: more tiling fixes v4: more tiling fixes v5: additional register init v6: rebase v7: fix gb_addr_config for KV/KB v8: drop wip KV bits for now, add missing config reg v9: fix cu count on Bonaire Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
register BAR is now at PCI BAR 5. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
New asics support non-privileged IBs. This allows us to skip IB checking in the driver since the hardware will check the command buffers for us. When using non-privileged IBs, if the CP encounters an illegal register in the command stream, it will halt and generate an interrupt. The CP needs to be reset to continue. For now just do a full GPU reset when this happens. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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- 12 Jun, 2013 5 commits
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Alex Deucher authored
Mac laptops with multiple GPUs apparently use the gmux driver for backlight control. Don't register a radeon backlight interface. We may need to add other pci ids for other hybrid mac laptops. Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=65377Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
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Alex Deucher authored
- remove adding 2 to checksum, this is incorrect. This was incorrectly introduced in: 92db7f6c http://lists.freedesktop.org/archives/dri-devel/2011-December/017717.html However, the off by 2 was due to adding the version twice. From the examples in the URL above: [Rafał Miłecki][RV620] fglrx: 0x7454: 00 A8 5E 79 R600_HDMI_VIDEOINFOFRAME_0 0x7458: 00 28 00 10 R600_HDMI_VIDEOINFOFRAME_1 0x745C: 00 48 00 28 R600_HDMI_VIDEOINFOFRAME_2 0x7460: 02 00 00 48 R600_HDMI_VIDEOINFOFRAME_3 =================== (0x82 + 0x2 + 0xD) + 0x1F8 = 0x289 -0x289 = 0x77 However, the payload sum is not 0x1f8, it's 0x1f6. 00 + A8 + 5E + 00 + 00 + 28 + 00 + 10 + 00 + 48 + 00 + 28 + 00 + 48 = 0x1f6 Bits 25:24 of HDMI_VIDEOINFOFRAME_3 are the packet version, not part of the payload. So the total would be: (0x82 + 0x2 + 0xD) + 0x1f6 = 0x287 -0x287 = 0x79 - properly emit the AVI infoframe version. This was not being emitted previous which is probably what caused the issue above. This should fix blank screen when HDMI audio is enabled on certain monitors. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org Cc: Rafał Miłecki <zajec5@gmail.com>
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Alex Deucher authored
This fixes the kernel side so that the ring should come up and ring and IB tests should work. The userspace UVD drivers will also need big endian fixes. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Jerome Glisse authored
UVD ring can't use scratch thus it does need writeback buffer to keep a valid address or radeon_ring_backup will trigger a kernel fault. It's ok to not unpin the write back buffer on suspend as it leave in gtt and thus does not need eviction. v2: Fix the uvd case. Reported and tracked by Wojtek <wojtask9@wp.pl> Signed-off-by: Jerome Glisse <jglisse@redhat.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Jerome Glisse authored
If a buffer is never bound to a virtual memory pagetable than don't try to unbind it. Only drawback is that we don't update the pagetable when unbinding the ib pool buffer which is fine because it only happens at suspend or module unload/shutdown. Fixes spurious messages about buffers without VM mappings. E.g.: radeon 0000:01:00.0: bo ffff88020afac400 don't has a mapping in vm ffff88021ca2b900 Cc: stable@kernel.org Signed-off-by: Jerome Glisse <jglisse@redhat.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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- 11 Jun, 2013 1 commit
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Dave Airlie authored
Merge tag 'drm-intel-fixes-2013-06-11' of git://people.freedesktop.org/~danvet/drm-intel into drm-fixes Daniel writes: Just tiny regression fixes here: - Two fixes to fix sdvo hotplug which broke in the hpd storm detection work. - One fix to patch-up the sdvo lvds regression fixer from the last pull - we need to prefer the vbt mode over edid modes. * tag 'drm-intel-fixes-2013-06-11' of git://people.freedesktop.org/~danvet/drm-intel: drm/i915: prefer VBT modes for SVDO-LVDS over EDID drm/i915: Enable hotplug interrupts after querying hw capabilities. drm/i915: Fix hotplug interrupt enabling for SDVOC
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- 10 Jun, 2013 11 commits
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git://github.com/patjak/drm-gma500Dave Airlie authored
Patrik writes: Two fixes for memory leaks split into Cedarview and Poulsbo versions, and a fix for properly setting the pipe base when using fbdev. It's on my todo-list to start unifying the chips since they are very similar, but until then I'd like to split them up in case there are side-effects on Cedarview that I cannot currently test. airled: Verified pull from github matches what I expected. * 'gma500-fixes' of git://github.com/patjak/drm-gma500: drm/gma500/cdv: Fix cursor gem obj referencing on cdv drm/gma500/psb: Fix cursor gem obj referencing on psb drm/gma500/cdv: Unpin framebuffer on crtc disable drm/gma500/psb: Unpin framebuffer on crtc disable drm/gma500: Add fb gtt offset to fb base
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git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spiLinus Torvalds authored
Pull spi fixes from Mark Brown: "A few nasty issues, particularly a race with the interrupt controller in the xilinx driver, together with a couple of more minor fixes and a much needed move of the mailing list away from sourceforge." * tag 'spi-v3.10-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi: spi: hspi: fixup long delay time spi: spi-xilinx: Remove ISR race condition spi: topcliff-pch: fix error return code in pch_spi_probe() spi: topcliff-pch: Pass correct pointer to free_irq() spi: Move mailing list to vger
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Linus Torvalds authored
Merge tag 'stable/for-linus-3.10-rc5-tag' of git://git.kernel.org/pub/scm/linux/kernel/git/konrad/xen Pull xen fixes from Konrad Rzeszutek Wilk: "Two bug-fixes for regressions: - xen/tmem stopped working after a certain combination of modprobe/swapon was used - cpu online/offlining would trigger WARN_ON." * tag 'stable/for-linus-3.10-rc5-tag' of git://git.kernel.org/pub/scm/linux/kernel/git/konrad/xen: xen/tmem: Don't over-write tmem_frontswap_poolid after tmem_frontswap_init set it. xen/smp: Fixup NOHZ per cpu data when onlining an offline CPU.
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git://git.kernel.org/pub/scm/linux/kernel/git/broonie/regmapLinus Torvalds authored
Pull regmap fixes from Mark Brown: "The biggest fix here is Lars-Peter's fix for custom locking callbacks which is pretty localised but important for those devices that use the feature. Otherwise we've got a couple of fairly small cleanups which would have been sent sooner were it not for letting Lars-Peter's patch soak for a while" * tag 'regmap-v3.10-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/regmap: regmap: rbtree: Fixed node range check on sync regmap: regcache: Fixup locking for custom lock callbacks regmap: debugfs: Check return value of regmap_write()
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git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6Linus Torvalds authored
Pull crypto fixes from Herbert Xu: "This fixes a build problem in sahara and temporarily disables two new optimisations because of performance regressions until a permanent fix is ready" * git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6: crypto: sahara - fix building as module crypto: blowfish - disable AVX2 implementation crypto: twofish - disable AVX2 implementation
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Konrad Rzeszutek Wilk authored
Commit 10a7a077 ("xen: tmem: enable Xen tmem shim to be built/loaded as a module") allows the tmem module to be loaded any time. For this work the frontswap API had to be able to asynchronously to call tmem_frontswap_init before or after the swap image had been set. That was added in git commit 905cd0e1 ("mm: frontswap: lazy initialization to allow tmem backends to build/run as modules"). Which means we could do this (The common case): modprobe tmem [so calls frontswap_register_ops, no ->init] modifies tmem_frontswap_poolid = -1 swapon /dev/xvda1 [__frontswap_init, calls -> init, tmem_frontswap_poolid is < 0 so tmem hypercall done] Or the failing one: swapon /dev/xvda1 [calls __frontswap_init, sets the need_init bitmap] modprobe tmem [calls frontswap_register_ops, -->init calls, finds out tmem_frontswap_poolid is 0, does not make a hypercall. Later in the module_init, sets tmem_frontswap_poolid=-1] Which meant that in the failing case we would not call the hypercall to initialize the pool and never be able to make any frontswap backend calls. Moving the frontswap_register_ops after setting the tmem_frontswap_poolid fixes it. Signed-off-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com> Reviewed-by: Bob Liu <bob.liu@oracle.com>
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Daniel Vetter authored
In commit 53d3b4d7 Author: Egbert Eich <eich@suse.de> Date: Tue Jun 4 17:13:21 2013 +0200 drm/i915/sdvo: Use &intel_sdvo->ddc instead of intel_sdvo->i2c for DDC Egbert Eich fixed a long-standing bug where we simply used a non-working i2c controller to read the EDID for SDVO-LVDS panels. Unfortunately some machines seem to not be able to cope with the mode provided in the EDID. Specifically they seem to not be able to cope with a 4x pixel mutliplier instead of a 2x one, which seems to have been worked around by slightly changing the panels native mode in the VBT so that the dotclock is just barely above 50MHz. Since it took forever to notice the breakage it's fairly safe to assume that at least for SDVO-LVDS panels the VBT contains fairly sane data. So just switch around the order and use VBT modes first. v2: Also add EDID modes just in case, and spell Egbert correctly. v3: Elaborate a bit more about what's going on on Chris' machine. Cc: Egbert Eich <eich@suse.de> Cc: Chris Wilson <chris@chris-wilson.co.uk> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=65524 Cc: stable@vger.kernel.org Reported-and-tested-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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Chris Wilson authored
sdvo->hotplug_active is initialised during intel_sdvo_setup_outputs(), and so we never enabled the hotplug interrupts on SDVO as we were checking too early. This regression has been introduced somewhere in the hpd rework for the storm detection and handling starting with commit 1d843f9d Author: Egbert Eich <eich@suse.de> Date: Mon Feb 25 12:06:49 2013 -0500 DRM/I915: Add enum hpd_pin to intel_encoder. and the follow-up patches to use the new encoder->hpd_pin variable for the different irq setup functions. The problem is that encoder->hpd_pin was set up _before_ the output setup was done and so before we could assess the hotplug capabilities of the outputs on an sdvo encoder. Reported-by: Alex Fiestas <afiestas@kde.org> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=58405Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> [danvet: Add regression note.] Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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Chris Wilson authored
A broken conditional would lead to SDVOC waiting upon hotplug events on SDVOB - and so miss all activity on its SDVO port. This regression has been introduced in commit 1d843f9d Author: Egbert Eich <eich@suse.de> Date: Mon Feb 25 12:06:49 2013 -0500 DRM/I915: Add enum hpd_pin to intel_encoder. References: https://bugs.freedesktop.org/show_bug.cgi?id=58405Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> [danvet: Add regression note.] Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpcLinus Torvalds authored
Pull powerpc fixes from Benjamin Herrenschmidt: "This is purely regressions (though not all recent ones) or stable material" * 'merge' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc: powerpc: Partial revert of "Context switch more PMU related SPRs" powerpc/perf: Fix deadlock caused by calling printk() in PMU exception powerpc/hw_breakpoints: Add DABRX cpu feature to fix 32-bit regression powerpc/power8: Update denormalization handler powerpc/pseries: Simplify denormalization handler powerpc/power8: Fix oprofile and perf powerpc/eeh: Don't check RTAS token to get PE addr powerpc/pci: Check the bus address instead of resource address in pcibios_fixup_resources
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git://git.linaro.org/people/rmk/linux-armLinus Torvalds authored
Pull ARM fixes from Russell King: "The biggest two fixes are fixing a compilation error with the decompressor, and a problem with our __my_cpu_offset implementation. Other changes are very trivial and small, which seems to be the way for most -rc stuff." * 'fixes' of git://git.linaro.org/people/rmk/linux-arm: ARM: 7747/1: pcpu: ensure __my_cpu_offset cannot be re-ordered across barrier() ARM: 7750/1: update legacy CPU ID in decompressor cache support jump table ARM: 7743/1: compressed/head.S: work around new binutils warning ARM: 7742/1: topology: export cpu_topology ARM: 7737/1: fix kernel decompressor compilation error with CONFIG_DEBUG_SEMIHOSTING
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- 09 Jun, 2013 1 commit
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Michael Ellerman authored
In commit 59affcd3 I added context switching of more PMU SPRs, because they are potentially exposed to userspace on Power8. However despite me being a smart arse in the commit message it's actually not correct. In particular it interacts badly with a global perf record. We will have to do something more complicated, but that will have to wait for 3.11. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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