- 15 Sep, 2020 40 commits
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Eryk Brol authored
[why] We want to trigger atomic check on connector, which DSC debugfs properties have changed. [how] Add a helper function that iterates through all active connectors and add them to the state if DSC debugfs parameters have changed. Signed-off-by:
Eryk Brol <eryk.brol@amd.com> Signed-off-by:
Mikita Lipski <mikita.lipski@amd.com> Acked-by:
Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Eryk Brol authored
[why] When comparing current DSC timing settings with enforced through debugfs we have to calculate number of both vertical and horisontal slices. So instead of doing that every time we should just use number of slices rather than setting its dimensions. [how] In connector's dsc preferred settings structure change slice height and slice width parameters to number of slices vertical and horisontal. Also calculate number of slices in debugfs rather in create_stream_for_sink. Signed-off-by:
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Eryk Brol authored
[why & how] Previously we were returning the number of bytes allocated for a write buffer from debugfs and when manually used it wouldn't rise any errors, but it wouldn't match the size of the parameters passed from userspace. In successful case return the size passed by usermode otherwise the error code is returned. That simplifies the parser helper and removes a potential error of returning mismatched input size. Signed-off-by:
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Joshua Aberback authored
[How] - use dc interface instead of hwss interface in cursor functions, to keep dc->idle_optimizations_allowed updated - add dc interface to check if idle optimizations might apply to a plane Signed-off-by:
Joshua Aberback <joshua.aberback@amd.com> Acked-by:
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Eric Yang authored
[Why] Send stream active state info to DMUB [How] Implement GPINT to notify stream mask Signed-off-by:
Eric Yang <Eric.Yang2@amd.com> Acked-by:
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Aric Cyr authored
Signed-off-by:
Aric Cyr <aric.cyr@amd.com> Acked-by:
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Anthony Koo authored
| [Header Changes] | - Add debug flag to log line numbers for PSR debug Signed-off-by:
Anthony Koo <Anthony.Koo@amd.com> Acked-by:
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Martin Leung authored
why: some functions may need be dependent on stutter period in the future how: Extract from stutter calculations and place into perf_params structure Signed-off-by:
Martin Leung <martin.leung@amd.com> Acked-by:
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Eryk Brol authored
[why] We need a virtual tool that would emulate a physical connector unplug to usermode, while connector is still physically plugged in. [how] Added a new option to debugfs entry "trigger_hotplug". It emulates hotplug irq handling scenario by clearing DC and DM connector states. It can be triggered with the following command: echo 0 > /sys/kernel/debug/dri/0/DP-X/trigger_hotplug Signed-off-by:
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Eryk Brol authored
[why] For debug purposes we want not to enable DSC on certain connectors even if algorithm deesires to do so, instead it should enable DSC on other capable connectors or fail the atomic check. [how] Adding the third option to connector's debugfs entry dsc_clock_en. Accepted inputs: 0x0 - connector is using default DSC enablement policy 0x1 - force enable DSC on the connector, if it supports DSC 0x2 - force disable DSC on the connector, if DSC is supported Ex. # echo 0x2 > /sys/kernel/debug/dri/0/DP-1/dsc_clock_en Signed-off-by: -
Dmytro Laktyushkin authored
This allows us to reuse these on different asics. Signed-off-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by:
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Aric Cyr authored
[Why] DCValidator is created/destroyed repeatedly for cofunctional validation which causes a lot of memory thrashing, particularly when Driver Verifer is enabled. [How] Implement a basic caching algorithm that will cache DCValidator with a matching topology. When a match is found, the DCValidator can be reused. If there is no match, a new one will be created and inserted into the cache if there is space or an unreference entry can be evicted. Signed-off-by:
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Zhan Liu authored
[Why] Idle optimization and PSR conflict each other. If both enabled at the same time, display flickering will be observed. [How] Disable idle optimization when PSR is enabled. Signed-off-by:
Zhan Liu <zhan.liu@amd.com> Acked-by:
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Bhawanpreet Lakha authored
[Why] Previously we were only calling add_topology when hdcp was being enabled. Now we call add_topology by default so the ERROR messages are printed if the firmware is not loaded. This error message is not relevant for normal display functionality so no need to print a ERROR message. [How] Change DRM_ERROR to DRM_INFO Signed-off-by:
Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Acked-by:
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Alvin Lee authored
[Why] There are situations where we go from 2 pipe to 1 pipe in MPO, but this isn't a pipe split being lost -- it's a plane disappearing in (i.e. video overlay goes away) so we lose one pipe. In these situations we don't want to disable the pipe in a separate operation from the rest of the pipe programming sequence. We only want to disable a pipe in a separate operation when we're actually disabling pipe split. [How] Make sure the pipe being lost has the same stream AND plane as the old top pipe to ensure. Signed-off-by:
Alvin Lee <alvin.lee2@amd.com> Acked-by:
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Zhan Liu authored
[Why] PSR needs to be enabled on DCN30. This is the driver part of PSR enablement. Also disabled retired DMCU on driver side, since DMCU is not supported on DCN30 anymore. [How] Add necessary changes to enable PSR on DCN30. Signed-off-by:
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Roman Li authored
[Why] ABM feature initialization was not executed due to early return. dm_late_init() had an early return in case if DMCU is not used. With the implementation of ABM on DMUB, DMCU can be disabled but ABM still needs to be initialized. [How] Remove verification for DMCU from the top of the function. The existing logic will handle the case when DMCU is not used. Signed-off-by:
Roman Li <roman.li@amd.com> Acked-by:
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George Shen authored
[Why] The function set_mst_bandwidth is poorly name since it isn't clear what it does, and it also does not reflect any part of the allocation sequence described in the DP spec. [How] Rename the function set_mst_bandwidth to set_throttled_vcp_size. Signed-off-by:
George Shen <george.shen@amd.com> Acked-by:
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Aric Cyr authored
[Why] When pipe locks are being taken we wait for flip pending to clear first. In some cases the pipe mapping is changed and the pending we're checking for will never clear. [How] Don't check disabled pipes for flip pending. Signed-off-by:
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Aidan Gratton authored
[HOW & WHY] Change max EDID size constant to 1280 to support 10-block EDIDs. Signed-off-by:
Aidan Gratton <Aidan.Gratton@amd.com> Acked-by:
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Ashley Thomas authored
[why] When link training failures occur for eDP, dp_disable_link_phy is called which powers OFF eDP panel. After link training retry delay, the next retry begins by calling dp_enable_link_phy which does not issue a correspnding eDP panel power ON, leaving panel powered OFF which leads to display OFF/dark. [how] Power ON eDP before next link training retry. Signed-off-by:
Ashley Thomas <Ashley.Thomas2@amd.com> Acked-by:
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Harmanprit Tatla authored
[Why] Currently clearing the wrong bit for CP_IRQ, and logic on when to clear needs to be fixed. [How] Corrected bit to clear and improved logic for decision to clear. Signed-off-by:
Harmanprit Tatla <harmanprit.tatla@amd.com> Acked-by:
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Wesley Chalmers authored
[WHY] Only the first pipe in ODM combine group should have nonzero recout offset. All other pipes should have recout offset 0; otherwise there will be gaps in the image. [HOW] Set recout.x to 0 if the pipe is not the leftmost ODM pipe. When computing viewports, calculate the horizontal offset of a pipe's src based on the current pipe's position in the ODM group, plus whatever offset the leftmost ODM pipe has; otherwise there will be discontinuity in the image. Since ODM combine can only combine pipes horizontally, nothing needs to be done for recout.y. Signed-off-by:
Wesley Chalmers <Wesley.Chalmers@amd.com> Acked-by:
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Wenjing Liu authored
[why] The cr training aux rd interval is modified without following specs requirements. According to the commit message the change was not intended to modify the value. Therefore it looks like it is caused by a typo in the change. Signed-off-by:
Wenjing Liu <wenjing.liu@amd.com> Acked-by:
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Aric Cyr authored
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Anthony Koo authored
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Rodrigo Siqueira authored
During the load processes for Renoir, our display code needs to retrieve the SMU clock and voltage table, however, this operation can fail which means that we have to check this scenario. Currently, we are not handling this case properly and as a result, we have seen the following dmesg log during the boot: RIP: 0010:rn_clk_mgr_construct+0x129/0x3d0 [amdgpu] ... Call Trace: dc_clk_mgr_create+0x16a/0x1b0 [amdgpu] dc_create+0x231/0x760 [amdgpu] This commit fixes this issue by checking the return status retrieved from the clock table before try to populate any bandwidth. Signed-off-by:
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Acked-by:
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Aric Cyr authored
Disable triplebuffering by default. Signed-off-by:
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Wenjing Liu authored
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Joshua Aberback authored
[Why] This assert triggers a false negative because there are more than 4 MPCCs on many asics. [How] - change assert comparisson - remove unused variable Signed-off-by:
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Harmanprit Tatla authored
[Why] Currently we do not clear the CP_IRQ bit upon receiving it. [How] Added a function to clear CP_IRQ bit. Signed-off-by:
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JinZe.Xu authored
[Why] If plane has changed, dcn20_detect_pipe_changes doesn't update dc_plane_state->update_flags, and the following dcn20_program_pipe can't reprogram hubp correctly. [How] Add a new flags bit "plane_changed" in pipe_ctx->update_flags.If old plane isn’t identical to new plane, this bit will be set and guide “dcn20_program_pipe” to programing HUBP correctly. Signed-off-by:
JinZe.Xu <JinZe.Xu@amd.com> Acked-by:
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Naveed Ashfaq authored
[why] Changing to smaller modes on OLED panel caused a blue screen crash as driver reported dram change during vactive when it shouldn't [how] Added an extra condition to prevent incorrect dram change timing Signed-off-by:
Naveed Ashfaq <Naveed.Ashfaq@amd.com> Acked-by:
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Aric Cyr authored
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Anthony Koo authored
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Jiansong Chen authored
This avoids smu issue when enabling runtime pptable update for sienna_cichlid and so on. Runtime pptable udpate is needed for test and debug purpose. Signed-off-by:
Jiansong Chen <Jiansong.Chen@amd.com> Reviewed-by:
Kenneth Feng <kenneth.feng@amd.com> Reviewed-by:
Evan Quan <evan.quan@amd.com> Signed-off-by:
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Flora Cui authored
use bool directly Signed-off-by:
Flora Cui <flora.cui@amd.com> Reviewed-by:
Guchun Chen <guchun.chen@amd.com> Signed-off-by:
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Mukul Joshi authored
SDMA utilization calculations are enabled/disabled by writing to SDMAx_PUB_DUMMY_REG2 register. Currently, enable this only for Arcturus. Signed-off-by:
Mukul Joshi <mukul.joshi@amd.com> Reviewed-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
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Aurabindo Pillai authored
[Why&How] Since there is no need for accessing crtc state in the interrupt handler, interrupts need not be disabled well in advance, and can be moved to commit_tail where it should be. Reviewed-by:
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by:
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Aurabindo Pillai authored
[Why&How] Currently commit_tail holds global locks and wait for dependencies which is against the DRM API contracts. Inorder to fix this, IRQ handler should be able to run without having to access crtc state. Required parameters are copied over so that they can be directly accessed from the interrupt handler Reviewed-by:
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