- 26 Sep, 2017 40 commits
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Alex Deucher authored
Signed-off-by:Alex Deucher <alexander.deucher@amd.com>
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Bhawanpreet Lakha authored
The pflip registor index was incorrect, this was overriding the macro and caused a dummy irq call. Signed-off-by:
Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Reviewed-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
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Shirish S authored
In the scenario of setting underlay, dc_validate_global_state() is called after constructing the context with all relevant bottom_pipe related configurations in dm_update_planes_state(). Currently, in dc_validate_global_state(), without checking for bottom_pipe's existence, the pipe_ctx structure is initialised to 0, hence nullyfying the plane_state of bottom_pipe which shall be accessed in populate_initial_data() called from bw_calcs(). Due to this null pointer access kernel panics and leads to reboot when underlay is tried to set. This patch fixes the issue by no longer clearing the top_pipe. This workaround is no longer required. Signed-off-by:
Shirish S <shirish.s@amd.com> Reviewed-by:
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Harry Wentland authored
It got refactored away and was never cleaned. Signed-off-by:
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Harry Wentland authored
Log DC init but default log level to 0 (default for amdgpu_dc_log) otherwise. Bug reporters can still make DC more chatty by using the dc_log module param. amdgpu.dc_log = 1 v2: Only provide runtime option, no compile time config Signed-off-by: -
Harry Wentland authored
Linux and Windows often desire different log levels. Signed-off-by:
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Harry Wentland authored
We want to make DC less chatty but still allow bug reporters to provide more detailed logs. Signed-off-by:
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Harry Wentland authored
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Harry Wentland authored
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Harry Wentland authored
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Harry Wentland authored
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Roman Li authored
- Fixing text console on FBC-enabled builds Signed-off-by:
Roman Li <Roman.Li@amd.com> Reviewed-by:
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Vitaly Prosyak authored
Signed-off-by:
Vitaly Prosyak <vitaly.prosyak@amd.com> Reviewed-by:
Charlene Liu <Charlene.Liu@amd.com> Reviewed-by:
Tony Cheng <Tony.Cheng@amd.com> Acked-by:
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Harry Wentland authored
The problem we're trying to fix is this (and similar): 1) X Desktop with single display 2) VT switch 3) Unplug display 4) VT switch back to X 5) re-plug same display Before this we'd fail at step 4 when trying to create a dc_stream_state because of a missing sink. This change will fake a sink in this case. The same scenario applies to S3 resume. Signed-off-by:
Andrey Grodzovsky <Andrey.Grodzovsky@amd.com> Acked-by:
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Harry Wentland authored
Stop using amdgpu_connector and roll our own. There is no overlap with amdgpu. Signed-off-by:
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pana authored
Signed-off-by:
Pandey, Arun <Arun.Pandey@amd.com> Reviewed-by:
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Harry Wentland authored
This simplifies clock source reprogramming a bit. Signed-off-by:
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Yue Hin Lau authored
Signed-off-by:
Yue Hin Lau <Yuehin.Lau@amd.com> Reviewed-by:
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Eric Bernstein authored
Signed-off-by:
Eric Bernstein <eric.bernstein@amd.com> Reviewed-by:
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Harry Wentland authored
This should be taken care of in validate now. All of timing sync is quite broken at the moment anyways. Will submit another patch set to address that. Signed-off-by:
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Harry Wentland authored
Still one more in dc_validate_global Signed-off-by:
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Harry Wentland authored
Powering down the clock source during unref is unsafe as we might want to unref during atomic_check Signed-off-by:
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Yue Hin Lau authored
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Andrew Jiang authored
Since there was no return statement in the fail block immediately preceding the context_alloc_fail block, any failure within the function caused a context alloc failed error message to be printed. Since the context_alloc_fail block is only used once, move it to where the goto is directly and accompany it with a return statement. Signed-off-by:
Andrew Jiang <Andrew.Jiang@amd.com> Reviewed-by:
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Tony Cheng authored
bug: default is mapped to no dithering. default to spatial dithering based on color depth Signed-off-by:
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Harry Wentland authored
This should only happen on full update. If this ever happens on regular pageflips it needs to be debugged. Signed-off-by:
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Charlene Liu authored
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Wenjing Liu authored
Signed-off-by:
Wenjing Liu <Wenjing.Liu@amd.com> Reviewed-by:
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Hersen Wu authored
RV1 support only USB-C active DP-2-HDMI dongle. HPD short pulse is generated only for DP signal. When processing HPD short pulse, it must be DP active dongle. No need for I2C-Over-AUX detection. v2: Add description Signed-off-by:
Hersen Wu <hersenxs.wu@amd.com> Reviewed-by:
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Shirish S authored
For MPO to work with per surface rendering and flipping, the previous logic of restricting plane[1] only as underlay needs to be removed. validate_surface_sets() now checks only the width and height bounds in case of underlay rather than checking format. Without this patch one cannot set underlay only. Signed-off-by:
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Hersen Wu authored
TODO: Current change only work for sucessive last fused pipe, like p3, or p3,p2. It does not work for fused p1,p2. Signed-off-by:
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Wenjing Liu authored
[Description] We originally use TPS4 phy test pattern for test pattern 7. On RV we switched to a new method to use CP2520. CP2520 should produce the same result. However in reality, it fails DP PHY automation test. We use the original method instead. Signed-off-by:
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Yongqiang Sun authored
Signed-off-by:
Yongqiang Sun <yongqiang.sun@amd.com> Reviewed-by:
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Yongqiang Sun authored
In case of vstartup happens before vsync, set vertical line start to 0. Signed-off-by:
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Logatharshan Thothiralingam authored
Signed-off-by:
Logatharshan Thothiralingam <logatharshan.thothiralingam@amd.com> Reviewed-by:
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Harry Wentland authored
No more need since Andrey's change to use drm_crtc's version Signed-off-by:
Michel Dänzer <michel.daenzer@amd.com> Signed-off-by:
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Yue Hin Lau authored
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Tony Cheng authored
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Harry Wentland authored
In a lot of case we fail validation of timings for legitimate reasons. No need to print an error. Signed-off-by:
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Harry Wentland authored
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