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  1. 22 Dec, 2015 3 commits
  3. 21 Dec, 2015 1 commit
    • Heiko Stuebner's avatar
      clk: rockchip: only enter pll slow-mode directly before reboots on rk3288 · dfff24bd
      Heiko Stuebner authored 
      As commit 1d33929e ("clk: rockchip: switch PLLs to slow mode before
reboot for rk3288") states, switching the PLLs to slow-mode is only
necessary when rebooting using the soft-reset done through the CRU.

The dwc2 controllers used create really big number of interrupts in
special constellations involving usb-hubs and their number is so high,
it can even overwhelm the interrupt handler if the cpu-speed os to low.

Right now the PLLs are put into slow-mode in a shutdown syscore_ops
callback which means it happens on all reboots (not only the soft-reset
ones) and even on poweroff actions.

This can result in the system not powering off and getting stuck instead,
so we should move the slow-mode change nearer to the actual reboot action.

For this we introduce the possiblity to also set a callback that gets
called from the restart-handler directly prior to restarting the system
and move the shutdown-callback to this new option.

With this the slow-mode switch is done only on the necessary reboots
and also has a smaller possibility of causing artifacts.

Fixes: 1d33929e ("clk: rockchip: switch PLLs to slow mode before reboot for rk3288")
Signed-off-by: default avatarHeiko Stuebner <heiko.stuebner@collabora.com>
Reviewed-by: default avatarDouglas Anderson <dianders@chromium.org>
      dfff24bd
  5. 16 Dec, 2015 1 commit
  7. 12 Dec, 2015 5 commits
  9. 09 Dec, 2015 2 commits
  11. 08 Dec, 2015 5 commits
  13. 03 Dec, 2015 4 commits
    • Heiko Stuebner's avatar
      clk: rockchip: fix rk3368 cpuclk divider offsets · 8ad0df33
      Heiko Stuebner authored 
      Due to a copy-paste error the the rk3368 cpuclk settings were acessing
rk3288-specific register offsets. This never caused problems till now,
as cpu frequency scaling in't used currently at all.
Reported-by: default avatarXing Zheng <zhengxing@rock-chips.com>
Signed-off-by: default avatarHeiko Stuebner <heiko@sntech.de>
      8ad0df33
    • Stephen Boyd's avatar
      Merge branch 'clk-fixes' into clk-next · 41cabbc2
      Stephen Boyd authored 
      * clk-fixes:
  clk: sunxi: pll2: Fix clock running too fast
  clk: scpi: add missing of_node_put
  clk: qoriq: fix memory leak
  imx/clk-pllv2: fix wrong do_div() usage
  imx/clk-pllv1: fix wrong do_div() usage
  clk: mmp: add linux/clk.h includes
  clk: ti: drop locking code from mux/divider drivers
  clk: ti816x: Add missing dmtimer clkdev entries
  clk: ti: fapll: fix wrong do_div() usage
  clk: ti: clkt_dpll: fix wrong do_div() usage
  clk: gpio: Get parent clk names in of_gpio_clk_setup()
      41cabbc2
    • Maxime Ripard's avatar
      clk: sunxi: pll2: Fix clock running too fast · 59f0ec23
      Maxime Ripard authored 
      Contrary to what the datasheet says, the pre divider doesn't seem to be
incremented by one in the PLL2, but just uses the value from the register,
with 0 being a bypass.

This fixes the audio playing too fast.

Since we now have the same pre-divider flags, and the only difference with
the A10 is the post-divider offset, also remove the structure to just pass
the offset as an argument.
Signed-off-by: default avatarMaxime Ripard <maxime.ripard@free-electrons.com>
Fixes: eb662f85 ("clk: sunxi: pll2: Add A13 support")
Signed-off-by: default avatarStephen Boyd <sboyd@codeaurora.org>
      59f0ec23
    • Masahiro Yamada's avatar
      clk: let of_clk_get_parent_name() fail for invalid clock-indices · 8da411cc
      Masahiro Yamada authored 
      Currently, of_clk_get_parent_name() returns a wrong parent clock name
when "clock-indices" property exists and the target index is not
found in the property.  In this case, NULL should be returned.

For example,

        oscillator {
                compatible = "myclocktype";
                #clock-cells = <1>;
                clock-indices = <1>, <3>;
                clock-output-names = "clka", "clkb";
        };

        consumer {
                compatible = "myclockconsumer";
                clocks = <&oscillator 0>, <&oscillator 1>;
        };

Currently, of_clk_get_parent_name(consumer_np, 0) returns "clka"
(and of_clk_get_parent_name(consumer_np, 1) also returns "clka",
this is correct).   Because the "clock-indices" in the clock parent
does not contain <0>, of_clk_get_parent_name(consumer_np, 0) should
return NULL.
Signed-off-by: default avatarMasahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: default avatarStephen Boyd <sboyd@codeaurora.org>
      8da411cc
  15. 02 Dec, 2015 1 commit
  17. 01 Dec, 2015 10 commits
    • Caesar Wang's avatar
      clk: rockchip: Force rk3368 PWM clock (and its parents) on · a7ce4050
      Caesar Wang authored 
      Most rk3368 boards (especially those with Pmic that followed the lead
from rk3368-evb-act8846) have a PWM regulator on them for vdd_logic.
This is the main voltage for all kinds of misc stuff including the
memory controller.

On these boards it is critically important to make sure that the PWM
never ever glitches and never loses its clock. Any glitch could
crash the system.

Right now there are no users of the PWM regulator and also Linux
thinks that the PWM regulator is disabled.  Things happen to work
because firmware configured the PWM and Linux doesn't touch it.
..and the PWM's clock is marked as "ignore unused".

...but things _stop_ working if we turn off serial console.  Why?
Because:
    1. Serial console shares a parent clock with the PWM (pclk_cpu)
    2. If we have no serial console then nobody is holding pclk_cpu on
       at reboot time.  It gets disabled.

We need to fix a lot of the above problems, but until we get
everything right the cleanest "hack" seems like it is to just keep
the "rk_pwm" clock on always.
Signed-off-by: default avatarCaesar Wang <wxt@rock-chips.com>
Signed-off-by: default avatarHeiko Stuebner <heiko@sntech.de>
      a7ce4050
    • Chris Zhong's avatar
      clk: rockchip: switch PLLs to slow mode before reboot for rk3288 · 1d33929e
      Chris Zhong authored 
      We've been seeing some crashes at reboot test on rk3288-based systems,
which boards have not reset pin connected to NPOR, they reboot by
setting 0xfdb9 to RK3288_GLB_SRST_FST register. If the APLL works in
a high frequency mode, some IPs might hang during soft reset.
It appears that we can fix the problem by switching to slow mode before
reboot, just like what we did before suspend.
Signed-off-by: default avatarChris Zhong <zyw@rock-chips.com>
Signed-off-by: default avatarHeiko Stuebner <heiko@sntech.de>
      1d33929e
    • Stephen Boyd's avatar
      Merge branch 'clk-msm8996' into clk-next · 0b9ddcc8
      Stephen Boyd authored 
      * clk-msm8996:
  clk: qcom: Add MSM8996 Multimedia Clock Controller (MMCC) driver
  clk: qcom: Add gfx3d ping-pong PLL frequency switching
  clk: qcom: Add MSM8996 Global Clock Control (GCC) driver
  clk: qcom: Add Alpha PLL support
  clk: divider: Cap table divider values to 'width' member
      0b9ddcc8
    • Stephen Boyd's avatar
      clk: qcom: Add MSM8996 Multimedia Clock Controller (MMCC) driver · c2526597
      Stephen Boyd authored 
      Add a driver for the multimedia clock controller found on MSM8996
based devices. This should allow most multimedia device drivers
to probe and control their clocks.
Signed-off-by: default avatarStephen Boyd <sboyd@codeaurora.org>
      c2526597
    • Stephen Boyd's avatar
      clk: qcom: Add gfx3d ping-pong PLL frequency switching · 55213e1a
      Stephen Boyd authored 
      The GPU clocks on msm8996 have three dedicated PLLs, MMPLL2,
MMPLL8, and MMPLL9. We leave MMPLL9 at the maximum speed (624
MHz), and we use MMPLL2 and MMPLL8 for the other frequencies. To
make switching frequencies faster, we ping-pong between MMPLL2
and MMPLL8 when we're switching between frequencies that aren't
the maximum. Implement custom rcg clk ops for this type of
frequency switching.
Signed-off-by: default avatarStephen Boyd <sboyd@codeaurora.org>
      55213e1a
    • Stephen Boyd's avatar
      clk: qcom: Add MSM8996 Global Clock Control (GCC) driver · b1e010c0
      Stephen Boyd authored 
      Add support for the global clock controller found on MSM8996
based devices. This should allow most non-multimedia device
drivers to probe and control their clocks.
Signed-off-by: default avatarStephen Boyd <sboyd@codeaurora.org>
      b1e010c0
    • Stephen Boyd's avatar
      clk: qcom: Add Alpha PLL support · 8ff1f4c4
      Stephen Boyd authored 
      Add support for configuring rates of, enabling, and disabling
Alpha PLLs. This is sufficient for the types of PLLs found in
the global and multimedia clock controllers.
Signed-off-by: default avatarStephen Boyd <sboyd@codeaurora.org>
      8ff1f4c4
    • Stephen Boyd's avatar
      clk: divider: Cap table divider values to 'width' member · fab88ca7
      Stephen Boyd authored 
      When we use a clk divider with a divider table, we limit the
maximum divider value in divider_get_val() to the
div_mask(width), but when we calculate the divider in
divider_round_rate() we don't consider that the maximum divider
may be limited by the width. Pass the width along to
_get_table_maxdiv() so that we only return the maximum divider
that is valid. This is useful for clocks that want to share the
same divider table while limiting the available dividers to some
subset of the table depending on the width of the bitfield.

Cc: Rajendra Nayak <rnayak@codeaurora.org>
Signed-off-by: default avatarStephen Boyd <sboyd@codeaurora.org>
      fab88ca7
    • Kuninori Morimoto's avatar
      clk: add CS2000 Fractional-N driver · 64dfbe24
      Kuninori Morimoto authored 
      This patch adds CS2000 Fractional-N driver as clock provider.
Signed-off-by: default avatarKuninori Morimoto <kuninori.morimoto.gx@renesas.com>
[sboyd@codeaurora.org: Fix unsigned checked for < 0 in
cs2000_ratio_get()]
Signed-off-by: default avatarStephen Boyd <sboyd@codeaurora.org>
      64dfbe24
    • Julia Lawall's avatar
      clk: scpi: add missing of_node_put · e80cf2e5
      Julia Lawall authored 
      for_each_available_child_of_node performs an of_node_get on each iteration,
so a break out of the loop requires an of_node_put.

The semantic patch that fixes this problem is as follows
(http://coccinelle.lip6.fr):

// <smpl>
@@
expression root,e;
local idexpression child;
@@

 for_each_available_child_of_node(root, child) {
   ... when != of_node_put(child)
       when != e = child
(
   return child;
|
+  of_node_put(child);
?  return ...;
)
   ...
 }
// </smpl>
Signed-off-by: default avatarJulia Lawall <Julia.Lawall@lip6.fr>
Acked-by: default avatarSudeep Holla <sudeep.holla@arm.com>
Signed-off-by: default avatarStephen Boyd <sboyd@codeaurora.org>
      e80cf2e5
  19. 30 Nov, 2015 6 commits
  21. 26 Nov, 2015 2 commits
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