- 15 May, 2020 3 commits
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Chris Ruehl authored
The original implementation set num_chipselect to ROCKCHIP_SPI_MAX_CS_NUM (2) which seems wrong here. spi0 has 2 native cs, all others just one. With enable and use of cs_gpiods / GPIO CS, its correct to set the num_chipselect from the num-cs property and set max_native_cs with the define. If num-cs is missing the default set to num_chipselect = 1. Signed-off-by:
Chris Ruehl <chris.ruehl@gtsys.com.hk> Link: https://lore.kernel.org/r/20200511083022.23678-4-chris.ruehl@gtsys.com.hkSigned-off-by:
Mark Brown <broonie@kernel.org>
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Chris Ruehl authored
Add support for spi slave mode in spi-rockchip. The register map has an entry for it. If spi-slave is set in dts, set this corresponding bit and add to mode_bits the SPI_NO_CS, allow slave mode without explicit CS use. Slave abort function had been added. Signed-off-by:
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Chris Ruehl authored
Cleanup, move from the compatibily layer struct spi_master over to struct spi_controller, and rename the related function calls. Signed-off-by:
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- 12 May, 2020 2 commits
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Andy Shevchenko authored
devm_platform_ioremap_resource() will issue a message in the error case. Thus, no need to duplicate in the driver. Signed-off-by:
Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20200512110315.58845-1-andriy.shevchenko@linux.intel.comSigned-off-by:
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Kunihiko Hayashi authored
Convert UniPhier SPI controller binding to DT schema format. Signed-off-by:
Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Reviewed-by:
Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/1587720562-15293-1-git-send-email-hayashi.kunihiko@socionext.comSigned-off-by:
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- 11 May, 2020 4 commits
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Jay Fang authored
Reduce unnecessary static memory allocation when CONFIG_ACPI is not enabled. Signed-off-by:
Jay Fang <f.fangjian@huawei.com> Link: https://lore.kernel.org/r/1588991392-24219-1-git-send-email-f.fangjian@huawei.comSigned-off-by:
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Alistair Francis authored
Set use_gpio_descriptors as true to support using generic GPIO lines for the chip select. Signed-off-by:
Alistair Francis <alistair@alistair23.me> Link: https://lore.kernel.org/r/20200511045330.690507-1-alistair@alistair23.meSigned-off-by:
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Kunihiko Hayashi authored
Use devm_platform_get_and_ioremap_resource() to simplify code instead of platform_get_resource() and devm_ioremap_resource(). This also gets the resource that the following code uses. Signed-off-by:
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Kunihiko Hayashi authored
The driver uses devm_ioremap_resource() which is only available when CONFIG_HAS_IOMEM is set, so the driver depends on this option. Signed-off-by:
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- 07 May, 2020 2 commits
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Andy Shevchenko authored
This flag is superfluous in all cases where it's being used, i.e. * ->can_dma() won't be called without dma_inited == 1 * DMA ->exit() callback can rely on txchan and rxchan variables So, get rid of dma_inited flag. Signed-off-by:
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Andy Shevchenko authored
Generic DMA setup doesn't rely on certain type of DMA controller and thus shouldn't use Intel Medfield settings, although it's harmless in this case. Signed-off-by:
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- 06 May, 2020 10 commits
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Jarkko Nikula authored
Elkhart Lake PSE SPI is capable to utilize PSE DMA engine which is described in ACPI. With help of acpi-dma module the support becomes a generic one. Thus, add Elkhart Lake PSE DMA support and generic DMA hooks in SPI DesignWare driver. Signed-off-by:
Jarkko Nikula <jarkko.nikula@linux.intel.com> Signed-off-by:
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Andy Shevchenko authored
In some cases, one of which is coming soon, we would like to have a struct device pointer to request DMA channel. For this purpose propagate it to ->dma_init() callback in DMA ops. Signed-off-by:
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Andy Shevchenko authored
In order to prepare driver for the extension to support newer hardware, add 'mfld' suffix to some related functions. While here, move DMA parameters assignment under existing #ifdef CONFIG_SPI_DW_MID_DMA. There is no functional change intended. Signed-off-by:
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Andy Shevchenko authored
There is no user of few headers without CONFIG_SPI_DW_MID_DMA being set. Move them under condition. While at it, remove unused slab.h there. Signed-off-by:
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Andy Shevchenko authored
spi-dw-mid.c along with spi-dw.h are direct users of irqreturn.h and nothing else is being used from interrupt.h. So, switch them to use the former instead of latter one. While here, move the header under #ifdef CONFIG_SPI_DW_MID_DMA in spi-dw-mid.c. Signed-off-by:
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Andy Shevchenko authored
The actual user of interrupt.h is spi-dw.h and not bus drivers. Move header there. Signed-off-by:
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Andy Shevchenko authored
After enabling new IP support in the driver couple of variables were left unused compiler is not happy about: .../spi-dw.c: In function ‘dw_spi_update_cr0’: .../spi-dw.c:264:17: warning: unused variable ‘dws’ [-Wunused-variable] 264 | struct dw_spi *dws = spi_controller_get_devdata(master); | ^~~ .../spi-dw.c: In function ‘dw_spi_update_cr0_v1_01a’: .../spi-dw.c:285:17: warning: unused variable ‘dws’ [-Wunused-variable] 285 | struct dw_spi *dws = spi_controller_get_devdata(master); | ^~~ Drop them for good. Signed-off-by: -
Andy Shevchenko authored
Some DMA controller drivers do not tolerate non-zero values in the DMA configuration structures. Zero them to avoid issues with such DMA controller drivers. Even despite above this is a good practice per se. Fixes: 7063c0d9 ("spi/dw_spi: add DMA support") Signed-off-by:
Feng Tang <feng.tang@intel.com> Cc: Feng Tang <feng.tang@intel.com> Link: https://lore.kernel.org/r/20200506153025.21441-1-andriy.shevchenko@linux.intel.comSigned-off-by:
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Wei Yongjun authored
Fix to return negative error code -ENOMEM from the dma mapping error handling case instead of 0, as done elsewhere in this function. Signed-off-by:
Wei Yongjun <weiyongjun1@huawei.com> Link: https://lore.kernel.org/r/20200506125607.90952-1-weiyongjun1@huawei.comSigned-off-by:
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Jason Yan authored
Fix the following coccicheck warning: drivers/spi/spi-armada-3700.c:283:8-11: Unneeded variable: "ret". Return "0" on line 315 Signed-off-by:
Jason Yan <yanaijie@huawei.com> Link: https://lore.kernel.org/r/20200506061911.19923-1-yanaijie@huawei.comSigned-off-by:
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- 05 May, 2020 9 commits
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Wan Ahmad Zainie authored
Document Intel Keem Bay SPI controller DT bindings. Signed-off-by:
Wan Ahmad Zainie <wan.ahmad.zainie.wan.mohamad@intel.com> Link: https://lore.kernel.org/r/20200505130618.554-7-wan.ahmad.zainie.wan.mohamad@intel.comSigned-off-by:
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Wan Ahmad Zainie authored
This patch adds compatible string "snps,dwc-ssi-1.01a" to the above DT binding document, to provide support for DesignWare DWC_ssi IP [1]. Current driver supports DW_apb_ssi IP [2]. References: [1] https://www.synopsys.com/dw/ipdir.php?c=dwc_ssi [2] https://www.synopsys.com/dw/ipdir.php?c=DW_apb_ssiSigned-off-by:
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Wan Ahmad Zainie authored
Add support for Intel Keem Bay SPI controller, which uses DesignWare DWC_ssi core. Bit 31 of CTRLR0 register is added for Keem Bay, to configure the device as a master or as a slave serial peripheral. Signed-off-by:
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Wan Ahmad Zainie authored
This patch adds initial support for DesignWare DWC_ssi soft IP. DWC_ssi is the enhanced version of DW_apb_ssi, which is currently supported by this driver. Their registers are same, but the bit fields of register CTRLR0 are different. DWC_ssi has additional features compared to DW_apb_ssi. Major enhancements in DWC_ssi are hyper bus protocol, boot mode support and advanced XIP support. DWC_ssi is an AHB slave device, whilst DW_apb_ssi is an APB slave device. Register offset DW_ssi DW_apb_ssi CTRLR0 0x00 0x00 CTRLR1 0x04 0x04 SSIENR 0x08 0x08 MWCR 0x0c 0x0c SER 0x10 0x10 BAUDR 0x14 0x14 TXFTLR 0x18 0x18 RXFTLR 0x1c 0x1c TXFLR 0x20 0x20 RXFLR 0x24 0x24 SR 0x28 0x28 IMR 0x2c 0x2c ISR 0x30 0x30 RISR 0x34 0x34 TXOICR 0x38 0x38 RXOICR 0x3c 0x3c RXUICR 0x40 0x40 MSTICR 0x44 0x44 ICR 0x48 0x48 DMACR 0x4c 0x4c DMATDLR 0x50 0x50 DMARDLR 0x54 0x54 IDR 0x58 0x58 SSI_VERSION_ID 0x5c 0x5c DRx (0 to 35) 0x60+i*0x4 0x60+i*0x4 RX_SAMPLE_DLY 0xf0 0xf0 SPI_CTRLR0 0xf4 0xf4 TXD_DRIVE_EDGE 0xf8 0xf8 XIP_MODE_BITS 0xfc RSVD Register configuration - CTRLR0 DW_ssi DW_apb_ssi SPI_HYPERBUS_EN bit[24] NONE SPI_FRF bit[23:22] bit[22:21] DFS_32 NONE bit[20:16] CFS bit[19:16] bit[15:12] SSTE bit[14] bit[24] SRL bit[13] bit[11] SLV_OE bit[12] bit[10] TMOD bit[11:10] bit[9:8] SCPOL | SPHA bit[9:8] bit[7:6] FRF bit[7:6] bit[5:4] DFS bit[4:0] bit[3:0] The documents used are [1] DW_apb_ssi_databook.pdf version 4.01a (2016.10a). [2] DWC_ssi_databook.pdf version 1.01a. Signed-off-by: -
Wan Ahmad Zainie authored
This patch adds update_cr0() callback, in struct dw_spi. Existing code that configure register CTRLR0 is moved into a new function, dw_spi_update_cr0(), and this will be the default. Suggested-by:
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Wan Ahmad Zainie authored
This patch will fix typo in the register name used in the source code, to be consistent with the register name used in the databook. Databook: DW_apb_ssi_databook.pdf version 4.01a Signed-off-by:
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Jacko Dirks authored
Signed-off-by:
Jacko Dirks <jdirks.linuxdev@gmail.com> Link: https://lore.kernel.org/r/20200503200033.GA3256@vasteMachineSigned-off-by:
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Mark Brown authored
Here's an assortment of drive-by fixes for the new AMD SPI driver. All of them are compile-tested only. Lukas Wunner (5): spi: amd: Fix duplicate iounmap in error path spi: amd: Pass probe errors back to driver core spi: amd: Drop duplicate driver data assignments spi: amd: Fix refcount underflow on remove spi: amd: Drop superfluous member from struct amd_spi drivers/spi/spi-amd.c | 27 +++++---------------------- 1 file changed, 5 insertions(+), 22 deletions(-) -- 2.26.2
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- 04 May, 2020 5 commits
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Lukas Wunner authored
The AMD SPI driver stores a pointer to the spi_master in struct amd_spi so that it can get from the latter to the former in amd_spi_fifo_xfer(). It's simpler to just pass the pointer from the sole caller amd_spi_master_transfer() and drop the pointer from struct amd_spi. Signed-off-by:
Lukas Wunner <lukas@wunner.de> Link: https://lore.kernel.org/r/a088b684ad292faf3bd036e51529e608e5c94638.1588590210.git.lukas@wunner.deSigned-off-by:
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Lukas Wunner authored
The AMD SPI driver calls spi_master_put() in its ->remove() hook even though the preceding call to spi_unregister_master() already drops a ref, thus leading to a refcount underflow. Drop the superfluous call to spi_master_put(). This only leaves the call to spi_unregister_master() in the ->remove() hook, so it's safe to change the ->probe() hook to use the devm version of spi_register_master() and drop the ->remove() hook altogether. Signed-off-by:
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Lukas Wunner authored
The AMD SPI driver calls platform_set_drvdata() on probe even though it's already been set by __spi_alloc_controller(). Likewise, it calls platform_set_drvdata() on remove even though it's going to be set by __device_release_driver(). Drop the duplicate assignments. Signed-off-by:
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Lukas Wunner authored
If probing fails, the AMD SPI driver pretends success to the driver core by returning 0. Return the errno instead. Signed-off-by:
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Lukas Wunner authored
The AMD SPI driver uses devm_ioremap_resource() to map its registers, so they're automatically unmapped via device_release() when the last ref on the SPI controller is dropped. The additional iounmap() in the ->probe() error path is thus unnecessary. Signed-off-by:
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- 30 Apr, 2020 2 commits
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Jules Irenge authored
Sparse reports a warning at atmel_spi_next_xfer_dma_submit() warning: context imbalance in atmel_spi_next_xfer_dma_submit() - unexpected unlock The root cause is the missing annotation at atmel_spi_next_xfer_dma_submit() Add the missing __must_hold(&as->lock) annotation Signed-off-by:
Jules Irenge <jbi.octave@gmail.com> Link: https://lore.kernel.org/r/20200429225723.31258-3-jbi.octave@gmail.comSigned-off-by:
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Evan Green authored
With a couple allies at Intel, and much badgering, I got confirmation from Intel that at least BXT suffers from the same SPI chip-select issue as Cannonlake (and beyond). The issue being that after going through runtime suspend/resume, toggling the chip-select line without also sending data does nothing. Add the quirk to BXT to briefly toggle dynamic clock gating off and on, forcing the fabric to wake up enough to notice the CS register change. Signed-off-by:
Evan Green <evgreen@chromium.org> Cc: Shobhit Srivastava <shobhit.srivastava@intel.com> Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20200427163238.1.Ib1faaabe236e37ea73be9b8dcc6aa034cb3c8804@changeidSigned-off-by:
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- 29 Apr, 2020 3 commits
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Patrice Chotard authored
Issue detected by unbinding/binding the stm32 qspi driver as following: root@stm32mp2:~# echo 40430000.spi > /sys/bus/platform/drivers/stm32-qspi/404300 00.spi/driver/unbind root@stm32mp2:~# echo 40430000.spi > /sys/bus/platform/drivers/stm32-qspi/bind [ 969.864021] stm32-qspi 40430000.spi: Unbalanced pm_runtime_enable! [ 970.225161] spi-nor spi0.0: mx66u51235f (65536 Kbytes) [ 970.935721] spi-nor spi0.1: mx66u51235f (65536 Kbytes) Fixes: 9d282c17 ("spi: stm32-qspi: Add pm_runtime support") Signed-off-by:
Patrice Chotard <patrice.chotard@st.com> Link: https://lore.kernel.org/r/20200429102625.25974-1-patrice.chotard@st.comSigned-off-by:
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Wei Yongjun authored
Fix to return negative error code -EPROBE_DEFER from the DMA probe defer error handling case instead of 0, as done elsewhere in this function. Signed-off-by:
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Wei Yongjun authored
In case of error, the function devm_ioremap_resource() returns ERR_PTR() and never returns NULL. The NULL test in the return value check should be replaced with IS_ERR(). Fixes: bbb336f3 ("spi: spi-amd: Add AMD SPI controller driver support") Signed-off-by:
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