Added LSDK-20.12 support and other enhancements / fixes

1. Added support for LSDK-20.12
2. Added initial support for secure boot; there are few atf patches that
will be added later
3. Fixed documentation in README.md withregards SPI flashing to use
cmp.b instead of cmp (the size is given in bytes)
4. Added ATF debug/release build environment variable
Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>

README.md

@@ -53,7 +53,7 @@ For SD card bootable images, plug in a micro SD into your machine and run the fo
 
 For SPI boot, boot thru SD card and then load the _xspi_ images to system memory and flash it using the `sf probe` and `sf update` commands. An example below loads the image through TFTP prototocl, flashes and then verifies the image -
 
-`sf probe; setenv ipaddr 192.168.15.223; setenv serverip 192.168.15.3; tftp 0xa0000000 lx2160acex7_xspi_2000_700_2600_8_5_2_xspi.img;sf update 0xa0000000 0 $filesize; sf read 0xa4000000 0 $filesize; cmp 0xa0000000 0xa4000000 $filesize`
+`sf probe; setenv ipaddr 192.168.15.223; setenv serverip 192.168.15.3; tftp 0xa0000000 lx2160acex7_xspi_2000_700_2600_8_5_2_xspi.img;sf update 0xa0000000 0 $filesize; sf read 0xa4000000 0 $filesize; cmp.b 0xa0000000 0xa4000000 $filesize`
 
 And then set boot DIP switch on COM to off/off/off/off from numbers 1 to 4 (dip number 5 is not used. Notice the marking 'ON' on the DIP switch)
 

patches/linux-LSDK-20.12/0001-arm64-dts-lx2160a-add-lx2160acex7-device-tree-build.patch

+From 9adba7be66753c3d8edce52c2d0afb0d6328ec03 Mon Sep 17 00:00:00 2001
+From: Rabeeh Khoury <rabeeh@solid-run.com>
+Date: Thu, 7 Jan 2021 17:03:59 +0200
+Subject: [PATCH] arm64: dts: lx2160a: add lx2160acex7 device tree build
+
+Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
+---
+ arch/arm64/boot/dts/freescale/Makefile | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
+index c3880d663..4aed43ff4 100644
+--- a/arch/arm64/boot/dts/freescale/Makefile
++++ b/arch/arm64/boot/dts/freescale/Makefile
+@@ -49,6 +49,7 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-rdb.dtb
+ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-qds.dtb
+ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-rdb.dtb
+ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2162a-qds.dtb
++dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-cex7.dtb
+ 
+ dtb-$(CONFIG_ARCH_MXC) += imx8mm-evk.dtb imx8mm-evk-rpmsg.dtb imx8mm-evk-rm67191.dtb \
+ 			  imx8mm-ddr4-evk.dtb imx8mm-evk-root.dtb imx8mm-evk-inmate.dtb \
+-- 
+2.25.1
+

patches/linux-LSDK-20.12/0002-arm64-dts-lx2160a-add-lx2160acex7-device-tree.patch

+From 35dc5b03bb8f7b93fb474c39d7689d39062ff81a Mon Sep 17 00:00:00 2001
+From: Rabeeh Khoury <rabeeh@solid-run.com>
+Date: Sun, 28 Jul 2019 14:21:06 +0300
+Subject: [PATCH 2/3] arm64: dts: lx2160a: add lx2160acex7 device tree
+
+The device tree enables the following features -
+1. dpmac17 RGMII MAC connected to Atheros AR8035 phy
+2. 2x MDIO busses
+3. 2x USB 3.0 controllers
+4. 4x SATA ports
+5. MT35X 512Mb SPI flash
+6. Temperature sensor on i2c0 channel 3
+7. AMC6821 temperature and PWM fan controller
+
+The module supports AMC6821 and EMC2301 PWM controllers where either can
+be assembled, but not both together since the PWM and TACH signals are
+shared between them.
+
+Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
+---
+ .../boot/dts/freescale/fsl-lx2160a-cex7.dts   | 190 ++++++++++++++++++
+ 1 file changed, 190 insertions(+)
+ create mode 100644 arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dts
+
+diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dts b/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dts
+new file mode 100644
+index 000000000000..872fcf9e724d
+--- /dev/null
++++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dts
+@@ -0,0 +1,190 @@
++// SPDX-License-Identifier: (GPL-2.0 OR MIT)
++//
++// Device Tree file for LX2160A-CEx7
++//
++// Copyright 2019 SolidRun ltd.
++
++/dts-v1/;
++
++#include "fsl-lx2160a.dtsi"
++
++/ {
++	model = "SolidRun LX2160A COM express type 7 module";
++	compatible = "fsl,lx2160a-cex7", "fsl,lx2160a";
++
++	aliases {
++		crypto = &crypto;
++		serial0 = &uart0;
++		serial1 = &uart1;
++	};
++
++	chosen {
++		stdout-path = "serial0:115200n8";
++	};
++
++	sb_3v3: regulator-sb3v3 {
++		compatible = "regulator-fixed";
++		regulator-name = "RT7290";
++		regulator-min-microvolt = <3300000>;
++		regulator-max-microvolt = <3300000>;
++		regulator-boot-on;
++		regulator-always-on;
++	};
++};
++
++&crypto {
++	status = "okay";
++};
++
++&esdhc0 {
++	sd-uhs-sdr104;
++	sd-uhs-sdr50;
++	sd-uhs-sdr25;
++	sd-uhs-sdr12;
++	status = "okay";
++};
++
++&esdhc1 {
++	mmc-hs200-1_8v;
++	mmc-hs400-1_8v;
++	bus-width = <8>;
++	status = "okay";
++};
++
++
++/*
++i2c busses are -
++/dev/i2c0 - CTRL #0 - connected to PCA9547 I2C switch
++/dev/i2c1 - CTRL #2 - COM module to carrier (general I2C_CK/I2C_DAT)
++/dev/i2c2 - CTRL #4 - Connected to RTC PCF2129AT (0x51), EEPROM (0x54,0x55,0x56,0x57)
++
++I2C switch -
++/dev/i2c3 - CH0 - SO-DIMMs SPD (0x51, 0x53), 2Kb EEPROM (0x57), bootable 512Kb eeprom (0x50)
++/dev/i2c4 - CH1 - 100MHz clk gen (address 0x6a)
++/dev/i2c5 - CH2 - LTC3882 DC-DC controller on 0x63
++/dev/i2c6 - CH3 - SA56004ED (0x4c), SA56004FD (0x4d), COM module SMB_CK,SMB_DAT and COM module 10G_LED_SDA,10G_LED_SCL
++/dev/i2c7 - CH4 - SFP #0 I2C
++/dev/i2c8 - CH5 - SFP #1 I2C
++/dev/i2c9 - CH6 - SFP #2 I2C
++/dev/i2c10 - CH7 - SFP #3 I2C
++
++
++*/
++
++
++
++&i2c0 {
++	status = "okay";
++
++	i2c-mux@77 {
++		compatible = "nxp,pca9547";
++		reg = <0x77>;
++		#address-cells = <1>;
++		#size-cells = <0>;
++
++		i2c@1 {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			reg = <0x1>;
++			fan-temperature-ctrlr@18 {
++				compatible = "ti,amc6821";
++				reg = <0x18>;
++				cooling-min-state = <0>;
++				cooling-max-state = <9>;
++				#cooling-cells = <2>;
++			};
++		};
++		i2c@3 {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			reg = <0x3>;
++
++			temperature-sensor@48 {
++				compatible = "nxp,sa56004";
++				reg = <0x48>;
++				vcc-supply = <&sb_3v3>;
++			};
++		};
++	};
++};
++
++&i2c2 {
++	status = "okay";
++};
++
++&i2c4 {
++	status = "okay";
++
++	rtc@51 {
++		compatible = "nxp,pcf2129";
++		reg = <0x51>;
++		// IRQ10_B
++		interrupts = <0 150 0x4>;
++	};
++};
++
++&fspi {
++	status = "okay";
++	flash0: mt35xu512aba@0 {
++		#address-cells = <1>;
++		#size-cells = <1>;
++		compatible = "micron,m25p80";
++		m25p,fast-read;
++		spi-max-frequency = <50000000>;
++		reg = <0>;
++		/* The following setting enables 1-1-8 (CMD-ADDR-DATA) mode */
++		spi-rx-bus-width = <8>;
++		spi-tx-bus-width = <1>;
++	};
++};
++
++&uart0 {
++	status = "okay";
++};
++
++&uart1 {
++	status = "okay";
++};
++
++&usb0 {
++	status = "okay";
++};
++
++&usb1 {
++	status = "okay";
++};
++
++&emdio1 {
++	status = "okay";
++	rgmii_phy1: ethernet-phy@1 {
++		/* AR8035 PHY - "compatible" property not strictly needed */
++		compatible = "ethernet-phy-id004d.d072";
++		reg = <0x1>;
++		/* Poll mode - no "interrupts" property defined */
++	};
++};
++
++&emdio2 {
++	status = "okay";
++};
++
++&dpmac17 {
++	phy-handle = <&rgmii_phy1>;
++	phy-connection-type = "rgmii-id";
++};
++
++&sata0 {
++	status = "okay";
++};
++
++&sata1 {
++	status = "okay";
++};
++
++&sata2 {
++	status = "okay";
++};
++
++&sata3 {
++	status = "okay";
++};
+-- 
+2.17.1
+

patches/linux-LSDK-20.12/0005-arm64-dts-lx2160a-cex7-add-ltc3882-support.patch

+From cca2439ac83136b9ed85f8519931018d4f5385e6 Mon Sep 17 00:00:00 2001
+From: Rabeeh Khoury <rabeeh@solid-run.com>
+Date: Sun, 12 Jan 2020 14:24:47 +0200
+Subject: [PATCH] arm64: dts: lx2160a-cex7: add ltc3882 support
+
+ltc3882 is lx2 cortex-a72 core voltage.
+this patch adds it to the device tree support; the driver is in
+drivers/hwmon/pmbus/ltc2978.c
+
+Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
+---
+ arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dts | 9 +++++++++
+ 1 file changed, 9 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dts b/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dts
+index 872fcf9e724d..1c1a0d47897d 100644
+--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dts
++++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dts
+@@ -94,6 +94,15 @@ I2C switch -
+ 				#cooling-cells = <2>;
+ 			};
+ 		};
++		i2c@2 {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			reg = <0x2>;
++			ltc3882@5c {
++				compatible = "ltc3882";
++				reg = <0x5c>;
++			};
++		};
+ 		i2c@3 {
+ 			#address-cells = <1>;
+ 			#size-cells = <0>;
+-- 
+2.17.1
+

patches/linux-LSDK-20.12/0006-arm64-dts-lx2160a-cex7-add-on-module-eeproms.patch

+From 05acb6ecc8eb7426c4664a1e8fd22ad69256d541 Mon Sep 17 00:00:00 2001
+From: Rabeeh Khoury <rabeeh@solid-run.com>
+Date: Sun, 26 Jan 2020 15:36:07 +0200
+Subject: [PATCH] arm64: dts: lx2160a-cex7: add on-module eeproms
+
+This patch adds 4 eeprom support on i2c mux channel #0 -
+1. Bootable 512Kbit eeprom at address 0x50.
+2. Memory SO-DIMMs SPD channels at 0x51 (upper SO-DIMM) and 0x53.
+3. 2Kb eeprom at 0x57 will be used by SolidRun to hold manufacturing
+data.
+
+Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
+---
+ .../boot/dts/freescale/fsl-lx2160a-cex7.dts   | 22 ++++++++++++++++++-
+ 1 file changed, 21 insertions(+), 1 deletion(-)
+
+diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dts b/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dts
+index 1c1a0d47897d..2b8f1118b37a 100644
+--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dts
++++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dts
+@@ -81,7 +81,27 @@ I2C switch -
+ 		reg = <0x77>;
+ 		#address-cells = <1>;
+ 		#size-cells = <0>;
+-
++		i2c@0 {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			reg = <0x0>;
++			24aa512@50 {
++				compatible = "atmel,24c512";
++				reg = <0x50>;
++			};
++			spd1@51 {
++				compatible = "atmel,spd";
++				reg = <0x51>;
++			};
++			spd2@53 {
++				compatible = "atmel,spd";
++				reg = <0x53>;
++			};
++			m24c02@57 {
++				compatible = "atmel,24c02";
++				reg = <0x57>;
++			};
++		};
+ 		i2c@1 {
+ 			#address-cells = <1>;
+ 			#size-cells = <0>;
+-- 
+2.17.1
+

patches/linux-LSDK-20.12/0009-usb-dwc3-core-add-support-for-disabling-SS-instances.patch

+From 2ce0d3a0c1e218d6e680115da21a0e9c180db845 Mon Sep 17 00:00:00 2001
+From: Rabeeh Khoury <rabeeh@solid-run.com>
+Date: Wed, 28 Oct 2020 20:06:16 +0200
+Subject: [PATCH] usb: dwc3: core: add support for disabling SS instances in
+ park mode
+
+This is a backport from mainline -
+commit 7ba6b09fda5e0cb741ee56f3264665e0edc64822
+Author: Neil Armstrong <narmstrong@baylibre.com>
+Date:   Fri Feb 21 10:15:31 2020 +0100
+
+   In certain circumstances, the XHCI SuperSpeed instance in park mode
+    can fail to recover, thus on Amlogic G12A/G12B/SM1 SoCs when there is high
+    load on the single XHCI SuperSpeed instance, the controller can crash like:
+     xhci-hcd xhci-hcd.0.auto: xHCI host not responding to stop endpoint command.
+     xhci-hcd xhci-hcd.0.auto: Host halt failed, -110
+     xhci-hcd xhci-hcd.0.auto: xHCI host controller not responding, assume dead
+     xhci-hcd xhci-hcd.0.auto: xHCI host not responding to stop endpoint command.
+     hub 2-1.1:1.0: hub_ext_port_status failed (err = -22)
+     xhci-hcd xhci-hcd.0.auto: HC died; cleaning up
+     usb 2-1.1-port1: cannot reset (err = -22)
+
+    Setting the PARKMODE_DISABLE_SS bit in the DWC3_USB3_GUCTL1 mitigates
+    the issue. The bit is described as :
+    "When this bit is set to '1' all SS bus instances in park mode are disabled"
+
+    Synopsys explains:
+    The GUCTL1.PARKMODE_DISABLE_SS is only available in
+    dwc_usb3 controller running in host mode.
+    This should not be set for other IPs.
+    This can be disabled by default based on IP, but I recommend to have a
+    property to enable this feature for devices that need this.
+
+    CC: Dongjin Kim <tobetter@gmail.com>
+    Cc: Jianxin Pan <jianxin.pan@amlogic.com>
+    Cc: Thinh Nguyen <thinhn@synopsys.com>
+    Cc: Jun Li <lijun.kernel@gmail.com>
+    Reported-by: Tim <elatllat@gmail.com>
+    Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
+    Signed-off-by: Felipe Balbi <balbi@kernel.org>
+
+Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
+---
+ arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 2 ++
+ drivers/usb/dwc3/core.c                        | 5 +++++
+ drivers/usb/dwc3/core.h                        | 4 ++++
+ 3 files changed, 11 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
+index fe9b8bf4d..201bc2292 100644
+--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
++++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
+@@ -994,6 +994,7 @@
+ 			snps,dis_rxdet_inp3_quirk;
+ 			snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
+ 			snps,host-vbus-glitches;
++			snps,parkmode-disable-ss-quirk;
+ 			dma-coherent;
+ 			status = "disabled";
+ 		};
+@@ -1009,6 +1010,7 @@
+ 			snps,dis_rxdet_inp3_quirk;
+ 			snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
+ 			snps,host-vbus-glitches;
++			snps,parkmode-disable-ss-quirk;
+ 			status = "disabled";
+ 		};
+ 
+diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
+index 5ed5a57f3..870f9cb14 100644
+--- a/drivers/usb/dwc3/core.c
++++ b/drivers/usb/dwc3/core.c
+@@ -1064,6 +1064,9 @@ static int dwc3_core_init(struct dwc3 *dwc)
+ 		if (dwc->dis_tx_ipgap_linecheck_quirk)
+ 			reg |= DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS;
+ 
++		if (dwc->parkmode_disable_ss_quirk)
++			reg |= DWC3_GUCTL1_PARKMODE_DISABLE_SS;
++
+ 		dwc3_writel(dwc->regs, DWC3_GUCTL1, reg);
+ 	}
+ 
+@@ -1400,6 +1403,8 @@ static void dwc3_get_properties(struct dwc3 *dwc)
+ 				"snps,dis-del-phy-power-chg-quirk");
+ 	dwc->dis_tx_ipgap_linecheck_quirk = device_property_read_bool(dev,
+ 				"snps,dis-tx-ipgap-linecheck-quirk");
++	dwc->parkmode_disable_ss_quirk = device_property_read_bool(dev,
++				"snps,parkmode-disable-ss-quirk");
+ 
+ 	dwc->tx_de_emphasis_quirk = device_property_read_bool(dev,
+ 				"snps,tx_de_emphasis_quirk");
+diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
+index 1ea3c50d2..63f0b5fb3 100644
+--- a/drivers/usb/dwc3/core.h
++++ b/drivers/usb/dwc3/core.h
+@@ -266,6 +266,7 @@
+ #define DWC3_GUCTL_HSTINAUTORETRY	BIT(14)
+ 
+ /* Global User Control 1 Register */
++#define DWC3_GUCTL1_PARKMODE_DISABLE_SS	BIT(17)
+ #define DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS	BIT(28)
+ #define DWC3_GUCTL1_DEV_L1_EXIT_BY_HW	BIT(24)
+ #define DWC3_GUCTL1_PARKMODE_DISABLE_SS	BIT(17)
+@@ -1041,6 +1042,8 @@ struct dwc3_scratchpad_array {
+  *			change quirk.
+  * @dis_tx_ipgap_linecheck_quirk: set if we disable u2mac linestate
+  *			check during HS transmit.
++ * @parkmode_disable_ss_quirk: set if we need to disable all SuperSpeed
++ *			instances in park mode.
+  * @tx_de_emphasis_quirk: set if we enable Tx de-emphasis quirk
+  * @tx_de_emphasis: Tx de-emphasis value
+  * 	0	- -6dB de-emphasis
+@@ -1236,6 +1239,7 @@ struct dwc3 {
+ 	unsigned		dis_u2_freeclk_exists_quirk:1;
+ 	unsigned		dis_del_phy_power_chg_quirk:1;
+ 	unsigned		dis_tx_ipgap_linecheck_quirk:1;
++	unsigned		parkmode_disable_ss_quirk:1;
+ 
+ 	unsigned		tx_de_emphasis_quirk:1;
+ 	unsigned		tx_de_emphasis:2;
+-- 
+2.25.1
+

patches/linux-LSDK-20.12/0010-arm64-dts-lx2160a-cex7-add-power-button-support.patch

+From b640a74851bf1fdc3abe49860e9efc498e4483a8 Mon Sep 17 00:00:00 2001
+From: Rabeeh Khoury <rabeeh@solid-run.com>
+Date: Tue, 8 Dec 2020 13:21:03 +0200
+Subject: [PATCH] arm64: dts: lx2160a-cex7: add power button support
+
+COM express PWRBTN# signal is connected as a GPIO to the LX2 SoC.
+Translate that power button click as KEY_POWER event.
+
+Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
+---
+ arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dts | 12 ++++++++++++
+ 1 file changed, 12 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dts b/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dts
+index 2b8f1118b..e2dfe4f67 100644
+--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dts
++++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dts
+@@ -7,6 +7,7 @@
+ /dts-v1/;
+ 
+ #include "fsl-lx2160a.dtsi"
++#include <dt-bindings/input/linux-event-codes.h>
+ 
+ / {
+ 	model = "SolidRun LX2160A COM express type 7 module";
+@@ -30,6 +31,17 @@
+ 		regulator-boot-on;
+ 		regulator-always-on;
+ 	};
++
++	gpio-keys {
++		compatible = "gpio-keys";
++
++		key {
++			label = "power";
++			linux,can-disable;
++			linux,code = <KEY_POWER>;
++			gpios = <&gpio2 6 GPIO_ACTIVE_LOW>;
++		};
++	};
+ };
+ 
+ &crypto {
+-- 
+2.25.1
+

patches/linux-LSDK-20.12/0011-aarm64-dts-lx2160a-cex7-add-secondary-spi-flash-supp.patch

+From 08ff0cc811d9e4616aad53b39e528544b0979fd7 Mon Sep 17 00:00:00 2001
+From: yazan shhady <yazan.shhady@solid-run.com>
+Date: Sun, 22 Nov 2020 14:44:32 +0200
+Subject: [PATCH] aarm64: dts: lx2160a-cex7: add secondary spi flash support
+
+---
+ arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dts | 10 ++++++++++
+ 1 file changed, 10 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dts b/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dts
+index 2b8f1118b37a..6f031412400a 100644
+--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dts
++++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dts
+@@ -165,6 +165,16 @@ I2C switch -
+ 		spi-rx-bus-width = <8>;
+ 		spi-tx-bus-width = <1>;
+ 	};
++	flash1: w25q32@1 {
++                #address-cells = <1>;
++                #size-cells = <1>;
++                compatible = "st,w25q32";
++                spi-max-frequency = <10000000>;
++                reg = <1>;
++                spi-rx-bus-width = <1>;
++                spi-tx-bus-width = <1>;
++        };
++
+ };
+ 
+ &uart0 {
+-- 
+2.25.1
+

patches/rcw-LSDK-20.12/0002-Set-io-pads-as-GPIO.patch

+From b184697cff85d8f98e765014309b97444ff1c5b7 Mon Sep 17 00:00:00 2001
+From: Rabeeh Khoury <rabeeh@solid-run.com>
+Date: Wed, 30 Oct 2019 11:43:37 +0200
+Subject: [PATCH 2/2] Set io pads as GPIO
+
+Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
+---
+ lx2160acex7/configs/lx2160a_defaults.rcwi | 9 +++++++--
+ 1 file changed, 7 insertions(+), 2 deletions(-)
+
+diff --git a/lx2160acex7/configs/lx2160a_defaults.rcwi b/lx2160acex7/configs/lx2160a_defaults.rcwi
+index 6fd65ec..dbc843f 100644
+--- a/lx2160acex7/configs/lx2160a_defaults.rcwi
++++ b/lx2160acex7/configs/lx2160a_defaults.rcwi
+@@ -9,11 +9,16 @@ HWA_CGA_M1_CLK_SEL=1
+ HWA_CGB_M1_CLK_SEL=7
+ BOOT_LOC=26
+ SYSCLK_FREQ=600
+-IIC2_PMUX=6
++IIC2_PMUX=1
+ IIC3_PMUX=0
+ IIC4_PMUX=2
+ USB3_CLK_FSEL=39
+ SRDS_DIV_PEX_S1=1
+ SRDS_DIV_PEX_S2=3
+ SRDS_DIV_PEX_S3=1
+-
++SDHC1_DIR_PMUX=1
++IRQ03_00_PMUX=1
++IRQ07_04_PMUX=1
++IRQ11_08_PMUX=1
++EVT20_PMUX=1
++EVT43_PMUX=1
+-- 
+2.17.1
+

patches/rcw-LSDK-20.12/0003-S2-enable-gen3-xspi-increase-divisor-to-28.patch

+From 3b0e8b6e242549c2ed992d7556d7966a77b6da86 Mon Sep 17 00:00:00 2001
+From: Rabeeh Khoury <rabeeh@solid-run.com>
+Date: Tue, 5 Nov 2019 10:35:32 +0200
+Subject: [PATCH] S2 - enable gen3, xspi increase divisor to 28
+
+Serdes group 2 enable PCIe gen 3
+XSPI increase divisor to 28 - this fixes UEFI SPI flash detection.
+
+Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
+---
+ lx2160acex7/configs/lx2160a_defaults.rcwi | 2 +-
+ lx2160acex7/configs/lx2160a_xspiboot.rcwi | 2 +-
+ 2 files changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/lx2160acex7/configs/lx2160a_defaults.rcwi b/lx2160acex7/configs/lx2160a_defaults.rcwi
+index dbc843f..3ea7683 100644
+--- a/lx2160acex7/configs/lx2160a_defaults.rcwi
++++ b/lx2160acex7/configs/lx2160a_defaults.rcwi
+@@ -14,7 +14,7 @@ IIC3_PMUX=0
+ IIC4_PMUX=2
+ USB3_CLK_FSEL=39
+ SRDS_DIV_PEX_S1=1
+-SRDS_DIV_PEX_S2=3
++SRDS_DIV_PEX_S2=1
+ SRDS_DIV_PEX_S3=1
+ SDHC1_DIR_PMUX=1
+ IRQ03_00_PMUX=1
+diff --git a/lx2160acex7/configs/lx2160a_xspiboot.rcwi b/lx2160acex7/configs/lx2160a_xspiboot.rcwi
+index eecc314..28310c9 100644
+--- a/lx2160acex7/configs/lx2160a_xspiboot.rcwi
++++ b/lx2160acex7/configs/lx2160a_xspiboot.rcwi
+@@ -14,4 +14,4 @@
+ #include <../lx2160asi/common.rcw>
+ 
+ /* Modify FlexSPI Clock Divisor value */
+-#include <../lx2160asi/flexspi_divisor_24.rcw>
++#include <../lx2160asi/flexspi_divisor_28.rcw>
+-- 
+2.17.1
+

patches/rcw-LSDK-20.12/0004-refactor-a009531-a008851-and-a011270.patch

+From c7c3ed47f1de7c20de348a6ca5fe0d5a18912f4b Mon Sep 17 00:00:00 2001
+From: Rabeeh Khoury <rabeeh@solid-run.com>
+Date: Mon, 23 Mar 2020 12:16:13 +0200
+Subject: [PATCH 4/4] refactor a009531, a008851 and a011270
+
+1. Add 'load conditional', 'jump condidional' and 'jump' to PBI
+instructions.
+2. Use SVR register to execute the PCIe workarounds on the relevant rev
+of the device.
+
+Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
+---
+ lx2160asi/a009531_a008851.rcw | 96 +++++++++++++++++++++++++++++++++++
+ lx2160asi/a011270.rcw         |  6 +++
+ rcw.py                        | 28 ++++++++++
+ 3 files changed, 130 insertions(+)
+ create mode 100644 lx2160asi/a009531_a008851.rcw
+
+diff --git a/lx2160asi/a009531_a008851.rcw b/lx2160asi/a009531_a008851.rcw
+new file mode 100644
+index 0000000..0eb7051
+--- /dev/null
++++ b/lx2160asi/a009531_a008851.rcw
+@@ -0,0 +1,96 @@
++/*
++ * Work-around for erratum A-009531
++ *
++ * Description:
++ * As defined in section 2.2.6.4, Relaxed Ordering and ID-Based Ordering (IDO)
++ * Attributes of the PCI Express Base Specification Rev 3.1, “A Completer
++ * is permitted to set IDO only if the IDO Completion Enable bit in the Device
++ * Control 2 Register is set. It is not required to copy the value of IDO from
++ * the Request into the Completion(s) for that Request".
++ *
++ * However, the PCI Express controller as the completer sets the IDO bit in the
++ * completion packet header, in response to non-posted requests (memory read) with
++ * IDO bit set in the packet header, even if the IDO Completion Enable bit in the
++ * Device Control 2 Register is not set.
++ *
++ * Impact:
++ * The PCI Express controller as the completer sends completion packets with IDO
++ * bit set in packet header even when the IDO Completion Enable bit is cleared in
++ * the controller’s Device Control 2 Register.
++ * Applicable for SNP PCIe controller
++ */
++
++/*
++ * Work-around for erratum A-008851
++ *
++ * Invalid transmitter/receiver preset values are used in Gen3 equalization
++ * phases during link training for RC mode
++ * This errata is valid only for PCI gen3.
++ * Workaround:
++ *  write 0x00000001 to MISC_CONTROL_1_OFF
++ *  write 0x4747 to Lane Equalization Control register for each lane
++ * Applicable for SNP PCIe controller
++ */
++
++.pbi
++/* Load condition SVR register mask major ID */
++loadc 0x01e000a4,0x000000f0
++
++/* If it is rev 2, skip the following jump command */
++jumpc 0x00000014,0x00000020
++
++/* Jump all the below instructions */
++jump 0x190 /* All instruction below including the jump are 0x190 bytes */
++
++loadc 0x01ea1080,0x70000000
++jumpc 0x00000034,0x00000000 
++write 0x03400098,0x00000000
++write 0x034008bc,0x00000001
++write 0x03400154,0x47474747
++write 0x03400158,0x47474747
++write 0x034008bc,0x00000000
++
++loadc 0x01ea1080,0x00700000
++jumpc 0x00000034,0x00000000 
++write 0x03500098,0x00000000
++write 0x035008bc,0x00000001
++write 0x03500154,0x47474747
++write 0x03500158,0x47474747
++write 0x035008bc,0x00000000
++
++loadc 0x01eb1080,0x70000000
++jumpc 0x00000044,0x00000000 
++write 0x03600098,0x00000000
++write 0x036008bc,0x00000001
++write 0x03600164,0x47474747
++write 0x03600168,0x47474747
++write 0x0360016c,0x47474747
++write 0x03600170,0x47474747
++write 0x036008bc,0x00000000
++
++loadc 0x01eb1080,0x00700000
++jumpc 0x00000034,0x00000000 
++write 0x03700098,0x00000000
++write 0x037008bc,0x00000001
++write 0x03700154,0x47474747
++write 0x03700158,0x47474747
++write 0x037008bc,0x00000000
++
++loadc 0x01ec1080,0x70000000
++jumpc 0x00000044,0x00000000 
++write 0x03800098,0x00000000
++write 0x038008bc,0x00000001
++write 0x03800164,0x47474747
++write 0x03800168,0x47474747
++write 0x0380016c,0x47474747
++write 0x03800170,0x47474747
++write 0x038008bc,0x00000000
++
++loadc 0x01ec1080,0x00700000
++jumpc 0x00000034,0x00000000 
++write 0x03900098,0x00000000
++write 0x039008bc,0x00000001
++write 0x03900154,0x47474747
++write 0x03900158,0x47474747
++write 0x039008bc,0x00000000
++.end
+diff --git a/lx2160asi/a011270.rcw b/lx2160asi/a011270.rcw
+index 0dc774d..5bd5558 100644
+--- a/lx2160asi/a011270.rcw
++++ b/lx2160asi/a011270.rcw
+@@ -4,6 +4,12 @@
+  */
+ 
+ .pbi
++/* Load condition SVR register mask major ID */
++loadc 0x01e000a4,0x000000f0
++/* If it is rev 1, skip the following jump command */
++jumpc 0x00000014,0x00000010
++/* Skip the following instructions by jumping to the end */
++jump  0x38
+ write 0x03400688,0x00000001
+ write 0x03500688,0x00000001
+ write 0x03600688,0x00000001
+diff --git a/rcw.py b/rcw.py
+index 863f755..c2d06f6 100755
+--- a/rcw.py
++++ b/rcw.py
+@@ -328,6 +328,34 @@ def build_pbi(lines):
+             v2 = struct.pack(endianess + 'L', p2)
+             subsection += v1
+             subsection += v2
++        elif op == 'loadc':
++            if p1 == None or p2 == None:
++                print('Error: "loadc" instruction requires two parameters')
++                return ''
++            v1 = struct.pack(endianess + 'L', 0x80140000)
++            v2 = struct.pack(endianess + 'L', p1)
++            v3 = struct.pack(endianess + 'L', p2)
++            subsection += v1
++            subsection += v2
++            subsection += v3
++        elif op == 'jumpc':
++            if p1 == None or p2 == None:
++                print('Error: "jumpc" instruction requires two parameters')
++                return ''
++            v1 = struct.pack(endianess + 'L', 0x80850000)
++            v2 = struct.pack(endianess + 'L', p1)
++            v3 = struct.pack(endianess + 'L', p2)
++            subsection += v1
++            subsection += v2
++            subsection += v3
++        elif op == 'jump':
++            if p1 == None:
++                print('Error: "jump" instruction requires a parameter')
++                return ''
++            v1 = struct.pack(endianess + 'L', 0x80840000)
++            v2 = struct.pack(endianess + 'L', p1)
++            subsection += v1
++            subsection += v2
+         elif op == 'awrite':
+             if p1 == None or p2 == None:
+                 print('Error: "awrite" instruction requires two parameters')
+-- 
+2.17.1
+

patches/rcw-LSDK-20.12/0006-lx2160a-add-SVR-check-for-a050234-to-apply-only-on-r.patch

+From 2ebdb6a46e6db66cc0b09c51260a90ea8abc4713 Mon Sep 17 00:00:00 2001
+From: Rabeeh Khoury <rabeeh@solid-run.com>
+Date: Mon, 23 Mar 2020 12:35:04 +0200
+Subject: [PATCH 6/8] lx2160a: add SVR check for a050234 to apply only on rev1
+
+Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
+---
+ lx2160asi/a050234.rcw | 6 ++++++
+ 1 file changed, 6 insertions(+)
+
+diff --git a/lx2160asi/a050234.rcw b/lx2160asi/a050234.rcw
+index 72a40e4..2130709 100644
+--- a/lx2160asi/a050234.rcw
++++ b/lx2160asi/a050234.rcw
+@@ -4,6 +4,12 @@
+  */
+ 
+ .pbi
++/* Load condition SVR register mask major ID */
++loadc 0x01e000a4,0x000000f0
++/* If it is rev 1, skip the following jump command */
++jumpc 0x00000014,0x00000010
++/* Skip the following instructions by jumping to the end */
++jump  0xc8
+ write 0x1ea1200,0x20081004
+ write 0x1ea1240,0x20081004
+ write 0x1ea1280,0x20081004
+-- 
+2.17.1
+

patches/rcw-LSDK-20.12/0007-lx2160acex7-pcie-workarounds-and-fan-full-speed.patch

+From 6d634d64528e5ba510c369a2ae19c337ae7d692e Mon Sep 17 00:00:00 2001
+From: Rabeeh Khoury <rabeeh@solid-run.com>
+Date: Mon, 23 Mar 2020 12:36:20 +0200
+Subject: [PATCH 7/8] lx2160acex7 - pcie workarounds and fan full speed
+
+1. Moves calling the workarounds to the _defaults.rcwi
+2. Toggle fan-full-speed GPIO. The fan controller starts throttling when
+a driver exists (i.e. kernel); in order to avoid overheating until then
+enable full speed.
+3. Run a050234.rcw on rev1 - fixes some issues observed when using Mellanox
+ConnectX-5 NICs
+4. Run a009531 and a00885 on rev2.
+
+Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
+---
+ lx2160acex7/configs/lx2160a_defaults.rcwi | 21 +++++++++++++++++----
+ lx2160acex7/configs/lx2160a_sdboot.rcwi   |  6 ------
+ lx2160acex7/configs/lx2160a_xspiboot.rcwi |  6 ------
+ 3 files changed, 17 insertions(+), 16 deletions(-)
+
+diff --git a/lx2160acex7/configs/lx2160a_defaults.rcwi b/lx2160acex7/configs/lx2160a_defaults.rcwi
+index 3ea7683..7af1f5b 100644
+--- a/lx2160acex7/configs/lx2160a_defaults.rcwi
++++ b/lx2160acex7/configs/lx2160a_defaults.rcwi
+@@ -1,10 +1,6 @@
+ #include <../lx2160asi/lx2160a.rcwi>
+ MEM_PLL_CFG=3
+ MEM2_PLL_CFG=3
+-C5_PLL_SEL=0
+-C6_PLL_SEL=0
+-C7_PLL_SEL=0
+-C8_PLL_SEL=0
+ HWA_CGA_M1_CLK_SEL=1
+ HWA_CGB_M1_CLK_SEL=7
+ BOOT_LOC=26
+@@ -22,3 +18,20 @@ IRQ07_04_PMUX=1
+ IRQ11_08_PMUX=1
+ EVT20_PMUX=1
+ EVT43_PMUX=1
++
++/* Drive the fan full speed pin */
++.pbi
++write 0x2320000,0x20000000
++.end
++
++/* Errata for SATA controller */
++#include <../lx2160asi/a010554.rcw>
++
++/* Errata for rev 1 PCIe controller */
++#include <../lx2160asi/a011270.rcw>
++
++/* Errata a050234 - fix elastic buffer threshold in rev 1 */
++#include <../lx2160asi/a050234.rcw>
++
++/* LX2 rev 2 PCIe Errata A-009531 and A-008851*/
++#include <../lx2160asi/a009531_a008851.rcw>
+diff --git a/lx2160acex7/configs/lx2160a_sdboot.rcwi b/lx2160acex7/configs/lx2160a_sdboot.rcwi
+index d537ea5..9086ffc 100644
+--- a/lx2160acex7/configs/lx2160a_sdboot.rcwi
++++ b/lx2160acex7/configs/lx2160a_sdboot.rcwi
+@@ -9,12 +9,6 @@ blockcopy 0x08,0x00100000,0x1800a000,0x00020000
+ /* Boot Location Pointer */
+ #include <../lx2160asi/bootlocptr_sd.rcw>
+ 
+-/* Errata for SATA controller */
+-#include <../lx2160asi/a010554.rcw>
+-
+-/* Errata for PCIe controller */
+-#include <../lx2160asi/a011270.rcw>
+-
+ /* common PBI commands */
+ #include <../lx2160asi/common.rcw>
+ 
+diff --git a/lx2160acex7/configs/lx2160a_xspiboot.rcwi b/lx2160acex7/configs/lx2160a_xspiboot.rcwi
+index 28310c9..fa092c9 100644
+--- a/lx2160acex7/configs/lx2160a_xspiboot.rcwi
++++ b/lx2160acex7/configs/lx2160a_xspiboot.rcwi
+@@ -4,12 +4,6 @@
+ /* Boot Location Pointer */
+ #include <../lx2160asi/bootlocptr_nor.rcw>
+ 
+-/* Errata for SATA controller */
+-#include <../lx2160asi/a010554.rcw>
+-
+-/* Errata for PCIe controller */
+-#include <../lx2160asi/a011270.rcw>
+-
+ /* common PBI commands */
+ #include <../lx2160asi/common.rcw>
+ 
+-- 
+2.17.1
+

patches/rcw-LSDK-20.12/0008-lx2160a-add-generic-bootloc-section.patch

+From f7f0ad5e568862f7dc70fbd0f790845ee576734d Mon Sep 17 00:00:00 2001
+From: Rabeeh Khoury <rabeeh@solid-run.com>
+Date: Tue, 24 Mar 2020 03:42:14 +0200
+Subject: [PATCH 8/8] lx2160a: add generic bootloc section
+
+The generic bootloc section does conditional blockcopy from SD/eMMC and
+SPI with some predefined addresses.
+Later on if ATF is used; those addresses are modified with ATF's
+create_pbl.c
+
+With this method a single boot image is unified for all the 3 different
+boot methods.
+
+Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
+---
+ lx2160acex7/configs/lx2160a_defaults.rcwi | 12 +++++
+ lx2160asi/bootlocptr.rcw                  | 62 +++++++++++++++++++++++
+ 2 files changed, 74 insertions(+)
+ create mode 100644 lx2160asi/bootlocptr.rcw
+
+diff --git a/lx2160acex7/configs/lx2160a_defaults.rcwi b/lx2160acex7/configs/lx2160a_defaults.rcwi
+index 7af1f5b..7997d49 100644
+--- a/lx2160acex7/configs/lx2160a_defaults.rcwi
++++ b/lx2160acex7/configs/lx2160a_defaults.rcwi
+@@ -35,3 +35,15 @@ write 0x2320000,0x20000000
+ 
+ /* LX2 rev 2 PCIe Errata A-009531 and A-008851*/
+ #include <../lx2160asi/a009531_a008851.rcw>
++
++/* Unified boot location copy */
++#include <../lx2160asi/bootlocptr.rcw>
++
++/* Errata to write on scratch reg for validation */
++#include <../lx2160asi/scratchrw1.rcw>
++
++/* common PBI commands */
++#include <../lx2160asi/common.rcw>
++
++/* Modify FlexSPI Clock Divisor value - for now keep it fixed value but using loadc/jumpc/jump it can be calculated on the fly */
++#include <../lx2160asi/flexspi_divisor_28.rcw>
+diff --git a/lx2160asi/bootlocptr.rcw b/lx2160asi/bootlocptr.rcw
+new file mode 100644
+index 0000000..645182f
+--- /dev/null
++++ b/lx2160asi/bootlocptr.rcw
+@@ -0,0 +1,62 @@
++/*
++ * Generic code for auto booting.
++ * For each section blockcopy followed by write to bootlocl then bootloch must
++ * be followed in each section since when using ATF with create_pbl script in
++ * auto mode; it counts on the sequence of to be in that order.
++ */
++
++/* Boot from SD - copy SPL Uboot to Ocram */
++.pbi
++/* Load condition PORSR1 and mask RCW_SRC */
++loadc 0x01e00000,0x07800000
++
++/* If it is 0x8 << 23 then skip the following jump command */
++jumpc 0x00000014,0x04000000
++
++/* Jump all the below instructions */
++jump 0x28 /* All instruction below including the jump are 40 bytes */
++
++/* blockcopy must be followed by two writes to bootlocl and bootloch */
++blockcopy 0x08,0x00100000,0x1800a000,0x00020000
++write 0x01e00400,0x1800a000
++write 0x01e00404,0x00000000
++.end
++
++/* Boot from eMMC - copy SPL Uboot to Ocram */
++.pbi
++/* Load condition PORSR1 and mask RCW_SRC */
++loadc 0x01e00000,0x07800000
++
++/* If it is 0x9 << 23 then skip the following jump command */
++jumpc 0x00000014,0x04800000
++
++/* Jump all the below instructions */
++jump 0x28 /* All instruction below including the jump are 40 bytes */
++
++/* blockcopy must be followed by two writes to bootlocl and bootloch */
++blockcopy 0x09,0x00100000,0x1800a000,0x00020000
++write 0x01e00400,0x1800a000
++write 0x01e00404,0x00000000
++.end
++
++/* XSPI boot Location Pointer */
++/*
++ * Set the boot location pointer to the NOR flash boot area.
++ */
++
++.pbi
++/* Load condition PORSR1 and mask RCW_SRC */
++loadc 0x01e00000,0x07800000
++
++/* If it is 0xf << 23 then skip the following jump command */
++jumpc 0x00000014,0x07800000
++
++/* Jump all the below instructions */
++jump 0x28 /* All instruction below including the jump are 0x190 bytes */
++
++/* blockcopy must be followed by two writes to bootlocl and bootloch */
++blockcopy 0x0f,0x00100000,0x1800a000,0x00020000
++write 0x01e00400,0x20100000
++write 0x01e00404,0x00000000
++.end
++
+-- 
+2.17.1
+

patches/rcw-LSDK-20.12/0010-lx2160acex7-remove-flexspi-divisor-optimization.patch

+From 4f1f779e2d0757ab1d328761c06dc09b9c6a3544 Mon Sep 17 00:00:00 2001
+From: Rabeeh Khoury <rabeeh@solid-run.com>
+Date: Tue, 1 Sep 2020 12:39:31 +0300
+Subject: [PATCH 10/10] lx2160acex7: remove flexspi divisor optimization
+
+Keep the flexspi divisor as default; which is 17MHz when the fabric at
+700MHz.
+The HoneyComb / ClearFog CX carrier boards holds an SPI flash that it's
+MUX is limited to 20MHz.
+
+Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
+---
+ lx2160acex7/configs/lx2160a_1900_600_2600.rcwi |  3 ---
+ lx2160acex7/configs/lx2160a_2000_700_2400.rcwi |  3 ---
+ lx2160acex7/configs/lx2160a_2000_700_2600.rcwi |  3 ---
+ lx2160acex7/configs/lx2160a_2000_700_2900.rcwi |  3 ---
+ lx2160acex7/configs/lx2160a_2000_700_3200.rcwi |  3 ---
+ lx2160acex7/configs/lx2160a_2400_700_3200.rcwi |  3 ---
+ lx2160acex7/configs/lx2160a_2500_700_3200.rcwi |  3 ---
+ lx2160acex7/configs/lx2160a_2600_700_3200.rcwi |  3 ---
+ lx2160acex7/configs/lx2160a_defaults.rcwi      | 10 ++++++++--
+ lx2160acex7/configs/lx2160a_xspiboot.rcwi      |  3 ---
+ 10 files changed, 8 insertions(+), 29 deletions(-)
+
+diff --git a/lx2160acex7/configs/lx2160a_1900_600_2600.rcwi b/lx2160acex7/configs/lx2160a_1900_600_2600.rcwi
+index 8b61021..a3b7b29 100644
+--- a/lx2160acex7/configs/lx2160a_1900_600_2600.rcwi
++++ b/lx2160acex7/configs/lx2160a_1900_600_2600.rcwi
+@@ -7,6 +7,3 @@ SYS_PLL_RAT=12
+ 
+ MEM_PLL_RAT=26
+ MEM2_PLL_RAT=26
+-
+-/* Modify FlexSPI Clock Divisor value */
+-/* #include <../lx2160asi/flexspi_divisor_24.rcw>*/
+diff --git a/lx2160acex7/configs/lx2160a_2000_700_2400.rcwi b/lx2160acex7/configs/lx2160a_2000_700_2400.rcwi
+index 6b0b150..4cb3abf 100644
+--- a/lx2160acex7/configs/lx2160a_2000_700_2400.rcwi
++++ b/lx2160acex7/configs/lx2160a_2000_700_2400.rcwi
+@@ -7,6 +7,3 @@ SYS_PLL_RAT=14
+ 
+ MEM_PLL_RAT=24
+ MEM2_PLL_RAT=24
+-
+-/* Modify FlexSPI Clock Divisor value */
+-/* #include <../lx2160asi/flexspi_divisor_28.rcw>*/
+diff --git a/lx2160acex7/configs/lx2160a_2000_700_2600.rcwi b/lx2160acex7/configs/lx2160a_2000_700_2600.rcwi
+index 21dce67..a5c436c 100644
+--- a/lx2160acex7/configs/lx2160a_2000_700_2600.rcwi
++++ b/lx2160acex7/configs/lx2160a_2000_700_2600.rcwi
+@@ -7,6 +7,3 @@ SYS_PLL_RAT=14
+ 
+ MEM_PLL_RAT=26
+ MEM2_PLL_RAT=26
+-
+-/* Modify FlexSPI Clock Divisor value */
+-/* #include <../lx2160asi/flexspi_divisor_28.rcw>*/
+diff --git a/lx2160acex7/configs/lx2160a_2000_700_2900.rcwi b/lx2160acex7/configs/lx2160a_2000_700_2900.rcwi
+index e6a8e30..d1db3fb 100644
+--- a/lx2160acex7/configs/lx2160a_2000_700_2900.rcwi
++++ b/lx2160acex7/configs/lx2160a_2000_700_2900.rcwi
+@@ -7,6 +7,3 @@ SYS_PLL_RAT=14
+ 
+ MEM_PLL_RAT=29
+ MEM2_PLL_RAT=29
+-
+-/* Modify FlexSPI Clock Divisor value */
+-/* #include <../lx2160asi/flexspi_divisor_28.rcw>*/
+diff --git a/lx2160acex7/configs/lx2160a_2000_700_3200.rcwi b/lx2160acex7/configs/lx2160a_2000_700_3200.rcwi
+index 27ee377..22fcadf 100644
+--- a/lx2160acex7/configs/lx2160a_2000_700_3200.rcwi
++++ b/lx2160acex7/configs/lx2160a_2000_700_3200.rcwi
+@@ -7,6 +7,3 @@ SYS_PLL_RAT=14
+ 
+ MEM_PLL_RAT=32
+ MEM2_PLL_RAT=32
+-
+-/* Modify FlexSPI Clock Divisor value */
+-#include <../lx2160asi/flexspi_divisor_28.rcw>
+diff --git a/lx2160acex7/configs/lx2160a_2400_700_3200.rcwi b/lx2160acex7/configs/lx2160a_2400_700_3200.rcwi
+index fc0fd6c..8f74ff0 100644
+--- a/lx2160acex7/configs/lx2160a_2400_700_3200.rcwi
++++ b/lx2160acex7/configs/lx2160a_2400_700_3200.rcwi
+@@ -7,6 +7,3 @@ SYS_PLL_RAT=14
+ 
+ MEM_PLL_RAT=32
+ MEM2_PLL_RAT=32
+-
+-/* Modify FlexSPI Clock Divisor value */
+-#include <../lx2160asi/flexspi_divisor_28.rcw>
+diff --git a/lx2160acex7/configs/lx2160a_2500_700_3200.rcwi b/lx2160acex7/configs/lx2160a_2500_700_3200.rcwi
+index 62d9069..2dc1460 100644
+--- a/lx2160acex7/configs/lx2160a_2500_700_3200.rcwi
++++ b/lx2160acex7/configs/lx2160a_2500_700_3200.rcwi
+@@ -7,6 +7,3 @@ SYS_PLL_RAT=14
+ 
+ MEM_PLL_RAT=32
+ MEM2_PLL_RAT=32
+-
+-/* Modify FlexSPI Clock Divisor value */
+-#include <../lx2160asi/flexspi_divisor_28.rcw>
+diff --git a/lx2160acex7/configs/lx2160a_2600_700_3200.rcwi b/lx2160acex7/configs/lx2160a_2600_700_3200.rcwi
+index e244917..d9fd795 100644
+--- a/lx2160acex7/configs/lx2160a_2600_700_3200.rcwi
++++ b/lx2160acex7/configs/lx2160a_2600_700_3200.rcwi
+@@ -7,6 +7,3 @@ SYS_PLL_RAT=14
+ 
+ MEM_PLL_RAT=32
+ MEM2_PLL_RAT=32
+-
+-/* Modify FlexSPI Clock Divisor value */
+-#include <../lx2160asi/flexspi_divisor_28.rcw>
+diff --git a/lx2160acex7/configs/lx2160a_defaults.rcwi b/lx2160acex7/configs/lx2160a_defaults.rcwi
+index 7997d49..359e86c 100644
+--- a/lx2160acex7/configs/lx2160a_defaults.rcwi
++++ b/lx2160acex7/configs/lx2160a_defaults.rcwi
+@@ -45,5 +45,11 @@ write 0x2320000,0x20000000
+ /* common PBI commands */
+ #include <../lx2160asi/common.rcw>
+ 
+-/* Modify FlexSPI Clock Divisor value - for now keep it fixed value but using loadc/jumpc/jump it can be calculated on the fly */
+-#include <../lx2160asi/flexspi_divisor_28.rcw>
++/*
++ * Do not modify the FlexSPI clock divisor value when using HoneyComb / ClearFog CX
++ * as carrier boards. The reason is that the analog mux used on the carrier board
++ * can't accomodate more than 20MHz SPI frequency. So keep the value default 0x14
++ * which indicates divide by 80. In 700MHz fabric clock this is around 17MHz SPI
++ * clock.
++ */
++/*#include <../lx2160asi/flexspi_divisor_28.rcw>*/
+diff --git a/lx2160acex7/configs/lx2160a_xspiboot.rcwi b/lx2160acex7/configs/lx2160a_xspiboot.rcwi
+index fa092c9..21782ec 100644
+--- a/lx2160acex7/configs/lx2160a_xspiboot.rcwi
++++ b/lx2160acex7/configs/lx2160a_xspiboot.rcwi
+@@ -6,6 +6,3 @@
+ 
+ /* common PBI commands */
+ #include <../lx2160asi/common.rcw>
+-
+-/* Modify FlexSPI Clock Divisor value */
+-#include <../lx2160asi/flexspi_divisor_28.rcw>
+-- 
+2.17.1
+

patches/rcw-LSDK-20.12/0011-lx210acex7-25Gbps-retimer-and-restructure-config.patch

+From d4a721d712d8fd9f03be2965e0b37bcd33148bdc Mon Sep 17 00:00:00 2001
+From: Rabeeh Khoury <rabeeh@solid-run.com>
+Date: Wed, 28 Oct 2020 16:44:35 +0200
+Subject: [PATCH] lx210acex7: 25Gbps retimer and restructure config
+
+1. Split SERDES configuration files that each SERDES block from the
+available 3 can be separately configured.
+2. Added SD1 lanes e,f,g,h include files that configures the SERDES
+lanes to suppoer 25Gbps rate with external retimer (using ClearFog CX
+revision 1.3 and newer).
+3. Added bus speeds 750 and 800MHz which are required to get wire speed
+DPDK performance on a 100Gbps link.
+
+Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
+---
+ lx2160acex7/configs/lx2160a_13_5_2.rcwi       |  3 ---
+ lx2160acex7/configs/lx2160a_17_4_2.rcwi       |  7 ------
+ .../configs/lx2160a_2000_750_3200.rcwi        |  9 +++++++
+ .../configs/lx2160a_2000_800_3200.rcwi        |  9 +++++++
+ lx2160acex7/configs/lx2160a_8_5_0.rcwi        |  7 ------
+ lx2160acex7/configs/lx2160a_SD1_13.rcwi       |  3 +++
+ lx2160acex7/configs/lx2160a_SD1_14.rcwi       |  3 +++
+ lx2160acex7/configs/lx2160a_SD1_17.rcwi       |  3 +++
+ lx2160acex7/configs/lx2160a_SD1_2.rcwi        |  4 +++
+ ...x2160a_20_5_2.rcwi => lx2160a_SD1_20.rcwi} |  2 --
+ ...{lx2160a_8_5_2.rcwi => lx2160a_SD1_8.rcwi} |  3 ---
+ lx2160acex7/configs/lx2160a_SD2_5.rcwi        |  1 +
+ lx2160acex7/configs/lx2160a_SD3_0.rcwi        |  1 +
+ lx2160acex7/configs/lx2160a_SD3_2.rcwi        |  1 +
+ lx2160acex7/configs/lx2160a_SD3_3.rcwi        |  1 +
+ .../lx2160a_cex7_hc_sd1_lanes_e_f.rcwi        | 24 ++++++++++++++++++
+ .../lx2160a_cex7_hc_sd1_lanes_g_h.rcwi        | 25 +++++++++++++++++++
+ 17 files changed, 84 insertions(+), 22 deletions(-)
+ delete mode 100644 lx2160acex7/configs/lx2160a_13_5_2.rcwi
+ delete mode 100644 lx2160acex7/configs/lx2160a_17_4_2.rcwi
+ create mode 100644 lx2160acex7/configs/lx2160a_2000_750_3200.rcwi
+ create mode 100644 lx2160acex7/configs/lx2160a_2000_800_3200.rcwi
+ delete mode 100644 lx2160acex7/configs/lx2160a_8_5_0.rcwi
+ create mode 100644 lx2160acex7/configs/lx2160a_SD1_13.rcwi
+ create mode 100644 lx2160acex7/configs/lx2160a_SD1_14.rcwi
+ create mode 100644 lx2160acex7/configs/lx2160a_SD1_17.rcwi
+ create mode 100644 lx2160acex7/configs/lx2160a_SD1_2.rcwi
+ rename lx2160acex7/configs/{lx2160a_20_5_2.rcwi => lx2160a_SD1_20.rcwi} (78%)
+ rename lx2160acex7/configs/{lx2160a_8_5_2.rcwi => lx2160a_SD1_8.rcwi} (79%)
+ create mode 100644 lx2160acex7/configs/lx2160a_SD2_5.rcwi
+ create mode 100644 lx2160acex7/configs/lx2160a_SD3_0.rcwi
+ create mode 100644 lx2160acex7/configs/lx2160a_SD3_2.rcwi
+ create mode 100644 lx2160acex7/configs/lx2160a_SD3_3.rcwi
+ create mode 100644 lx2160acex7/configs/lx2160a_cex7_hc_sd1_lanes_e_f.rcwi
+ create mode 100644 lx2160acex7/configs/lx2160a_cex7_hc_sd1_lanes_g_h.rcwi
+
+diff --git a/lx2160acex7/configs/lx2160a_13_5_2.rcwi b/lx2160acex7/configs/lx2160a_13_5_2.rcwi
+deleted file mode 100644
+index 76f44bc..0000000
+--- a/lx2160acex7/configs/lx2160a_13_5_2.rcwi
++++ /dev/null
+@@ -1,3 +0,0 @@
+-SRDS_PRTCL_S1=13
+-SRDS_PRTCL_S2=5
+-SRDS_PRTCL_S3=2
+diff --git a/lx2160acex7/configs/lx2160a_17_4_2.rcwi b/lx2160acex7/configs/lx2160a_17_4_2.rcwi
+deleted file mode 100644
+index 358972d..0000000
+--- a/lx2160acex7/configs/lx2160a_17_4_2.rcwi
++++ /dev/null
+@@ -1,7 +0,0 @@
+-SRDS_PRTCL_S1=17
+-SRDS_PRTCL_S2=4
+-SRDS_PRTCL_S3=2
+-
+-/*SRDS_INTRA_REF_CLK_S1 = 1*/ /* PLLF used for PLLS */
+-/*SRDS_PLL_REF_CLK_SEL_S1=2*/
+-
+diff --git a/lx2160acex7/configs/lx2160a_2000_750_3200.rcwi b/lx2160acex7/configs/lx2160a_2000_750_3200.rcwi
+new file mode 100644
+index 0000000..84d544d
+--- /dev/null
++++ b/lx2160acex7/configs/lx2160a_2000_750_3200.rcwi
+@@ -0,0 +1,9 @@
++CGA_PLL1_RAT=20
++CGA_PLL2_RAT=20
++CGB_PLL1_RAT=20
++CGB_PLL2_RAT=9
++
++SYS_PLL_RAT=15
++
++MEM_PLL_RAT=32
++MEM2_PLL_RAT=32
+diff --git a/lx2160acex7/configs/lx2160a_2000_800_3200.rcwi b/lx2160acex7/configs/lx2160a_2000_800_3200.rcwi
+new file mode 100644
+index 0000000..31d7cfd
+--- /dev/null
++++ b/lx2160acex7/configs/lx2160a_2000_800_3200.rcwi
+@@ -0,0 +1,9 @@
++CGA_PLL1_RAT=20
++CGA_PLL2_RAT=20
++CGB_PLL1_RAT=20
++CGB_PLL2_RAT=9
++
++SYS_PLL_RAT=16
++
++MEM_PLL_RAT=32
++MEM2_PLL_RAT=32
+diff --git a/lx2160acex7/configs/lx2160a_8_5_0.rcwi b/lx2160acex7/configs/lx2160a_8_5_0.rcwi
+deleted file mode 100644
+index 62ff153..0000000
+--- a/lx2160acex7/configs/lx2160a_8_5_0.rcwi
++++ /dev/null
+@@ -1,7 +0,0 @@
+-SRDS_PRTCL_S1=8 /* should be 8 */
+-SRDS_PRTCL_S2=5
+-SRDS_PRTCL_S3=0
+-
+-SRDS_INTRA_REF_CLK_S1 = 1 /* PLLF used for PLLS */
+-SRDS_PLL_REF_CLK_SEL_S1=2
+-SRDS_PLL_PD_PLL1=1
+diff --git a/lx2160acex7/configs/lx2160a_SD1_13.rcwi b/lx2160acex7/configs/lx2160a_SD1_13.rcwi
+new file mode 100644
+index 0000000..61b1eea
+--- /dev/null
++++ b/lx2160acex7/configs/lx2160a_SD1_13.rcwi
+@@ -0,0 +1,3 @@
++SRDS_PRTCL_S1=13
++#include <configs/lx2160a_cex7_hc_sd1_lanes_e_f.rcwi>
++#include <configs/lx2160a_cex7_hc_sd1_lanes_g_h.rcwi>
+diff --git a/lx2160acex7/configs/lx2160a_SD1_14.rcwi b/lx2160acex7/configs/lx2160a_SD1_14.rcwi
+new file mode 100644
+index 0000000..75e3fab
+--- /dev/null
++++ b/lx2160acex7/configs/lx2160a_SD1_14.rcwi
+@@ -0,0 +1,3 @@
++SRDS_PRTCL_S1=14
++#include <configs/lx2160a_cex7_hc_sd1_lanes_e_f.rcwi>
++#include <configs/lx2160a_cex7_hc_sd1_lanes_g_h.rcwi>
+diff --git a/lx2160acex7/configs/lx2160a_SD1_17.rcwi b/lx2160acex7/configs/lx2160a_SD1_17.rcwi
+new file mode 100644
+index 0000000..5504271
+--- /dev/null
++++ b/lx2160acex7/configs/lx2160a_SD1_17.rcwi
+@@ -0,0 +1,3 @@
++SRDS_PRTCL_S1=17
++#include <configs/lx2160a_cex7_hc_sd1_lanes_e_f.rcwi>
++#include <configs/lx2160a_cex7_hc_sd1_lanes_g_h.rcwi>
+diff --git a/lx2160acex7/configs/lx2160a_SD1_2.rcwi b/lx2160acex7/configs/lx2160a_SD1_2.rcwi
+new file mode 100644
+index 0000000..0f013e6
+--- /dev/null
++++ b/lx2160acex7/configs/lx2160a_SD1_2.rcwi
+@@ -0,0 +1,4 @@
++SRDS_PRTCL_S1=2
++
++SRDS_PLL_REF_CLK_SEL_S1=0
++SRDS_PLL_PD_PLL1=1
+diff --git a/lx2160acex7/configs/lx2160a_20_5_2.rcwi b/lx2160acex7/configs/lx2160a_SD1_20.rcwi
+similarity index 78%
+rename from lx2160acex7/configs/lx2160a_20_5_2.rcwi
+rename to lx2160acex7/configs/lx2160a_SD1_20.rcwi
+index c2c7bea..053aee7 100644
+--- a/lx2160acex7/configs/lx2160a_20_5_2.rcwi
++++ b/lx2160acex7/configs/lx2160a_SD1_20.rcwi
+@@ -1,6 +1,4 @@
+ SRDS_PRTCL_S1=20
+-SRDS_PRTCL_S2=5
+-SRDS_PRTCL_S3=2
+ 
+ SRDS_INTRA_REF_CLK_S1 = 1 /* PLLF used for PLLS */
+ SRDS_PLL_REF_CLK_SEL_S1=2
+diff --git a/lx2160acex7/configs/lx2160a_8_5_2.rcwi b/lx2160acex7/configs/lx2160a_SD1_8.rcwi
+similarity index 79%
+rename from lx2160acex7/configs/lx2160a_8_5_2.rcwi
+rename to lx2160acex7/configs/lx2160a_SD1_8.rcwi
+index d7d707a..abd6dfd 100644
+--- a/lx2160acex7/configs/lx2160a_8_5_2.rcwi
++++ b/lx2160acex7/configs/lx2160a_SD1_8.rcwi
+@@ -1,7 +1,4 @@
+ SRDS_PRTCL_S1=8 /* should be 8 */
+-SRDS_PRTCL_S2=5
+-SRDS_PRTCL_S3=2
+-
+ SRDS_INTRA_REF_CLK_S1 = 1 /* PLLF used for PLLS */
+ SRDS_PLL_REF_CLK_SEL_S1=2
+ SRDS_PLL_PD_PLL1=1
+diff --git a/lx2160acex7/configs/lx2160a_SD2_5.rcwi b/lx2160acex7/configs/lx2160a_SD2_5.rcwi
+new file mode 100644
+index 0000000..559a90c
+--- /dev/null
++++ b/lx2160acex7/configs/lx2160a_SD2_5.rcwi
+@@ -0,0 +1 @@
++SRDS_PRTCL_S2=5
+diff --git a/lx2160acex7/configs/lx2160a_SD3_0.rcwi b/lx2160acex7/configs/lx2160a_SD3_0.rcwi
+new file mode 100644
+index 0000000..1904856
+--- /dev/null
++++ b/lx2160acex7/configs/lx2160a_SD3_0.rcwi
+@@ -0,0 +1 @@
++SRDS_PRTCL_S3=0
+diff --git a/lx2160acex7/configs/lx2160a_SD3_2.rcwi b/lx2160acex7/configs/lx2160a_SD3_2.rcwi
+new file mode 100644
+index 0000000..b9c3e6f
+--- /dev/null
++++ b/lx2160acex7/configs/lx2160a_SD3_2.rcwi
+@@ -0,0 +1 @@
++SRDS_PRTCL_S3=2
+diff --git a/lx2160acex7/configs/lx2160a_SD3_3.rcwi b/lx2160acex7/configs/lx2160a_SD3_3.rcwi
+new file mode 100644
+index 0000000..4695755
+--- /dev/null
++++ b/lx2160acex7/configs/lx2160a_SD3_3.rcwi
+@@ -0,0 +1 @@
++SRDS_PRTCL_S3=3
+diff --git a/lx2160acex7/configs/lx2160a_cex7_hc_sd1_lanes_e_f.rcwi b/lx2160acex7/configs/lx2160a_cex7_hc_sd1_lanes_e_f.rcwi
+new file mode 100644
+index 0000000..d870a4b
+--- /dev/null
++++ b/lx2160acex7/configs/lx2160a_cex7_hc_sd1_lanes_e_f.rcwi
+@@ -0,0 +1,24 @@
++/*
++ * SERDES tuning based on the following hardware -
++ * - SolidRun COM express type 7 revision 1.7 and newer
++ * - SolidRun ClearFog CX revision 1.3 with TI retimers and EPT COM express headers
++ */
++
++.pbi
++/* Lane E (SD1 TX/RX 3) */
++write 0x01EA0C28,0x00000000
++write 0x01EA0C30,0x20868120
++write 0x01EA0C34,0x23000000
++write 0x01EA0C68,0x80000000
++write 0x01EA0C74,0x00002020
++write 0x01EA0C80,0x00008000
++
++/* Lane F (SD1 TX/RX 2)*/
++write 0x01EA0D28,0x00000000
++write 0x01EA0D30,0x20868120
++write 0x01EA0D34,0x23000000
++write 0x01EA0D68,0x80000000
++write 0x01EA0D74,0x00002020
++write 0x01EA0D80,0x00008000
++.end
++
+diff --git a/lx2160acex7/configs/lx2160a_cex7_hc_sd1_lanes_g_h.rcwi b/lx2160acex7/configs/lx2160a_cex7_hc_sd1_lanes_g_h.rcwi
+new file mode 100644
+index 0000000..4097b77
+--- /dev/null
++++ b/lx2160acex7/configs/lx2160a_cex7_hc_sd1_lanes_g_h.rcwi
+@@ -0,0 +1,25 @@
++/*
++ * SERDES tuning based on the following hardware -
++ * - SolidRun COM express type 7 revision 1.7 and newer
++ * - SolidRun ClearFog CX revision 1.3 with TI retimers and EPT COM express headers
++ */
++
++.pbi
++/* Lane G (SD1 TX/RX 1)*/
++write 0x01EA0E28,0x00000000
++write 0x01EA0E30,0x20818120
++write 0x01EA0E34,0x23000000
++write 0x01EA0E68,0x80000000
++write 0x01EA0E74,0x00002020
++write 0x01EA0E80,0x00008000
++
++/* Lane H (SD1 TX/RX 0)*/
++write 0x01EA0F28,0x00000000
++write 0x01EA0F30,0x20818120
++write 0x01EA0F34,0x23000000
++write 0x01EA0F68,0x80000000
++write 0x01EA0F74,0x00002020
++write 0x01EA0F80,0x00008000
++
++.end
++
+-- 
+2.25.1
+

patches/rcw-LSDK-20.12/0012-lx2160acex7-adjust-lanes-e-and-f-for-25g-links.patch

+From 08fedde7e5422756a898dd389250aa1a30c97c7d Mon Sep 17 00:00:00 2001
+From: Rabeeh Khoury <rabeeh@solid-run.com>
+Date: Thu, 29 Oct 2020 17:42:50 +0200
+Subject: [PATCH] lx2160acex7: adjust lanes e and f for 25g links
+
+Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
+---
+ lx2160acex7/configs/lx2160a_cex7_hc_sd1_lanes_e_f.rcwi | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/lx2160acex7/configs/lx2160a_cex7_hc_sd1_lanes_e_f.rcwi b/lx2160acex7/configs/lx2160a_cex7_hc_sd1_lanes_e_f.rcwi
+index d870a4b..bd35bdc 100644
+--- a/lx2160acex7/configs/lx2160a_cex7_hc_sd1_lanes_e_f.rcwi
++++ b/lx2160acex7/configs/lx2160a_cex7_hc_sd1_lanes_e_f.rcwi
+@@ -7,7 +7,7 @@
+ .pbi
+ /* Lane E (SD1 TX/RX 3) */
+ write 0x01EA0C28,0x00000000
+-write 0x01EA0C30,0x20868120
++write 0x01EA0C30,0x20818120
+ write 0x01EA0C34,0x23000000
+ write 0x01EA0C68,0x80000000
+ write 0x01EA0C74,0x00002020
+@@ -15,7 +15,7 @@ write 0x01EA0C80,0x00008000
+ 
+ /* Lane F (SD1 TX/RX 2)*/
+ write 0x01EA0D28,0x00000000
+-write 0x01EA0D30,0x20868120
++write 0x01EA0D30,0x20818120
+ write 0x01EA0D34,0x23000000
+ write 0x01EA0D68,0x80000000
+ write 0x01EA0D74,0x00002020
+-- 
+2.25.1
+

patches/rcw-LSDK-20.12/0013-lx2160acex7-added-SERDES-bank-2-with-pcie-x8.patch

+From 30614556e914de366769e6d1bd235d9caa3c6528 Mon Sep 17 00:00:00 2001
+From: Rabeeh Khoury <rabeeh@solid-run.com>
+Date: Tue, 3 Nov 2020 15:34:34 +0200
+Subject: [PATCH] lx2160acex7: added SERDES bank 2 with pcie x8
+
+Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
+---
+ lx2160acex7/configs/lx2160a_SD2_2.rcwi | 1 +
+ 1 file changed, 1 insertion(+)
+ create mode 100644 lx2160acex7/configs/lx2160a_SD2_2.rcwi
+
+diff --git a/lx2160acex7/configs/lx2160a_SD2_2.rcwi b/lx2160acex7/configs/lx2160a_SD2_2.rcwi
+new file mode 100644
+index 0000000..daeeb5e
+--- /dev/null
++++ b/lx2160acex7/configs/lx2160a_SD2_2.rcwi
+@@ -0,0 +1 @@
++SRDS_PRTCL_S2=2
+-- 
+2.25.1
+

patches/rcw-LSDK-20.12/0014-lx2160acex7-set-correctly-sdcard-card-detect-and-wri.patch

+From ec8c382532d01a3e26491dbcfe2ad854a164006f Mon Sep 17 00:00:00 2001
+From: Rabeeh Khoury <rabeeh@solid-run.com>
+Date: Thu, 3 Dec 2020 19:55:07 +0200
+Subject: [PATCH] lx2160acex7: set correctly sdcard card detect and write
+ protect pmux
+
+Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
+---
+ lx2160acex7/configs/lx2160a_defaults.rcwi | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/lx2160acex7/configs/lx2160a_defaults.rcwi b/lx2160acex7/configs/lx2160a_defaults.rcwi
+index 359e86c..30e0399 100644
+--- a/lx2160acex7/configs/lx2160a_defaults.rcwi
++++ b/lx2160acex7/configs/lx2160a_defaults.rcwi
+@@ -5,7 +5,7 @@ HWA_CGA_M1_CLK_SEL=1
+ HWA_CGB_M1_CLK_SEL=7
+ BOOT_LOC=26
+ SYSCLK_FREQ=600
+-IIC2_PMUX=1
++IIC2_PMUX=6
+ IIC3_PMUX=0
+ IIC4_PMUX=2
+ USB3_CLK_FSEL=39
+-- 
+2.25.1
+

patches/rcw-LSDK-20.12/9999-lx2160acex7-add-SD1-mode-4-serdes-configuration.patch

+From 2ae3b51f85375e32b818cb64fbe42750d1d6254f Mon Sep 17 00:00:00 2001
+From: Russell King <rmk@armlinux.org.uk>
+Date: Thu, 23 Jan 2020 15:53:30 +0000
+Subject: [PATCH] lx2160acex7: add SD1 mode 4 serdes configuration
+
+Add mode 4 serdes configuration for SGMII and 1000BASE-X on serdes 1.
+
+Signed-off-by: Russell King <rmk@armlinux.org.uk>
+---
+ lx2160acex7/configs/lx2160a_SD1_4.rcwi | 4 ++++
+ 1 file changed, 4 insertions(+)
+ create mode 100644 lx2160acex7/configs/lx2160a_SD1_4.rcwi
+
+diff --git a/lx2160acex7/configs/lx2160a_SD1_4.rcwi b/lx2160acex7/configs/lx2160a_SD1_4.rcwi
+new file mode 100644
+index 000000000000..ec8ca959b59b
+--- /dev/null
++++ b/lx2160acex7/configs/lx2160a_SD1_4.rcwi
+@@ -0,0 +1,4 @@
++SRDS_PRTCL_S1=4
++/* SRDS_INTRA_REF_CLK_S1 = 1 PLLF used for PLLS */
++SRDS_PLL_REF_CLK_SEL_S1=0
++SRDS_PLL_PD_PLL1=1
+-- 
+2.20.1
+

patches/u-boot-LSDK-20.12/0001-armv8-add-lx2160acex7-build-inclusion.patch

+From 79520a7c7c201ca1f75ee01bd8b4d6b6a1257d59 Mon Sep 17 00:00:00 2001
+From: Rabeeh Khoury <rabeeh@solid-run.com>
+Date: Tue, 12 Jan 2021 11:42:10 +0200
+Subject: [PATCH] armv8: add lx2160acex7 build inclusion
+
+Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
+---
+ arch/arm/Kconfig           | 13 +++++++++++++
+ arch/arm/cpu/armv8/Kconfig |  1 +
+ arch/arm/dts/Makefile      |  3 ++-
+ 3 files changed, 16 insertions(+), 1 deletion(-)
+
+diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
+index 01fb4089dc..9005935dd9 100644
+--- a/arch/arm/Kconfig
++++ b/arch/arm/Kconfig
+@@ -1231,6 +1231,18 @@ config TARGET_LX2160ARDB
+ 	  is a high-performance development platform that supports the
+ 	  QorIQ LX2160A/LX2120A/LX2080A Layerscape Architecture processor.
+ 
++config TARGET_LX2160ACEX7
++	bool "Support lx2160acex7"
++	select ARCH_LX2160A
++	select ARCH_MISC_INIT
++	select ARM64
++	select ARMV8_MULTIENTRY
++	select BOARD_LATE_INIT
++	help
++	  Support for SolidRun LX2160A based com express type 7 module and
++	  platform. The lx2160acex7 high-performance platform that supports the
++	  QorIQ LX2160A/LX2120A/LX2080A Layerscape Architecture processor.
++
+ config TARGET_LX2160AQDS
+ 	bool "Support lx2160aqds"
+ 	select ARCH_LX2160A
+@@ -1863,6 +1875,7 @@ source "board/freescale/ls1012aqds/Kconfig"
+ source "board/freescale/ls1012ardb/Kconfig"
+ source "board/freescale/ls1012afrdm/Kconfig"
+ source "board/freescale/lx2160a/Kconfig"
++source "board/solidrun/lx2160a/Kconfig"
+ source "board/freescale/mx35pdk/Kconfig"
+ source "board/freescale/s32v234evb/Kconfig"
+ source "board/grinn/chiliboard/Kconfig"
+diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig
+index a4fec595fa..7fffca107f 100644
+--- a/arch/arm/cpu/armv8/Kconfig
++++ b/arch/arm/cpu/armv8/Kconfig
+@@ -110,6 +110,7 @@ config PSCI_RESET
+ 		   !TARGET_LS1046AFRWY && \
+ 		   !TARGET_LS2081ARDB && !TARGET_LX2160ARDB && \
+ 		   !TARGET_LX2160AQDS && !TARGET_LX2162AQDS && \
++		   !TARGET_LX2160ACEX7 && \
+ 		   !ARCH_UNIPHIER && !TARGET_S32V234EVB
+ 	help
+ 	  Most armv8 systems have PSCI support enabled in EL3, either through
+diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
+index 72466c73f3..2dda738e59 100644
+--- a/arch/arm/dts/Makefile
++++ b/arch/arm/dts/Makefile
+@@ -376,7 +376,8 @@ dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \
+ 	fsl-ls1028a-qds-lpuart.dtb \
+ 	fsl-lx2160a-rdb.dtb \
+ 	fsl-lx2160a-qds.dtb \
+-	fsl-lx2162a-qds.dtb
++	fsl-lx2162a-qds.dtb \
++	fsl-lx2160a-cex7.dtb
+ dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \
+ 	fsl-ls1043a-qds-lpuart.dtb \
+ 	fsl-ls1043a-rdb.dtb \
+-- 
+2.25.1
+

patches/u-boot-LSDK-20.12/0003-armv8-lx2160acex7-defconfig-and-main-platform-includ.patch

+From 62af256d25d61136913a739b14452b6d35eff3dc Mon Sep 17 00:00:00 2001
+From: Rabeeh Khoury <rabeeh@solid-run.com>
+Date: Sun, 28 Jul 2019 13:29:31 +0300
+Subject: [PATCH 3/6] armv8: lx2160acex7: defconfig and main platform include
+
+This patch add lx2160acex7 main defconfig and main include file.
+Notice that the defconfig doesn't support the secured boot mode where a
+follow up patch will cover this.
+
+Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
+---
+ configs/lx2160acex7_tfa_defconfig | 73 ++++++++++++++++++++++++++
+ include/configs/lx2160acex7.h     | 85 +++++++++++++++++++++++++++++++
+ 2 files changed, 158 insertions(+)
+ create mode 100644 configs/lx2160acex7_tfa_defconfig
+ create mode 100644 include/configs/lx2160acex7.h
+
+diff --git a/configs/lx2160acex7_tfa_defconfig b/configs/lx2160acex7_tfa_defconfig
+new file mode 100644
+index 0000000000..d59de7d054
+--- /dev/null
++++ b/configs/lx2160acex7_tfa_defconfig
+@@ -0,0 +1,73 @@
++CONFIG_ARM=y
++CONFIG_TARGET_LX2160ACEX7=y
++CONFIG_SYS_TEXT_BASE=0x82000000
++CONFIG_SYS_MALLOC_F_LEN=0x6000
++CONFIG_EMC2301=y
++CONFIG_TFABOOT=y
++CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
++CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
++CONFIG_AHCI=y
++CONFIG_NR_DRAM_BANKS=3
++CONFIG_FIT_VERBOSE=y
++CONFIG_OF_BOARD_SETUP=y
++CONFIG_OF_BOARD_FIXUP=y
++CONFIG_OF_STDOUT_VIA_ALIAS=y
++CONFIG_BOOTDELAY=10
++CONFIG_USE_BOOTARGS=y
++CONFIG_BOOTARGS="console=ttyAMA0,115200 root=/dev/ram0 earlycon=pl011,mmio32,0x21c0000 ramdisk_size=0x2000000 default_hugepagesz=1024m hugepagesz=1024m hugepages=2 pci=pcie_bus_perf"
++# CONFIG_USE_BOOTCOMMAND is not set
++CONFIG_CMD_GREPENV=y
++CONFIG_CMD_EEPROM=y
++CONFIG_CMD_GPT=y
++CONFIG_CMD_I2C=y
++CONFIG_CMD_MMC=y
++CONFIG_CMD_PCI=y
++CONFIG_CMD_SF=y
++CONFIG_CMD_USB=y
++CONFIG_CMD_CACHE=y
++CONFIG_MP=y
++CONFIG_OF_CONTROL=y
++CONFIG_DEFAULT_DEVICE_TREE="fsl-lx2160a-cex7"
++CONFIG_ENV_IS_IN_MMC=y
++CONFIG_ENV_IS_IN_SPI_FLASH=y
++CONFIG_NET_RANDOM_ETHADDR=y
++CONFIG_DM=y
++CONFIG_SATA_CEVA=y
++CONFIG_FSL_CAAM=y
++CONFIG_DM_MMC=y
++CONFIG_FSL_ESDHC=y
++CONFIG_DM_SPI_FLASH=y
++CONFIG_SPI_FLASH=y
++CONFIG_SPI_FLASH_SPANSION=y
++CONFIG_SPI_FLASH_STMICRO=y
++CONFIG_SPI_FLASH_MICRON=y
++CONFIG_SPI_FLASH_WINBOND=y
++# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
++CONFIG_PHYLIB=y
++CONFIG_NETDEVICES=y
++CONFIG_PHY_GIGE=y
++CONFIG_CMD_NET=y
++CONFIG_CMD_PING=y
++CONFIG_CMD_PXE=y
++CONFIG_CMD_MII=y
++CONFIG_CMD_DHCP=y
++CONFIG_CMD_FAT=y
++CONFIG_CMD_EXT2=y
++CONFIG_PCI=y
++CONFIG_DM_PCI=y
++CONFIG_DM_PCI_COMPAT=y
++CONFIG_PCIE_LAYERSCAPE_GEN4=y
++CONFIG_PHY_ATHEROS=y
++CONFIG_E1000=y
++CONFIG_DM_SCSI=y
++CONFIG_DM_SERIAL=y
++CONFIG_SERIAL_PROBE_ALL=y
++CONFIG_SPI=y
++CONFIG_DM_SPI=y
++CONFIG_NXP_FSPI=y
++# CONFIG_SYS_NXP_FSPI_AHB=y
++CONFIG_USB=y
++CONFIG_DM_USB=y
++CONFIG_USB_XHCI_HCD=y
++CONFIG_USB_XHCI_DWC3=y
++CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+diff --git a/include/configs/lx2160acex7.h b/include/configs/lx2160acex7.h
+new file mode 100644
+index 0000000000..478cd8242f
+--- /dev/null
++++ b/include/configs/lx2160acex7.h
+@@ -0,0 +1,85 @@
++/* SPDX-License-Identifier: GPL-2.0+ */
++/*
++ * Copyright 2019 SolidRun ltd.
++ */
++
++#ifndef __LX2_CEX7_H
++#define __LX2_CEX7_H
++
++#include "lx2160a_common.h"
++
++/*#define CONFIG_SYS_FSL_ESDHC_USE_PIO*/
++/* VID */
++
++#define I2C_MUX_CH_VOL_MONITOR		0x2
++/* Voltage monitor on channel 2*/
++#define I2C_VOL_MONITOR_ADDR		0x5c
++#define I2C_VOL_MONITOR_BUS_V_OFFSET	0x2
++#define I2C_VOL_MONITOR_BUS_V_OVF	0x1
++#define I2C_VOL_MONITOR_BUS_V_SHIFT	3
++#define CONFIG_VID_FLS_ENV		"lx2160acex7_vdd_mv"
++#define CONFIG_VID
++
++/* The lowest and highest voltage allowed*/
++#define VDD_MV_MIN			700
++#define VDD_MV_MAX			855
++
++/* PM Bus commands code for LTC3882*/
++#define PMBUS_CMD_PAGE                  0x0
++#define PMBUS_CMD_READ_VOUT             0x8B
++#define PMBUS_CMD_PAGE_PLUS_WRITE       0x05
++#define PMBUS_CMD_VOUT_COMMAND          0x21
++#define PWM_CHANNEL0                    0x0
++
++#define CONFIG_VOL_MONITOR_LTC3882_SET
++#define CONFIG_VOL_MONITOR_LTC3882_READ
++
++/* RTC */
++#define CONFIG_SYS_RTC_BUS_NUM		4
++
++/* MAC/PHY configuration */
++#if defined(CONFIG_FSL_MC_ENET)
++#define CONFIG_MII
++#define CONFIG_ETHPRIME		"DPMAC17@rgmii-id"
++
++#define RGMII_PHY_ADDR1		0x01
++
++#endif
++
++/* EMC2301 */
++#define I2C_MUX_CH_EMC2301	0x01
++#define I2C_EMC2301_ADDR	0x2f
++#define I2C_EMC2301_CMD		0x40
++#define I2C_EMC2301_PWM		0x80
++
++/* EEPROM */
++#undef CONFIG_ID_EEPROM /* Fixme */
++#define CONFIG_SYS_I2C_EEPROM_NXID
++#define CONFIG_SYS_EEPROM_BUS_NUM	           0
++#define CONFIG_SYS_I2C_EEPROM_ADDR	           0x57
++#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	    1
++#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS     3
++#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
++
++/* Initial environment variables */
++#define CONFIG_EXTRA_ENV_SETTINGS		\
++	EXTRA_ENV_SETTINGS			\
++	"lx2160acex7_vdd_mv=800\0"		\
++	"BOARD=lx2160acex7\0"			\
++	"xspi_bootcmd=echo Trying load from flexspi..;"		\
++		"sf probe 0:0 && sf read $load_addr "		\
++		"$kernel_start $kernel_size ; env exists secureboot &&"	\
++		"sf read $kernelheader_addr_r $kernelheader_start "	\
++		"$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
++		" bootm $load_addr#$BOARD\0"			\
++	"sd_bootcmd=echo Trying load from sd card..;"		\
++		"mmcinfo; mmc read $load_addr "			\
++		"$kernel_addr_sd $kernel_size_sd ;"		\
++		"env exists secureboot && mmc read $kernelheader_addr_r "\
++		"$kernelhdr_addr_sd $kernelhdr_size_sd "	\
++		" && esbc_validate ${kernelheader_addr_r};"	\
++		"bootm $load_addr#$BOARD\0"
++
++#include <asm/fsl_secure_boot.h>
++
++#endif /* __LX2_CEX7_H */
+-- 
+2.17.1
+

patches/u-boot-LSDK-20.12/0005-armv8-lx2160acex7-lx2160acex-device-tree.patch

+From f8ac0b82bf2af732251419f05b9058e78ca2dbec Mon Sep 17 00:00:00 2001
+From: Rabeeh Khoury <rabeeh@solid-run.com>
+Date: Sun, 28 Jul 2019 13:37:22 +0300
+Subject: [PATCH 5/6] armv8: lx2160acex7: lx2160acex device tree
+
+Based on NXP's LX2160ARDB device tree; it defines -
+1. MX35X based SPI flash
+2. SDHC0 (SD card) and SDHC1 (eMMC)
+3. 4 SATA ports that depending on SERDES configuration they can get
+connected to external SATA drives
+
+Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
+---
+ arch/arm/dts/fsl-lx2160a-cex7.dts | 63 +++++++++++++++++++++++++++++++
+ 1 file changed, 63 insertions(+)
+ create mode 100644 arch/arm/dts/fsl-lx2160a-cex7.dts
+
+diff --git a/arch/arm/dts/fsl-lx2160a-cex7.dts b/arch/arm/dts/fsl-lx2160a-cex7.dts
+new file mode 100644
+index 0000000000..4fbcaafb0e
+--- /dev/null
++++ b/arch/arm/dts/fsl-lx2160a-cex7.dts
+@@ -0,0 +1,63 @@
++// SPDX-License-Identifier: GPL-2.0+ OR X11
++/*
++ * SolidRun LX2160ACEX7 device tree source
++ *
++ * Author:	Rabeeh Khoury <rabeeh@solid-run.com>
++ *
++ * Copyright 2019 SolidRun ltd.
++ *
++ */
++
++/dts-v1/;
++
++#include "fsl-lx2160a.dtsi"
++
++/ {
++	model = "SolidRun LX2160ACEX7 COM express type 7 based board";
++	compatible = "fsl,lx2160acex7", "fsl,lx2160a";
++
++	aliases {
++		spi0 = &fspi;
++	};
++};
++
++&fspi {
++	bus-num = <0>;
++	status = "okay";
++
++	qflash0: MT35XU512ABA1G12@0 {
++		#address-cells = <1>;
++		#size-cells = <1>;
++		compatible = "spi-flash";
++		spi-max-frequency = <50000000>;
++		reg = <0>;
++		/* The following setting enables 1-1-8 (CMD-ADDR-DATA) mode */
++		fspi-rx-bus-width = <8>; /* 8 FSPI Rx lines */
++		fspi-tx-bus-width = <1>; /* 1 FSPI Tx line */
++	};
++
++};
++
++&esdhc0 {
++	status = "okay";
++};
++
++&esdhc1 {
++	status = "okay";
++};
++
++&sata0 {
++	status = "okay";
++};
++
++&sata1 {
++	status = "okay";
++};
++
++&sata2 {
++	status = "okay";
++};
++
++&sata3 {
++	status = "okay";
++};
+-- 
+2.17.1
+

patches/u-boot-LSDK-20.12/0008-uboot-add-nvme-commands-and-for-distroboot.patch

+From a1fddcaae71a95bd4b9963c9000b9c88b6d152d5 Mon Sep 17 00:00:00 2001
+From: Rabeeh Khoury <rabeeh@solid-run.com>
+Date: Mon, 11 Nov 2019 23:45:31 +0200
+Subject: [PATCH] uboot - add nvme commands and for distroboot
+
+Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
+---
+ configs/lx2160acex7_tfa_defconfig | 2 ++
+ include/configs/lx2160a_common.h  | 3 ++-
+ 2 files changed, 4 insertions(+), 1 deletion(-)
+
+diff --git a/configs/lx2160acex7_tfa_defconfig b/configs/lx2160acex7_tfa_defconfig
+index d59de7d054..3891d2a7c4 100644
+--- a/configs/lx2160acex7_tfa_defconfig
++++ b/configs/lx2160acex7_tfa_defconfig
+@@ -25,6 +25,8 @@ CONFIG_CMD_PCI=y
+ CONFIG_CMD_SF=y
+ CONFIG_CMD_USB=y
+ CONFIG_CMD_CACHE=y
++CONFIG_CMD_NVME=y
++CONFIG_NVME=y
+ CONFIG_MP=y
+ CONFIG_OF_CONTROL=y
+ CONFIG_DEFAULT_DEVICE_TREE="fsl-lx2160a-cex7"
+diff --git a/include/configs/lx2160a_common.h b/include/configs/lx2160a_common.h
+index 34cc29685d..7c2d749a9e 100644
+--- a/include/configs/lx2160a_common.h
++++ b/include/configs/lx2160a_common.h
+@@ -306,6 +306,7 @@ int select_i2c_ch_pca9547_sec(unsigned char ch);
+ 	func(MMC, mmc, 0) \
+ 	func(MMC, mmc, 1) \
+ 	func(SCSI, scsi, 0) \
++	func(NVME, nvme, 0) \
+ 	func(DHCP, dhcp, na)
+ #include <config_distro_bootcmd.h>
+ 
+-- 
+2.17.1
+

patches/u-boot-LSDK-20.12/0009-armv8-lx2160acex7-Fix-booting-from-NVMe-drives.patch

+From 4a5e1552f13acc1e8ee91b456ea37e9d39bdae01 Mon Sep 17 00:00:00 2001
+From: Rabeeh Khoury <rabeeh@solid-run.com>
+Date: Mon, 23 Mar 2020 13:32:09 +0200
+Subject: [PATCH] armv8: lx2160acex7: Fix booting from NVMe drives
+
+Currently NVMe is not initialized so u-boot fails to read kernel from
+NVMe drive. This patch modifies default environment so it initializes
+NVMe as part of default startup script...
+
+Credit to Damjan Marion <dmarion@me.com> on fixing that on LSDK-19.09.
+
+Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
+---
+ include/configs/lx2160a_common.h | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/include/configs/lx2160a_common.h b/include/configs/lx2160a_common.h
+index bacad51bfb..cee462ef63 100644
+--- a/include/configs/lx2160a_common.h
++++ b/include/configs/lx2160a_common.h
+@@ -248,6 +248,7 @@ int select_i2c_ch_pca9547_sec(unsigned char ch);
+ 	BOOTENV					\
+ 	"mcmemsize=0x70000000\0"		\
+ 	XSPI_MC_INIT_CMD				\
++	"nvme_need_init=true\0" \
+ 	"scan_dev_for_boot_part="		\
+ 		"part list ${devtype} ${devnum} devplist; "	\
+ 		"env exists devplist || setenv devplist 1; "	\
+-- 
+2.17.1
+

patches/u-boot-LSDK-20.12/0015-lx2160a-cex7-move-from-lsdk-19.06-to-lsdk-19.09.patch

+From 1dee00c3e75cd6ca9060b526ab5cd3eb376363a6 Mon Sep 17 00:00:00 2001
+From: Rabeeh Khoury <rabeeh@solid-run.com>
+Date: Mon, 3 Feb 2020 14:26:55 +0200
+Subject: [PATCH] lx2160a-cex7 : move from lsdk-19.06 to lsdk-19.09
+
+Following is a list of changes -
+1. I2C moved to DM model
+2. removed emc2301 support
+3. synchronized vid.c with NXP's driver. But it is still not functional
+in u-boot
+4. Added eMMC to distroboot target list
+
+Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
+---
+ arch/arm/dts/fsl-lx2160a-cex7.dts |  14 +
+ board/solidrun/common/Makefile    |   1 -
+ board/solidrun/common/emc2301.c   |  31 --
+ board/solidrun/common/vid.c       | 638 +++++++++++++++++++++++++++++-
+ board/solidrun/lx2160a/lx2160a.c  |   8 +
+ configs/lx2160acex7_tfa_defconfig |   8 +-
+ include/configs/lx2160a_common.h  |   1 +
+ 7 files changed, 666 insertions(+), 35 deletions(-)
+ delete mode 100644 board/solidrun/common/emc2301.c
+
+diff --git a/arch/arm/dts/fsl-lx2160a-cex7.dts b/arch/arm/dts/fsl-lx2160a-cex7.dts
+index 4fbcaafb0e..4ca67df25a 100644
+--- a/arch/arm/dts/fsl-lx2160a-cex7.dts
++++ b/arch/arm/dts/fsl-lx2160a-cex7.dts
+@@ -46,6 +46,20 @@
+ 	status = "okay";
+ };
+ 
++&i2c0 {
++	status = "okay";
++	u-boot,dm-pre-reloc;
++};
++
++&i2c4 {
++	status = "okay";
++
++	rtc@51 {
++		compatible = "pcf2127-rtc";
++		reg = <0x51>;
++	};
++};
++
+ &sata0 {
+ 	status = "okay";
+ };
+diff --git a/board/solidrun/lx2160a/lx2160a.c b/board/solidrun/lx2160a/lx2160a.c
+index b0d9f1012e..3713e91351 100644
+--- a/board/solidrun/lx2160a/lx2160a.c
++++ b/board/solidrun/lx2160a/lx2160a.c
+@@ -62,7 +62,15 @@ int select_i2c_ch_pca9547(u8 ch)
+ {
+ 	int ret;
+ 
++#ifndef CONFIG_DM_I2C
+ 	ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
++#else
++	struct udevice *dev;
++
++	ret = i2c_get_chip_for_busnum(0, I2C_MUX_PCA_ADDR_PRI, 1, &dev);
++	if (!ret)
++		ret = dm_i2c_write(dev, 0, &ch, 1);
++#endif
+ 	if (ret) {
+ 		puts("PCA: failed to select proper channel\n");
+ 		return ret;
+diff --git a/configs/lx2160acex7_tfa_defconfig b/configs/lx2160acex7_tfa_defconfig
+index 3891d2a7c4..89a47adb23 100644
+--- a/configs/lx2160acex7_tfa_defconfig
++++ b/configs/lx2160acex7_tfa_defconfig
+@@ -2,7 +2,6 @@ CONFIG_ARM=y
+ CONFIG_TARGET_LX2160ACEX7=y
+ CONFIG_SYS_TEXT_BASE=0x82000000
+ CONFIG_SYS_MALLOC_F_LEN=0x6000
+-CONFIG_EMC2301=y
+ CONFIG_TFABOOT=y
+ CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
+ CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
+@@ -73,3 +72,10 @@ CONFIG_DM_USB=y
+ CONFIG_USB_XHCI_HCD=y
+ CONFIG_USB_XHCI_DWC3=y
+ CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
++CONFIG_DM_I2C=y
++CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
++CONFIG_I2C_DEFAULT_BUS_NUMBER=0
++CONFIG_DM_RTC=y
++CONFIG_DM_GPIO=y
++CONFIG_CMD_DATE=y
++CONFIG_RTC_PCF2127=y
+-- 
+2.17.1
+

patches/u-boot-LSDK-20.12/0016-lx2160acex7-pcie-fixup-and-boot-from-eMMC-print.patch

+From d2e368b0df941fe8958df4f44dd2c7cfc32d0fb8 Mon Sep 17 00:00:00 2001
+From: Rabeeh Khoury <rabeeh@solid-run.com>
+Date: Mon, 23 Mar 2020 12:53:48 +0200
+Subject: [PATCH 16/16] lx2160acex7: pcie fixup and boot from eMMC print
+
+Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
+---
+ board/solidrun/lx2160a/lx2160a.c  | 66 +++++++++++++++++++++++++++++++
+ configs/lx2160acex7_tfa_defconfig |  3 +-
+ 2 files changed, 68 insertions(+), 1 deletion(-)
+
+diff --git a/board/solidrun/lx2160a/lx2160a.c b/board/solidrun/lx2160a/lx2160a.c
+index 3713e91351..b7211a2d5c 100644
+--- a/board/solidrun/lx2160a/lx2160a.c
++++ b/board/solidrun/lx2160a/lx2160a.c
+@@ -20,6 +20,8 @@
+ #include <efi_loader.h>
+ #include <asm/arch/mmu.h>
+ #include <hwconfig.h>
++#include <asm/arch/clock.h>
++#include <asm/arch/config.h>
+ #include <asm/arch/fsl_serdes.h>
+ #include <asm/arch/soc.h>
+ #include "../../freescale/common/vid.h"
+@@ -106,6 +108,66 @@ int board_early_init_f(void)
+ #ifdef CONFIG_OF_BOARD_FIXUP
+ int board_fix_fdt(void *fdt)
+ {
++	char *reg_name, *old_str, *new_str;
++	const char *reg_names;
++	int names_len, old_str_len, new_str_len, remaining_str_len;
++	struct str_map {
++		char *old_str;
++		char *new_str;
++	} reg_names_map[] = {
++		{ "ccsr", "dbi" },
++		{ "pf_ctrl", "ctrl" }
++	};
++	int off = -1, i;
++
++	if (IS_SVR_REV(get_svr(), 1, 0))
++		return 0;
++
++	off = fdt_node_offset_by_compatible(fdt, -1, "fsl,lx2160a-pcie");
++	while (off != -FDT_ERR_NOTFOUND) {
++		fdt_setprop(fdt, off, "compatible", "fsl,ls-pcie",
++			    strlen("fsl,ls-pcie") + 1);
++
++		reg_names = fdt_getprop(fdt, off, "reg-names", &names_len);
++		if (!reg_names)
++			continue;
++
++		reg_name = (char *)reg_names;
++		remaining_str_len = names_len - (reg_name - reg_names);
++		i = 0;
++		while ((i < ARRAY_SIZE(reg_names_map)) && remaining_str_len) {
++			old_str = reg_names_map[i].old_str;
++			new_str = reg_names_map[i].new_str;
++			old_str_len = strlen(old_str);
++			new_str_len = strlen(new_str);
++			if (memcmp(reg_name, old_str, old_str_len) == 0) {
++				/* first only leave required bytes for new_str
++				 * and copy rest of the string after it
++				 */
++				memcpy(reg_name + new_str_len,
++				       reg_name + old_str_len,
++				       remaining_str_len - old_str_len);
++				/* Now copy new_str */
++				memcpy(reg_name, new_str, new_str_len);
++				names_len -= old_str_len;
++				names_len += new_str_len;
++				i++;
++			}
++
++			reg_name = memchr(reg_name, '\0', remaining_str_len);
++			if (!reg_name)
++				break;
++
++			reg_name += 1;
++
++			remaining_str_len = names_len - (reg_name - reg_names);
++		}
++
++		fdt_setprop(fdt, off, "reg-names", reg_names, names_len);
++		off = fdt_node_offset_by_compatible(fdt, off,
++						    "fsl,lx2160a-pcie");
++	}
++
+ 	return 0;
+ }
+ #endif
+@@ -135,6 +197,10 @@ int checkboard(void)
+ 
+ 	if (src == BOOT_SOURCE_SD_MMC) {
+ 		puts("SD\n");
++	} else if (src == BOOT_SOURCE_SD_MMC2) {
++		puts("eMMC\n");
++	} else {
++		puts("FlexSPI DEV#0\n");
+ 	}
+ 	puts("SERDES1 Reference: Clock1 = 161.13MHz Clock2 = 100MHz\n");
+ 	puts("SERDES2 Reference: Clock1 = 100MHz Clock2 = 100MHz\n");
+diff --git a/configs/lx2160acex7_tfa_defconfig b/configs/lx2160acex7_tfa_defconfig
+index 89a47adb23..2a3441d263 100644
+--- a/configs/lx2160acex7_tfa_defconfig
++++ b/configs/lx2160acex7_tfa_defconfig
+@@ -2,6 +2,7 @@ CONFIG_ARM=y
+ CONFIG_TARGET_LX2160ACEX7=y
+ CONFIG_SYS_TEXT_BASE=0x82000000
+ CONFIG_SYS_MALLOC_F_LEN=0x6000
++CONFIG_FSPI_AHB_EN_4BYTE=y
+ CONFIG_TFABOOT=y
+ CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
+ CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
+@@ -59,6 +60,7 @@ CONFIG_PCI=y
+ CONFIG_DM_PCI_COMPAT=y
+ CONFIG_PCIE_LAYERSCAPE_GEN4=y
+ CONFIG_PHY_ATHEROS=y
++CONFIG_PCIE_LAYERSCAPE=y
+ CONFIG_E1000=y
+ CONFIG_DM_SCSI=y
+ CONFIG_DM_SERIAL=y
+-- 
+2.17.1
+

patches/u-boot-LSDK-20.12/0017-lx2160a-cex7-set-mmc-dev-to-0-when-attempting-sd_boo.patch

+From 1ec9f76ce5813ec7f2f825aecf0b9c6a2d8d1cf0 Mon Sep 17 00:00:00 2001
+From: Rabeeh Khoury <rabeeh@solid-run.com>
+Date: Mon, 23 Mar 2020 15:13:11 +0200
+Subject: [PATCH 17/17] lx2160a-cex7: set mmc dev to 0 when attempting
+ sd_bootcmd
+
+When attempting sd_bootcmd which is the fallback of failed distroboot
+then set mmc dev to 0; since distroboot already set that variable to 1.
+
+Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
+---
+ include/configs/lx2160acex7.h | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/include/configs/lx2160acex7.h b/include/configs/lx2160acex7.h
+index 478cd8242f..7116e038a1 100644
+--- a/include/configs/lx2160acex7.h
++++ b/include/configs/lx2160acex7.h
+@@ -73,7 +73,7 @@
+ 		"$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
+ 		" bootm $load_addr#$BOARD\0"			\
+ 	"sd_bootcmd=echo Trying load from sd card..;"		\
+-		"mmcinfo; mmc read $load_addr "			\
++		"mmc dev 0; mmcinfo; mmc read $load_addr "			\
+ 		"$kernel_addr_sd $kernel_size_sd ;"		\
+ 		"env exists secureboot && mmc read $kernelheader_addr_r "\
+ 		"$kernelhdr_addr_sd $kernelhdr_size_sd "	\
+-- 
+2.17.1
+

patches/u-boot-LSDK-20.12/0018-lx2160acex7-Misc-fixes-to-support-LSDK-20.04.patch

+From 341eb7a1e9ce5f7764f39002b96e7975955cac0e Mon Sep 17 00:00:00 2001
+From: Rabeeh Khoury <rabeeh@solid-run.com>
+Date: Mon, 4 May 2020 22:52:02 +0300
+Subject: [PATCH] lx2160acex7: Misc fixes to support LSDK-20.04
+
+Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
+---
+ arch/arm/Kconfig                  |  1 +
+ board/solidrun/lx2160a/lx2160a.c  |  4 +++-
+ configs/lx2160acex7_tfa_defconfig | 24 ++++++++++++------------
+ 3 files changed, 16 insertions(+), 13 deletions(-)
+
+diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
+index 8615e1673f..c78e17a0ed 100644
+--- a/arch/arm/Kconfig
++++ b/arch/arm/Kconfig
+@@ -1195,6 +1195,7 @@ config TARGET_LX2160ACEX7
+ 	select ARCH_MISC_INIT
+ 	select ARM64
+ 	select ARMV8_MULTIENTRY
++	select ARCH_SUPPORT_TFABOOT
+ 	select BOARD_LATE_INIT
+ 	help
+ 	  Support for SolidRun LX2160A based com express type 7 module and
+diff --git a/board/solidrun/lx2160a/lx2160a.c b/board/solidrun/lx2160a/lx2160a.c
+index b7211a2d5c..975431fd53 100644
+--- a/board/solidrun/lx2160a/lx2160a.c
++++ b/board/solidrun/lx2160a/lx2160a.c
+@@ -16,7 +16,7 @@
+ #include <fdt_support.h>
+ #include <linux/libfdt.h>
+ #include <fsl-mc/fsl_mc.h>
+-#include <environment.h>
++#include <env_internal.h>
+ #include <efi_loader.h>
+ #include <asm/arch/mmu.h>
+ #include <hwconfig.h>
+@@ -26,6 +26,8 @@
+ #include <asm/arch/soc.h>
+ #include "../../freescale/common/vid.h"
+ #include <fsl_immap.h>
++#include <asm/arch-fsl-layerscape/fsl_icid.h>
++#include <asm/gic-v3.h>
+ 
+ #ifdef CONFIG_EMC2301
+ #include "../common/emc2301.h"
+diff --git a/configs/lx2160acex7_tfa_defconfig b/configs/lx2160acex7_tfa_defconfig
+index 2a3441d263..d2e62a6e91 100644
+--- a/configs/lx2160acex7_tfa_defconfig
++++ b/configs/lx2160acex7_tfa_defconfig
+@@ -1,16 +1,15 @@
+ CONFIG_ARM=y
+ CONFIG_TARGET_LX2160ACEX7=y
++CONFIG_TFABOOT=y
+ CONFIG_SYS_TEXT_BASE=0x82000000
+ CONFIG_SYS_MALLOC_F_LEN=0x6000
+ CONFIG_FSPI_AHB_EN_4BYTE=y
+-CONFIG_TFABOOT=y
++CONFIG_NR_DRAM_BANKS=3
+ CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
+ CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
+ CONFIG_AHCI=y
+-CONFIG_NR_DRAM_BANKS=3
+ CONFIG_FIT_VERBOSE=y
+ CONFIG_OF_BOARD_SETUP=y
+-CONFIG_OF_BOARD_FIXUP=y
+ CONFIG_OF_STDOUT_VIA_ALIAS=y
+ CONFIG_BOOTDELAY=10
+ CONFIG_USE_BOOTARGS=y
+@@ -29,6 +28,7 @@ CONFIG_CMD_NVME=y
+ CONFIG_NVME=y
+ CONFIG_MP=y
+ CONFIG_OF_CONTROL=y
++CONFIG_OF_BOARD_FIXUP=y
+ CONFIG_DEFAULT_DEVICE_TREE="fsl-lx2160a-cex7"
+ CONFIG_ENV_IS_IN_MMC=y
+ CONFIG_ENV_IS_IN_SPI_FLASH=y
+@@ -36,6 +36,10 @@ CONFIG_NET_RANDOM_ETHADDR=y
+ CONFIG_DM=y
+ CONFIG_SATA_CEVA=y
+ CONFIG_FSL_CAAM=y
++CONFIG_DM_GPIO=y
++CONFIG_DM_I2C=y
++CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
++CONFIG_I2C_DEFAULT_BUS_NUMBER=0
+ CONFIG_DM_MMC=y
+ CONFIG_FSL_ESDHC=y
+ CONFIG_DM_SPI_FLASH=y
+@@ -55,28 +59,24 @@ CONFIG_CMD_MII=y
+ CONFIG_CMD_DHCP=y
+ CONFIG_CMD_FAT=y
+ CONFIG_CMD_EXT2=y
++CONFIG_E1000=y
+ CONFIG_PCI=y
+ CONFIG_DM_PCI=y
+ CONFIG_DM_PCI_COMPAT=y
+ CONFIG_PCIE_LAYERSCAPE_GEN4=y
+ CONFIG_PHY_ATHEROS=y
+ CONFIG_PCIE_LAYERSCAPE=y
+-CONFIG_E1000=y
++CONFIG_DM_RTC=y
++CONFIG_RTC_PCF2127=y
++
+ CONFIG_DM_SCSI=y
+ CONFIG_DM_SERIAL=y
+-CONFIG_SERIAL_PROBE_ALL=y
+ CONFIG_SPI=y
+ CONFIG_DM_SPI=y
+ CONFIG_NXP_FSPI=y
+-# CONFIG_SYS_NXP_FSPI_AHB=y
+ CONFIG_USB=y
+ CONFIG_DM_USB=y
+ CONFIG_USB_XHCI_HCD=y
+ CONFIG_USB_XHCI_DWC3=y
+ CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+-CONFIG_DM_I2C=y
+-CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+-CONFIG_I2C_DEFAULT_BUS_NUMBER=0
+-CONFIG_DM_RTC=y
+-CONFIG_DM_GPIO=y
+ CONFIG_CMD_DATE=y
+-CONFIG_RTC_PCF2127=y
++CONFIG_GIC_V3_ITS=y
+-- 
+2.17.1
+

patches/u-boot-LSDK-20.12/0019-lx2160acex7-misc-fixes-to-get-booting-from-eMMC-func.patch

+From 1e1e86ebef25670922c7e1e65d897a4dba9a806f Mon Sep 17 00:00:00 2001
+From: Rabeeh Khoury <rabeeh@solid-run.com>
+Date: Tue, 5 May 2020 01:01:01 +0300
+Subject: [PATCH] lx2160acex7: misc fixes to get booting from eMMC functional
+
+Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
+---
+ include/configs/lx2160a_common.h | 10 ++++++++++
+ include/configs/lx2160acex7.h    | 14 ++++++++------
+ 2 files changed, 18 insertions(+), 6 deletions(-)
+
+diff --git a/include/configs/lx2160a_common.h b/include/configs/lx2160a_common.h
+index 8983e615d1..d65e5c5cf2 100644
+--- a/include/configs/lx2160a_common.h
++++ b/include/configs/lx2160a_common.h
+@@ -225,6 +225,16 @@ int select_i2c_ch_pca9547_sec(unsigned char ch);
+ 	"esbc_validate 0x80680000 ;"		\
+ 	"fsl_mc start mc 0x80a00000 0x80e00000\0"
+ 
++#define SD2_MC_INIT_CMD				\
++	"mmc dev 1; mmc read 0x80a00000 0x5000 0x1200;"	\
++	"mmc read 0x80e00000 0x7000 0x800;"	\
++	"env exists secureboot && "		\
++	"mmc read 0x80640000 0x3200 0x20 && "	\
++	"mmc read 0x80680000 0x3400 0x20 && "	\
++	"esbc_validate 0x80640000 && "		\
++	"esbc_validate 0x80680000 ;"		\
++	"fsl_mc start mc 0x80a00000 0x80e00000\0"
++
+ #define EXTRA_ENV_SETTINGS			\
+ 	"hwconfig=fsl_ddr:bank_intlv=auto\0"	\
+ 	"ramdisk_addr=0x800000\0"		\
+diff --git a/include/configs/lx2160acex7.h b/include/configs/lx2160acex7.h
+index 7116e038a1..310168db47 100644
+--- a/include/configs/lx2160acex7.h
++++ b/include/configs/lx2160acex7.h
+@@ -46,11 +46,6 @@
+ 
+ #endif
+ 
+-/* EMC2301 */
+-#define I2C_MUX_CH_EMC2301	0x01
+-#define I2C_EMC2301_ADDR	0x2f
+-#define I2C_EMC2301_CMD		0x40
+-#define I2C_EMC2301_PWM		0x80
+ 
+ /* EEPROM */
+ #undef CONFIG_ID_EEPROM /* Fixme */
+@@ -73,7 +68,14 @@
+ 		"$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
+ 		" bootm $load_addr#$BOARD\0"			\
+ 	"sd_bootcmd=echo Trying load from sd card..;"		\
+-		"mmc dev 0; mmcinfo; mmc read $load_addr "			\
++		"mmcinfo; mmc read $load_addr "			\
++		"$kernel_addr_sd $kernel_size_sd ;"		\
++		"env exists secureboot && mmc read $kernelheader_addr_r "\
++		"$kernelhdr_addr_sd $kernelhdr_size_sd "	\
++		" && esbc_validate ${kernelheader_addr_r};"	\
++		"bootm $load_addr#$BOARD\0"			\
++	"emmc_bootcmd=echo Trying load from emmc card..;"	\
++		"mmc dev 1; mmcinfo; mmc read $load_addr "	\
+ 		"$kernel_addr_sd $kernel_size_sd ;"		\
+ 		"env exists secureboot && mmc read $kernelheader_addr_r "\
+ 		"$kernelhdr_addr_sd $kernelhdr_size_sd "	\
+-- 
+2.17.1
+