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Commit e89f4ca6 authored by Josua Mayer's avatar Josua Mayer
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clearfog-cx/honeycomb: add support for serdes 1 protocol 20 (2x 40G)

parent e2825118
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patches/linux-LSDK-21.08/0050-arm64-dts-lx2160a-clearfog-itx-add-dpmac1-2-for-40G-.patch 0 → 100644
View file @ e89f4ca6
From dd33a19abb61f56ce74a16e4cad842949e45276c Mon Sep 17 00:00:00 2001
From: Josua Mayer <josua@solid-run.com>
Date: Mon, 3 Apr 2023 13:25:50 +0300
Subject: [PATCH] arm64: dts: lx2160a-clearfog-itx: add dpmac1&2 for 40G/100G
NICs
network interfaces bundling multiple serdes lanes for either 40G or 100G
use dpmac numbers 1 & 2. Enable the corresponding pcs nodes, but do not
configure any sfp or serdes runtime configuration.
Signed-off-by: Josua Mayer <josua@solid-run.com>
---
.../dts/freescale/fsl-lx2160a-clearfog-itx.dtsi | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-itx.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-itx.dtsi
index 86036bd39b6a..3aa8a1fe50d0 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-itx.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-itx.dtsi
@@ -67,7 +67,16 @@ sfp3: sfp-3 {
};
};
+&dpmac1 {
+ managed = "in-band-status";
+};
+
+&dpmac2 {
+ managed = "in-band-status";
+};
+
&dpmac3 {
+ sfp = <&qsfp0>;
managed = "in-band-status";
phys = <&serdes_1 7>;
};
@@ -135,6 +144,14 @@ carrier_flash: w25q32@1 {
};
};
+&pcs_mdio1 {
+ status = "okay";
+};
+
+&pcs_mdio2 {
+ status = "okay";
+};
+
&pcs_mdio3 {
status = "okay";
};
--
2.35.3
patches/mc-utils/0013-lx2160acex7-update-dpl-dpc-for-serdes-1-protocol-20-.patch 0 → 100644
View file @ e89f4ca6
From 9def3cbab084d93bcc52b45656aef0006c71b0e1 Mon Sep 17 00:00:00 2001
From: Josua Mayer <josua@solid-run.com>
Date: Mon, 3 Apr 2023 13:23:31 +0300
Subject: [PATCH] lx2160acex7: update dpl/dpc for serdes 1 protocol 20 (2x40G)
Signed-off-by: Josua Mayer <josua@solid-run.com>
---
config/lx2160a/CEX7/dpc-dual-40g.dts | 76 ++-
config/lx2160a/CEX7/dpl-eth.dual-40g.19.dts | 610 ++++++++++++--------
2 files changed, 404 insertions(+), 282 deletions(-)
diff --git a/config/lx2160a/CEX7/dpc-dual-40g.dts b/config/lx2160a/CEX7/dpc-dual-40g.dts
index 0601a07..a7a6329 100644
--- a/config/lx2160a/CEX7/dpc-dual-40g.dts
+++ b/config/lx2160a/CEX7/dpc-dual-40g.dts
@@ -1,42 +1,36 @@
/*
-* Copyright 2018 NXP
-*
-* Redistribution and use in source and binary forms, with or without
-* modification, are permitted provided that the following conditions are met:
-* * Redistributions of source code must retain the above copyright
-* notice, this list of conditions and the following disclaimer.
-* * Redistributions in binary form must reproduce the above copyright
-* notice, this list of conditions and the following disclaimer in the
-* documentation and/or other materials provided with the distribution.
-* * Neither the name of the above-listed copyright holders nor the
-* names of any contributors may be used to endorse or promote products
-* derived from this software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
-* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.
-*/
-
-/*
-* This DPC showcases one Linux configuration for lx2160a boards.
-*/
+ * Copyright 2020 NXP
+ * Copyright 2022 Josua Mayer <josua@solid-run.com>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of the above-listed copyright holders nor the
+ * names of any contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
/dts-v1/;
/ {
-
resources {
-
icid_pools {
-
icid_pool@1 {
num = <0x64>;
base_icid = <0x0>;
@@ -45,7 +39,6 @@
};
mc_general {
-
log {
mode = "LOG_MODE_ON";
level = "LOG_LEVEL_WARNING";
@@ -59,26 +52,29 @@
};
controllers {
-
qbman {
/* Transform this number of 8-WQ channels into four times
* as many 2-WQ channels. This allows the creation of a
* larger number of DPCONs.
*/
- wq_ch_conversion = <32>;
+ wq_ch_conversion = <64>;
};
};
board_info {
ports {
+ /* SGMII */
+ mac@17 {
+ link_type = "MAC_LINK_TYPE_PHY";
+ };
+
+ /* Serdes 1 */
mac@1 {
- link_type = "MAC_LINK_TYPE_FIXED";
+ link_type = "MAC_LINK_TYPE_BACKPLANE";
};
+
mac@2 {
- link_type = "MAC_LINK_TYPE_FIXED";
- };
- mac@17 {
- link_type = "MAC_LINK_TYPE_PHY";
+ link_type = "MAC_LINK_TYPE_BACKPLANE";
};
};
};
diff --git a/config/lx2160a/CEX7/dpl-eth.dual-40g.19.dts b/config/lx2160a/CEX7/dpl-eth.dual-40g.19.dts
index 5619fd2..4273c15 100644
--- a/config/lx2160a/CEX7/dpl-eth.dual-40g.19.dts
+++ b/config/lx2160a/CEX7/dpl-eth.dual-40g.19.dts
@@ -1,88 +1,52 @@
-/*
- * Copyright 2018 NXP
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the above-listed copyright holders nor the
- * names of any contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
/dts-v1/;
-
/ {
- dpl-version = <0xa>;
+ dpl-version = <10>;
/*****************************************************************
* Containers
*****************************************************************/
containers {
+
dprc@1 {
+ compatible = "fsl,dprc";
parent = "none";
- options = "DPRC_CFG_OPT_SPAWN_ALLOWED", "DPRC_CFG_OPT_ALLOC_ALLOWED", "DPRC_CFG_OPT_IRQ_CFG_ALLOWED";
- objects {
- /* ------------ DPNIs --------------*/
- obj_set@dpni {
- type = "dpni";
- ids = <0x0>;
- };
-
-
- /* ------------ DPMACs --------------*/
- obj_set@dpmac {
- type = "dpmac";
- ids = <0x1 0x2 0x11>;
- };
+ options = "DPRC_CFG_OPT_SPAWN_ALLOWED", "DPRC_CFG_OPT_ALLOC_ALLOWED", "DPRC_CFG_OPT_OBJ_CREATE_ALLOWED", "DPRC_CFG_OPT_TOPOLOGY_CHANGES_ALLOWED", "DPRC_CFG_OPT_IRQ_CFG_ALLOWED";
+ objects {
- /* ------------ DPBPs --------------*/
+ /* -------------- DPBPs --------------*/
obj_set@dpbp {
type = "dpbp";
- ids = <0x0 0x1>;
+ ids = <0 1 2 >;
};
- /* ------------ DPIOs --------------*/
- obj_set@dpio {
- type = "dpio";
- ids = <0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xa 0xb 0xc 0xd 0xe 0xf>;
+ /* -------------- DPCONs --------------*/
+ obj_set@dpcon {
+ type = "dpcon";
+ ids = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 >;
};
- /* ------------ DPMCPs --------------*/
- obj_set@dpmcp {
- type = "dpmcp";
- ids = <0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xa 0xb 0xc 0xd 0xe 0xf 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1a 0x1b 0x1c 0x1d 0x1e 0x1f 0x20 0x21 0x22 0x23>;
+ /* -------------- DPIOs --------------*/
+ obj_set@dpio {
+ type = "dpio";
+ ids = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 >;
};
- /* ------------ DPCON --------------*/
- obj_set@dpcon {
- type = "dpcon";
- ids = <0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xa 0xb 0xc 0xd 0xe 0xf 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1a 0x1b 0x1c 0x1d 0x1e 0x1f>;
+ /* -------------- DPMACs --------------*/
+ obj_set@dpmac {
+ type = "dpmac";
+ ids = <1 2 17 >;
};
- /* ------------ DPSECI --------------*/
- obj@700 {
- obj_name = "dpseci@0";
+ /* -------------- DPMCPs --------------*/
+ obj_set@dpmcp {
+ type = "dpmcp";
+ ids = <1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 >;
};
- /* ------------ DPRTC --------------*/
- obj@800 {
- obj_name="dprtc@0";
+ /* -------------- DPNIs --------------*/
+ obj_set@dpni {
+ type = "dpni";
+ ids = <0 >;
};
};
};
@@ -93,415 +57,593 @@
*****************************************************************/
objects {
- /* ------------ DPNI --------------*/
- dpni@0 {
- options = "DPNI_OPT_HAS_KEY_MASKING";
- num_queues = <0x10>;
- num_tcs = <0x1>;
- };
- dpni@1 {
- options = "DPNI_OPT_HAS_KEY_MASKING";
- num_queues = <0x10>;
- num_tcs = <0x1>;
- };
- dpni@2 {
- options = "DPNI_OPT_HAS_KEY_MASKING";
- num_queues = <0x10>;
- num_tcs = <0x1>;
- };
- dpni@3 {
- options = "DPNI_OPT_HAS_KEY_MASKING";
- num_queues = <0x10>;
- num_tcs = <0x1>;
- };
- dpni@4 {
- options = "DPNI_OPT_HAS_KEY_MASKING";
- num_queues = <0x10>;
- num_tcs = <0x1>;
- };
- dpni@5 {
- options = "DPNI_OPT_HAS_KEY_MASKING";
- num_queues = <0x10>;
- num_tcs = <0x1>;
- };
- dpni@6 {
- options = "DPNI_OPT_HAS_KEY_MASKING";
- num_queues = <0x10>;
- num_tcs = <0x1>;
- };
- dpni@7 {
- options = "DPNI_OPT_HAS_KEY_MASKING";
- num_queues = <0x10>;
- num_tcs = <0x1>;
- };
- dpni@8 {
- options = "DPNI_OPT_HAS_KEY_MASKING";
- num_queues = <0x10>;
- num_tcs = <0x1>;
+ dpbp@0 {
+ compatible = "fsl,dpbp";
};
- dpmac@1 {
+
+ dpbp@1 {
+ compatible = "fsl,dpbp";
};
- dpmac@2 {
+
+ dpbp@2 {
+ compatible = "fsl,dpbp";
};
- dpmac@3 {
+ dpcon@0 {
+ compatible = "fsl,dpcon";
+ num_priorities = <0x2>;
};
- dpmac@4 {
+ dpcon@1 {
+ compatible = "fsl,dpcon";
+ num_priorities = <0x2>;
};
- dpmac@5 {
+ dpcon@2 {
+ compatible = "fsl,dpcon";
+ num_priorities = <0x2>;
};
- dpmac@6 {
+ dpcon@3 {
+ compatible = "fsl,dpcon";
+ num_priorities = <0x2>;
};
- dpmac@7 {
+
+ dpcon@4 {
+ compatible = "fsl,dpcon";
+ num_priorities = <0x2>;
};
- dpmac@8 {
+
+ dpcon@5 {
+ compatible = "fsl,dpcon";
+ num_priorities = <0x2>;
};
- dpmac@9 {
+
+ dpcon@6 {
+ compatible = "fsl,dpcon";
+ num_priorities = <0x2>;
};
- dpmac@10 {
+
+ dpcon@7 {
+ compatible = "fsl,dpcon";
+ num_priorities = <0x2>;
};
- dpmac@17 {
+ dpcon@8 {
+ compatible = "fsl,dpcon";
+ num_priorities = <0x2>;
};
- dpmac@18 {
+ dpcon@9 {
+ compatible = "fsl,dpcon";
+ num_priorities = <0x2>;
};
- /* ------------ DPBP --------------*/
- dpbp@0 {
+ dpcon@10 {
+ compatible = "fsl,dpcon";
+ num_priorities = <0x2>;
};
- dpbp@1 {
+ dpcon@11 {
+ compatible = "fsl,dpcon";
+ num_priorities = <0x2>;
+ };
+
+ dpcon@12 {
+ compatible = "fsl,dpcon";
+ num_priorities = <0x2>;
+ };
+
+ dpcon@13 {
+ compatible = "fsl,dpcon";
+ num_priorities = <0x2>;
+ };
+
+ dpcon@14 {
+ compatible = "fsl,dpcon";
+ num_priorities = <0x2>;
+ };
+
+ dpcon@15 {
+ compatible = "fsl,dpcon";
+ num_priorities = <0x2>;
+ };
+
+ dpcon@16 {
+ compatible = "fsl,dpcon";
+ num_priorities = <0x2>;
+ };
+
+ dpcon@17 {
+ compatible = "fsl,dpcon";
+ num_priorities = <0x2>;
+ };
+
+ dpcon@18 {
+ compatible = "fsl,dpcon";
+ num_priorities = <0x2>;
+ };
+
+ dpcon@19 {
+ compatible = "fsl,dpcon";
+ num_priorities = <0x2>;
+ };
+
+ dpcon@20 {
+ compatible = "fsl,dpcon";
+ num_priorities = <0x2>;
+ };
+
+ dpcon@21 {
+ compatible = "fsl,dpcon";
+ num_priorities = <0x2>;
+ };
+
+ dpcon@22 {
+ compatible = "fsl,dpcon";
+ num_priorities = <0x2>;
+ };
+
+ dpcon@23 {
+ compatible = "fsl,dpcon";
+ num_priorities = <0x2>;
+ };
+
+ dpcon@24 {
+ compatible = "fsl,dpcon";
+ num_priorities = <0x2>;
+ };
+
+ dpcon@25 {
+ compatible = "fsl,dpcon";
+ num_priorities = <0x2>;
+ };
+
+ dpcon@26 {
+ compatible = "fsl,dpcon";
+ num_priorities = <0x2>;
+ };
+
+ dpcon@27 {
+ compatible = "fsl,dpcon";
+ num_priorities = <0x2>;
+ };
+
+ dpcon@28 {
+ compatible = "fsl,dpcon";
+ num_priorities = <0x2>;
+ };
+
+ dpcon@29 {
+ compatible = "fsl,dpcon";
+ num_priorities = <0x2>;
+ };
+
+ dpcon@30 {
+ compatible = "fsl,dpcon";
+ num_priorities = <0x2>;
+ };
+
+ dpcon@31 {
+ compatible = "fsl,dpcon";
+ num_priorities = <0x2>;
+ };
+
+ dpcon@32 {
+ compatible = "fsl,dpcon";
+ num_priorities = <0x2>;
};
+ dpcon@33 {
+ compatible = "fsl,dpcon";
+ num_priorities = <0x2>;
+ };
+
+ dpcon@34 {
+ compatible = "fsl,dpcon";
+ num_priorities = <0x2>;
+ };
+
+ dpcon@35 {
+ compatible = "fsl,dpcon";
+ num_priorities = <0x2>;
+ };
+
+ dpcon@36 {
+ compatible = "fsl,dpcon";
+ num_priorities = <0x2>;
+ };
+
+ dpcon@37 {
+ compatible = "fsl,dpcon";
+ num_priorities = <0x2>;
+ };
+
+ dpcon@38 {
+ compatible = "fsl,dpcon";
+ num_priorities = <0x2>;
+ };
+
+ dpcon@39 {
+ compatible = "fsl,dpcon";
+ num_priorities = <0x2>;
+ };
+
+ dpcon@40 {
+ compatible = "fsl,dpcon";
+ num_priorities = <0x2>;
+ };
+
+ dpcon@41 {
+ compatible = "fsl,dpcon";
+ num_priorities = <0x2>;
+ };
+
+ dpcon@42 {
+ compatible = "fsl,dpcon";
+ num_priorities = <0x2>;
+ };
+
+ dpcon@43 {
+ compatible = "fsl,dpcon";
+ num_priorities = <0x2>;
+ };
+
+ dpcon@44 {
+ compatible = "fsl,dpcon";
+ num_priorities = <0x2>;
+ };
+
+ dpcon@45 {
+ compatible = "fsl,dpcon";
+ num_priorities = <0x2>;
+ };
+
+ dpcon@46 {
+ compatible = "fsl,dpcon";
+ num_priorities = <0x2>;
+ };
+
+ dpcon@47 {
+ compatible = "fsl,dpcon";
+ num_priorities = <0x2>;
+ };
- /* ------------ DPIO --------------*/
dpio@0 {
+ compatible = "fsl,dpio";
channel_mode = "DPIO_LOCAL_CHANNEL";
num_priorities = <0x8>;
};
dpio@1 {
+ compatible = "fsl,dpio";
channel_mode = "DPIO_LOCAL_CHANNEL";
num_priorities = <0x8>;
};
dpio@2 {
+ compatible = "fsl,dpio";
channel_mode = "DPIO_LOCAL_CHANNEL";
num_priorities = <0x8>;
};
dpio@3 {
+ compatible = "fsl,dpio";
channel_mode = "DPIO_LOCAL_CHANNEL";
num_priorities = <0x8>;
};
dpio@4 {
+ compatible = "fsl,dpio";
channel_mode = "DPIO_LOCAL_CHANNEL";
num_priorities = <0x8>;
};
dpio@5 {
+ compatible = "fsl,dpio";
channel_mode = "DPIO_LOCAL_CHANNEL";
num_priorities = <0x8>;
};
dpio@6 {
+ compatible = "fsl,dpio";
channel_mode = "DPIO_LOCAL_CHANNEL";
num_priorities = <0x8>;
};
dpio@7 {
+ compatible = "fsl,dpio";
channel_mode = "DPIO_LOCAL_CHANNEL";
num_priorities = <0x8>;
};
dpio@8 {
+ compatible = "fsl,dpio";
channel_mode = "DPIO_LOCAL_CHANNEL";
num_priorities = <0x8>;
};
dpio@9 {
+ compatible = "fsl,dpio";
channel_mode = "DPIO_LOCAL_CHANNEL";
num_priorities = <0x8>;
};
dpio@10 {
+ compatible = "fsl,dpio";
channel_mode = "DPIO_LOCAL_CHANNEL";
num_priorities = <0x8>;
};
dpio@11 {
+ compatible = "fsl,dpio";
channel_mode = "DPIO_LOCAL_CHANNEL";
num_priorities = <0x8>;
};
dpio@12 {
+ compatible = "fsl,dpio";
channel_mode = "DPIO_LOCAL_CHANNEL";
num_priorities = <0x8>;
};
dpio@13 {
+ compatible = "fsl,dpio";
channel_mode = "DPIO_LOCAL_CHANNEL";
num_priorities = <0x8>;
};
dpio@14 {
+ compatible = "fsl,dpio";
channel_mode = "DPIO_LOCAL_CHANNEL";
num_priorities = <0x8>;
};
dpio@15 {
+ compatible = "fsl,dpio";
channel_mode = "DPIO_LOCAL_CHANNEL";
num_priorities = <0x8>;
};
- /* ------------ DPMCP --------------*/
+ dpmac@1 {
+ compatible = "fsl,dpmac";
+ };
+
+ dpmac@2 {
+ compatible = "fsl,dpmac";
+ };
+
+ dpmac@17 {
+ compatible = "fsl,dpmac";
+ };
+
dpmcp@1 {
+ compatible = "fsl,dpmcp";
};
dpmcp@2 {
+ compatible = "fsl,dpmcp";
};
dpmcp@3 {
+ compatible = "fsl,dpmcp";
};
dpmcp@4 {
+ compatible = "fsl,dpmcp";
};
dpmcp@5 {
+ compatible = "fsl,dpmcp";
};
dpmcp@6 {
+ compatible = "fsl,dpmcp";
};
dpmcp@7 {
+ compatible = "fsl,dpmcp";
};
dpmcp@8 {
+ compatible = "fsl,dpmcp";
};
dpmcp@9 {
+ compatible = "fsl,dpmcp";
};
dpmcp@10 {
+ compatible = "fsl,dpmcp";
};
dpmcp@11 {
+ compatible = "fsl,dpmcp";
};
dpmcp@12 {
+ compatible = "fsl,dpmcp";
};
dpmcp@13 {
+ compatible = "fsl,dpmcp";
};
dpmcp@14 {
+ compatible = "fsl,dpmcp";
};
dpmcp@15 {
+ compatible = "fsl,dpmcp";
};
dpmcp@16 {
+ compatible = "fsl,dpmcp";
};
dpmcp@17 {
+ compatible = "fsl,dpmcp";
};
dpmcp@18 {
+ compatible = "fsl,dpmcp";
};
dpmcp@19 {
+ compatible = "fsl,dpmcp";
};
dpmcp@20 {
+ compatible = "fsl,dpmcp";
};
dpmcp@21 {
+ compatible = "fsl,dpmcp";
};
dpmcp@22 {
+ compatible = "fsl,dpmcp";
};
dpmcp@23 {
+ compatible = "fsl,dpmcp";
};
dpmcp@24 {
+ compatible = "fsl,dpmcp";
};
dpmcp@25 {
+ compatible = "fsl,dpmcp";
};
dpmcp@26 {
+ compatible = "fsl,dpmcp";
};
dpmcp@27 {
+ compatible = "fsl,dpmcp";
};
dpmcp@28 {
+ compatible = "fsl,dpmcp";
};
dpmcp@29 {
+ compatible = "fsl,dpmcp";
};
dpmcp@30 {
+ compatible = "fsl,dpmcp";
};
dpmcp@31 {
+ compatible = "fsl,dpmcp";
};
dpmcp@32 {
+ compatible = "fsl,dpmcp";
};
dpmcp@33 {
+ compatible = "fsl,dpmcp";
};
dpmcp@34 {
+ compatible = "fsl,dpmcp";
};
dpmcp@35 {
+ compatible = "fsl,dpmcp";
};
- /* ------------ DPCON --------------*/
- dpcon@0 {
- num_priorities = <0x2>;
- };
-
- dpcon@1 {
- num_priorities = <0x2>;
- };
-
- dpcon@2 {
- num_priorities = <0x2>;
- };
-
- dpcon@3 {
- num_priorities = <0x2>;
- };
-
- dpcon@4 {
- num_priorities = <0x2>;
- };
-
- dpcon@5 {
- num_priorities = <0x2>;
- };
-
- dpcon@6 {
- num_priorities = <0x2>;
+ dpmcp@36 {
+ compatible = "fsl,dpmcp";
};
- dpcon@7 {
- num_priorities = <0x2>;
+ dpmcp@37 {
+ compatible = "fsl,dpmcp";
};
- dpcon@8 {
- num_priorities = <0x2>;
+ dpmcp@38 {
+ compatible = "fsl,dpmcp";
};
- dpcon@9 {
- num_priorities = <0x2>;
+ dpmcp@39 {
+ compatible = "fsl,dpmcp";
};
- dpcon@10 {
- num_priorities = <0x2>;
+ dpmcp@40 {
+ compatible = "fsl,dpmcp";
};
- dpcon@11 {
- num_priorities = <0x2>;
+ dpmcp@41 {
+ compatible = "fsl,dpmcp";
};
- dpcon@12 {
- num_priorities = <0x2>;
+ dpmcp@42 {
+ compatible = "fsl,dpmcp";
};
- dpcon@13 {
- num_priorities = <0x2>;
+ dpmcp@43 {
+ compatible = "fsl,dpmcp";
};
- dpcon@14 {
- num_priorities = <0x2>;
+ dpmcp@44 {
+ compatible = "fsl,dpmcp";
};
- dpcon@15 {
- num_priorities = <0x2>;
- };
- dpcon@16 {
- num_priorities = <0x2>;
+ dpmcp@45 {
+ compatible = "fsl,dpmcp";
};
- dpcon@17 {
- num_priorities = <0x2>;
+ dpmcp@46 {
+ compatible = "fsl,dpmcp";
};
- dpcon@18 {
- num_priorities = <0x2>;
+ dpmcp@47 {
+ compatible = "fsl,dpmcp";
};
- dpcon@19 {
- num_priorities = <0x2>;
+ dpmcp@48 {
+ compatible = "fsl,dpmcp";
};
- dpcon@20 {
- num_priorities = <0x2>;
+ dpmcp@49 {
+ compatible = "fsl,dpmcp";
};
- dpcon@21 {
- num_priorities = <0x2>;
+ dpmcp@50 {
+ compatible = "fsl,dpmcp";
};
- dpcon@22 {
- num_priorities = <0x2>;
+ dpmcp@51 {
+ compatible = "fsl,dpmcp";
};
- dpcon@23 {
- num_priorities = <0x2>;
- };
-
- dpcon@24 {
- num_priorities = <0x2>;
+ dpmcp@52 {
+ compatible = "fsl,dpmcp";
};
- dpcon@25 {
- num_priorities = <0x2>;
+ dpmcp@53 {
+ compatible = "fsl,dpmcp";
};
- dpcon@26 {
- num_priorities = <0x2>;
+ dpmcp@54 {
+ compatible = "fsl,dpmcp";
};
- dpcon@27 {
- num_priorities = <0x2>;
- };
-
- dpcon@28 {
- num_priorities = <0x2>;
- };
-
- dpcon@29 {
- num_priorities = <0x2>;
- };
-
- dpcon@30 {
- num_priorities = <0x2>;
- };
-
- dpcon@31 {
- num_priorities = <0x2>;
- };
-
- /* ------------ DPSECI --------------*/
- dpseci@0 {
- priorities = <0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01>;
- options = "DPSECI_OPT_HAS_CG";
- };
-
- /* ------------ DPRTC --------------*/
- dprtc@0 {
- compatible="fsl,dprtc";
+ dpni@0 {
+ compatible = "fsl,dpni";
+ type = "DPNI_TYPE_NIC";
+ num_queues = <16>;
+ num_tcs = <1>;
+ num_cgs = <1>;
+ mac_filter_entries = <16>;
+ vlan_filter_entries = <0>;
+ fs_entries = <64>;
+ qos_entries = <0>;
+ dist_key_size = <56>;
};
};
@@ -509,26 +651,10 @@
* Connections
*****************************************************************/
connections {
- connection@1 {
+
+ connection@1{
endpoint1 = "dpni@0";
endpoint2 = "dpmac@17";
};
-/* connection@2 {
- endpoint1 = "dpni@1";
- endpoint2 = "dpmac@3";
- };
- connection@3 {
- endpoint1 = "dpni@2";
- endpoint2 = "dpmac@4";
- };
- connection@4 {
- endpoint1 = "dpni@3";
- endpoint2 = "dpmac@5";
- };
- connection@5 {
- endpoint1 = "dpni@4";
- endpoint2 = "dpmac@6";
- };*/
};
};
-
--
2.35.3
patches/rcw-LSDK-21.08/0026-lx2160acex7-add-comments-for-SD1-protocol-20.patch 0 → 100644
View file @ e89f4ca6
From effea436bc371d6852e8988f48ccbd69df61530f Mon Sep 17 00:00:00 2001
From: Josua Mayer <josua@solid-run.com>
Date: Mon, 3 Apr 2023 11:54:29 +0300
Subject: [PATCH] lx2160acex7: add comments for SD1 protocol 20
---
lx2160acex7/configs/lx2160a_SD1_20.rcwi | 17 +++++++++++++++--
1 file changed, 15 insertions(+), 2 deletions(-)
diff --git a/lx2160acex7/configs/lx2160a_SD1_20.rcwi b/lx2160acex7/configs/lx2160a_SD1_20.rcwi
index 053aee7..28df171 100644
--- a/lx2160acex7/configs/lx2160a_SD1_20.rcwi
+++ b/lx2160acex7/configs/lx2160a_SD1_20.rcwi
@@ -1,5 +1,18 @@
+/* Serdes 1 Protocol 20: 2x40Gbps */
SRDS_PRTCL_S1=20
-SRDS_INTRA_REF_CLK_S1 = 1 /* PLLF used for PLLS */
-SRDS_PLL_REF_CLK_SEL_S1=2
+/* Disable Serdes 1 PLLF */
SRDS_PLL_PD_PLL1=1
+
+/* Use Serdes 1 PLLF for PLLS */
+SRDS_INTRA_REF_CLK_S1=1
+
+/* Enable Serdes 1 PLLS */
+SRDS_PLL_PD_PLL2=0
+
+/*
+ * Select Serdes 1 PLLF frequency 100MHz (don't care): Bit 0 = 0
+ * Select Serdes 1 PLLS frequency 161.1328125MHz (not documented in RM): Bit 1 = 1
+ * (See QorIQ LX2162A Reference Manual, Rev. 1, 12/2021, 4.9.8.9 Reset Control Word (RCW) Register Descriptions, Bits 932-933)
+ */
+SRDS_PLL_REF_CLK_SEL_S1=2
--
2.35.3
patches/u-boot-LSDK-21.08/0042-lx2160acex7-configure-retimer-for-serdes1-protocol-2.patch 0 → 100644
View file @ e89f4ca6
From 7666610c11ea33aba76070d2cfa142276d23066d Mon Sep 17 00:00:00 2001
From: Josua Mayer <josua@solid-run.com>
Date: Mon, 3 Apr 2023 13:19:07 +0300
Subject: [PATCH] lx2160acex7: configure retimer for serdes1 protocol 20
(40Gbps)
Signed-off-by: Josua Mayer <josua@solid-run.com>
---
board/solidrun/lx2160a/eth_lx2160acex7.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/board/solidrun/lx2160a/eth_lx2160acex7.c b/board/solidrun/lx2160a/eth_lx2160acex7.c
index 6a696deafe..d7a1d76619 100644
--- a/board/solidrun/lx2160a/eth_lx2160acex7.c
+++ b/board/solidrun/lx2160a/eth_lx2160acex7.c
@@ -330,6 +330,7 @@ int fsl_board_late_init(void) {
if (get_svr() & 0x800) { /* LX2162A SOM variants */
switch (srds_s1) {
case 8:
+ /* Setup 10g retimer on lanes e,f,g,h */
setup_retimer_lx2162_25g(0);
break;
case 15:
@@ -353,6 +354,8 @@ int fsl_board_late_init(void) {
} else {
switch (srds_s1) {
case 8:
+ case 20:
+ /* Setup 10g retimer on lanes e,f,g,h */
setup_retimer_25g(0);
break;
case 13:
--
2.35.3
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