clearfog-cx/honeycomb: add support for serdes 1 protocol 20 (2x 40G)

patches/linux-LSDK-21.08/0050-arm64-dts-lx2160a-clearfog-itx-add-dpmac1-2-for-40G-.patch

+From dd33a19abb61f56ce74a16e4cad842949e45276c Mon Sep 17 00:00:00 2001
+From: Josua Mayer <josua@solid-run.com>
+Date: Mon, 3 Apr 2023 13:25:50 +0300
+Subject: [PATCH] arm64: dts: lx2160a-clearfog-itx: add dpmac1&2 for 40G/100G
+ NICs
+
+network interfaces bundling multiple serdes lanes for either 40G or 100G
+use dpmac numbers 1 & 2. Enable the corresponding pcs nodes, but do not
+configure any sfp or serdes runtime configuration.
+
+Signed-off-by: Josua Mayer <josua@solid-run.com>
+---
+ .../dts/freescale/fsl-lx2160a-clearfog-itx.dtsi | 17 +++++++++++++++++
+ 1 file changed, 17 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-itx.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-itx.dtsi
+index 86036bd39b6a..3aa8a1fe50d0 100644
+--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-itx.dtsi
++++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-itx.dtsi
+@@ -67,7 +67,16 @@ sfp3: sfp-3 {
+ 	};
+ };
+ 
++&dpmac1 {
++	managed = "in-band-status";
++};
++
++&dpmac2 {
++	managed = "in-band-status";
++};
++
+ &dpmac3 {
++	sfp = <&qsfp0>;
+ 	managed = "in-band-status";
+ 	phys = <&serdes_1 7>;
+ };
+@@ -135,6 +144,14 @@ carrier_flash: w25q32@1 {
+         };
+ };
+ 
++&pcs_mdio1 {
++	status = "okay";
++};
++
++&pcs_mdio2 {
++	status = "okay";
++};
++
+ &pcs_mdio3 {
+ 	status = "okay";
+ };
+-- 
+2.35.3
+

patches/rcw-LSDK-21.08/0026-lx2160acex7-add-comments-for-SD1-protocol-20.patch

+From effea436bc371d6852e8988f48ccbd69df61530f Mon Sep 17 00:00:00 2001
+From: Josua Mayer <josua@solid-run.com>
+Date: Mon, 3 Apr 2023 11:54:29 +0300
+Subject: [PATCH] lx2160acex7: add comments for SD1 protocol 20
+
+---
+ lx2160acex7/configs/lx2160a_SD1_20.rcwi | 17 +++++++++++++++--
+ 1 file changed, 15 insertions(+), 2 deletions(-)
+
+diff --git a/lx2160acex7/configs/lx2160a_SD1_20.rcwi b/lx2160acex7/configs/lx2160a_SD1_20.rcwi
+index 053aee7..28df171 100644
+--- a/lx2160acex7/configs/lx2160a_SD1_20.rcwi
++++ b/lx2160acex7/configs/lx2160a_SD1_20.rcwi
+@@ -1,5 +1,18 @@
++/* Serdes 1 Protocol 20: 2x40Gbps */
+ SRDS_PRTCL_S1=20
+ 
+-SRDS_INTRA_REF_CLK_S1 = 1 /* PLLF used for PLLS */
+-SRDS_PLL_REF_CLK_SEL_S1=2
++/* Disable Serdes 1 PLLF */
+ SRDS_PLL_PD_PLL1=1
++
++/* Use Serdes 1 PLLF for PLLS */
++SRDS_INTRA_REF_CLK_S1=1
++
++/* Enable Serdes 1 PLLS */
++SRDS_PLL_PD_PLL2=0
++
++/*
++ * Select Serdes 1 PLLF frequency 100MHz (don't care): Bit 0 = 0
++ * Select Serdes 1 PLLS frequency 161.1328125MHz (not documented in RM): Bit 1 = 1
++ * (See QorIQ LX2162A Reference Manual, Rev. 1, 12/2021, 4.9.8.9 Reset Control Word (RCW) Register Descriptions, Bits 932-933)
++ */
++SRDS_PLL_REF_CLK_SEL_S1=2
+-- 
+2.35.3
+

patches/u-boot-LSDK-21.08/0042-lx2160acex7-configure-retimer-for-serdes1-protocol-2.patch

+From 7666610c11ea33aba76070d2cfa142276d23066d Mon Sep 17 00:00:00 2001
+From: Josua Mayer <josua@solid-run.com>
+Date: Mon, 3 Apr 2023 13:19:07 +0300
+Subject: [PATCH] lx2160acex7: configure retimer for serdes1 protocol 20
+ (40Gbps)
+
+Signed-off-by: Josua Mayer <josua@solid-run.com>
+---
+ board/solidrun/lx2160a/eth_lx2160acex7.c | 3 +++
+ 1 file changed, 3 insertions(+)
+
+diff --git a/board/solidrun/lx2160a/eth_lx2160acex7.c b/board/solidrun/lx2160a/eth_lx2160acex7.c
+index 6a696deafe..d7a1d76619 100644
+--- a/board/solidrun/lx2160a/eth_lx2160acex7.c
++++ b/board/solidrun/lx2160a/eth_lx2160acex7.c
+@@ -330,6 +330,7 @@ int fsl_board_late_init(void) {
+ 	if (get_svr() & 0x800) { /* LX2162A SOM variants */
+ 		switch (srds_s1) {
+ 			case 8:
++				/* Setup 10g retimer on lanes e,f,g,h */
+ 				setup_retimer_lx2162_25g(0);
+ 				break;
+ 			case 15:
+@@ -353,6 +354,8 @@ int fsl_board_late_init(void) {
+ 	} else {
+ 		switch (srds_s1) {
+ 			case 8:
++			case 20:
++				/* Setup 10g retimer on lanes e,f,g,h */
+ 				setup_retimer_25g(0);
+ 				break;
+ 			case 13:
+-- 
+2.35.3
+