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Commit 01470645 authored by Jun Lei's avatar Jun Lei Committed by Alex Deucher
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drm/amd/display: Extend soc BB capabilitiy 

[why]
Some parts are consuming dangerously close to maximum number of states
supported when updating the BB (i.e. 8).

[how]
Change maximum stages from 9 to 20.
Acked-by: default avatarRodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: default avatarJun Lei <jun.lei@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 6366b003
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Showing with 784 additions and 227 deletions
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
View file @ 01470645
...@@ -3410,6 +3410,277 @@ void dcn32_calculate_dlg_params(struct dc *dc, struct dc_state *context, display ...@@ -3410,6 +3410,277 @@ void dcn32_calculate_dlg_params(struct dc *dc, struct dc_state *context, display
} }
} }
static void get_optimal_ntuple(struct _vcs_dpi_voltage_scaling_st *entry)
{
if (entry->dcfclk_mhz > 0) {
float bw_on_sdp = entry->dcfclk_mhz * dcn3_2_soc.return_bus_width_bytes * ((float)dcn3_2_soc.pct_ideal_sdp_bw_after_urgent / 100);
entry->fabricclk_mhz = bw_on_sdp / (dcn3_2_soc.return_bus_width_bytes * ((float)dcn3_2_soc.pct_ideal_fabric_bw_after_urgent / 100));
entry->dram_speed_mts = bw_on_sdp / (dcn3_2_soc.num_chans *
dcn3_2_soc.dram_channel_width_bytes * ((float)dcn3_2_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_only / 100));
} else if (entry->fabricclk_mhz > 0) {
float bw_on_fabric = entry->fabricclk_mhz * dcn3_2_soc.return_bus_width_bytes * ((float)dcn3_2_soc.pct_ideal_fabric_bw_after_urgent / 100);
entry->dcfclk_mhz = bw_on_fabric / (dcn3_2_soc.return_bus_width_bytes * ((float)dcn3_2_soc.pct_ideal_sdp_bw_after_urgent / 100));
entry->dram_speed_mts = bw_on_fabric / (dcn3_2_soc.num_chans *
dcn3_2_soc.dram_channel_width_bytes * ((float)dcn3_2_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_only / 100));
} else if (entry->dram_speed_mts > 0) {
float bw_on_dram = entry->dram_speed_mts * dcn3_2_soc.num_chans *
dcn3_2_soc.dram_channel_width_bytes * ((float)dcn3_2_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_only / 100);
entry->fabricclk_mhz = bw_on_dram / (dcn3_2_soc.return_bus_width_bytes * ((float)dcn3_2_soc.pct_ideal_fabric_bw_after_urgent / 100));
entry->dcfclk_mhz = bw_on_dram / (dcn3_2_soc.return_bus_width_bytes * ((float)dcn3_2_soc.pct_ideal_sdp_bw_after_urgent / 100));
}
}
static float calculate_net_bw_in_kbytes_sec(struct _vcs_dpi_voltage_scaling_st *entry)
{
float memory_bw_kbytes_sec = entry->dram_speed_mts * dcn3_2_soc.num_chans *
dcn3_2_soc.dram_channel_width_bytes * ((float)dcn3_2_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_only / 100);
float fabric_bw_kbytes_sec = entry->fabricclk_mhz * dcn3_2_soc.return_bus_width_bytes * ((float)dcn3_2_soc.pct_ideal_fabric_bw_after_urgent / 100);
float sdp_bw_kbytes_sec = entry->dcfclk_mhz * dcn3_2_soc.return_bus_width_bytes * ((float)dcn3_2_soc.pct_ideal_sdp_bw_after_urgent / 100);
float limiting_bw_kbytes_sec = memory_bw_kbytes_sec;
if (fabric_bw_kbytes_sec < limiting_bw_kbytes_sec)
limiting_bw_kbytes_sec = fabric_bw_kbytes_sec;
if (sdp_bw_kbytes_sec < limiting_bw_kbytes_sec)
limiting_bw_kbytes_sec = sdp_bw_kbytes_sec;
return limiting_bw_kbytes_sec;
}
static void insert_entry_into_table_sorted(struct _vcs_dpi_voltage_scaling_st *table, unsigned int *num_entries,
struct _vcs_dpi_voltage_scaling_st *entry)
{
int index = 0;
int i = 0;
float net_bw_of_new_state = 0;
if (*num_entries == 0) {
table[0] = *entry;
(*num_entries)++;
} else {
net_bw_of_new_state = calculate_net_bw_in_kbytes_sec(entry);
while (net_bw_of_new_state > calculate_net_bw_in_kbytes_sec(&table[index])) {
index++;
if (index >= *num_entries)
break;
}
for (i = *num_entries; i > index; i--) {
table[i] = table[i - 1];
}
table[index] = *entry;
(*num_entries)++;
}
}
static void remove_entry_from_table_at_index(struct _vcs_dpi_voltage_scaling_st *table, unsigned int *num_entries,
unsigned int index)
{
int i;
if (*num_entries == 0)
return;
for (i = index; i < *num_entries - 1; i++) {
table[i] = table[i + 1];
}
memset(&table[--(*num_entries)], 0, sizeof(struct _vcs_dpi_voltage_scaling_st));
}
static int build_synthetic_soc_states(struct clk_bw_params *bw_params,
struct _vcs_dpi_voltage_scaling_st *table, unsigned int *num_entries)
{
int i, j;
struct _vcs_dpi_voltage_scaling_st entry = {0};
unsigned int max_dcfclk_mhz = 0, max_dispclk_mhz = 0, max_dppclk_mhz = 0,
max_phyclk_mhz = 0, max_dtbclk_mhz = 0, max_fclk_mhz = 0, max_uclk_mhz = 0;
unsigned int min_dcfclk_mhz = 199, min_fclk_mhz = 299;
static const unsigned int num_dcfclk_stas = 5;
unsigned int dcfclk_sta_targets[DC__VOLTAGE_STATES] = {199, 615, 906, 1324, 1564};
unsigned int num_uclk_dpms = 0;
unsigned int num_fclk_dpms = 0;
unsigned int num_dcfclk_dpms = 0;
for (i = 0; i < MAX_NUM_DPM_LVL; i++) {
if (bw_params->clk_table.entries[i].dcfclk_mhz > max_dcfclk_mhz)
max_dcfclk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz;
if (bw_params->clk_table.entries[i].fclk_mhz > max_fclk_mhz)
max_fclk_mhz = bw_params->clk_table.entries[i].fclk_mhz;
if (bw_params->clk_table.entries[i].memclk_mhz > max_uclk_mhz)
max_uclk_mhz = bw_params->clk_table.entries[i].memclk_mhz;
if (bw_params->clk_table.entries[i].dispclk_mhz > max_dispclk_mhz)
max_dispclk_mhz = bw_params->clk_table.entries[i].dispclk_mhz;
if (bw_params->clk_table.entries[i].dppclk_mhz > max_dppclk_mhz)
max_dppclk_mhz = bw_params->clk_table.entries[i].dppclk_mhz;
if (bw_params->clk_table.entries[i].phyclk_mhz > max_phyclk_mhz)
max_phyclk_mhz = bw_params->clk_table.entries[i].phyclk_mhz;
if (bw_params->clk_table.entries[i].dtbclk_mhz > max_dtbclk_mhz)
max_dtbclk_mhz = bw_params->clk_table.entries[i].dtbclk_mhz;
if (bw_params->clk_table.entries[i].memclk_mhz > 0)
num_uclk_dpms++;
if (bw_params->clk_table.entries[i].fclk_mhz > 0)
num_fclk_dpms++;
if (bw_params->clk_table.entries[i].dcfclk_mhz > 0)
num_dcfclk_dpms++;
}
if (!max_dcfclk_mhz || !max_dispclk_mhz || !max_dtbclk_mhz)
return -1;
if (max_dppclk_mhz == 0)
max_dppclk_mhz = max_dispclk_mhz;
if (max_fclk_mhz == 0)
max_fclk_mhz = max_dcfclk_mhz * dcn3_2_soc.pct_ideal_sdp_bw_after_urgent / dcn3_2_soc.pct_ideal_fabric_bw_after_urgent;
if (max_phyclk_mhz == 0)
max_phyclk_mhz = dcn3_2_soc.clock_limits[0].phyclk_mhz;
*num_entries = 0;
entry.dispclk_mhz = max_dispclk_mhz;
entry.dscclk_mhz = max_dispclk_mhz / 3;
entry.dppclk_mhz = max_dppclk_mhz;
entry.dtbclk_mhz = max_dtbclk_mhz;
entry.phyclk_mhz = max_phyclk_mhz;
entry.phyclk_d18_mhz = dcn3_2_soc.clock_limits[0].phyclk_d18_mhz;
entry.phyclk_d32_mhz = dcn3_2_soc.clock_limits[0].phyclk_d32_mhz;
// Insert all the DCFCLK STAs
for (i = 0; i < num_dcfclk_stas; i++) {
entry.dcfclk_mhz = dcfclk_sta_targets[i];
entry.fabricclk_mhz = 0;
entry.dram_speed_mts = 0;
get_optimal_ntuple(&entry);
insert_entry_into_table_sorted(table, num_entries, &entry);
}
// Insert the max DCFCLK
entry.dcfclk_mhz = max_dcfclk_mhz;
entry.fabricclk_mhz = 0;
entry.dram_speed_mts = 0;
get_optimal_ntuple(&entry);
insert_entry_into_table_sorted(table, num_entries, &entry);
// Insert the UCLK DPMS
for (i = 0; i < num_uclk_dpms; i++) {
entry.dcfclk_mhz = 0;
entry.fabricclk_mhz = 0;
entry.dram_speed_mts = bw_params->clk_table.entries[i].memclk_mhz * 16;
get_optimal_ntuple(&entry);
insert_entry_into_table_sorted(table, num_entries, &entry);
}
// If FCLK is coarse grained, insert individual DPMs.
if (num_fclk_dpms > 2) {
for (i = 0; i < num_fclk_dpms; i++) {
entry.dcfclk_mhz = 0;
entry.fabricclk_mhz = bw_params->clk_table.entries[i].fclk_mhz;
entry.dram_speed_mts = 0;
get_optimal_ntuple(&entry);
insert_entry_into_table_sorted(table, num_entries, &entry);
}
}
// If FCLK fine grained, only insert max
else {
entry.dcfclk_mhz = 0;
entry.fabricclk_mhz = max_fclk_mhz;
entry.dram_speed_mts = 0;
get_optimal_ntuple(&entry);
insert_entry_into_table_sorted(table, num_entries, &entry);
}
// At this point, the table contains all "points of interest" based on
// DPMs from PMFW, and STAs. Table is sorted by BW, and all clock
// ratios (by derate, are exact).
// Remove states that require higher clocks than are supported
for (i = *num_entries - 1; i >= 0 ; i--) {
if (table[i].dcfclk_mhz > max_dcfclk_mhz ||
table[i].fabricclk_mhz > max_fclk_mhz ||
table[i].dram_speed_mts > max_uclk_mhz * 16)
remove_entry_from_table_at_index(table, num_entries, i);
}
// At this point, the table only contains supported points of interest
// it could be used as is, but some states may be redundant due to
// coarse grained nature of some clocks, so we want to round up to
// coarse grained DPMs and remove duplicates.
// Round up UCLKs
for (i = *num_entries - 1; i >= 0 ; i--) {
for (j = 0; j < num_uclk_dpms; j++) {
if (bw_params->clk_table.entries[j].memclk_mhz * 16 >= table[i].dram_speed_mts) {
table[i].dram_speed_mts = bw_params->clk_table.entries[j].memclk_mhz * 16;
break;
}
}
}
// If FCLK is coarse grained, round up to next DPMs
if (num_fclk_dpms > 2) {
for (i = *num_entries - 1; i >= 0 ; i--) {
for (j = 0; j < num_fclk_dpms; j++) {
if (bw_params->clk_table.entries[j].fclk_mhz >= table[i].fabricclk_mhz) {
table[i].fabricclk_mhz = bw_params->clk_table.entries[j].fclk_mhz;
break;
}
}
}
}
// Otherwise, round up to minimum.
else {
for (i = *num_entries - 1; i >= 0 ; i--) {
if (table[i].fabricclk_mhz < min_fclk_mhz) {
table[i].fabricclk_mhz = min_fclk_mhz;
break;
}
}
}
// Round DCFCLKs up to minimum
for (i = *num_entries - 1; i >= 0 ; i--) {
if (table[i].dcfclk_mhz < min_dcfclk_mhz) {
table[i].dcfclk_mhz = min_dcfclk_mhz;
break;
}
}
// Remove duplicate states, note duplicate states are always neighbouring since table is sorted.
i = 0;
while (i < *num_entries - 1) {
if (table[i].dcfclk_mhz == table[i + 1].dcfclk_mhz &&
table[i].fabricclk_mhz == table[i + 1].fabricclk_mhz &&
table[i].dram_speed_mts == table[i + 1].dram_speed_mts)
remove_entry_from_table_at_index(table, num_entries, i + 1);
else
i++;
}
// Fix up the state indicies
for (i = *num_entries - 1; i >= 0 ; i--) {
table[i].state = i;
}
return 0;
}
/* dcn32_update_bw_bounding_box /* dcn32_update_bw_bounding_box
* This would override some dcn3_2 ip_or_soc initial parameters hardcoded from spreadsheet * This would override some dcn3_2 ip_or_soc initial parameters hardcoded from spreadsheet
* with actual values as per dGPU SKU: * with actual values as per dGPU SKU:
...@@ -3491,139 +3762,150 @@ static void dcn32_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw ...@@ -3491,139 +3762,150 @@ static void dcn32_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw
/* Overrides Clock levelsfrom CLK Mgr table entries as reported by PM FW */ /* Overrides Clock levelsfrom CLK Mgr table entries as reported by PM FW */
if ((!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) && (bw_params->clk_table.entries[0].memclk_mhz)) { if ((!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) && (bw_params->clk_table.entries[0].memclk_mhz)) {
unsigned int i = 0, j = 0, num_states = 0; if (dc->debug.use_legacy_soc_bb_mechanism) {
unsigned int i = 0, j = 0, num_states = 0;
unsigned int dcfclk_mhz[DC__VOLTAGE_STATES] = {0};
unsigned int dram_speed_mts[DC__VOLTAGE_STATES] = {0}; unsigned int dcfclk_mhz[DC__VOLTAGE_STATES] = {0};
unsigned int optimal_uclk_for_dcfclk_sta_targets[DC__VOLTAGE_STATES] = {0}; unsigned int dram_speed_mts[DC__VOLTAGE_STATES] = {0};
unsigned int optimal_dcfclk_for_uclk[DC__VOLTAGE_STATES] = {0}; unsigned int optimal_uclk_for_dcfclk_sta_targets[DC__VOLTAGE_STATES] = {0};
unsigned int optimal_dcfclk_for_uclk[DC__VOLTAGE_STATES] = {0};
unsigned int dcfclk_sta_targets[DC__VOLTAGE_STATES] = {615, 906, 1324, 1564}; unsigned int min_dcfclk = UINT_MAX;
unsigned int num_dcfclk_sta_targets = 4, num_uclk_states = 0; /* Set 199 as first value in STA target array to have a minimum DCFCLK value.
unsigned int max_dcfclk_mhz = 0, max_dispclk_mhz = 0, max_dppclk_mhz = 0, max_phyclk_mhz = 0; * For DCN32 we set min to 199 so minimum FCLK DPM0 (300Mhz can be achieved) */
unsigned int dcfclk_sta_targets[DC__VOLTAGE_STATES] = {199, 615, 906, 1324, 1564};
for (i = 0; i < MAX_NUM_DPM_LVL; i++) { unsigned int num_dcfclk_sta_targets = 4, num_uclk_states = 0;
if (bw_params->clk_table.entries[i].dcfclk_mhz > max_dcfclk_mhz) unsigned int max_dcfclk_mhz = 0, max_dispclk_mhz = 0, max_dppclk_mhz = 0, max_phyclk_mhz = 0;
max_dcfclk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz;
if (bw_params->clk_table.entries[i].dispclk_mhz > max_dispclk_mhz) for (i = 0; i < MAX_NUM_DPM_LVL; i++) {
max_dispclk_mhz = bw_params->clk_table.entries[i].dispclk_mhz; if (bw_params->clk_table.entries[i].dcfclk_mhz > max_dcfclk_mhz)
if (bw_params->clk_table.entries[i].dppclk_mhz > max_dppclk_mhz) max_dcfclk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz;
max_dppclk_mhz = bw_params->clk_table.entries[i].dppclk_mhz; if (bw_params->clk_table.entries[i].dcfclk_mhz != 0 &&
if (bw_params->clk_table.entries[i].phyclk_mhz > max_phyclk_mhz) bw_params->clk_table.entries[i].dcfclk_mhz < min_dcfclk)
max_phyclk_mhz = bw_params->clk_table.entries[i].phyclk_mhz; min_dcfclk = bw_params->clk_table.entries[i].dcfclk_mhz;
} if (bw_params->clk_table.entries[i].dispclk_mhz > max_dispclk_mhz)
if (!max_dcfclk_mhz) max_dispclk_mhz = bw_params->clk_table.entries[i].dispclk_mhz;
max_dcfclk_mhz = dcn3_2_soc.clock_limits[0].dcfclk_mhz; if (bw_params->clk_table.entries[i].dppclk_mhz > max_dppclk_mhz)
if (!max_dispclk_mhz) max_dppclk_mhz = bw_params->clk_table.entries[i].dppclk_mhz;
max_dispclk_mhz = dcn3_2_soc.clock_limits[0].dispclk_mhz; if (bw_params->clk_table.entries[i].phyclk_mhz > max_phyclk_mhz)
if (!max_dppclk_mhz) max_phyclk_mhz = bw_params->clk_table.entries[i].phyclk_mhz;
max_dppclk_mhz = dcn3_2_soc.clock_limits[0].dppclk_mhz; }
if (!max_phyclk_mhz) if (min_dcfclk > dcfclk_sta_targets[0])
max_phyclk_mhz = dcn3_2_soc.clock_limits[0].phyclk_mhz; dcfclk_sta_targets[0] = min_dcfclk;
if (!max_dcfclk_mhz)
if (max_dcfclk_mhz > dcfclk_sta_targets[num_dcfclk_sta_targets-1]) { max_dcfclk_mhz = dcn3_2_soc.clock_limits[0].dcfclk_mhz;
// If max DCFCLK is greater than the max DCFCLK STA target, insert into the DCFCLK STA target array if (!max_dispclk_mhz)
dcfclk_sta_targets[num_dcfclk_sta_targets] = max_dcfclk_mhz; max_dispclk_mhz = dcn3_2_soc.clock_limits[0].dispclk_mhz;
num_dcfclk_sta_targets++; if (!max_dppclk_mhz)
} else if (max_dcfclk_mhz < dcfclk_sta_targets[num_dcfclk_sta_targets-1]) { max_dppclk_mhz = dcn3_2_soc.clock_limits[0].dppclk_mhz;
// If max DCFCLK is less than the max DCFCLK STA target, cap values and remove duplicates if (!max_phyclk_mhz)
for (i = 0; i < num_dcfclk_sta_targets; i++) { max_phyclk_mhz = dcn3_2_soc.clock_limits[0].phyclk_mhz;
if (dcfclk_sta_targets[i] > max_dcfclk_mhz) {
dcfclk_sta_targets[i] = max_dcfclk_mhz; if (max_dcfclk_mhz > dcfclk_sta_targets[num_dcfclk_sta_targets-1]) {
break; // If max DCFCLK is greater than the max DCFCLK STA target, insert into the DCFCLK STA target array
dcfclk_sta_targets[num_dcfclk_sta_targets] = max_dcfclk_mhz;
num_dcfclk_sta_targets++;
} else if (max_dcfclk_mhz < dcfclk_sta_targets[num_dcfclk_sta_targets-1]) {
// If max DCFCLK is less than the max DCFCLK STA target, cap values and remove duplicates
for (i = 0; i < num_dcfclk_sta_targets; i++) {
if (dcfclk_sta_targets[i] > max_dcfclk_mhz) {
dcfclk_sta_targets[i] = max_dcfclk_mhz;
break;
}
} }
// Update size of array since we "removed" duplicates
num_dcfclk_sta_targets = i + 1;
} }
// Update size of array since we "removed" duplicates
num_dcfclk_sta_targets = i + 1;
}
num_uclk_states = bw_params->clk_table.num_entries; num_uclk_states = bw_params->clk_table.num_entries;
// Calculate optimal dcfclk for each uclk // Calculate optimal dcfclk for each uclk
for (i = 0; i < num_uclk_states; i++) { for (i = 0; i < num_uclk_states; i++) {
dcn32_get_optimal_dcfclk_fclk_for_uclk(bw_params->clk_table.entries[i].memclk_mhz * 16, dcn32_get_optimal_dcfclk_fclk_for_uclk(bw_params->clk_table.entries[i].memclk_mhz * 16,
&optimal_dcfclk_for_uclk[i], NULL); &optimal_dcfclk_for_uclk[i], NULL);
if (optimal_dcfclk_for_uclk[i] < bw_params->clk_table.entries[0].dcfclk_mhz) { if (optimal_dcfclk_for_uclk[i] < bw_params->clk_table.entries[0].dcfclk_mhz) {
optimal_dcfclk_for_uclk[i] = bw_params->clk_table.entries[0].dcfclk_mhz; optimal_dcfclk_for_uclk[i] = bw_params->clk_table.entries[0].dcfclk_mhz;
}
} }
}
// Calculate optimal uclk for each dcfclk sta target // Calculate optimal uclk for each dcfclk sta target
for (i = 0; i < num_dcfclk_sta_targets; i++) { for (i = 0; i < num_dcfclk_sta_targets; i++) {
for (j = 0; j < num_uclk_states; j++) { for (j = 0; j < num_uclk_states; j++) {
if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j]) { if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j]) {
optimal_uclk_for_dcfclk_sta_targets[i] = optimal_uclk_for_dcfclk_sta_targets[i] =
bw_params->clk_table.entries[j].memclk_mhz * 16; bw_params->clk_table.entries[j].memclk_mhz * 16;
break; break;
}
} }
} }
}
i = 0; i = 0;
j = 0; j = 0;
// create the final dcfclk and uclk table // create the final dcfclk and uclk table
while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) { while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) {
if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j] && i < num_dcfclk_sta_targets) { if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j] && i < num_dcfclk_sta_targets) {
dcfclk_mhz[num_states] = dcfclk_sta_targets[i]; dcfclk_mhz[num_states] = dcfclk_sta_targets[i];
dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++]; dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++];
} else {
if (j < num_uclk_states && optimal_dcfclk_for_uclk[j] <= max_dcfclk_mhz) {
dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j];
dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16;
} else { } else {
j = num_uclk_states; if (j < num_uclk_states && optimal_dcfclk_for_uclk[j] <= max_dcfclk_mhz) {
dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j];
dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16;
} else {
j = num_uclk_states;
}
} }
} }
}
while (i < num_dcfclk_sta_targets && num_states < DC__VOLTAGE_STATES) { while (i < num_dcfclk_sta_targets && num_states < DC__VOLTAGE_STATES) {
dcfclk_mhz[num_states] = dcfclk_sta_targets[i]; dcfclk_mhz[num_states] = dcfclk_sta_targets[i];
dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++]; dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++];
} }
while (j < num_uclk_states && num_states < DC__VOLTAGE_STATES &&
optimal_dcfclk_for_uclk[j] <= max_dcfclk_mhz) {
dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j];
dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16;
}
dcn3_2_soc.num_states = num_states;
for (i = 0; i < dcn3_2_soc.num_states; i++) {
dcn3_2_soc.clock_limits[i].state = i;
dcn3_2_soc.clock_limits[i].dcfclk_mhz = dcfclk_mhz[i];
dcn3_2_soc.clock_limits[i].fabricclk_mhz = dcfclk_mhz[i];
/* Fill all states with max values of all these clocks */ while (j < num_uclk_states && num_states < DC__VOLTAGE_STATES &&
dcn3_2_soc.clock_limits[i].dispclk_mhz = max_dispclk_mhz; optimal_dcfclk_for_uclk[j] <= max_dcfclk_mhz) {
dcn3_2_soc.clock_limits[i].dppclk_mhz = max_dppclk_mhz; dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j];
dcn3_2_soc.clock_limits[i].phyclk_mhz = max_phyclk_mhz; dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16;
dcn3_2_soc.clock_limits[i].dscclk_mhz = max_dispclk_mhz / 3; }
/* Populate from bw_params for DTBCLK, SOCCLK */ dcn3_2_soc.num_states = num_states;
if (i > 0) { for (i = 0; i < dcn3_2_soc.num_states; i++) {
if (!bw_params->clk_table.entries[i].dtbclk_mhz) { dcn3_2_soc.clock_limits[i].state = i;
dcn3_2_soc.clock_limits[i].dtbclk_mhz = dcn3_2_soc.clock_limits[i-1].dtbclk_mhz; dcn3_2_soc.clock_limits[i].dcfclk_mhz = dcfclk_mhz[i];
} else { dcn3_2_soc.clock_limits[i].fabricclk_mhz = dcfclk_mhz[i];
/* Fill all states with max values of all these clocks */
dcn3_2_soc.clock_limits[i].dispclk_mhz = max_dispclk_mhz;
dcn3_2_soc.clock_limits[i].dppclk_mhz = max_dppclk_mhz;
dcn3_2_soc.clock_limits[i].phyclk_mhz = max_phyclk_mhz;
dcn3_2_soc.clock_limits[i].dscclk_mhz = max_dispclk_mhz / 3;
/* Populate from bw_params for DTBCLK, SOCCLK */
if (i > 0) {
if (!bw_params->clk_table.entries[i].dtbclk_mhz) {
dcn3_2_soc.clock_limits[i].dtbclk_mhz = dcn3_2_soc.clock_limits[i-1].dtbclk_mhz;
} else {
dcn3_2_soc.clock_limits[i].dtbclk_mhz = bw_params->clk_table.entries[i].dtbclk_mhz;
}
} else if (bw_params->clk_table.entries[i].dtbclk_mhz) {
dcn3_2_soc.clock_limits[i].dtbclk_mhz = bw_params->clk_table.entries[i].dtbclk_mhz; dcn3_2_soc.clock_limits[i].dtbclk_mhz = bw_params->clk_table.entries[i].dtbclk_mhz;
} }
} else if (bw_params->clk_table.entries[i].dtbclk_mhz) {
dcn3_2_soc.clock_limits[i].dtbclk_mhz = bw_params->clk_table.entries[i].dtbclk_mhz;
}
if (!bw_params->clk_table.entries[i].socclk_mhz && i > 0) if (!bw_params->clk_table.entries[i].socclk_mhz && i > 0)
dcn3_2_soc.clock_limits[i].socclk_mhz = dcn3_2_soc.clock_limits[i-1].socclk_mhz; dcn3_2_soc.clock_limits[i].socclk_mhz = dcn3_2_soc.clock_limits[i-1].socclk_mhz;
else else
dcn3_2_soc.clock_limits[i].socclk_mhz = bw_params->clk_table.entries[i].socclk_mhz; dcn3_2_soc.clock_limits[i].socclk_mhz = bw_params->clk_table.entries[i].socclk_mhz;
if (!dram_speed_mts[i] && i > 0) if (!dram_speed_mts[i] && i > 0)
dcn3_2_soc.clock_limits[i].dram_speed_mts = dcn3_2_soc.clock_limits[i-1].dram_speed_mts; dcn3_2_soc.clock_limits[i].dram_speed_mts = dcn3_2_soc.clock_limits[i-1].dram_speed_mts;
else else
dcn3_2_soc.clock_limits[i].dram_speed_mts = dram_speed_mts[i]; dcn3_2_soc.clock_limits[i].dram_speed_mts = dram_speed_mts[i];
/* These clocks cannot come from bw_params, always fill from dcn3_2_soc[0] */ /* These clocks cannot come from bw_params, always fill from dcn3_2_soc[0] */
/* PHYCLK_D18, PHYCLK_D32 */ /* PHYCLK_D18, PHYCLK_D32 */
dcn3_2_soc.clock_limits[i].phyclk_d18_mhz = dcn3_2_soc.clock_limits[0].phyclk_d18_mhz; dcn3_2_soc.clock_limits[i].phyclk_d18_mhz = dcn3_2_soc.clock_limits[0].phyclk_d18_mhz;
dcn3_2_soc.clock_limits[i].phyclk_d32_mhz = dcn3_2_soc.clock_limits[0].phyclk_d32_mhz; dcn3_2_soc.clock_limits[i].phyclk_d32_mhz = dcn3_2_soc.clock_limits[0].phyclk_d32_mhz;
}
} else {
build_synthetic_soc_states(bw_params, dcn3_2_soc.clock_limits, &dcn3_2_soc.num_states);
} }
/* Re-init DML with updated bb */ /* Re-init DML with updated bb */
......
drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c
View file @ 01470645
...@@ -1717,6 +1717,277 @@ static void dcn321_get_optimal_dcfclk_fclk_for_uclk(unsigned int uclk_mts, ...@@ -1717,6 +1717,277 @@ static void dcn321_get_optimal_dcfclk_fclk_for_uclk(unsigned int uclk_mts,
(dcn3_21_soc.return_bus_width_bytes * (dcn3_21_soc.max_avg_sdp_bw_use_normal_percent / 100)); (dcn3_21_soc.return_bus_width_bytes * (dcn3_21_soc.max_avg_sdp_bw_use_normal_percent / 100));
} }
static void get_optimal_ntuple(struct _vcs_dpi_voltage_scaling_st *entry)
{
if (entry->dcfclk_mhz > 0) {
float bw_on_sdp = entry->dcfclk_mhz * dcn3_21_soc.return_bus_width_bytes * ((float)dcn3_21_soc.pct_ideal_sdp_bw_after_urgent / 100);
entry->fabricclk_mhz = bw_on_sdp / (dcn3_21_soc.return_bus_width_bytes * ((float)dcn3_21_soc.pct_ideal_fabric_bw_after_urgent / 100));
entry->dram_speed_mts = bw_on_sdp / (dcn3_21_soc.num_chans *
dcn3_21_soc.dram_channel_width_bytes * ((float)dcn3_21_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_only / 100));
} else if (entry->fabricclk_mhz > 0) {
float bw_on_fabric = entry->fabricclk_mhz * dcn3_21_soc.return_bus_width_bytes * ((float)dcn3_21_soc.pct_ideal_fabric_bw_after_urgent / 100);
entry->dcfclk_mhz = bw_on_fabric / (dcn3_21_soc.return_bus_width_bytes * ((float)dcn3_21_soc.pct_ideal_sdp_bw_after_urgent / 100));
entry->dram_speed_mts = bw_on_fabric / (dcn3_21_soc.num_chans *
dcn3_21_soc.dram_channel_width_bytes * ((float)dcn3_21_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_only / 100));
} else if (entry->dram_speed_mts > 0) {
float bw_on_dram = entry->dram_speed_mts * dcn3_21_soc.num_chans *
dcn3_21_soc.dram_channel_width_bytes * ((float)dcn3_21_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_only / 100);
entry->fabricclk_mhz = bw_on_dram / (dcn3_21_soc.return_bus_width_bytes * ((float)dcn3_21_soc.pct_ideal_fabric_bw_after_urgent / 100));
entry->dcfclk_mhz = bw_on_dram / (dcn3_21_soc.return_bus_width_bytes * ((float)dcn3_21_soc.pct_ideal_sdp_bw_after_urgent / 100));
}
}
static float calculate_net_bw_in_kbytes_sec(struct _vcs_dpi_voltage_scaling_st *entry)
{
float memory_bw_kbytes_sec = entry->dram_speed_mts * dcn3_21_soc.num_chans *
dcn3_21_soc.dram_channel_width_bytes * ((float)dcn3_21_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_only / 100);
float fabric_bw_kbytes_sec = entry->fabricclk_mhz * dcn3_21_soc.return_bus_width_bytes * ((float)dcn3_21_soc.pct_ideal_fabric_bw_after_urgent / 100);
float sdp_bw_kbytes_sec = entry->dcfclk_mhz * dcn3_21_soc.return_bus_width_bytes * ((float)dcn3_21_soc.pct_ideal_sdp_bw_after_urgent / 100);
float limiting_bw_kbytes_sec = memory_bw_kbytes_sec;
if (fabric_bw_kbytes_sec < limiting_bw_kbytes_sec)
limiting_bw_kbytes_sec = fabric_bw_kbytes_sec;
if (sdp_bw_kbytes_sec < limiting_bw_kbytes_sec)
limiting_bw_kbytes_sec = sdp_bw_kbytes_sec;
return limiting_bw_kbytes_sec;
}
static void insert_entry_into_table_sorted(struct _vcs_dpi_voltage_scaling_st *table, unsigned int *num_entries,
struct _vcs_dpi_voltage_scaling_st *entry)
{
int index = 0;
int i = 0;
float net_bw_of_new_state = 0;
if (*num_entries == 0) {
table[0] = *entry;
(*num_entries)++;
} else {
net_bw_of_new_state = calculate_net_bw_in_kbytes_sec(entry);
while (net_bw_of_new_state > calculate_net_bw_in_kbytes_sec(&table[index])) {
index++;
if (index >= *num_entries)
break;
}
for (i = *num_entries; i > index; i--) {
table[i] = table[i - 1];
}
table[index] = *entry;
(*num_entries)++;
}
}
static void remove_entry_from_table_at_index(struct _vcs_dpi_voltage_scaling_st *table, unsigned int *num_entries,
unsigned int index)
{
int i;
if (*num_entries == 0)
return;
for (i = index; i < *num_entries - 1; i++) {
table[i] = table[i + 1];
}
memset(&table[--(*num_entries)], 0, sizeof(struct _vcs_dpi_voltage_scaling_st));
}
static int build_synthetic_soc_states(struct clk_bw_params *bw_params,
struct _vcs_dpi_voltage_scaling_st *table, unsigned int *num_entries)
{
int i, j;
struct _vcs_dpi_voltage_scaling_st entry = {0};
unsigned int max_dcfclk_mhz = 0, max_dispclk_mhz = 0, max_dppclk_mhz = 0,
max_phyclk_mhz = 0, max_dtbclk_mhz = 0, max_fclk_mhz = 0, max_uclk_mhz = 0;
unsigned int min_dcfclk_mhz = 199, min_fclk_mhz = 299;
static const unsigned int num_dcfclk_stas = 5;
unsigned int dcfclk_sta_targets[DC__VOLTAGE_STATES] = {199, 615, 906, 1324, 1564};
unsigned int num_uclk_dpms = 0;
unsigned int num_fclk_dpms = 0;
unsigned int num_dcfclk_dpms = 0;
for (i = 0; i < MAX_NUM_DPM_LVL; i++) {
if (bw_params->clk_table.entries[i].dcfclk_mhz > max_dcfclk_mhz)
max_dcfclk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz;
if (bw_params->clk_table.entries[i].fclk_mhz > max_fclk_mhz)
max_fclk_mhz = bw_params->clk_table.entries[i].fclk_mhz;
if (bw_params->clk_table.entries[i].memclk_mhz > max_uclk_mhz)
max_uclk_mhz = bw_params->clk_table.entries[i].memclk_mhz;
if (bw_params->clk_table.entries[i].dispclk_mhz > max_dispclk_mhz)
max_dispclk_mhz = bw_params->clk_table.entries[i].dispclk_mhz;
if (bw_params->clk_table.entries[i].dppclk_mhz > max_dppclk_mhz)
max_dppclk_mhz = bw_params->clk_table.entries[i].dppclk_mhz;
if (bw_params->clk_table.entries[i].phyclk_mhz > max_phyclk_mhz)
max_phyclk_mhz = bw_params->clk_table.entries[i].phyclk_mhz;
if (bw_params->clk_table.entries[i].dtbclk_mhz > max_dtbclk_mhz)
max_dtbclk_mhz = bw_params->clk_table.entries[i].dtbclk_mhz;
if (bw_params->clk_table.entries[i].memclk_mhz > 0)
num_uclk_dpms++;
if (bw_params->clk_table.entries[i].fclk_mhz > 0)
num_fclk_dpms++;
if (bw_params->clk_table.entries[i].dcfclk_mhz > 0)
num_dcfclk_dpms++;
}
if (!max_dcfclk_mhz || !max_dispclk_mhz || !max_dtbclk_mhz)
return -1;
if (max_dppclk_mhz == 0)
max_dppclk_mhz = max_dispclk_mhz;
if (max_fclk_mhz == 0)
max_fclk_mhz = max_dcfclk_mhz * dcn3_21_soc.pct_ideal_sdp_bw_after_urgent / dcn3_21_soc.pct_ideal_fabric_bw_after_urgent;
if (max_phyclk_mhz == 0)
max_phyclk_mhz = dcn3_21_soc.clock_limits[0].phyclk_mhz;
*num_entries = 0;
entry.dispclk_mhz = max_dispclk_mhz;
entry.dscclk_mhz = max_dispclk_mhz / 3;
entry.dppclk_mhz = max_dppclk_mhz;
entry.dtbclk_mhz = max_dtbclk_mhz;
entry.phyclk_mhz = max_phyclk_mhz;
entry.phyclk_d18_mhz = dcn3_21_soc.clock_limits[0].phyclk_d18_mhz;
entry.phyclk_d32_mhz = dcn3_21_soc.clock_limits[0].phyclk_d32_mhz;
// Insert all the DCFCLK STAs
for (i = 0; i < num_dcfclk_stas; i++) {
entry.dcfclk_mhz = dcfclk_sta_targets[i];
entry.fabricclk_mhz = 0;
entry.dram_speed_mts = 0;
get_optimal_ntuple(&entry);
insert_entry_into_table_sorted(table, num_entries, &entry);
}
// Insert the max DCFCLK
entry.dcfclk_mhz = max_dcfclk_mhz;
entry.fabricclk_mhz = 0;
entry.dram_speed_mts = 0;
get_optimal_ntuple(&entry);
insert_entry_into_table_sorted(table, num_entries, &entry);
// Insert the UCLK DPMS
for (i = 0; i < num_uclk_dpms; i++) {
entry.dcfclk_mhz = 0;
entry.fabricclk_mhz = 0;
entry.dram_speed_mts = bw_params->clk_table.entries[i].memclk_mhz * 16;
get_optimal_ntuple(&entry);
insert_entry_into_table_sorted(table, num_entries, &entry);
}
// If FCLK is coarse grained, insert individual DPMs.
if (num_fclk_dpms > 2) {
for (i = 0; i < num_fclk_dpms; i++) {
entry.dcfclk_mhz = 0;
entry.fabricclk_mhz = bw_params->clk_table.entries[i].fclk_mhz;
entry.dram_speed_mts = 0;
get_optimal_ntuple(&entry);
insert_entry_into_table_sorted(table, num_entries, &entry);
}
}
// If FCLK fine grained, only insert max
else {
entry.dcfclk_mhz = 0;
entry.fabricclk_mhz = max_fclk_mhz;
entry.dram_speed_mts = 0;
get_optimal_ntuple(&entry);
insert_entry_into_table_sorted(table, num_entries, &entry);
}
// At this point, the table contains all "points of interest" based on
// DPMs from PMFW, and STAs. Table is sorted by BW, and all clock
// ratios (by derate, are exact).
// Remove states that require higher clocks than are supported
for (i = *num_entries - 1; i >= 0 ; i--) {
if (table[i].dcfclk_mhz > max_dcfclk_mhz ||
table[i].fabricclk_mhz > max_fclk_mhz ||
table[i].dram_speed_mts > max_uclk_mhz * 16)
remove_entry_from_table_at_index(table, num_entries, i);
}
// At this point, the table only contains supported points of interest
// it could be used as is, but some states may be redundant due to
// coarse grained nature of some clocks, so we want to round up to
// coarse grained DPMs and remove duplicates.
// Round up UCLKs
for (i = *num_entries - 1; i >= 0 ; i--) {
for (j = 0; j < num_uclk_dpms; j++) {
if (bw_params->clk_table.entries[j].memclk_mhz * 16 >= table[i].dram_speed_mts) {
table[i].dram_speed_mts = bw_params->clk_table.entries[j].memclk_mhz * 16;
break;
}
}
}
// If FCLK is coarse grained, round up to next DPMs
if (num_fclk_dpms > 2) {
for (i = *num_entries - 1; i >= 0 ; i--) {
for (j = 0; j < num_fclk_dpms; j++) {
if (bw_params->clk_table.entries[j].fclk_mhz >= table[i].fabricclk_mhz) {
table[i].fabricclk_mhz = bw_params->clk_table.entries[j].fclk_mhz;
break;
}
}
}
}
// Otherwise, round up to minimum.
else {
for (i = *num_entries - 1; i >= 0 ; i--) {
if (table[i].fabricclk_mhz < min_fclk_mhz) {
table[i].fabricclk_mhz = min_fclk_mhz;
break;
}
}
}
// Round DCFCLKs up to minimum
for (i = *num_entries - 1; i >= 0 ; i--) {
if (table[i].dcfclk_mhz < min_dcfclk_mhz) {
table[i].dcfclk_mhz = min_dcfclk_mhz;
break;
}
}
// Remove duplicate states, note duplicate states are always neighbouring since table is sorted.
i = 0;
while (i < *num_entries - 1) {
if (table[i].dcfclk_mhz == table[i + 1].dcfclk_mhz &&
table[i].fabricclk_mhz == table[i + 1].fabricclk_mhz &&
table[i].dram_speed_mts == table[i + 1].dram_speed_mts)
remove_entry_from_table_at_index(table, num_entries, i + 1);
else
i++;
}
// Fix up the state indicies
for (i = *num_entries - 1; i >= 0 ; i--) {
table[i].state = i;
}
return 0;
}
/* dcn321_update_bw_bounding_box /* dcn321_update_bw_bounding_box
* This would override some dcn3_2 ip_or_soc initial parameters hardcoded from spreadsheet * This would override some dcn3_2 ip_or_soc initial parameters hardcoded from spreadsheet
* with actual values as per dGPU SKU: * with actual values as per dGPU SKU:
...@@ -1797,139 +2068,143 @@ static void dcn321_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *b ...@@ -1797,139 +2068,143 @@ static void dcn321_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *b
/* Overrides Clock levelsfrom CLK Mgr table entries as reported by PM FW */ /* Overrides Clock levelsfrom CLK Mgr table entries as reported by PM FW */
if ((!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) && (bw_params->clk_table.entries[0].memclk_mhz)) { if ((!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) && (bw_params->clk_table.entries[0].memclk_mhz)) {
unsigned int i = 0, j = 0, num_states = 0; if (dc->debug.use_legacy_soc_bb_mechanism) {
unsigned int i = 0, j = 0, num_states = 0;
unsigned int dcfclk_mhz[DC__VOLTAGE_STATES] = {0};
unsigned int dram_speed_mts[DC__VOLTAGE_STATES] = {0}; unsigned int dcfclk_mhz[DC__VOLTAGE_STATES] = {0};
unsigned int optimal_uclk_for_dcfclk_sta_targets[DC__VOLTAGE_STATES] = {0}; unsigned int dram_speed_mts[DC__VOLTAGE_STATES] = {0};
unsigned int optimal_dcfclk_for_uclk[DC__VOLTAGE_STATES] = {0}; unsigned int optimal_uclk_for_dcfclk_sta_targets[DC__VOLTAGE_STATES] = {0};
unsigned int optimal_dcfclk_for_uclk[DC__VOLTAGE_STATES] = {0};
unsigned int dcfclk_sta_targets[DC__VOLTAGE_STATES] = {615, 906, 1324, 1564};
unsigned int num_dcfclk_sta_targets = 4, num_uclk_states = 0; unsigned int dcfclk_sta_targets[DC__VOLTAGE_STATES] = {615, 906, 1324, 1564};
unsigned int max_dcfclk_mhz = 0, max_dispclk_mhz = 0, max_dppclk_mhz = 0, max_phyclk_mhz = 0; unsigned int num_dcfclk_sta_targets = 4, num_uclk_states = 0;
unsigned int max_dcfclk_mhz = 0, max_dispclk_mhz = 0, max_dppclk_mhz = 0, max_phyclk_mhz = 0;
for (i = 0; i < MAX_NUM_DPM_LVL; i++) {
if (bw_params->clk_table.entries[i].dcfclk_mhz > max_dcfclk_mhz) for (i = 0; i < MAX_NUM_DPM_LVL; i++) {
max_dcfclk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz; if (bw_params->clk_table.entries[i].dcfclk_mhz > max_dcfclk_mhz)
if (bw_params->clk_table.entries[i].dispclk_mhz > max_dispclk_mhz) max_dcfclk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz;
max_dispclk_mhz = bw_params->clk_table.entries[i].dispclk_mhz; if (bw_params->clk_table.entries[i].dispclk_mhz > max_dispclk_mhz)
if (bw_params->clk_table.entries[i].dppclk_mhz > max_dppclk_mhz) max_dispclk_mhz = bw_params->clk_table.entries[i].dispclk_mhz;
max_dppclk_mhz = bw_params->clk_table.entries[i].dppclk_mhz; if (bw_params->clk_table.entries[i].dppclk_mhz > max_dppclk_mhz)
if (bw_params->clk_table.entries[i].phyclk_mhz > max_phyclk_mhz) max_dppclk_mhz = bw_params->clk_table.entries[i].dppclk_mhz;
max_phyclk_mhz = bw_params->clk_table.entries[i].phyclk_mhz; if (bw_params->clk_table.entries[i].phyclk_mhz > max_phyclk_mhz)
} max_phyclk_mhz = bw_params->clk_table.entries[i].phyclk_mhz;
if (!max_dcfclk_mhz) }
max_dcfclk_mhz = dcn3_21_soc.clock_limits[0].dcfclk_mhz; if (!max_dcfclk_mhz)
if (!max_dispclk_mhz) max_dcfclk_mhz = dcn3_21_soc.clock_limits[0].dcfclk_mhz;
max_dispclk_mhz = dcn3_21_soc.clock_limits[0].dispclk_mhz; if (!max_dispclk_mhz)
if (!max_dppclk_mhz) max_dispclk_mhz = dcn3_21_soc.clock_limits[0].dispclk_mhz;
max_dppclk_mhz = dcn3_21_soc.clock_limits[0].dppclk_mhz; if (!max_dppclk_mhz)
if (!max_phyclk_mhz) max_dppclk_mhz = dcn3_21_soc.clock_limits[0].dppclk_mhz;
max_phyclk_mhz = dcn3_21_soc.clock_limits[0].phyclk_mhz; if (!max_phyclk_mhz)
max_phyclk_mhz = dcn3_21_soc.clock_limits[0].phyclk_mhz;
if (max_dcfclk_mhz > dcfclk_sta_targets[num_dcfclk_sta_targets-1]) {
// If max DCFCLK is greater than the max DCFCLK STA target, insert into the DCFCLK STA target array if (max_dcfclk_mhz > dcfclk_sta_targets[num_dcfclk_sta_targets-1]) {
dcfclk_sta_targets[num_dcfclk_sta_targets] = max_dcfclk_mhz; // If max DCFCLK is greater than the max DCFCLK STA target, insert into the DCFCLK STA target array
num_dcfclk_sta_targets++; dcfclk_sta_targets[num_dcfclk_sta_targets] = max_dcfclk_mhz;
} else if (max_dcfclk_mhz < dcfclk_sta_targets[num_dcfclk_sta_targets-1]) { num_dcfclk_sta_targets++;
// If max DCFCLK is less than the max DCFCLK STA target, cap values and remove duplicates } else if (max_dcfclk_mhz < dcfclk_sta_targets[num_dcfclk_sta_targets-1]) {
for (i = 0; i < num_dcfclk_sta_targets; i++) { // If max DCFCLK is less than the max DCFCLK STA target, cap values and remove duplicates
if (dcfclk_sta_targets[i] > max_dcfclk_mhz) { for (i = 0; i < num_dcfclk_sta_targets; i++) {
dcfclk_sta_targets[i] = max_dcfclk_mhz; if (dcfclk_sta_targets[i] > max_dcfclk_mhz) {
break; dcfclk_sta_targets[i] = max_dcfclk_mhz;
break;
}
} }
// Update size of array since we "removed" duplicates
num_dcfclk_sta_targets = i + 1;
} }
// Update size of array since we "removed" duplicates
num_dcfclk_sta_targets = i + 1;
}
num_uclk_states = bw_params->clk_table.num_entries; num_uclk_states = bw_params->clk_table.num_entries;
// Calculate optimal dcfclk for each uclk // Calculate optimal dcfclk for each uclk
for (i = 0; i < num_uclk_states; i++) { for (i = 0; i < num_uclk_states; i++) {
dcn321_get_optimal_dcfclk_fclk_for_uclk(bw_params->clk_table.entries[i].memclk_mhz * 16, dcn321_get_optimal_dcfclk_fclk_for_uclk(bw_params->clk_table.entries[i].memclk_mhz * 16,
&optimal_dcfclk_for_uclk[i], NULL); &optimal_dcfclk_for_uclk[i], NULL);
if (optimal_dcfclk_for_uclk[i] < bw_params->clk_table.entries[0].dcfclk_mhz) { if (optimal_dcfclk_for_uclk[i] < bw_params->clk_table.entries[0].dcfclk_mhz) {
optimal_dcfclk_for_uclk[i] = bw_params->clk_table.entries[0].dcfclk_mhz; optimal_dcfclk_for_uclk[i] = bw_params->clk_table.entries[0].dcfclk_mhz;
}
} }
}
// Calculate optimal uclk for each dcfclk sta target // Calculate optimal uclk for each dcfclk sta target
for (i = 0; i < num_dcfclk_sta_targets; i++) { for (i = 0; i < num_dcfclk_sta_targets; i++) {
for (j = 0; j < num_uclk_states; j++) { for (j = 0; j < num_uclk_states; j++) {
if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j]) { if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j]) {
optimal_uclk_for_dcfclk_sta_targets[i] = optimal_uclk_for_dcfclk_sta_targets[i] =
bw_params->clk_table.entries[j].memclk_mhz * 16; bw_params->clk_table.entries[j].memclk_mhz * 16;
break; break;
}
} }
} }
}
i = 0; i = 0;
j = 0; j = 0;
// create the final dcfclk and uclk table // create the final dcfclk and uclk table
while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) { while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) {
if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j] && i < num_dcfclk_sta_targets) { if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j] && i < num_dcfclk_sta_targets) {
dcfclk_mhz[num_states] = dcfclk_sta_targets[i]; dcfclk_mhz[num_states] = dcfclk_sta_targets[i];
dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++]; dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++];
} else {
if (j < num_uclk_states && optimal_dcfclk_for_uclk[j] <= max_dcfclk_mhz) {
dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j];
dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16;
} else { } else {
j = num_uclk_states; if (j < num_uclk_states && optimal_dcfclk_for_uclk[j] <= max_dcfclk_mhz) {
dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j];
dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16;
} else {
j = num_uclk_states;
}
} }
} }
}
while (i < num_dcfclk_sta_targets && num_states < DC__VOLTAGE_STATES) { while (i < num_dcfclk_sta_targets && num_states < DC__VOLTAGE_STATES) {
dcfclk_mhz[num_states] = dcfclk_sta_targets[i]; dcfclk_mhz[num_states] = dcfclk_sta_targets[i];
dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++]; dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++];
} }
while (j < num_uclk_states && num_states < DC__VOLTAGE_STATES && while (j < num_uclk_states && num_states < DC__VOLTAGE_STATES &&
optimal_dcfclk_for_uclk[j] <= max_dcfclk_mhz) { optimal_dcfclk_for_uclk[j] <= max_dcfclk_mhz) {
dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j]; dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j];
dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16; dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16;
} }
dcn3_21_soc.num_states = num_states; dcn3_21_soc.num_states = num_states;
for (i = 0; i < dcn3_21_soc.num_states; i++) { for (i = 0; i < dcn3_21_soc.num_states; i++) {
dcn3_21_soc.clock_limits[i].state = i; dcn3_21_soc.clock_limits[i].state = i;
dcn3_21_soc.clock_limits[i].dcfclk_mhz = dcfclk_mhz[i]; dcn3_21_soc.clock_limits[i].dcfclk_mhz = dcfclk_mhz[i];
dcn3_21_soc.clock_limits[i].fabricclk_mhz = dcfclk_mhz[i]; dcn3_21_soc.clock_limits[i].fabricclk_mhz = dcfclk_mhz[i];
/* Fill all states with max values of all these clocks */ /* Fill all states with max values of all these clocks */
dcn3_21_soc.clock_limits[i].dispclk_mhz = max_dispclk_mhz; dcn3_21_soc.clock_limits[i].dispclk_mhz = max_dispclk_mhz;
dcn3_21_soc.clock_limits[i].dppclk_mhz = max_dppclk_mhz; dcn3_21_soc.clock_limits[i].dppclk_mhz = max_dppclk_mhz;
dcn3_21_soc.clock_limits[i].phyclk_mhz = max_phyclk_mhz; dcn3_21_soc.clock_limits[i].phyclk_mhz = max_phyclk_mhz;
dcn3_21_soc.clock_limits[i].dscclk_mhz = max_dispclk_mhz / 3; dcn3_21_soc.clock_limits[i].dscclk_mhz = max_dispclk_mhz / 3;
/* Populate from bw_params for DTBCLK, SOCCLK */ /* Populate from bw_params for DTBCLK, SOCCLK */
if (i > 0) { if (i > 0) {
if (!bw_params->clk_table.entries[i].dtbclk_mhz) { if (!bw_params->clk_table.entries[i].dtbclk_mhz) {
dcn3_21_soc.clock_limits[i].dtbclk_mhz = dcn3_21_soc.clock_limits[i-1].dtbclk_mhz; dcn3_21_soc.clock_limits[i].dtbclk_mhz = dcn3_21_soc.clock_limits[i-1].dtbclk_mhz;
} else { } else {
dcn3_21_soc.clock_limits[i].dtbclk_mhz = bw_params->clk_table.entries[i].dtbclk_mhz; dcn3_21_soc.clock_limits[i].dtbclk_mhz = bw_params->clk_table.entries[i].dtbclk_mhz;
}
} else if (bw_params->clk_table.entries[i].dtbclk_mhz) {
dcn3_21_soc.clock_limits[i].dtbclk_mhz = bw_params->clk_table.entries[i].dtbclk_mhz;
} }
} else if (bw_params->clk_table.entries[i].dtbclk_mhz) {
dcn3_21_soc.clock_limits[i].dtbclk_mhz = bw_params->clk_table.entries[i].dtbclk_mhz;
}
if (!bw_params->clk_table.entries[i].socclk_mhz && i > 0) if (!bw_params->clk_table.entries[i].socclk_mhz && i > 0)
dcn3_21_soc.clock_limits[i].socclk_mhz = dcn3_21_soc.clock_limits[i-1].socclk_mhz; dcn3_21_soc.clock_limits[i].socclk_mhz = dcn3_21_soc.clock_limits[i-1].socclk_mhz;
else else
dcn3_21_soc.clock_limits[i].socclk_mhz = bw_params->clk_table.entries[i].socclk_mhz; dcn3_21_soc.clock_limits[i].socclk_mhz = bw_params->clk_table.entries[i].socclk_mhz;
if (!dram_speed_mts[i] && i > 0) if (!dram_speed_mts[i] && i > 0)
dcn3_21_soc.clock_limits[i].dram_speed_mts = dcn3_21_soc.clock_limits[i-1].dram_speed_mts; dcn3_21_soc.clock_limits[i].dram_speed_mts = dcn3_21_soc.clock_limits[i-1].dram_speed_mts;
else else
dcn3_21_soc.clock_limits[i].dram_speed_mts = dram_speed_mts[i]; dcn3_21_soc.clock_limits[i].dram_speed_mts = dram_speed_mts[i];
/* These clocks cannot come from bw_params, always fill from dcn3_21_soc[0] */ /* These clocks cannot come from bw_params, always fill from dcn3_21_soc[0] */
/* PHYCLK_D18, PHYCLK_D32 */ /* PHYCLK_D18, PHYCLK_D32 */
dcn3_21_soc.clock_limits[i].phyclk_d18_mhz = dcn3_21_soc.clock_limits[0].phyclk_d18_mhz; dcn3_21_soc.clock_limits[i].phyclk_d18_mhz = dcn3_21_soc.clock_limits[0].phyclk_d18_mhz;
dcn3_21_soc.clock_limits[i].phyclk_d32_mhz = dcn3_21_soc.clock_limits[0].phyclk_d32_mhz; dcn3_21_soc.clock_limits[i].phyclk_d32_mhz = dcn3_21_soc.clock_limits[0].phyclk_d32_mhz;
}
} else {
build_synthetic_soc_states(bw_params, dcn3_21_soc.clock_limits, &dcn3_21_soc.num_states);
} }
/* Re-init DML with updated bb */ /* Re-init DML with updated bb */
......
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