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Commit 01dd2545 authored by Andi Kleen's avatar Andi Kleen Committed by Arnaldo Carvalho de Melo
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perf vendor events: Add WestmereEP-SP V2 event file 

Add a Intel event file for perf.
Signed-off-by: default avatarAndi Kleen <ak@linux.intel.com>
Cc: Jiri Olsa <jolsa@redhat.com>
Cc: Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com>
Link: http://lkml.kernel.org/n/tip-rvc0618wzt6indqmvsbpsuwv@git.kernel.org
[ Lowercased the directory and file names ]
Signed-off-by: default avatarArnaldo Carvalho de Melo <acme@redhat.com>
parent 1f888acd
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tools/perf/pmu-events/arch/x86/mapfile.csv
View file @ 01dd2545
......@@ -30,3 +30,5 @@ GenuineIntel-6-4D,v13,silvermont,core
GenuineIntel-6-4C,v13,silvermont,core
GenuineIntel-6-2A,v15,sandybridge,core
GenuineIntel-6-2C,v2,westmereep-dp,core
GenuineIntel-6-2C,v2,westmereep-dp,core
GenuineIntel-6-25,v2,westmereep-sp,core
tools/perf/pmu-events/arch/x86/westmereep-sp/cache.json 0 → 100644
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This source diff could not be displayed because it is too large. You can view the blob instead.
tools/perf/pmu-events/arch/x86/westmereep-sp/floating-point.json 0 → 100644
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[
{
"PEBS": "1",
"EventCode": "0xF7",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "FP_ASSIST.ALL",
"SampleAfterValue": "20000",
"BriefDescription": "X87 Floating point assists (Precise Event)"
},
{
"PEBS": "1",
"EventCode": "0xF7",
"Counter": "0,1,2,3",
"UMask": "0x4",
"EventName": "FP_ASSIST.INPUT",
"SampleAfterValue": "20000",
"BriefDescription": "X87 Floating poiint assists for invalid input value (Precise Event)"
},
{
"PEBS": "1",
"EventCode": "0xF7",
"Counter": "0,1,2,3",
"UMask": "0x2",
"EventName": "FP_ASSIST.OUTPUT",
"SampleAfterValue": "20000",
"BriefDescription": "X87 Floating point assists for invalid output value (Precise Event)"
},
{
"EventCode": "0x10",
"Counter": "0,1,2,3",
"UMask": "0x2",
"EventName": "FP_COMP_OPS_EXE.MMX",
"SampleAfterValue": "2000000",
"BriefDescription": "MMX Uops"
},
{
"EventCode": "0x10",
"Counter": "0,1,2,3",
"UMask": "0x80",
"EventName": "FP_COMP_OPS_EXE.SSE_DOUBLE_PRECISION",
"SampleAfterValue": "2000000",
"BriefDescription": "SSE* FP double precision Uops"
},
{
"EventCode": "0x10",
"Counter": "0,1,2,3",
"UMask": "0x4",
"EventName": "FP_COMP_OPS_EXE.SSE_FP",
"SampleAfterValue": "2000000",
"BriefDescription": "SSE and SSE2 FP Uops"
},
{
"EventCode": "0x10",
"Counter": "0,1,2,3",
"UMask": "0x10",
"EventName": "FP_COMP_OPS_EXE.SSE_FP_PACKED",
"SampleAfterValue": "2000000",
"BriefDescription": "SSE FP packed Uops"
},
{
"EventCode": "0x10",
"Counter": "0,1,2,3",
"UMask": "0x20",
"EventName": "FP_COMP_OPS_EXE.SSE_FP_SCALAR",
"SampleAfterValue": "2000000",
"BriefDescription": "SSE FP scalar Uops"
},
{
"EventCode": "0x10",
"Counter": "0,1,2,3",
"UMask": "0x40",
"EventName": "FP_COMP_OPS_EXE.SSE_SINGLE_PRECISION",
"SampleAfterValue": "2000000",
"BriefDescription": "SSE* FP single precision Uops"
},
{
"EventCode": "0x10",
"Counter": "0,1,2,3",
"UMask": "0x8",
"EventName": "FP_COMP_OPS_EXE.SSE2_INTEGER",
"SampleAfterValue": "2000000",
"BriefDescription": "SSE2 integer Uops"
},
{
"EventCode": "0x10",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "FP_COMP_OPS_EXE.X87",
"SampleAfterValue": "2000000",
"BriefDescription": "Computational floating-point operations executed"
},
{
"EventCode": "0xCC",
"Counter": "0,1,2,3",
"UMask": "0x3",
"EventName": "FP_MMX_TRANS.ANY",
"SampleAfterValue": "2000000",
"BriefDescription": "All Floating Point to and from MMX transitions"
},
{
"EventCode": "0xCC",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "FP_MMX_TRANS.TO_FP",
"SampleAfterValue": "2000000",
"BriefDescription": "Transitions from MMX to Floating Point instructions"
},
{
"EventCode": "0xCC",
"Counter": "0,1,2,3",
"UMask": "0x2",
"EventName": "FP_MMX_TRANS.TO_MMX",
"SampleAfterValue": "2000000",
"BriefDescription": "Transitions from Floating Point to MMX instructions"
},
{
"EventCode": "0x12",
"Counter": "0,1,2,3",
"UMask": "0x4",
"EventName": "SIMD_INT_128.PACK",
"SampleAfterValue": "200000",
"BriefDescription": "128 bit SIMD integer pack operations"
},
{
"EventCode": "0x12",
"Counter": "0,1,2,3",
"UMask": "0x20",
"EventName": "SIMD_INT_128.PACKED_ARITH",
"SampleAfterValue": "200000",
"BriefDescription": "128 bit SIMD integer arithmetic operations"
},
{
"EventCode": "0x12",
"Counter": "0,1,2,3",
"UMask": "0x10",
"EventName": "SIMD_INT_128.PACKED_LOGICAL",
"SampleAfterValue": "200000",
"BriefDescription": "128 bit SIMD integer logical operations"
},
{
"EventCode": "0x12",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "SIMD_INT_128.PACKED_MPY",
"SampleAfterValue": "200000",
"BriefDescription": "128 bit SIMD integer multiply operations"
},
{
"EventCode": "0x12",
"Counter": "0,1,2,3",
"UMask": "0x2",
"EventName": "SIMD_INT_128.PACKED_SHIFT",
"SampleAfterValue": "200000",
"BriefDescription": "128 bit SIMD integer shift operations"
},
{
"EventCode": "0x12",
"Counter": "0,1,2,3",
"UMask": "0x40",
"EventName": "SIMD_INT_128.SHUFFLE_MOVE",
"SampleAfterValue": "200000",
"BriefDescription": "128 bit SIMD integer shuffle/move operations"
},
{
"EventCode": "0x12",
"Counter": "0,1,2,3",
"UMask": "0x8",
"EventName": "SIMD_INT_128.UNPACK",
"SampleAfterValue": "200000",
"BriefDescription": "128 bit SIMD integer unpack operations"
},
{
"EventCode": "0xFD",
"Counter": "0,1,2,3",
"UMask": "0x4",
"EventName": "SIMD_INT_64.PACK",
"SampleAfterValue": "200000",
"BriefDescription": "SIMD integer 64 bit pack operations"
},
{
"EventCode": "0xFD",
"Counter": "0,1,2,3",
"UMask": "0x20",
"EventName": "SIMD_INT_64.PACKED_ARITH",
"SampleAfterValue": "200000",
"BriefDescription": "SIMD integer 64 bit arithmetic operations"
},
{
"EventCode": "0xFD",
"Counter": "0,1,2,3",
"UMask": "0x10",
"EventName": "SIMD_INT_64.PACKED_LOGICAL",
"SampleAfterValue": "200000",
"BriefDescription": "SIMD integer 64 bit logical operations"
},
{
"EventCode": "0xFD",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "SIMD_INT_64.PACKED_MPY",
"SampleAfterValue": "200000",
"BriefDescription": "SIMD integer 64 bit packed multiply operations"
},
{
"EventCode": "0xFD",
"Counter": "0,1,2,3",
"UMask": "0x2",
"EventName": "SIMD_INT_64.PACKED_SHIFT",
"SampleAfterValue": "200000",
"BriefDescription": "SIMD integer 64 bit shift operations"
},
{
"EventCode": "0xFD",
"Counter": "0,1,2,3",
"UMask": "0x40",
"EventName": "SIMD_INT_64.SHUFFLE_MOVE",
"SampleAfterValue": "200000",
"BriefDescription": "SIMD integer 64 bit shuffle/move operations"
},
{
"EventCode": "0xFD",
"Counter": "0,1,2,3",
"UMask": "0x8",
"EventName": "SIMD_INT_64.UNPACK",
"SampleAfterValue": "200000",
"BriefDescription": "SIMD integer 64 bit unpack operations"
}
]
\ No newline at end of file
tools/perf/pmu-events/arch/x86/westmereep-sp/frontend.json 0 → 100644
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[
{
"EventCode": "0xD0",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "MACRO_INSTS.DECODED",
"SampleAfterValue": "2000000",
"BriefDescription": "Instructions decoded"
},
{
"EventCode": "0xA6",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "MACRO_INSTS.FUSIONS_DECODED",
"SampleAfterValue": "2000000",
"BriefDescription": "Macro-fused instructions decoded"
},
{
"EventCode": "0x19",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "TWO_UOP_INSTS_DECODED",
"SampleAfterValue": "2000000",
"BriefDescription": "Two Uop instructions decoded"
}
]
\ No newline at end of file
tools/perf/pmu-events/arch/x86/westmereep-sp/memory.json 0 → 100644
View file @ 01dd2545
[
{
"EventCode": "0xB7, 0xBB",
"MSRValue": "0x6011",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100000",
"BriefDescription": "Offcore data reads satisfied by any DRAM",
"Offcore": "1"
},
{
"EventCode": "0xB7, 0xBB",
"MSRValue": "0xF811",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100000",
"BriefDescription": "Offcore data reads that missed the LLC",
"Offcore": "1"
},
{
"EventCode": "0xB7, 0xBB",
"MSRValue": "0x2011",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100000",
"BriefDescription": "Offcore data reads satisfied by the local DRAM",
"Offcore": "1"
},
{
"EventCode": "0xB7, 0xBB",
"MSRValue": "0x4011",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100000",
"BriefDescription": "Offcore data reads satisfied by a remote DRAM",
"Offcore": "1"
},
{
"EventCode": "0xB7, 0xBB",
"MSRValue": "0x6044",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100000",
"BriefDescription": "Offcore code reads satisfied by any DRAM",
"Offcore": "1"
},
{
"EventCode": "0xB7, 0xBB",
"MSRValue": "0xF844",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_LLC_MISS",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100000",
"BriefDescription": "Offcore code reads that missed the LLC",
"Offcore": "1"
},
{
"EventCode": "0xB7, 0xBB",
"MSRValue": "0x2044",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100000",
"BriefDescription": "Offcore code reads satisfied by the local DRAM",
"Offcore": "1"
},
{
"EventCode": "0xB7, 0xBB",
"MSRValue": "0x4044",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100000",
"BriefDescription": "Offcore code reads satisfied by a remote DRAM",
"Offcore": "1"
},
{
"EventCode": "0xB7, 0xBB",
"MSRValue": "0x60FF",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100000",
"BriefDescription": "Offcore requests satisfied by any DRAM",
"Offcore": "1"
},
{
"EventCode": "0xB7, 0xBB",
"MSRValue": "0xF8FF",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_LLC_MISS",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100000",
"BriefDescription": "Offcore requests that missed the LLC",
"Offcore": "1"
},
{
"EventCode": "0xB7, 0xBB",
"MSRValue": "0x20FF",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100000",
"BriefDescription": "Offcore requests satisfied by the local DRAM",
"Offcore": "1"
},
{
"EventCode": "0xB7, 0xBB",
"MSRValue": "0x40FF",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100000",
"BriefDescription": "Offcore requests satisfied by a remote DRAM",
"Offcore": "1"
},
{
"EventCode": "0xB7, 0xBB",
"MSRValue": "0x6022",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100000",
"BriefDescription": "Offcore RFO requests satisfied by any DRAM",
"Offcore": "1"
},
{
"EventCode": "0xB7, 0xBB",
"MSRValue": "0xF822",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100000",
"BriefDescription": "Offcore RFO requests that missed the LLC",
"Offcore": "1"
},
{
"EventCode": "0xB7, 0xBB",
"MSRValue": "0x2022",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100000",
"BriefDescription": "Offcore RFO requests satisfied by the local DRAM",
"Offcore": "1"
},
{
"EventCode": "0xB7, 0xBB",
"MSRValue": "0x4022",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100000",
"BriefDescription": "Offcore RFO requests satisfied by a remote DRAM",
"Offcore": "1"
},
{
"EventCode": "0xB7, 0xBB",
"MSRValue": "0x6008",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.COREWB.ANY_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100000",
"BriefDescription": "Offcore writebacks to any DRAM",
"Offcore": "1"
},
{
"EventCode": "0xB7, 0xBB",
"MSRValue": "0xF808",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.COREWB.ANY_LLC_MISS",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100000",
"BriefDescription": "Offcore writebacks that missed the LLC",
"Offcore": "1"
},
{
"EventCode": "0xB7, 0xBB",
"MSRValue": "0x2008",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.COREWB.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100000",
"BriefDescription": "Offcore writebacks to the local DRAM",
"Offcore": "1"
},
{
"EventCode": "0xB7, 0xBB",
"MSRValue": "0x4008",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100000",
"BriefDescription": "Offcore writebacks to a remote DRAM",
"Offcore": "1"
},
{
"EventCode": "0xB7, 0xBB",
"MSRValue": "0x6077",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100000",
"BriefDescription": "Offcore code or data read requests satisfied by any DRAM",
"Offcore": "1"
},
{
"EventCode": "0xB7, 0xBB",
"MSRValue": "0xF877",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_LLC_MISS",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100000",
"BriefDescription": "Offcore code or data read requests that missed the LLC",
"Offcore": "1"
},
{
"EventCode": "0xB7, 0xBB",
"MSRValue": "0x2077",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100000",
"BriefDescription": "Offcore code or data read requests satisfied by the local DRAM",
"Offcore": "1"
},
{
"EventCode": "0xB7, 0xBB",
"MSRValue": "0x4077",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100000",
"BriefDescription": "Offcore code or data read requests satisfied by a remote DRAM",
"Offcore": "1"
},
{
"EventCode": "0xB7, 0xBB",
"MSRValue": "0x6033",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100000",
"BriefDescription": "Offcore request = all data, response = any DRAM",
"Offcore": "1"
},
{
"EventCode": "0xB7, 0xBB",
"MSRValue": "0xF833",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_LLC_MISS",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100000",
"BriefDescription": "Offcore request = all data, response = any LLC miss",
"Offcore": "1"
},
{
"EventCode": "0xB7, 0xBB",
"MSRValue": "0x2033",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100000",
"BriefDescription": "Offcore data reads, RFO's and prefetches statisfied by the local DRAM.",
"Offcore": "1"
},
{
"EventCode": "0xB7, 0xBB",
"MSRValue": "0x4033",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100000",
"BriefDescription": "Offcore data reads, RFO's and prefetches statisfied by the remote DRAM",
"Offcore": "1"
},
{
"EventCode": "0xB7, 0xBB",
"MSRValue": "0x6003",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100000",
"BriefDescription": "Offcore demand data requests satisfied by any DRAM",
"Offcore": "1"
},
{
"EventCode": "0xB7, 0xBB",
"MSRValue": "0xF803",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_LLC_MISS",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100000",
"BriefDescription": "Offcore demand data requests that missed the LLC",
"Offcore": "1"
},
{
"EventCode": "0xB7, 0xBB",
"MSRValue": "0x2003",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100000",
"BriefDescription": "Offcore demand data requests satisfied by the local DRAM",
"Offcore": "1"
},
{
"EventCode": "0xB7, 0xBB",
"MSRValue": "0x4003",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100000",
"BriefDescription": "Offcore demand data requests satisfied by a remote DRAM",
"Offcore": "1"
},
{
"EventCode": "0xB7, 0xBB",
"MSRValue": "0x6001",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100000",
"BriefDescription": "Offcore demand data reads satisfied by any DRAM",
"Offcore": "1"
},
{
"EventCode": "0xB7, 0xBB",
"MSRValue": "0xF801",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_LLC_MISS",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100000",
"BriefDescription": "Offcore demand data reads that missed the LLC",
"Offcore": "1"
},
{
"EventCode": "0xB7, 0xBB",
"MSRValue": "0x2001",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100000",
"BriefDescription": "Offcore demand data reads satisfied by the local DRAM",
"Offcore": "1"
},
{
"EventCode": "0xB7, 0xBB",
"MSRValue": "0x4001",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100000",
"BriefDescription": "Offcore demand data reads satisfied by a remote DRAM",
"Offcore": "1"
},
{
"EventCode": "0xB7, 0xBB",
"MSRValue": "0x6004",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100000",
"BriefDescription": "Offcore demand code reads satisfied by any DRAM",
"Offcore": "1"
},
{
"EventCode": "0xB7, 0xBB",
"MSRValue": "0xF804",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_LLC_MISS",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100000",
"BriefDescription": "Offcore demand code reads that missed the LLC",
"Offcore": "1"
},
{
"EventCode": "0xB7, 0xBB",
"MSRValue": "0x2004",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100000",
"BriefDescription": "Offcore demand code reads satisfied by the local DRAM",
"Offcore": "1"
},
{
"EventCode": "0xB7, 0xBB",
"MSRValue": "0x4004",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100000",
"BriefDescription": "Offcore demand code reads satisfied by a remote DRAM",
"Offcore": "1"
},
{
"EventCode": "0xB7, 0xBB",
"MSRValue": "0x6002",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100000",
"BriefDescription": "Offcore demand RFO requests satisfied by any DRAM",
"Offcore": "1"
},
{
"EventCode": "0xB7, 0xBB",
"MSRValue": "0xF802",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_LLC_MISS",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100000",
"BriefDescription": "Offcore demand RFO requests that missed the LLC",
"Offcore": "1"
},
{
"EventCode": "0xB7, 0xBB",
"MSRValue": "0x2002",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100000",
"BriefDescription": "Offcore demand RFO requests satisfied by the local DRAM",
"Offcore": "1"
},
{
"EventCode": "0xB7, 0xBB",
"MSRValue": "0x4002",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100000",
"BriefDescription": "Offcore demand RFO requests satisfied by a remote DRAM",
"Offcore": "1"
},
{
"EventCode": "0xB7, 0xBB",
"MSRValue": "0x6080",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.OTHER.ANY_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100000",
"BriefDescription": "Offcore other requests satisfied by any DRAM",
"Offcore": "1"
},
{
"EventCode": "0xB7, 0xBB",
"MSRValue": "0xF880",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.OTHER.ANY_LLC_MISS",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100000",
"BriefDescription": "Offcore other requests that missed the LLC",
"Offcore": "1"
},
{
"EventCode": "0xB7, 0xBB",
"MSRValue": "0x4080",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100000",
"BriefDescription": "Offcore other requests satisfied by a remote DRAM",
"Offcore": "1"
},
{
"EventCode": "0xB7, 0xBB",
"MSRValue": "0x6050",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100000",
"BriefDescription": "Offcore prefetch data requests satisfied by any DRAM",
"Offcore": "1"
},
{
"EventCode": "0xB7, 0xBB",
"MSRValue": "0xF850",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_LLC_MISS",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100000",
"BriefDescription": "Offcore prefetch data requests that missed the LLC",
"Offcore": "1"
},
{
"EventCode": "0xB7, 0xBB",
"MSRValue": "0x2050",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.PF_DATA.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100000",
"BriefDescription": "Offcore prefetch data requests satisfied by the local DRAM",
"Offcore": "1"
},
{
"EventCode": "0xB7, 0xBB",
"MSRValue": "0x4050",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100000",
"BriefDescription": "Offcore prefetch data requests satisfied by a remote DRAM",
"Offcore": "1"
},
{
"EventCode": "0xB7, 0xBB",
"MSRValue": "0x6010",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100000",
"BriefDescription": "Offcore prefetch data reads satisfied by any DRAM",
"Offcore": "1"
},
{
"EventCode": "0xB7, 0xBB",
"MSRValue": "0xF810",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_LLC_MISS",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100000",
"BriefDescription": "Offcore prefetch data reads that missed the LLC",
"Offcore": "1"
},
{
"EventCode": "0xB7, 0xBB",
"MSRValue": "0x2010",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100000",
"BriefDescription": "Offcore prefetch data reads satisfied by the local DRAM",
"Offcore": "1"
},
{
"EventCode": "0xB7, 0xBB",
"MSRValue": "0x4010",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100000",
"BriefDescription": "Offcore prefetch data reads satisfied by a remote DRAM",
"Offcore": "1"
},
{
"EventCode": "0xB7, 0xBB",
"MSRValue": "0x6040",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100000",
"BriefDescription": "Offcore prefetch code reads satisfied by any DRAM",
"Offcore": "1"
},
{
"EventCode": "0xB7, 0xBB",
"MSRValue": "0xF840",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_LLC_MISS",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100000",
"BriefDescription": "Offcore prefetch code reads that missed the LLC",
"Offcore": "1"
},
{
"EventCode": "0xB7, 0xBB",
"MSRValue": "0x2040",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100000",
"BriefDescription": "Offcore prefetch code reads satisfied by the local DRAM",
"Offcore": "1"
},
{
"EventCode": "0xB7, 0xBB",
"MSRValue": "0x4040",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100000",
"BriefDescription": "Offcore prefetch code reads satisfied by a remote DRAM",
"Offcore": "1"
},
{
"EventCode": "0xB7, 0xBB",
"MSRValue": "0x6020",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100000",
"BriefDescription": "Offcore prefetch RFO requests satisfied by any DRAM",
"Offcore": "1"
},
{
"EventCode": "0xB7, 0xBB",
"MSRValue": "0xF820",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_LLC_MISS",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100000",
"BriefDescription": "Offcore prefetch RFO requests that missed the LLC",
"Offcore": "1"
},
{
"EventCode": "0xB7, 0xBB",
"MSRValue": "0x2020",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.PF_RFO.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100000",
"BriefDescription": "Offcore prefetch RFO requests satisfied by the local DRAM",
"Offcore": "1"
},
{
"EventCode": "0xB7, 0xBB",
"MSRValue": "0x4020",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100000",
"BriefDescription": "Offcore prefetch RFO requests satisfied by a remote DRAM",
"Offcore": "1"
},
{
"EventCode": "0xB7, 0xBB",
"MSRValue": "0x6070",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100000",
"BriefDescription": "Offcore prefetch requests satisfied by any DRAM",
"Offcore": "1"
},
{
"EventCode": "0xB7, 0xBB",
"MSRValue": "0xF870",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100000",
"BriefDescription": "Offcore prefetch requests that missed the LLC",
"Offcore": "1"
},
{
"EventCode": "0xB7, 0xBB",
"MSRValue": "0x2070",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.PREFETCH.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100000",
"BriefDescription": "Offcore prefetch requests satisfied by the local DRAM",
"Offcore": "1"
},
{
"EventCode": "0xB7, 0xBB",
"MSRValue": "0x4070",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100000",
"BriefDescription": "Offcore prefetch requests satisfied by a remote DRAM",
"Offcore": "1"
}
]
\ No newline at end of file
tools/perf/pmu-events/arch/x86/westmereep-sp/other.json 0 → 100644
View file @ 01dd2545
[
{
"EventCode": "0xE8",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "BPU_CLEARS.EARLY",
"SampleAfterValue": "2000000",
"BriefDescription": "Early Branch Prediciton Unit clears"
},
{
"EventCode": "0xE8",
"Counter": "0,1,2,3",
"UMask": "0x2",
"EventName": "BPU_CLEARS.LATE",
"SampleAfterValue": "2000000",
"BriefDescription": "Late Branch Prediction Unit clears"
},
{
"EventCode": "0xE5",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "BPU_MISSED_CALL_RET",
"SampleAfterValue": "2000000",
"BriefDescription": "Branch prediction unit missed call or return"
},
{
"EventCode": "0xD5",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "ES_REG_RENAMES",
"SampleAfterValue": "2000000",
"BriefDescription": "ES segment renames"
},
{
"EventCode": "0x6C",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "IO_TRANSACTIONS",
"SampleAfterValue": "2000000",
"BriefDescription": "I/O transactions"
},
{
"EventCode": "0x80",
"Counter": "0,1,2,3",
"UMask": "0x4",
"EventName": "L1I.CYCLES_STALLED",
"SampleAfterValue": "2000000",
"BriefDescription": "L1I instruction fetch stall cycles"
},
{
"EventCode": "0x80",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "L1I.HITS",
"SampleAfterValue": "2000000",
"BriefDescription": "L1I instruction fetch hits"
},
{
"EventCode": "0x80",
"Counter": "0,1,2,3",
"UMask": "0x2",
"EventName": "L1I.MISSES",
"SampleAfterValue": "2000000",
"BriefDescription": "L1I instruction fetch misses"
},
{
"EventCode": "0x80",
"Counter": "0,1,2,3",
"UMask": "0x3",
"EventName": "L1I.READS",
"SampleAfterValue": "2000000",
"BriefDescription": "L1I Instruction fetches"
},
{
"EventCode": "0x82",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "LARGE_ITLB.HIT",
"SampleAfterValue": "200000",
"BriefDescription": "Large ITLB hit"
},
{
"EventCode": "0x3",
"Counter": "0,1,2,3",
"UMask": "0x2",
"EventName": "LOAD_BLOCK.OVERLAP_STORE",
"SampleAfterValue": "200000",
"BriefDescription": "Loads that partially overlap an earlier store"
},
{
"EventCode": "0x13",
"Counter": "0,1,2,3",
"UMask": "0x7",
"EventName": "LOAD_DISPATCH.ANY",
"SampleAfterValue": "2000000",
"BriefDescription": "All loads dispatched"
},
{
"EventCode": "0x13",
"Counter": "0,1,2,3",
"UMask": "0x4",
"EventName": "LOAD_DISPATCH.MOB",
"SampleAfterValue": "2000000",
"BriefDescription": "Loads dispatched from the MOB"
},
{
"EventCode": "0x13",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "LOAD_DISPATCH.RS",
"SampleAfterValue": "2000000",
"BriefDescription": "Loads dispatched that bypass the MOB"
},
{
"EventCode": "0x13",
"Counter": "0,1,2,3",
"UMask": "0x2",
"EventName": "LOAD_DISPATCH.RS_DELAYED",
"SampleAfterValue": "2000000",
"BriefDescription": "Loads dispatched from stage 305"
},
{
"EventCode": "0x7",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "PARTIAL_ADDRESS_ALIAS",
"SampleAfterValue": "200000",
"BriefDescription": "False dependencies due to partial address aliasing"
},
{
"EventCode": "0xD2",
"Counter": "0,1,2,3",
"UMask": "0xf",
"EventName": "RAT_STALLS.ANY",
"SampleAfterValue": "2000000",
"BriefDescription": "All RAT stall cycles"
},
{
"EventCode": "0xD2",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "RAT_STALLS.FLAGS",
"SampleAfterValue": "2000000",
"BriefDescription": "Flag stall cycles"
},
{
"EventCode": "0xD2",
"Counter": "0,1,2,3",
"UMask": "0x2",
"EventName": "RAT_STALLS.REGISTERS",
"SampleAfterValue": "2000000",
"BriefDescription": "Partial register stall cycles"
},
{
"EventCode": "0xD2",
"Counter": "0,1,2,3",
"UMask": "0x4",
"EventName": "RAT_STALLS.ROB_READ_PORT",
"SampleAfterValue": "2000000",
"BriefDescription": "ROB read port stalls cycles"
},
{
"EventCode": "0xD2",
"Counter": "0,1,2,3",
"UMask": "0x8",
"EventName": "RAT_STALLS.SCOREBOARD",
"SampleAfterValue": "2000000",
"BriefDescription": "Scoreboard stall cycles"
},
{
"EventCode": "0x4",
"Counter": "0,1,2,3",
"UMask": "0x7",
"EventName": "SB_DRAIN.ANY",
"SampleAfterValue": "200000",
"BriefDescription": "All Store buffer stall cycles"
},
{
"EventCode": "0xD4",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "SEG_RENAME_STALLS",
"SampleAfterValue": "2000000",
"BriefDescription": "Segment rename stall cycles"
},
{
"EventCode": "0xB8",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "SNOOP_RESPONSE.HIT",
"SampleAfterValue": "100000",
"BriefDescription": "Thread responded HIT to snoop"
},
{
"EventCode": "0xB8",
"Counter": "0,1,2,3",
"UMask": "0x2",
"EventName": "SNOOP_RESPONSE.HITE",
"SampleAfterValue": "100000",
"BriefDescription": "Thread responded HITE to snoop"
},
{
"EventCode": "0xB8",
"Counter": "0,1,2,3",
"UMask": "0x4",
"EventName": "SNOOP_RESPONSE.HITM",
"SampleAfterValue": "100000",
"BriefDescription": "Thread responded HITM to snoop"
},
{
"EventCode": "0xB4",
"Counter": "0,1,2,3",
"UMask": "0x4",
"EventName": "SNOOPQ_REQUESTS.CODE",
"SampleAfterValue": "100000",
"BriefDescription": "Snoop code requests"
},
{
"EventCode": "0xB4",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "SNOOPQ_REQUESTS.DATA",
"SampleAfterValue": "100000",
"BriefDescription": "Snoop data requests"
},
{
"EventCode": "0xB4",
"Counter": "0,1,2,3",
"UMask": "0x2",
"EventName": "SNOOPQ_REQUESTS.INVALIDATE",
"SampleAfterValue": "100000",
"BriefDescription": "Snoop invalidate requests"
},
{
"EventCode": "0xB3",
"UMask": "0x4",
"EventName": "SNOOPQ_REQUESTS_OUTSTANDING.CODE",
"SampleAfterValue": "2000000",
"BriefDescription": "Outstanding snoop code requests"
},
{
"EventCode": "0xB3",
"UMask": "0x4",
"EventName": "SNOOPQ_REQUESTS_OUTSTANDING.CODE_NOT_EMPTY",
"SampleAfterValue": "2000000",
"BriefDescription": "Cycles snoop code requests queued",
"CounterMask": "1"
},
{
"EventCode": "0xB3",
"UMask": "0x1",
"EventName": "SNOOPQ_REQUESTS_OUTSTANDING.DATA",
"SampleAfterValue": "2000000",
"BriefDescription": "Outstanding snoop data requests"
},
{
"EventCode": "0xB3",
"UMask": "0x1",
"EventName": "SNOOPQ_REQUESTS_OUTSTANDING.DATA_NOT_EMPTY",
"SampleAfterValue": "2000000",
"BriefDescription": "Cycles snoop data requests queued",
"CounterMask": "1"
},
{
"EventCode": "0xB3",
"UMask": "0x2",
"EventName": "SNOOPQ_REQUESTS_OUTSTANDING.INVALIDATE",
"SampleAfterValue": "2000000",
"BriefDescription": "Outstanding snoop invalidate requests"
},
{
"EventCode": "0xB3",
"UMask": "0x2",
"EventName": "SNOOPQ_REQUESTS_OUTSTANDING.INVALIDATE_NOT_EMPTY",
"SampleAfterValue": "2000000",
"BriefDescription": "Cycles snoop invalidate requests queued",
"CounterMask": "1"
},
{
"EventCode": "0xF6",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "SQ_FULL_STALL_CYCLES",
"SampleAfterValue": "2000000",
"BriefDescription": "Super Queue full stall cycles"
}
]
\ No newline at end of file
tools/perf/pmu-events/arch/x86/westmereep-sp/pipeline.json 0 → 100644
View file @ 01dd2545
[
{
"EventCode": "0x14",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "ARITH.CYCLES_DIV_BUSY",
"SampleAfterValue": "2000000",
"BriefDescription": "Cycles the divider is busy"
},
{
"EventCode": "0x14",
"Invert": "1",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "ARITH.DIV",
"SampleAfterValue": "2000000",
"BriefDescription": "Divide Operations executed",
"CounterMask": "1",
"EdgeDetect": "1"
},
{
"EventCode": "0x14",
"Counter": "0,1,2,3",
"UMask": "0x2",
"EventName": "ARITH.MUL",
"SampleAfterValue": "2000000",
"BriefDescription": "Multiply operations executed"
},
{
"EventCode": "0xE6",
"Counter": "0,1,2,3",
"UMask": "0x2",
"EventName": "BACLEAR.BAD_TARGET",
"SampleAfterValue": "2000000",
"BriefDescription": "BACLEAR asserted with bad target address"
},
{
"EventCode": "0xE6",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "BACLEAR.CLEAR",
"SampleAfterValue": "2000000",
"BriefDescription": "BACLEAR asserted, regardless of cause "
},
{
"EventCode": "0xA7",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "BACLEAR_FORCE_IQ",
"SampleAfterValue": "2000000",
"BriefDescription": "Instruction queue forced BACLEAR"
},
{
"EventCode": "0xE0",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "BR_INST_DECODED",
"SampleAfterValue": "2000000",
"BriefDescription": "Branch instructions decoded"
},
{
"EventCode": "0x88",
"Counter": "0,1,2,3",
"UMask": "0x7f",
"EventName": "BR_INST_EXEC.ANY",
"SampleAfterValue": "200000",
"BriefDescription": "Branch instructions executed"
},
{
"EventCode": "0x88",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "BR_INST_EXEC.COND",
"SampleAfterValue": "200000",
"BriefDescription": "Conditional branch instructions executed"
},
{
"EventCode": "0x88",
"Counter": "0,1,2,3",
"UMask": "0x2",
"EventName": "BR_INST_EXEC.DIRECT",
"SampleAfterValue": "200000",
"BriefDescription": "Unconditional branches executed"
},
{
"EventCode": "0x88",
"Counter": "0,1,2,3",
"UMask": "0x10",
"EventName": "BR_INST_EXEC.DIRECT_NEAR_CALL",
"SampleAfterValue": "20000",
"BriefDescription": "Unconditional call branches executed"
},
{
"EventCode": "0x88",
"Counter": "0,1,2,3",
"UMask": "0x20",
"EventName": "BR_INST_EXEC.INDIRECT_NEAR_CALL",
"SampleAfterValue": "20000",
"BriefDescription": "Indirect call branches executed"
},
{
"EventCode": "0x88",
"Counter": "0,1,2,3",
"UMask": "0x4",
"EventName": "BR_INST_EXEC.INDIRECT_NON_CALL",
"SampleAfterValue": "20000",
"BriefDescription": "Indirect non call branches executed"
},
{
"EventCode": "0x88",
"Counter": "0,1,2,3",
"UMask": "0x30",
"EventName": "BR_INST_EXEC.NEAR_CALLS",
"SampleAfterValue": "20000",
"BriefDescription": "Call branches executed"
},
{
"EventCode": "0x88",
"Counter": "0,1,2,3",
"UMask": "0x7",
"EventName": "BR_INST_EXEC.NON_CALLS",
"SampleAfterValue": "200000",
"BriefDescription": "All non call branches executed"
},
{
"EventCode": "0x88",
"Counter": "0,1,2,3",
"UMask": "0x8",
"EventName": "BR_INST_EXEC.RETURN_NEAR",
"SampleAfterValue": "20000",
"BriefDescription": "Indirect return branches executed"
},
{
"EventCode": "0x88",
"Counter": "0,1,2,3",
"UMask": "0x40",
"EventName": "BR_INST_EXEC.TAKEN",
"SampleAfterValue": "200000",
"BriefDescription": "Taken branches executed"
},
{
"PEBS": "1",
"EventCode": "0xC4",
"Counter": "0,1,2,3",
"UMask": "0x4",
"EventName": "BR_INST_RETIRED.ALL_BRANCHES",
"SampleAfterValue": "200000",
"BriefDescription": "Retired branch instructions (Precise Event)"
},
{
"PEBS": "1",
"EventCode": "0xC4",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "BR_INST_RETIRED.CONDITIONAL",
"SampleAfterValue": "200000",
"BriefDescription": "Retired conditional branch instructions (Precise Event)"
},
{
"PEBS": "1",
"EventCode": "0xC4",
"Counter": "0,1,2,3",
"UMask": "0x2",
"EventName": "BR_INST_RETIRED.NEAR_CALL",
"SampleAfterValue": "20000",
"BriefDescription": "Retired near call instructions (Precise Event)"
},
{
"EventCode": "0x89",
"Counter": "0,1,2,3",
"UMask": "0x7f",
"EventName": "BR_MISP_EXEC.ANY",
"SampleAfterValue": "20000",
"BriefDescription": "Mispredicted branches executed"
},
{
"EventCode": "0x89",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "BR_MISP_EXEC.COND",
"SampleAfterValue": "20000",
"BriefDescription": "Mispredicted conditional branches executed"
},
{
"EventCode": "0x89",
"Counter": "0,1,2,3",
"UMask": "0x2",
"EventName": "BR_MISP_EXEC.DIRECT",
"SampleAfterValue": "20000",
"BriefDescription": "Mispredicted unconditional branches executed"
},
{
"EventCode": "0x89",
"Counter": "0,1,2,3",
"UMask": "0x10",
"EventName": "BR_MISP_EXEC.DIRECT_NEAR_CALL",
"SampleAfterValue": "2000",
"BriefDescription": "Mispredicted non call branches executed"
},
{
"EventCode": "0x89",
"Counter": "0,1,2,3",
"UMask": "0x20",
"EventName": "BR_MISP_EXEC.INDIRECT_NEAR_CALL",
"SampleAfterValue": "2000",
"BriefDescription": "Mispredicted indirect call branches executed"
},
{
"EventCode": "0x89",
"Counter": "0,1,2,3",
"UMask": "0x4",
"EventName": "BR_MISP_EXEC.INDIRECT_NON_CALL",
"SampleAfterValue": "2000",
"BriefDescription": "Mispredicted indirect non call branches executed"
},
{
"EventCode": "0x89",
"Counter": "0,1,2,3",
"UMask": "0x30",
"EventName": "BR_MISP_EXEC.NEAR_CALLS",
"SampleAfterValue": "2000",
"BriefDescription": "Mispredicted call branches executed"
},
{
"EventCode": "0x89",
"Counter": "0,1,2,3",
"UMask": "0x7",
"EventName": "BR_MISP_EXEC.NON_CALLS",
"SampleAfterValue": "20000",
"BriefDescription": "Mispredicted non call branches executed"
},
{
"EventCode": "0x89",
"Counter": "0,1,2,3",
"UMask": "0x8",
"EventName": "BR_MISP_EXEC.RETURN_NEAR",
"SampleAfterValue": "2000",
"BriefDescription": "Mispredicted return branches executed"
},
{
"EventCode": "0x89",
"Counter": "0,1,2,3",
"UMask": "0x40",
"EventName": "BR_MISP_EXEC.TAKEN",
"SampleAfterValue": "20000",
"BriefDescription": "Mispredicted taken branches executed"
},
{
"PEBS": "1",
"EventCode": "0xC5",
"Counter": "0,1,2,3",
"UMask": "0x4",
"EventName": "BR_MISP_RETIRED.ALL_BRANCHES",
"SampleAfterValue": "20000",
"BriefDescription": "Mispredicted retired branch instructions (Precise Event)"
},
{
"PEBS": "1",
"EventCode": "0xC5",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "BR_MISP_RETIRED.CONDITIONAL",
"SampleAfterValue": "20000",
"BriefDescription": "Mispredicted conditional retired branches (Precise Event)"
},
{
"PEBS": "1",
"EventCode": "0xC5",
"Counter": "0,1,2,3",
"UMask": "0x2",
"EventName": "BR_MISP_RETIRED.NEAR_CALL",
"SampleAfterValue": "2000",
"BriefDescription": "Mispredicted near retired calls (Precise Event)"
},
{
"EventCode": "0x0",
"Counter": "Fixed counter 3",
"UMask": "0x0",
"EventName": "CPU_CLK_UNHALTED.REF",
"SampleAfterValue": "2000000",
"BriefDescription": "Reference cycles when thread is not halted (fixed counter)"
},
{
"EventCode": "0x3C",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "CPU_CLK_UNHALTED.REF_P",
"SampleAfterValue": "100000",
"BriefDescription": "Reference base clock (133 Mhz) cycles when thread is not halted (programmable counter)"
},
{
"EventCode": "0x0",
"Counter": "Fixed counter 2",
"UMask": "0x0",
"EventName": "CPU_CLK_UNHALTED.THREAD",
"SampleAfterValue": "2000000",
"BriefDescription": "Cycles when thread is not halted (fixed counter)"
},
{
"EventCode": "0x3C",
"Counter": "0,1,2,3",
"UMask": "0x0",
"EventName": "CPU_CLK_UNHALTED.THREAD_P",
"SampleAfterValue": "2000000",
"BriefDescription": "Cycles when thread is not halted (programmable counter)"
},
{
"EventCode": "0x3C",
"Invert": "1",
"Counter": "0,1,2,3",
"UMask": "0x0",
"EventName": "CPU_CLK_UNHALTED.TOTAL_CYCLES",
"SampleAfterValue": "2000000",
"BriefDescription": "Total CPU cycles",
"CounterMask": "2"
},
{
"EventCode": "0x87",
"Counter": "0,1,2,3",
"UMask": "0xf",
"EventName": "ILD_STALL.ANY",
"SampleAfterValue": "2000000",
"BriefDescription": "Any Instruction Length Decoder stall cycles"
},
{
"EventCode": "0x87",
"Counter": "0,1,2,3",
"UMask": "0x4",
"EventName": "ILD_STALL.IQ_FULL",
"SampleAfterValue": "2000000",
"BriefDescription": "Instruction Queue full stall cycles"
},
{
"EventCode": "0x87",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "ILD_STALL.LCP",
"SampleAfterValue": "2000000",
"BriefDescription": "Length Change Prefix stall cycles"
},
{
"EventCode": "0x87",
"Counter": "0,1,2,3",
"UMask": "0x2",
"EventName": "ILD_STALL.MRU",
"SampleAfterValue": "2000000",
"BriefDescription": "Stall cycles due to BPU MRU bypass"
},
{
"EventCode": "0x87",
"Counter": "0,1,2,3",
"UMask": "0x8",
"EventName": "ILD_STALL.REGEN",
"SampleAfterValue": "2000000",
"BriefDescription": "Regen stall cycles"
},
{
"EventCode": "0x18",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "INST_DECODED.DEC0",
"SampleAfterValue": "2000000",
"BriefDescription": "Instructions that must be decoded by decoder 0"
},
{
"EventCode": "0x1E",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "INST_QUEUE_WRITE_CYCLES",
"SampleAfterValue": "2000000",
"BriefDescription": "Cycles instructions are written to the instruction queue"
},
{
"EventCode": "0x17",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "INST_QUEUE_WRITES",
"SampleAfterValue": "2000000",
"BriefDescription": "Instructions written to instruction queue."
},
{
"EventCode": "0x0",
"Counter": "Fixed counter 1",
"UMask": "0x0",
"EventName": "INST_RETIRED.ANY",
"SampleAfterValue": "2000000",
"BriefDescription": "Instructions retired (fixed counter)"
},
{
"PEBS": "1",
"EventCode": "0xC0",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "INST_RETIRED.ANY_P",
"SampleAfterValue": "2000000",
"BriefDescription": "Instructions retired (Programmable counter and Precise Event)"
},
{
"PEBS": "1",
"EventCode": "0xC0",
"Counter": "0,1,2,3",
"UMask": "0x4",
"EventName": "INST_RETIRED.MMX",
"SampleAfterValue": "2000000",
"BriefDescription": "Retired MMX instructions (Precise Event)"
},
{
"PEBS": "1",
"EventCode": "0xC0",
"Invert": "1",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "INST_RETIRED.TOTAL_CYCLES",
"SampleAfterValue": "2000000",
"BriefDescription": "Total cycles (Precise Event)",
"CounterMask": "16"
},
{
"PEBS": "1",
"EventCode": "0xC0",
"Counter": "0,1,2,3",
"UMask": "0x2",
"EventName": "INST_RETIRED.X87",
"SampleAfterValue": "2000000",
"BriefDescription": "Retired floating-point operations (Precise Event)"
},
{
"EventCode": "0x4C",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "LOAD_HIT_PRE",
"SampleAfterValue": "200000",
"BriefDescription": "Load operations conflicting with software prefetches"
},
{
"EventCode": "0xA8",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "LSD.ACTIVE",
"SampleAfterValue": "2000000",
"BriefDescription": "Cycles when uops were delivered by the LSD",
"CounterMask": "1"
},
{
"EventCode": "0xA8",
"Invert": "1",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "LSD.INACTIVE",
"SampleAfterValue": "2000000",
"BriefDescription": "Cycles no uops were delivered by the LSD",
"CounterMask": "1"
},
{
"EventCode": "0x20",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "LSD_OVERFLOW",
"SampleAfterValue": "2000000",
"BriefDescription": "Loops that can't stream from the instruction queue"
},
{
"EventCode": "0xC3",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "MACHINE_CLEARS.CYCLES",
"SampleAfterValue": "20000",
"BriefDescription": "Cycles machine clear asserted"
},
{
"EventCode": "0xC3",
"Counter": "0,1,2,3",
"UMask": "0x2",
"EventName": "MACHINE_CLEARS.MEM_ORDER",
"SampleAfterValue": "20000",
"BriefDescription": "Execution pipeline restart due to Memory ordering conflicts"
},
{
"EventCode": "0xC3",
"Counter": "0,1,2,3",
"UMask": "0x4",
"EventName": "MACHINE_CLEARS.SMC",
"SampleAfterValue": "20000",
"BriefDescription": "Self-Modifying Code detected"
},
{
"EventCode": "0xA2",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "RESOURCE_STALLS.ANY",
"SampleAfterValue": "2000000",
"BriefDescription": "Resource related stall cycles"
},
{
"EventCode": "0xA2",
"Counter": "0,1,2,3",
"UMask": "0x20",
"EventName": "RESOURCE_STALLS.FPCW",
"SampleAfterValue": "2000000",
"BriefDescription": "FPU control word write stall cycles"
},
{
"EventCode": "0xA2",
"Counter": "0,1,2,3",
"UMask": "0x2",
"EventName": "RESOURCE_STALLS.LOAD",
"SampleAfterValue": "2000000",
"BriefDescription": "Load buffer stall cycles"
},
{
"EventCode": "0xA2",
"Counter": "0,1,2,3",
"UMask": "0x40",
"EventName": "RESOURCE_STALLS.MXCSR",
"SampleAfterValue": "2000000",
"BriefDescription": "MXCSR rename stall cycles"
},
{
"EventCode": "0xA2",
"Counter": "0,1,2,3",
"UMask": "0x80",
"EventName": "RESOURCE_STALLS.OTHER",
"SampleAfterValue": "2000000",
"BriefDescription": "Other Resource related stall cycles"
},
{
"EventCode": "0xA2",
"Counter": "0,1,2,3",
"UMask": "0x10",
"EventName": "RESOURCE_STALLS.ROB_FULL",
"SampleAfterValue": "2000000",
"BriefDescription": "ROB full stall cycles"
},
{
"EventCode": "0xA2",
"Counter": "0,1,2,3",
"UMask": "0x4",
"EventName": "RESOURCE_STALLS.RS_FULL",
"SampleAfterValue": "2000000",
"BriefDescription": "Reservation Station full stall cycles"
},
{
"EventCode": "0xA2",
"Counter": "0,1,2,3",
"UMask": "0x8",
"EventName": "RESOURCE_STALLS.STORE",
"SampleAfterValue": "2000000",
"BriefDescription": "Store buffer stall cycles"
},
{
"PEBS": "1",
"EventCode": "0xC7",
"Counter": "0,1,2,3",
"UMask": "0x4",
"EventName": "SSEX_UOPS_RETIRED.PACKED_DOUBLE",
"SampleAfterValue": "200000",
"BriefDescription": "SIMD Packed-Double Uops retired (Precise Event)"
},
{
"PEBS": "1",
"EventCode": "0xC7",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "SSEX_UOPS_RETIRED.PACKED_SINGLE",
"SampleAfterValue": "200000",
"BriefDescription": "SIMD Packed-Single Uops retired (Precise Event)"
},
{
"PEBS": "1",
"EventCode": "0xC7",
"Counter": "0,1,2,3",
"UMask": "0x8",
"EventName": "SSEX_UOPS_RETIRED.SCALAR_DOUBLE",
"SampleAfterValue": "200000",
"BriefDescription": "SIMD Scalar-Double Uops retired (Precise Event)"
},
{
"PEBS": "1",
"EventCode": "0xC7",
"Counter": "0,1,2,3",
"UMask": "0x2",
"EventName": "SSEX_UOPS_RETIRED.SCALAR_SINGLE",
"SampleAfterValue": "200000",
"BriefDescription": "SIMD Scalar-Single Uops retired (Precise Event)"
},
{
"PEBS": "1",
"EventCode": "0xC7",
"Counter": "0,1,2,3",
"UMask": "0x10",
"EventName": "SSEX_UOPS_RETIRED.VECTOR_INTEGER",
"SampleAfterValue": "200000",
"BriefDescription": "SIMD Vector Integer Uops retired (Precise Event)"
},
{
"EventCode": "0xDB",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "UOP_UNFUSION",
"SampleAfterValue": "2000000",
"BriefDescription": "Uop unfusions due to FP exceptions"
},
{
"EventCode": "0xD1",
"Counter": "0,1,2,3",
"UMask": "0x4",
"EventName": "UOPS_DECODED.ESP_FOLDING",
"SampleAfterValue": "2000000",
"BriefDescription": "Stack pointer instructions decoded"
},
{
"EventCode": "0xD1",
"Counter": "0,1,2,3",
"UMask": "0x8",
"EventName": "UOPS_DECODED.ESP_SYNC",
"SampleAfterValue": "2000000",
"BriefDescription": "Stack pointer sync operations"
},
{
"EventCode": "0xD1",
"Counter": "0,1,2,3",
"UMask": "0x2",
"EventName": "UOPS_DECODED.MS_CYCLES_ACTIVE",
"SampleAfterValue": "2000000",
"BriefDescription": "Uops decoded by Microcode Sequencer",
"CounterMask": "1"
},
{
"EventCode": "0xD1",
"Invert": "1",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "UOPS_DECODED.STALL_CYCLES",
"SampleAfterValue": "2000000",
"BriefDescription": "Cycles no Uops are decoded",
"CounterMask": "1"
},
{
"EventCode": "0xB1",
"Counter": "0,1,2,3",
"UMask": "0x3f",
"AnyThread": "1",
"EventName": "UOPS_EXECUTED.CORE_ACTIVE_CYCLES",
"SampleAfterValue": "2000000",
"BriefDescription": "Cycles Uops executed on any port (core count)",
"CounterMask": "1"
},
{
"EventCode": "0xB1",
"Counter": "0,1,2,3",
"UMask": "0x1f",
"AnyThread": "1",
"EventName": "UOPS_EXECUTED.CORE_ACTIVE_CYCLES_NO_PORT5",
"SampleAfterValue": "2000000",
"BriefDescription": "Cycles Uops executed on ports 0-4 (core count)",
"CounterMask": "1"
},
{
"EventCode": "0xB1",
"Invert": "1",
"Counter": "0,1,2,3",
"UMask": "0x3f",
"AnyThread": "1",
"EventName": "UOPS_EXECUTED.CORE_STALL_COUNT",
"SampleAfterValue": "2000000",
"BriefDescription": "Uops executed on any port (core count)",
"CounterMask": "1",
"EdgeDetect": "1"
},
{
"EventCode": "0xB1",
"Invert": "1",
"Counter": "0,1,2,3",
"UMask": "0x1f",
"AnyThread": "1",
"EventName": "UOPS_EXECUTED.CORE_STALL_COUNT_NO_PORT5",
"SampleAfterValue": "2000000",
"BriefDescription": "Uops executed on ports 0-4 (core count)",
"CounterMask": "1",
"EdgeDetect": "1"
},
{
"EventCode": "0xB1",
"Invert": "1",
"Counter": "0,1,2,3",
"UMask": "0x3f",
"AnyThread": "1",
"EventName": "UOPS_EXECUTED.CORE_STALL_CYCLES",
"SampleAfterValue": "2000000",
"BriefDescription": "Cycles no Uops issued on any port (core count)",
"CounterMask": "1"
},
{
"EventCode": "0xB1",
"Invert": "1",
"Counter": "0,1,2,3",
"UMask": "0x1f",
"AnyThread": "1",
"EventName": "UOPS_EXECUTED.CORE_STALL_CYCLES_NO_PORT5",
"SampleAfterValue": "2000000",
"BriefDescription": "Cycles no Uops issued on ports 0-4 (core count)",
"CounterMask": "1"
},
{
"EventCode": "0xB1",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "UOPS_EXECUTED.PORT0",
"SampleAfterValue": "2000000",
"BriefDescription": "Uops executed on port 0"
},
{
"EventCode": "0xB1",
"Counter": "0,1,2,3",
"UMask": "0x40",
"EventName": "UOPS_EXECUTED.PORT015",
"SampleAfterValue": "2000000",
"BriefDescription": "Uops issued on ports 0, 1 or 5"
},
{
"EventCode": "0xB1",
"Invert": "1",
"Counter": "0,1,2,3",
"UMask": "0x40",
"EventName": "UOPS_EXECUTED.PORT015_STALL_CYCLES",
"SampleAfterValue": "2000000",
"BriefDescription": "Cycles no Uops issued on ports 0, 1 or 5",
"CounterMask": "1"
},
{
"EventCode": "0xB1",
"Counter": "0,1,2,3",
"UMask": "0x2",
"EventName": "UOPS_EXECUTED.PORT1",
"SampleAfterValue": "2000000",
"BriefDescription": "Uops executed on port 1"
},
{
"EventCode": "0xB1",
"Counter": "0,1,2,3",
"UMask": "0x4",
"AnyThread": "1",
"EventName": "UOPS_EXECUTED.PORT2_CORE",
"SampleAfterValue": "2000000",
"BriefDescription": "Uops executed on port 2 (core count)"
},
{
"EventCode": "0xB1",
"Counter": "0,1,2,3",
"UMask": "0x80",
"AnyThread": "1",
"EventName": "UOPS_EXECUTED.PORT234_CORE",
"SampleAfterValue": "2000000",
"BriefDescription": "Uops issued on ports 2, 3 or 4"
},
{
"EventCode": "0xB1",
"Counter": "0,1,2,3",
"UMask": "0x8",
"AnyThread": "1",
"EventName": "UOPS_EXECUTED.PORT3_CORE",
"SampleAfterValue": "2000000",
"BriefDescription": "Uops executed on port 3 (core count)"
},
{
"EventCode": "0xB1",
"Counter": "0,1,2,3",
"UMask": "0x10",
"AnyThread": "1",
"EventName": "UOPS_EXECUTED.PORT4_CORE",
"SampleAfterValue": "2000000",
"BriefDescription": "Uops executed on port 4 (core count)"
},
{
"EventCode": "0xB1",
"Counter": "0,1,2,3",
"UMask": "0x20",
"EventName": "UOPS_EXECUTED.PORT5",
"SampleAfterValue": "2000000",
"BriefDescription": "Uops executed on port 5"
},
{
"EventCode": "0xE",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "UOPS_ISSUED.ANY",
"SampleAfterValue": "2000000",
"BriefDescription": "Uops issued"
},
{
"EventCode": "0xE",
"Invert": "1",
"Counter": "0,1,2,3",
"UMask": "0x1",
"AnyThread": "1",
"EventName": "UOPS_ISSUED.CORE_STALL_CYCLES",
"SampleAfterValue": "2000000",
"BriefDescription": "Cycles no Uops were issued on any thread",
"CounterMask": "1"
},
{
"EventCode": "0xE",
"Counter": "0,1,2,3",
"UMask": "0x1",
"AnyThread": "1",
"EventName": "UOPS_ISSUED.CYCLES_ALL_THREADS",
"SampleAfterValue": "2000000",
"BriefDescription": "Cycles Uops were issued on either thread",
"CounterMask": "1"
},
{
"EventCode": "0xE",
"Counter": "0,1,2,3",
"UMask": "0x2",
"EventName": "UOPS_ISSUED.FUSED",
"SampleAfterValue": "2000000",
"BriefDescription": "Fused Uops issued"
},
{
"EventCode": "0xE",
"Invert": "1",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "UOPS_ISSUED.STALL_CYCLES",
"SampleAfterValue": "2000000",
"BriefDescription": "Cycles no Uops were issued",
"CounterMask": "1"
},
{
"PEBS": "1",
"EventCode": "0xC2",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "UOPS_RETIRED.ACTIVE_CYCLES",
"SampleAfterValue": "2000000",
"BriefDescription": "Cycles Uops are being retired",
"CounterMask": "1"
},
{
"PEBS": "1",
"EventCode": "0xC2",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "UOPS_RETIRED.ANY",
"SampleAfterValue": "2000000",
"BriefDescription": "Uops retired (Precise Event)"
},
{
"PEBS": "1",
"EventCode": "0xC2",
"Counter": "0,1,2,3",
"UMask": "0x4",
"EventName": "UOPS_RETIRED.MACRO_FUSED",
"SampleAfterValue": "2000000",
"BriefDescription": "Macro-fused Uops retired (Precise Event)"
},
{
"PEBS": "1",
"EventCode": "0xC2",
"Counter": "0,1,2,3",
"UMask": "0x2",
"EventName": "UOPS_RETIRED.RETIRE_SLOTS",
"SampleAfterValue": "2000000",
"BriefDescription": "Retirement slots used (Precise Event)"
},
{
"PEBS": "1",
"EventCode": "0xC2",
"Invert": "1",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "UOPS_RETIRED.STALL_CYCLES",
"SampleAfterValue": "2000000",
"BriefDescription": "Cycles Uops are not retiring (Precise Event)",
"CounterMask": "1"
},
{
"PEBS": "1",
"EventCode": "0xC2",
"Invert": "1",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "UOPS_RETIRED.TOTAL_CYCLES",
"SampleAfterValue": "2000000",
"BriefDescription": "Total cycles using precise uop retired event (Precise Event)",
"CounterMask": "16"
},
{
"PEBS": "2",
"EventCode": "0xC0",
"Invert": "1",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "INST_RETIRED.TOTAL_CYCLES_PS",
"SampleAfterValue": "2000000",
"BriefDescription": "Total cycles (Precise Event)",
"CounterMask": "16"
}
]
\ No newline at end of file
tools/perf/pmu-events/arch/x86/westmereep-sp/virtual-memory.json 0 → 100644
View file @ 01dd2545
[
{
"EventCode": "0x8",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "DTLB_LOAD_MISSES.ANY",
"SampleAfterValue": "200000",
"BriefDescription": "DTLB load misses"
},
{
"EventCode": "0x8",
"Counter": "0,1,2,3",
"UMask": "0x20",
"EventName": "DTLB_LOAD_MISSES.PDE_MISS",
"SampleAfterValue": "200000",
"BriefDescription": "DTLB load miss caused by low part of address"
},
{
"EventCode": "0x8",
"Counter": "0,1,2,3",
"UMask": "0x10",
"EventName": "DTLB_LOAD_MISSES.STLB_HIT",
"SampleAfterValue": "2000000",
"BriefDescription": "DTLB second level hit"
},
{
"EventCode": "0x8",
"Counter": "0,1,2,3",
"UMask": "0x2",
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",
"SampleAfterValue": "200000",
"BriefDescription": "DTLB load miss page walks complete"
},
{
"EventCode": "0x8",
"Counter": "0,1,2,3",
"UMask": "0x4",
"EventName": "DTLB_LOAD_MISSES.WALK_CYCLES",
"SampleAfterValue": "200000",
"BriefDescription": "DTLB load miss page walk cycles"
},
{
"EventCode": "0x49",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "DTLB_MISSES.ANY",
"SampleAfterValue": "200000",
"BriefDescription": "DTLB misses"
},
{
"EventCode": "0x49",
"Counter": "0,1,2,3",
"UMask": "0x80",
"EventName": "DTLB_MISSES.LARGE_WALK_COMPLETED",
"SampleAfterValue": "200000",
"BriefDescription": "DTLB miss large page walks"
},
{
"EventCode": "0x49",
"Counter": "0,1,2,3",
"UMask": "0x10",
"EventName": "DTLB_MISSES.STLB_HIT",
"SampleAfterValue": "200000",
"BriefDescription": "DTLB first level misses but second level hit"
},
{
"EventCode": "0x49",
"Counter": "0,1,2,3",
"UMask": "0x2",
"EventName": "DTLB_MISSES.WALK_COMPLETED",
"SampleAfterValue": "200000",
"BriefDescription": "DTLB miss page walks"
},
{
"EventCode": "0x49",
"Counter": "0,1,2,3",
"UMask": "0x4",
"EventName": "DTLB_MISSES.WALK_CYCLES",
"SampleAfterValue": "2000000",
"BriefDescription": "DTLB miss page walk cycles"
},
{
"EventCode": "0x4F",
"Counter": "0,1,2,3",
"UMask": "0x10",
"EventName": "EPT.WALK_CYCLES",
"SampleAfterValue": "2000000",
"BriefDescription": "Extended Page Table walk cycles"
},
{
"EventCode": "0xAE",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "ITLB_FLUSH",
"SampleAfterValue": "2000000",
"BriefDescription": "ITLB flushes"
},
{
"PEBS": "1",
"EventCode": "0xC8",
"Counter": "0,1,2,3",
"UMask": "0x20",
"EventName": "ITLB_MISS_RETIRED",
"SampleAfterValue": "200000",
"BriefDescription": "Retired instructions that missed the ITLB (Precise Event)"
},
{
"EventCode": "0x85",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "ITLB_MISSES.ANY",
"SampleAfterValue": "200000",
"BriefDescription": "ITLB miss"
},
{
"EventCode": "0x85",
"Counter": "0,1,2,3",
"UMask": "0x2",
"EventName": "ITLB_MISSES.WALK_COMPLETED",
"SampleAfterValue": "200000",
"BriefDescription": "ITLB miss page walks"
},
{
"EventCode": "0x85",
"Counter": "0,1,2,3",
"UMask": "0x4",
"EventName": "ITLB_MISSES.WALK_CYCLES",
"SampleAfterValue": "2000000",
"BriefDescription": "ITLB miss page walk cycles"
},
{
"PEBS": "1",
"EventCode": "0xCB",
"Counter": "0,1,2,3",
"UMask": "0x80",
"EventName": "MEM_LOAD_RETIRED.DTLB_MISS",
"SampleAfterValue": "200000",
"BriefDescription": "Retired loads that miss the DTLB (Precise Event)"
},
{
"PEBS": "1",
"EventCode": "0xC",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "MEM_STORE_RETIRED.DTLB_MISS",
"SampleAfterValue": "200000",
"BriefDescription": "Retired stores that miss the DTLB (Precise Event)"
}
]
\ No newline at end of file
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