Commit 044034ef authored by Peng Fan's avatar Peng Fan Committed by Abel Vesa

clk: imx: clk-fracn-gppll: fix mfd value

According to spec:
A value of 0 is disallowed and should not be programmed in this register

Fix to 1.

Fixes: 1b26cb8a ("clk: imx: support fracn gppll")
Signed-off-by: default avatarPeng Fan <peng.fan@nxp.com>
Reviewed-by: default avatarJacky Bai <ping.bai@nxp.com>
Reviewed-by: default avatarAbel Vesa <abel.vesa@linaro.org>
Link: https://lore.kernel.org/r/20220609132902.3504651-5-peng.fan@oss.nxp.comSigned-off-by: default avatarAbel Vesa <abel.vesa@linaro.org>
parent ebb4f1eb
...@@ -64,10 +64,10 @@ struct clk_fracn_gppll { ...@@ -64,10 +64,10 @@ struct clk_fracn_gppll {
* Fout = Fvco / (rdiv * odiv) * Fout = Fvco / (rdiv * odiv)
*/ */
static const struct imx_fracn_gppll_rate_table fracn_tbl[] = { static const struct imx_fracn_gppll_rate_table fracn_tbl[] = {
PLL_FRACN_GP(650000000U, 81, 0, 0, 0, 3), PLL_FRACN_GP(650000000U, 81, 0, 1, 0, 3),
PLL_FRACN_GP(594000000U, 198, 0, 0, 0, 8), PLL_FRACN_GP(594000000U, 198, 0, 1, 0, 8),
PLL_FRACN_GP(560000000U, 70, 0, 0, 0, 3), PLL_FRACN_GP(560000000U, 70, 0, 1, 0, 3),
PLL_FRACN_GP(400000000U, 50, 0, 0, 0, 3), PLL_FRACN_GP(400000000U, 50, 0, 1, 0, 3),
PLL_FRACN_GP(393216000U, 81, 92, 100, 0, 5) PLL_FRACN_GP(393216000U, 81, 92, 100, 0, 5)
}; };
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment