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Commit 04a94bab authored by Linus Torvalds's avatar Linus Torvalds
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Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cooloney/blackfin-2.6 

* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cooloney/blackfin-2.6: (24 commits)
  [Blackfin] arch: import defines for BF547 -- it is just like the BF548, but no CAN
  [Blackfin] arch: fix build fails only include header files when enabled
  [Blackfin] arch: declare default INSTALL_PATH for Blackfin ports
  [Blackfin] arch: Encourage users to use the spidev character driver: Provide platform support
  [Blackfin] arch: Enable UART2 and UART3 for bf548
  [Blackfin] arch: Enable NET2272 on BF561-EZkit - remove request_mem_region
  [Blackfin] arch:Fix BUG [#3876] pfbutton test for BTN3 on bf533 don't show complete info
  [Blackfin] arch: remove duplicated definitions of the line discipline numbers N_* in asm-blackfin/termios.h
  [Blackfin] arch: fix building with mtd uclinux by putting the mtd_phys option into the function it actually gets used in
  [Blackfin] arch: simpler header and update dates
  [Blackfin] arch: move the init sections to the end of memory
  [Blackfin] arch: change the trace buffer control start/stop logic in the exception handlers
  [Blackfin] arch: fix typo in printk message
  [Blackfin] arch: this is an ezkit, not a stamp, so fixup the init function name
  [Blackfin] arch: add slightly better help text for CPLB_INFO
  [Blackfin] arch: Fix BUG - Enable ISP1362 driver to work ok with BF561
  [Blackfin] arch: Fix header file information
  [Blackfin] arch: Add Support for ISP1362
  [Blackfin] arch: add support for cmdline partitioning to the BF533-STAMP flash map driver and enable it as a module by default
  [Blackfin] arch: hook up set_irq_wake in Blackfin's irq code
  ...
parents 765cdb6c 920e526f
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arch/blackfin/Kconfig
View file @ 04a94bab
......@@ -544,7 +544,7 @@ config EXCPT_IRQ_SYSC_L1
default y
help
If enabled, the entire ASM lowlevel exception and interrupt entry code
(STORE/RESTORE CONTEXT) is linked into L1 instruction memory.
(STORE/RESTORE CONTEXT) is linked into L1 instruction memory.
(less latency)
config DO_IRQ_L1
......@@ -904,29 +904,38 @@ config ARCH_SUSPEND_POSSIBLE
depends on !SMP
choice
prompt "Select PM Wakeup Event Source"
default PM_WAKEUP_GPIO_BY_SIC_IWR
prompt "Default Power Saving Mode"
depends on PM
help
If you have a GPIO already configured as input with the corresponding PORTx_MASK
bit set - "Specify Wakeup Event by SIC_IWR value"
default PM_BFIN_SLEEP_DEEPER
config PM_BFIN_SLEEP_DEEPER
bool "Sleep Deeper"
help
Sleep "Deeper" Mode (High Power Savings) - This mode reduces dynamic
power dissipation by disabling the clock to the processor core (CCLK).
Furthermore, Standby sets the internal power supply voltage (VDDINT)
to 0.85 V to provide the greatest power savings, while preserving the
processor state.
The PLL and system clock (SCLK) continue to operate at a very low
frequency of about 3.3 MHz. To preserve data integrity in the SDRAM,
the SDRAM is put into Self Refresh Mode. Typically an external event
such as GPIO interrupt or RTC activity wakes up the processor.
Various Peripherals such as UART, SPORT, PPI may not function as
normal during Sleep Deeper, due to the reduced SCLK frequency.
When in the sleep mode, system DMA access to L1 memory is not supported.
config PM_BFIN_SLEEP
bool "Sleep"
help
Sleep Mode (High Power Savings) - The sleep mode reduces power
dissipation by disabling the clock to the processor core (CCLK).
The PLL and system clock (SCLK), however, continue to operate in
this mode. Typically an external event or RTC activity will wake
up the processor. When in the sleep mode,
system DMA access to L1 memory is not supported.
endchoice
config PM_WAKEUP_GPIO_BY_SIC_IWR
bool "Specify Wakeup Event by SIC_IWR value"
config PM_WAKEUP_BY_GPIO
bool "Cause Wakeup Event by GPIO"
config PM_WAKEUP_GPIO_API
bool "Configure Wakeup Event by PM GPIO API"
endchoice
config PM_WAKEUP_SIC_IWR
hex "Wakeup Events (SIC_IWR)"
depends on PM_WAKEUP_GPIO_BY_SIC_IWR
default 0x8 if (BF537 || BF536 || BF534)
default 0x80 if (BF533 || BF532 || BF531)
default 0x80 if (BF54x)
default 0x80 if (BF52x)
config PM_WAKEUP_GPIO_NUMBER
int "Wakeup GPIO number"
......
arch/blackfin/Kconfig.debug
View file @ 04a94bab
......@@ -164,7 +164,7 @@ config DUAL_CORE_TEST_MODULE
config CPLB_INFO
bool "Display the CPLB information"
help
Display the CPLB information.
Display the CPLB information via /proc/cplbinfo.
config ACCESS_CHECK
bool "Check the user pointer address"
......
arch/blackfin/Makefile
View file @ 04a94bab
......@@ -119,6 +119,7 @@ archclean:
$(Q)$(MAKE) $(clean)=$(boot)
INSTALL_PATH ?= /tftpboot
boot := arch/$(ARCH)/boot
BOOT_TARGETS = vmImage
PHONY += $(BOOT_TARGETS) install
......
arch/blackfin/configs/BF533-STAMP_defconfig
View file @ 04a94bab
......@@ -216,8 +216,6 @@ CONFIG_MEM_SIZE=128
CONFIG_MEM_ADD_WIDTH=11
CONFIG_ENET_FLASH_PIN=0
CONFIG_BOOT_LOAD=0x1000
CONFIG_BFIN_SCRATCH_REG_RETN=y
# CONFIG_BFIN_SCRATCH_REG_RETE is not set
# CONFIG_BFIN_SCRATCH_REG_CYCLES is not set
......@@ -483,7 +481,7 @@ CONFIG_MTD=y
# CONFIG_MTD_CONCAT is not set
CONFIG_MTD_PARTITIONS=y
# CONFIG_MTD_REDBOOT_PARTS is not set
# CONFIG_MTD_CMDLINE_PARTS is not set
CONFIG_MTD_CMDLINE_PARTS=y
#
# User Modules And Translation Layers
......@@ -500,8 +498,8 @@ CONFIG_MTD_BLOCK=y
#
# RAM/ROM/Flash chip drivers
#
# CONFIG_MTD_CFI is not set
CONFIG_MTD_JEDECPROBE=m
CONFIG_MTD_CFI=m
# CONFIG_MTD_JEDECPROBE is not set
CONFIG_MTD_GEN_PROBE=m
# CONFIG_MTD_CFI_ADV_OPTIONS is not set
CONFIG_MTD_MAP_BANK_WIDTH_1=y
......@@ -515,8 +513,9 @@ CONFIG_MTD_CFI_I2=y
# CONFIG_MTD_CFI_I4 is not set
# CONFIG_MTD_CFI_I8 is not set
# CONFIG_MTD_CFI_INTELEXT is not set
# CONFIG_MTD_CFI_AMDSTD is not set
CONFIG_MTD_CFI_AMDSTD=m
# CONFIG_MTD_CFI_STAA is not set
CONFIG_MTD_CFI_UTIL=m
CONFIG_MTD_RAM=y
CONFIG_MTD_ROM=m
# CONFIG_MTD_ABSENT is not set
......@@ -526,6 +525,11 @@ CONFIG_MTD_ROM=m
#
CONFIG_MTD_COMPLEX_MAPPINGS=y
# CONFIG_MTD_PHYSMAP is not set
CONFIG_MTD_BF5xx=m
CONFIG_BFIN_FLASH_BANK_0=0x7BB0
CONFIG_BFIN_FLASH_BANK_1=0x7BB0
CONFIG_BFIN_FLASH_BANK_2=0x7BB0
CONFIG_BFIN_FLASH_BANK_3=0x7BB0
# CONFIG_MTD_UCLINUX is not set
# CONFIG_MTD_PLATRAM is not set
......
arch/blackfin/kernel/bfin_dma_5xx.c
View file @ 04a94bab
......@@ -104,6 +104,16 @@ int request_dma(unsigned int channel, char *device_id)
mutex_unlock(&(dma_ch[channel].dmalock));
#ifdef CONFIG_BF54x
if (channel >= CH_UART2_RX && channel <= CH_UART3_TX &&
strncmp(device_id, "BFIN_UART", 9) == 0)
dma_ch[channel].regs->peripheral_map |=
(channel - CH_UART2_RX + 0xC);
else
dma_ch[channel].regs->peripheral_map |=
(channel - CH_UART2_RX + 0x6);
#endif
dma_ch[channel].device_id = device_id;
dma_ch[channel].irq_callback = NULL;
......
arch/blackfin/kernel/bfin_gpio.c
View file @ 04a94bab
......@@ -186,7 +186,7 @@ static struct str_ident {
char name[RESOURCE_LABEL_SIZE];
} str_ident[MAX_RESOURCES];
#ifdef CONFIG_PM
#if defined(CONFIG_PM) && !defined(CONFIG_BF54x)
static unsigned short wakeup_map[gpio_bank(MAX_BLACKFIN_GPIOS)];
static unsigned char wakeup_flags_map[MAX_BLACKFIN_GPIOS];
static struct gpio_port_s gpio_bank_saved[gpio_bank(MAX_BLACKFIN_GPIOS)];
......@@ -696,9 +696,8 @@ static int bfin_gpio_wakeup_type(unsigned gpio, unsigned char type)
return 0;
}
u32 gpio_pm_setup(void)
u32 bfin_pm_setup(void)
{
u32 sic_iwr = 0;
u16 bank, mask, i, gpio;
for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE) {
......@@ -723,7 +722,8 @@ u32 gpio_pm_setup(void)
gpio = i;
while (mask) {
if (mask & 1) {
if ((mask & 1) && (wakeup_flags_map[gpio] !=
PM_WAKE_IGNORE)) {
reserved_gpio_map[gpio_bank(gpio)] |=
gpio_bit(gpio);
bfin_gpio_wakeup_type(gpio,
......@@ -734,21 +734,17 @@ u32 gpio_pm_setup(void)
mask >>= 1;
}
sic_iwr |= 1 <<
(sic_iwr_irqs[bank] - (IRQ_CORETMR + 1));
bfin_internal_set_wake(sic_iwr_irqs[bank], 1);
gpio_bankb[bank]->maskb_set = wakeup_map[gpio_bank(i)];
}
}
AWA_DUMMY_READ(maskb_set);
if (sic_iwr)
return sic_iwr;
else
return IWR_ENABLE_ALL;
return 0;
}
void gpio_pm_restore(void)
void bfin_pm_restore(void)
{
u16 bank, mask, i;
......@@ -768,7 +764,7 @@ void gpio_pm_restore(void)
reserved_gpio_map[bank] =
gpio_bank_saved[bank].reserved;
bfin_internal_set_wake(sic_iwr_irqs[bank], 0);
}
gpio_bankb[bank]->maskb = gpio_bank_saved[bank].maskb;
......
arch/blackfin/kernel/cplb-mpu/cplbinit.c
View file @ 04a94bab
......@@ -26,6 +26,10 @@
#include <asm/cplb.h>
#include <asm/cplbinit.h>
#if ANOMALY_05000263
# error the MPU will not function safely while Anomaly 05000263 applies
#endif
struct cplb_entry icplb_tbl[MAX_CPLBS];
struct cplb_entry dcplb_tbl[MAX_CPLBS];
......
arch/blackfin/kernel/init_task.c
View file @ 04a94bab
......@@ -57,5 +57,5 @@ EXPORT_SYMBOL(init_task);
* "init_task" linker map entry.
*/
union thread_union init_thread_union
__attribute__ ((__section__(".data.init_task"))) = {
__attribute__ ((__section__(".init_task.data"))) = {
INIT_THREAD_INFO(init_task)};
arch/blackfin/kernel/setup.c
View file @ 04a94bab
/*
* File: arch/blackfin/kernel/setup.c
* Based on:
* Author:
* arch/blackfin/kernel/setup.c
*
* Created:
* Description:
* Copyright 2004-2006 Analog Devices Inc.
*
* Modified:
* Copyright 2004-2006 Analog Devices Inc.
* Enter bugs at http://blackfin.uclinux.org/
*
* Bugs: Enter bugs at http://blackfin.uclinux.org/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, see the file COPYING, or write
* to the Free Software Foundation, Inc.,
* 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
* Licensed under the GPL-2 or later.
*/
#include <linux/delay.h>
......@@ -34,6 +15,7 @@
#include <linux/cpu.h>
#include <linux/module.h>
#include <linux/tty.h>
#include <linux/pfn.h>
#include <linux/ext2_fs.h>
#include <linux/cramfs_fs.h>
......@@ -47,6 +29,8 @@
#include <asm/fixed_code.h>
#include <asm/early_printk.h>
static DEFINE_PER_CPU(struct cpu, cpu_devices);
u16 _bfin_swrst;
unsigned long memory_start, memory_end, physical_mem_end;
......@@ -67,6 +51,29 @@ EXPORT_SYMBOL(mtd_size);
char __initdata command_line[COMMAND_LINE_SIZE];
/* boot memmap, for parsing "memmap=" */
#define BFIN_MEMMAP_MAX 128 /* number of entries in bfin_memmap */
#define BFIN_MEMMAP_RAM 1
#define BFIN_MEMMAP_RESERVED 2
struct bfin_memmap {
int nr_map;
struct bfin_memmap_entry {
unsigned long long addr; /* start of memory segment */
unsigned long long size;
unsigned long type;
} map[BFIN_MEMMAP_MAX];
} bfin_memmap __initdata;
/* for memmap sanitization */
struct change_member {
struct bfin_memmap_entry *pentry; /* pointer to original entry */
unsigned long long addr; /* address for this change point */
};
static struct change_member change_point_list[2*BFIN_MEMMAP_MAX] __initdata;
static struct change_member *change_point[2*BFIN_MEMMAP_MAX] __initdata;
static struct bfin_memmap_entry *overlap_list[BFIN_MEMMAP_MAX] __initdata;
static struct bfin_memmap_entry new_map[BFIN_MEMMAP_MAX] __initdata;
void __init bf53x_cache_init(void)
{
#if defined(CONFIG_BFIN_DCACHE) || defined(CONFIG_BFIN_ICACHE)
......@@ -123,12 +130,224 @@ void __init bf53x_relocate_l1_mem(void)
}
/* add_memory_region to memmap */
static void __init add_memory_region(unsigned long long start,
unsigned long long size, int type)
{
int i;
i = bfin_memmap.nr_map;
if (i == BFIN_MEMMAP_MAX) {
printk(KERN_ERR "Ooops! Too many entries in the memory map!\n");
return;
}
bfin_memmap.map[i].addr = start;
bfin_memmap.map[i].size = size;
bfin_memmap.map[i].type = type;
bfin_memmap.nr_map++;
}
/*
* Sanitize the boot memmap, removing overlaps.
*/
static int __init sanitize_memmap(struct bfin_memmap_entry *map, int *pnr_map)
{
struct change_member *change_tmp;
unsigned long current_type, last_type;
unsigned long long last_addr;
int chgidx, still_changing;
int overlap_entries;
int new_entry;
int old_nr, new_nr, chg_nr;
int i;
/*
Visually we're performing the following (1,2,3,4 = memory types)
Sample memory map (w/overlaps):
____22__________________
______________________4_
____1111________________
_44_____________________
11111111________________
____________________33__
___________44___________
__________33333_________
______________22________
___________________2222_
_________111111111______
_____________________11_
_________________4______
Sanitized equivalent (no overlap):
1_______________________
_44_____________________
___1____________________
____22__________________
______11________________
_________1______________
__________3_____________
___________44___________
_____________33_________
_______________2________
________________1_______
_________________4______
___________________2____
____________________33__
______________________4_
*/
/* if there's only one memory region, don't bother */
if (*pnr_map < 2)
return -1;
old_nr = *pnr_map;
/* bail out if we find any unreasonable addresses in memmap */
for (i = 0; i < old_nr; i++)
if (map[i].addr + map[i].size < map[i].addr)
return -1;
/* create pointers for initial change-point information (for sorting) */
for (i = 0; i < 2*old_nr; i++)
change_point[i] = &change_point_list[i];
/* record all known change-points (starting and ending addresses),
omitting those that are for empty memory regions */
chgidx = 0;
for (i = 0; i < old_nr; i++) {
if (map[i].size != 0) {
change_point[chgidx]->addr = map[i].addr;
change_point[chgidx++]->pentry = &map[i];
change_point[chgidx]->addr = map[i].addr + map[i].size;
change_point[chgidx++]->pentry = &map[i];
}
}
chg_nr = chgidx; /* true number of change-points */
/* sort change-point list by memory addresses (low -> high) */
still_changing = 1;
while (still_changing) {
still_changing = 0;
for (i = 1; i < chg_nr; i++) {
/* if <current_addr> > <last_addr>, swap */
/* or, if current=<start_addr> & last=<end_addr>, swap */
if ((change_point[i]->addr < change_point[i-1]->addr) ||
((change_point[i]->addr == change_point[i-1]->addr) &&
(change_point[i]->addr == change_point[i]->pentry->addr) &&
(change_point[i-1]->addr != change_point[i-1]->pentry->addr))
) {
change_tmp = change_point[i];
change_point[i] = change_point[i-1];
change_point[i-1] = change_tmp;
still_changing = 1;
}
}
}
/* create a new memmap, removing overlaps */
overlap_entries = 0; /* number of entries in the overlap table */
new_entry = 0; /* index for creating new memmap entries */
last_type = 0; /* start with undefined memory type */
last_addr = 0; /* start with 0 as last starting address */
/* loop through change-points, determining affect on the new memmap */
for (chgidx = 0; chgidx < chg_nr; chgidx++) {
/* keep track of all overlapping memmap entries */
if (change_point[chgidx]->addr == change_point[chgidx]->pentry->addr) {
/* add map entry to overlap list (> 1 entry implies an overlap) */
overlap_list[overlap_entries++] = change_point[chgidx]->pentry;
} else {
/* remove entry from list (order independent, so swap with last) */
for (i = 0; i < overlap_entries; i++) {
if (overlap_list[i] == change_point[chgidx]->pentry)
overlap_list[i] = overlap_list[overlap_entries-1];
}
overlap_entries--;
}
/* if there are overlapping entries, decide which "type" to use */
/* (larger value takes precedence -- 1=usable, 2,3,4,4+=unusable) */
current_type = 0;
for (i = 0; i < overlap_entries; i++)
if (overlap_list[i]->type > current_type)
current_type = overlap_list[i]->type;
/* continue building up new memmap based on this information */
if (current_type != last_type) {
if (last_type != 0) {
new_map[new_entry].size =
change_point[chgidx]->addr - last_addr;
/* move forward only if the new size was non-zero */
if (new_map[new_entry].size != 0)
if (++new_entry >= BFIN_MEMMAP_MAX)
break; /* no more space left for new entries */
}
if (current_type != 0) {
new_map[new_entry].addr = change_point[chgidx]->addr;
new_map[new_entry].type = current_type;
last_addr = change_point[chgidx]->addr;
}
last_type = current_type;
}
}
new_nr = new_entry; /* retain count for new entries */
/* copy new mapping into original location */
memcpy(map, new_map, new_nr*sizeof(struct bfin_memmap_entry));
*pnr_map = new_nr;
return 0;
}
static void __init print_memory_map(char *who)
{
int i;
for (i = 0; i < bfin_memmap.nr_map; i++) {
printk(KERN_DEBUG " %s: %016Lx - %016Lx ", who,
bfin_memmap.map[i].addr,
bfin_memmap.map[i].addr + bfin_memmap.map[i].size);
switch (bfin_memmap.map[i].type) {
case BFIN_MEMMAP_RAM:
printk("(usable)\n");
break;
case BFIN_MEMMAP_RESERVED:
printk("(reserved)\n");
break;
default: printk("type %lu\n", bfin_memmap.map[i].type);
break;
}
}
}
static __init int parse_memmap(char *arg)
{
unsigned long long start_at, mem_size;
if (!arg)
return -EINVAL;
mem_size = memparse(arg, &arg);
if (*arg == '@') {
start_at = memparse(arg+1, &arg);
add_memory_region(start_at, mem_size, BFIN_MEMMAP_RAM);
} else if (*arg == '$') {
start_at = memparse(arg+1, &arg);
add_memory_region(start_at, mem_size, BFIN_MEMMAP_RESERVED);
}
return 0;
}
/*
* Initial parsing of the command line. Currently, we support:
* - Controlling the linux memory size: mem=xxx[KMG]
* - Controlling the physical memory size: max_mem=xxx[KMG][$][#]
* $ -> reserved memory is dcacheable
* # -> reserved memory is icacheable
* - "memmap=XXX[KkmM][@][$]XXX[KkmM]" defines a memory region
* @ from <start> to <start>+<mem>, type RAM
* $ from <start> to <start>+<mem>, type RESERVED
*
*/
static __init void parse_cmdline_early(char *cmdline_p)
{
......@@ -136,7 +355,6 @@ static __init void parse_cmdline_early(char *cmdline_p)
unsigned int memsize;
for (;;) {
if (c == ' ') {
if (!memcmp(to, "mem=", 4)) {
to += 4;
memsize = memparse(to, &to);
......@@ -162,6 +380,9 @@ static __init void parse_cmdline_early(char *cmdline_p)
} else if (!memcmp(to, "earlyprintk=", 12)) {
to += 12;
setup_early_printk(to);
} else if (!memcmp(to, "memmap=", 7)) {
to += 7;
parse_memmap(to);
}
}
c = *(to++);
......@@ -170,75 +391,36 @@ static __init void parse_cmdline_early(char *cmdline_p)
}
}
void __init setup_arch(char **cmdline_p)
/*
* Setup memory defaults from user config.
* The physical memory layout looks like:
*
* [_rambase, _ramstart]: kernel image
* [memory_start, memory_end]: dynamic memory managed by kernel
* [memory_end, _ramend]: reserved memory
* [meory_mtd_start(memory_end),
* memory_mtd_start + mtd_size]: rootfs (if any)
* [_ramend - DMA_UNCACHED_REGION,
* _ramend]: uncached DMA region
* [_ramend, physical_mem_end]: memory not managed by kernel
*
*/
static __init void memory_setup(void)
{
int bootmap_size;
unsigned long l1_length, sclk, cclk;
#ifdef CONFIG_MTD_UCLINUX
unsigned long mtd_phys = 0;
#endif
#ifdef CONFIG_DUMMY_CONSOLE
conswitchp = &dummy_con;
#endif
#if defined(CONFIG_CMDLINE_BOOL)
strncpy(&command_line[0], CONFIG_CMDLINE, sizeof(command_line));
command_line[sizeof(command_line) - 1] = 0;
#endif
/* Keep a copy of command line */
*cmdline_p = &command_line[0];
memcpy(boot_command_line, command_line, COMMAND_LINE_SIZE);
boot_command_line[COMMAND_LINE_SIZE - 1] = '\0';
/* setup memory defaults from the user config */
physical_mem_end = 0;
_ramend = CONFIG_MEM_SIZE * 1024 * 1024;
parse_cmdline_early(&command_line[0]);
cclk = get_cclk();
sclk = get_sclk();
#if !defined(CONFIG_BFIN_KERNEL_CLOCK)
if (ANOMALY_05000273 && cclk == sclk)
panic("ANOMALY 05000273, SCLK can not be same as CCLK");
#endif
_rambase = (unsigned long)_stext;
_ramstart = (unsigned long)_end;
#ifdef BF561_FAMILY
if (ANOMALY_05000266) {
bfin_read_IMDMA_D0_IRQ_STATUS();
bfin_read_IMDMA_D1_IRQ_STATUS();
if (DMA_UNCACHED_REGION > (_ramend - _ramstart)) {
console_init();
panic("DMA region exceeds memory limit: %lu.\n",
_ramend - _ramstart);
}
#endif
printk(KERN_INFO "Hardware Trace ");
if (bfin_read_TBUFCTL() & 0x1 )
printk("Active ");
else
printk("Off ");
if (bfin_read_TBUFCTL() & 0x2)
printk("and Enabled\n");
else
printk("and Disabled\n");
#if defined(CONFIG_CHR_DEV_FLASH) || defined(CONFIG_BLK_DEV_FLASH)
/* we need to initialize the Flashrom device here since we might
* do things with flash early on in the boot
*/
flash_probe();
#endif
if (physical_mem_end == 0)
physical_mem_end = _ramend;
/* by now the stack is part of the init task */
memory_end = _ramend - DMA_UNCACHED_REGION;
_ramstart = (unsigned long)__bss_stop;
_rambase = (unsigned long)_stext;
#ifdef CONFIG_MPU
/* Round up to multiple of 4MB. */
memory_start = (_ramstart + 0x3fffff) & ~0x3fffff;
......@@ -292,7 +474,7 @@ void __init setup_arch(char **cmdline_p)
}
/* Relocate MTD image to the top of memory after the uncached memory area */
dma_memcpy((char *)memory_end, __bss_stop, mtd_size);
dma_memcpy((char *)memory_end, _end, mtd_size);
memory_mtd_start = memory_end;
_ebss = memory_mtd_start; /* define _ebss for compatible */
......@@ -319,13 +501,175 @@ void __init setup_arch(char **cmdline_p)
#endif
#if !defined(CONFIG_MTD_UCLINUX)
memory_end -= SIZE_4K; /*In case there is no valid CPLB behind memory_end make sure we don't get to close*/
/*In case there is no valid CPLB behind memory_end make sure we don't get to close*/
memory_end -= SIZE_4K;
#endif
init_mm.start_code = (unsigned long)_stext;
init_mm.end_code = (unsigned long)_etext;
init_mm.end_data = (unsigned long)_edata;
init_mm.brk = (unsigned long)0;
printk(KERN_INFO "Board Memory: %ldMB\n", physical_mem_end >> 20);
printk(KERN_INFO "Kernel Managed Memory: %ldMB\n", _ramend >> 20);
printk(KERN_INFO "Memory map:\n"
KERN_INFO " text = 0x%p-0x%p\n"
KERN_INFO " rodata = 0x%p-0x%p\n"
KERN_INFO " bss = 0x%p-0x%p\n"
KERN_INFO " data = 0x%p-0x%p\n"
KERN_INFO " stack = 0x%p-0x%p\n"
KERN_INFO " init = 0x%p-0x%p\n"
KERN_INFO " available = 0x%p-0x%p\n"
#ifdef CONFIG_MTD_UCLINUX
KERN_INFO " rootfs = 0x%p-0x%p\n"
#endif
#if DMA_UNCACHED_REGION > 0
KERN_INFO " DMA Zone = 0x%p-0x%p\n"
#endif
, _stext, _etext,
__start_rodata, __end_rodata,
__bss_start, __bss_stop,
_sdata, _edata,
(void *)&init_thread_union,
(void *)((int)(&init_thread_union) + 0x2000),
__init_begin, __init_end,
(void *)_ramstart, (void *)memory_end
#ifdef CONFIG_MTD_UCLINUX
, (void *)memory_mtd_start, (void *)(memory_mtd_start + mtd_size)
#endif
#if DMA_UNCACHED_REGION > 0
, (void *)(_ramend - DMA_UNCACHED_REGION), (void *)(_ramend)
#endif
);
}
static __init void setup_bootmem_allocator(void)
{
int bootmap_size;
int i;
unsigned long min_pfn, max_pfn;
unsigned long curr_pfn, last_pfn, size;
/* mark memory between memory_start and memory_end usable */
add_memory_region(memory_start,
memory_end - memory_start, BFIN_MEMMAP_RAM);
/* sanity check for overlap */
sanitize_memmap(bfin_memmap.map, &bfin_memmap.nr_map);
print_memory_map("boot memmap");
min_pfn = PAGE_OFFSET >> PAGE_SHIFT;
max_pfn = memory_end >> PAGE_SHIFT;
/*
* give all the memory to the bootmap allocator, tell it to put the
* boot mem_map at the start of memory.
*/
bootmap_size = init_bootmem_node(NODE_DATA(0),
memory_start >> PAGE_SHIFT, /* map goes here */
min_pfn, max_pfn);
/* register the memmap regions with the bootmem allocator */
for (i = 0; i < bfin_memmap.nr_map; i++) {
/*
* Reserve usable memory
*/
if (bfin_memmap.map[i].type != BFIN_MEMMAP_RAM)
continue;
/*
* We are rounding up the start address of usable memory:
*/
curr_pfn = PFN_UP(bfin_memmap.map[i].addr);
if (curr_pfn >= max_pfn)
continue;
/*
* ... and at the end of the usable range downwards:
*/
last_pfn = PFN_DOWN(bfin_memmap.map[i].addr +
bfin_memmap.map[i].size);
if (last_pfn > max_pfn)
last_pfn = max_pfn;
/*
* .. finally, did all the rounding and playing
* around just make the area go away?
*/
if (last_pfn <= curr_pfn)
continue;
size = last_pfn - curr_pfn;
free_bootmem(PFN_PHYS(curr_pfn), PFN_PHYS(size));
}
/* reserve memory before memory_start, including bootmap */
reserve_bootmem(PAGE_OFFSET,
memory_start + bootmap_size + PAGE_SIZE - 1 - PAGE_OFFSET,
BOOTMEM_DEFAULT);
}
void __init setup_arch(char **cmdline_p)
{
unsigned long l1_length, sclk, cclk;
#ifdef CONFIG_DUMMY_CONSOLE
conswitchp = &dummy_con;
#endif
#if defined(CONFIG_CMDLINE_BOOL)
strncpy(&command_line[0], CONFIG_CMDLINE, sizeof(command_line));
command_line[sizeof(command_line) - 1] = 0;
#endif
/* Keep a copy of command line */
*cmdline_p = &command_line[0];
memcpy(boot_command_line, command_line, COMMAND_LINE_SIZE);
boot_command_line[COMMAND_LINE_SIZE - 1] = '\0';
/* setup memory defaults from the user config */
physical_mem_end = 0;
_ramend = CONFIG_MEM_SIZE * 1024 * 1024;
memset(&bfin_memmap, 0, sizeof(bfin_memmap));
parse_cmdline_early(&command_line[0]);
if (physical_mem_end == 0)
physical_mem_end = _ramend;
memory_setup();
cclk = get_cclk();
sclk = get_sclk();
#if !defined(CONFIG_BFIN_KERNEL_CLOCK)
if (ANOMALY_05000273 && cclk == sclk)
panic("ANOMALY 05000273, SCLK can not be same as CCLK");
#endif
#ifdef BF561_FAMILY
if (ANOMALY_05000266) {
bfin_read_IMDMA_D0_IRQ_STATUS();
bfin_read_IMDMA_D1_IRQ_STATUS();
}
#endif
printk(KERN_INFO "Hardware Trace ");
if (bfin_read_TBUFCTL() & 0x1)
printk("Active ");
else
printk("Off ");
if (bfin_read_TBUFCTL() & 0x2)
printk("and Enabled\n");
else
printk("and Disabled\n");
#if defined(CONFIG_CHR_DEV_FLASH) || defined(CONFIG_BLK_DEV_FLASH)
/* we need to initialize the Flashrom device here since we might
* do things with flash early on in the boot
*/
flash_probe();
#endif
_bfin_swrst = bfin_read_SWRST();
if (_bfin_swrst & RESET_DOUBLE)
......@@ -335,7 +679,7 @@ void __init setup_arch(char **cmdline_p)
else if (_bfin_swrst & RESET_SOFTWARE)
printk(KERN_NOTICE "Reset caused by Software reset\n");
printk(KERN_INFO "Blackfin support (C) 2004-2007 Analog Devices, Inc.\n");
printk(KERN_INFO "Blackfin support (C) 2004-2008 Analog Devices, Inc.\n");
if (bfin_compiled_revid() == 0xffff)
printk(KERN_INFO "Compiled for ADSP-%s Rev any\n", CPU);
else if (bfin_compiled_revid() == -1)
......@@ -361,55 +705,8 @@ void __init setup_arch(char **cmdline_p)
if (ANOMALY_05000273 && (cclk >> 1) <= sclk)
printk("\n\n\nANOMALY_05000273: CCLK must be >= 2*SCLK !!!\n\n\n");
printk(KERN_INFO "Board Memory: %ldMB\n", physical_mem_end >> 20);
printk(KERN_INFO "Kernel Managed Memory: %ldMB\n", _ramend >> 20);
printk(KERN_INFO "Memory map:\n"
KERN_INFO " text = 0x%p-0x%p\n"
KERN_INFO " rodata = 0x%p-0x%p\n"
KERN_INFO " data = 0x%p-0x%p\n"
KERN_INFO " stack = 0x%p-0x%p\n"
KERN_INFO " init = 0x%p-0x%p\n"
KERN_INFO " bss = 0x%p-0x%p\n"
KERN_INFO " available = 0x%p-0x%p\n"
#ifdef CONFIG_MTD_UCLINUX
KERN_INFO " rootfs = 0x%p-0x%p\n"
#endif
#if DMA_UNCACHED_REGION > 0
KERN_INFO " DMA Zone = 0x%p-0x%p\n"
#endif
, _stext, _etext,
__start_rodata, __end_rodata,
_sdata, _edata,
(void *)&init_thread_union, (void *)((int)(&init_thread_union) + 0x2000),
__init_begin, __init_end,
__bss_start, __bss_stop,
(void *)_ramstart, (void *)memory_end
#ifdef CONFIG_MTD_UCLINUX
, (void *)memory_mtd_start, (void *)(memory_mtd_start + mtd_size)
#endif
#if DMA_UNCACHED_REGION > 0
, (void *)(_ramend - DMA_UNCACHED_REGION), (void *)(_ramend)
#endif
);
setup_bootmem_allocator();
/*
* give all the memory to the bootmap allocator, tell it to put the
* boot mem_map at the start of memory
*/
bootmap_size = init_bootmem_node(NODE_DATA(0), memory_start >> PAGE_SHIFT, /* map goes here */
PAGE_OFFSET >> PAGE_SHIFT,
memory_end >> PAGE_SHIFT);
/*
* free the usable memory, we have to make sure we do not free
* the bootmem bitmap so we then reserve it after freeing it :-)
*/
free_bootmem(memory_start, memory_end - memory_start);
reserve_bootmem(memory_start, bootmap_size, BOOTMEM_DEFAULT);
/*
* get kmalloc into gear
*/
paging_init();
/* check the size of the l1 area */
......@@ -450,15 +747,15 @@ void __init setup_arch(char **cmdline_p)
static int __init topology_init(void)
{
#if defined (CONFIG_BF561)
static struct cpu cpu[2];
register_cpu(&cpu[0], 0);
register_cpu(&cpu[1], 1);
int cpu;
for_each_possible_cpu(cpu) {
struct cpu *c = &per_cpu(cpu_devices, cpu);
register_cpu(c, cpu);
}
return 0;
#else
static struct cpu cpu[1];
return register_cpu(cpu, 0);
#endif
}
subsys_initcall(topology_init);
......
arch/blackfin/kernel/traps.c
View file @ 04a94bab
......@@ -649,7 +649,7 @@ void dump_bfin_process(struct pt_regs *fp)
if (context & 0x0020 && (fp->seqstat & SEQSTAT_EXCAUSE) == VEC_HWERR)
printk(KERN_NOTICE "HW Error context\n");
else if (context & 0x0020)
printk(KERN_NOTICE "Defered Exception context\n");
printk(KERN_NOTICE "Deferred Exception context\n");
else if (context & 0x3FC0)
printk(KERN_NOTICE "Interrupt context\n");
else if (context & 0x4000)
......
arch/blackfin/kernel/vmlinux.lds.S
View file @ 04a94bab
......@@ -41,6 +41,9 @@ _jiffies = _jiffies_64;
SECTIONS
{
. = CONFIG_BOOT_LOAD;
/* Neither the text, ro_data or bss section need to be aligned
* So pack them back to back
*/
.text :
{
__text = .;
......@@ -58,22 +61,25 @@ SECTIONS
*(__ex_table)
___stop___ex_table = .;
. = ALIGN(4);
__etext = .;
}
RO_DATA(PAGE_SIZE)
/* Just in case the first read only is a 32-bit access */
RO_DATA(4)
.bss :
{
. = ALIGN(4);
___bss_start = .;
*(.bss .bss.*)
*(COMMON)
___bss_stop = .;
}
.data :
{
/* make sure the init_task is aligned to the
* kernel thread size so we can locate the kernel
* stack properly and quickly.
*/
__sdata = .;
. = ALIGN(THREAD_SIZE);
*(.data.init_task)
/* This gets done first, so the glob doesn't suck it in */
. = ALIGN(32);
*(.data.cacheline_aligned)
......@@ -81,10 +87,22 @@ SECTIONS
*(.data.*)
CONSTRUCTORS
/* make sure the init_task is aligned to the
* kernel thread size so we can locate the kernel
* stack properly and quickly.
*/
. = ALIGN(THREAD_SIZE);
*(.init_task.data)
__edata = .;
}
/* The init section should be last, so when we free it, it goes into
* the general memory pool, and (hopefully) will decrease fragmentation
* a tiny bit. The init section has a _requirement_ that it be
* PAGE_SIZE aligned
*/
. = ALIGN(PAGE_SIZE);
___init_begin = .;
.init.text :
......@@ -179,16 +197,7 @@ SECTIONS
. = ALIGN(PAGE_SIZE);
___init_end = .;
.bss :
{
. = ALIGN(4);
___bss_start = .;
*(.bss .bss.*)
*(COMMON)
. = ALIGN(4);
___bss_stop = .;
__end = .;
}
__end =.;
STABS_DEBUG
......
arch/blackfin/mach-bf527/boards/ezkit.c
View file @ 04a94bab
......@@ -41,7 +41,9 @@
#include <linux/irq.h>
#include <linux/interrupt.h>
#include <linux/usb/sl811.h>
#if defined(CONFIG_USB_MUSB_HDRC) || defined(CONFIG_USB_MUSB_HDRC_MODULE)
#include <linux/usb/musb.h>
#endif
#include <asm/cplb.h>
#include <asm/dma.h>
#include <asm/bfin5xx_spi.h>
......@@ -517,6 +519,14 @@ static struct bfin5xx_spi_chip spi_wm8731_chip_info = {
.bits_per_word = 16,
};
#endif
#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
static struct bfin5xx_spi_chip spidev_chip_info = {
.enable_dma = 0,
.bits_per_word = 8,
};
#endif
static struct spi_board_info bfin_spi_board_info[] __initdata = {
#if defined(CONFIG_MTD_M25P80) \
|| defined(CONFIG_MTD_M25P80_MODULE)
......@@ -634,6 +644,15 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
.mode = SPI_MODE_0,
},
#endif
#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
{
.modalias = "spidev",
.max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
.bus_num = 0,
.chip_select = 1,
.controller_data = &spidev_chip_info,
},
#endif
};
/* SPI controller data */
......
arch/blackfin/mach-bf533/boards/ezkit.c
View file @ 04a94bab
......@@ -34,7 +34,9 @@
#include <linux/mtd/partitions.h>
#include <linux/spi/spi.h>
#include <linux/spi/flash.h>
#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
#include <linux/usb/isp1362.h>
#endif
#include <linux/ata_platform.h>
#include <linux/irq.h>
#include <asm/dma.h>
......@@ -134,6 +136,13 @@ static struct bfin5xx_spi_chip ad1836_spi_chip_info = {
};
#endif
#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
static struct bfin5xx_spi_chip spidev_chip_info = {
.enable_dma = 0,
.bits_per_word = 8,
};
#endif
static struct spi_board_info bfin_spi_board_info[] __initdata = {
#if defined(CONFIG_MTD_M25P80) || defined(CONFIG_MTD_M25P80_MODULE)
{
......@@ -168,6 +177,15 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
.controller_data = &ad1836_spi_chip_info,
},
#endif
#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
{
.modalias = "spidev",
.max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
.bus_num = 0,
.chip_select = 1,
.controller_data = &spidev_chip_info,
},
#endif
};
/* SPI (0) */
......
arch/blackfin/mach-bf533/boards/stamp.c
View file @ 04a94bab
......@@ -226,6 +226,13 @@ static struct bfin5xx_spi_chip spi_mmc_chip_info = {
};
#endif
#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
static struct bfin5xx_spi_chip spidev_chip_info = {
.enable_dma = 0,
.bits_per_word = 8,
};
#endif
static struct spi_board_info bfin_spi_board_info[] __initdata = {
#if defined(CONFIG_MTD_M25P80) || defined(CONFIG_MTD_M25P80_MODULE)
{
......@@ -312,6 +319,15 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
.mode = SPI_MODE_2,
},
#endif
#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
{
.modalias = "spidev",
.max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
.bus_num = 0,
.chip_select = 1,
.controller_data = &spidev_chip_info,
},
#endif
};
/* SPI (0) */
......@@ -423,9 +439,9 @@ static struct platform_device bfin_pata_device = {
#include <linux/gpio_keys.h>
static struct gpio_keys_button bfin_gpio_keys_table[] = {
{BTN_0, GPIO_PF5, 1, "gpio-keys: BTN0"},
{BTN_1, GPIO_PF6, 1, "gpio-keys: BTN1"},
{BTN_2, GPIO_PF8, 1, "gpio-keys: BTN2"},
{BTN_0, GPIO_PF5, 0, "gpio-keys: BTN0"},
{BTN_1, GPIO_PF6, 0, "gpio-keys: BTN1"},
{BTN_2, GPIO_PF8, 0, "gpio-keys: BTN2"},
};
static struct gpio_keys_platform_data bfin_gpio_keys_data = {
......
arch/blackfin/mach-bf537/boards/stamp.c
View file @ 04a94bab
......@@ -487,6 +487,13 @@ static const struct ad7877_platform_data bfin_ad7877_ts_info = {
};
#endif
#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
static struct bfin5xx_spi_chip spidev_chip_info = {
.enable_dma = 0,
.bits_per_word = 8,
};
#endif
static struct spi_board_info bfin_spi_board_info[] __initdata = {
#if defined(CONFIG_MTD_M25P80) \
|| defined(CONFIG_MTD_M25P80_MODULE)
......@@ -593,6 +600,15 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
.controller_data = &spi_ad7877_chip_info,
},
#endif
#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
{
.modalias = "spidev",
.max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
.bus_num = 0,
.chip_select = 1,
.controller_data = &spidev_chip_info,
},
#endif
};
/* SPI controller data */
......
arch/blackfin/mach-bf548/boards/ezkit.c
View file @ 04a94bab
......@@ -37,7 +37,9 @@
#include <linux/spi/flash.h>
#include <linux/irq.h>
#include <linux/interrupt.h>
#if defined(CONFIG_USB_MUSB_HDRC) || defined(CONFIG_USB_MUSB_HDRC_MODULE)
#include <linux/usb/musb.h>
#endif
#include <asm/bfin5xx_spi.h>
#include <asm/cplb.h>
#include <asm/dma.h>
......@@ -420,6 +422,13 @@ static const struct ad7877_platform_data bfin_ad7877_ts_info = {
};
#endif
#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
static struct bfin5xx_spi_chip spidev_chip_info = {
.enable_dma = 0,
.bits_per_word = 8,
};
#endif
static struct spi_board_info bf54x_spi_board_info[] __initdata = {
#if defined(CONFIG_MTD_M25P80) \
|| defined(CONFIG_MTD_M25P80_MODULE)
......@@ -445,6 +454,15 @@ static struct spi_board_info bf54x_spi_board_info[] __initdata = {
.controller_data = &spi_ad7877_chip_info,
},
#endif
#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
{
.modalias = "spidev",
.max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
.bus_num = 0,
.chip_select = 1,
.controller_data = &spidev_chip_info,
},
#endif
};
/* SPI (0) */
......@@ -631,7 +649,7 @@ static struct platform_device *ezkit_devices[] __initdata = {
&ezkit_flash_device,
};
static int __init stamp_init(void)
static int __init ezkit_init(void)
{
printk(KERN_INFO "%s(): registering device resources\n", __FUNCTION__);
platform_add_devices(ezkit_devices, ARRAY_SIZE(ezkit_devices));
......@@ -644,4 +662,4 @@ static int __init stamp_init(void)
return 0;
}
arch_initcall(stamp_init);
arch_initcall(ezkit_init);
arch/blackfin/mach-bf548/dma.c
View file @ 04a94bab
/*
* File: arch/blackfin/mach-bf561/dma.c
* File: arch/blackfin/mach-bf548/dma.c
* Based on:
* Author:
*
......@@ -7,7 +7,7 @@
* Description: This file contains the simple DMA Implementation for Blackfin
*
* Modified:
* Copyright 2004-2007 Analog Devices Inc.
* Copyright 2004-2008 Analog Devices Inc.
*
* Bugs: Enter bugs at http://blackfin.uclinux.org/
*
......
arch/blackfin/mach-bf561/boards/ezkit.c
View file @ 04a94bab
......@@ -92,6 +92,68 @@ void __exit bfin_isp1761_exit(void)
arch_initcall(bfin_isp1761_init);
#endif
#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
#include <linux/usb/isp1362.h>
static struct resource isp1362_hcd_resources[] = {
{
.start = 0x2c060000,
.end = 0x2c060000,
.flags = IORESOURCE_MEM,
}, {
.start = 0x2c060004,
.end = 0x2c060004,
.flags = IORESOURCE_MEM,
}, {
.start = IRQ_PF8,
.end = IRQ_PF8,
.flags = IORESOURCE_IRQ,
},
};
static struct isp1362_platform_data isp1362_priv = {
.sel15Kres = 1,
.clknotstop = 0,
.oc_enable = 0,
.int_act_high = 0,
.int_edge_triggered = 0,
.remote_wakeup_connected = 0,
.no_power_switching = 1,
.power_switching_mode = 0,
};
static struct platform_device isp1362_hcd_device = {
.name = "isp1362-hcd",
.id = 0,
.dev = {
.platform_data = &isp1362_priv,
},
.num_resources = ARRAY_SIZE(isp1362_hcd_resources),
.resource = isp1362_hcd_resources,
};
#endif
#if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE)
static struct resource net2272_bfin_resources[] = {
{
.start = 0x2C000000,
.end = 0x2C000000 + 0x7F,
.flags = IORESOURCE_MEM,
}, {
.start = IRQ_PF10,
.end = IRQ_PF10,
.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
},
};
static struct platform_device net2272_bfin_device = {
.name = "net2272",
.id = -1,
.num_resources = ARRAY_SIZE(net2272_bfin_resources),
.resource = net2272_bfin_resources,
};
#endif
/*
* USB-LAN EzExtender board
* Driver needs to know address, irq and flag pin.
......@@ -204,6 +266,13 @@ static struct bfin5xx_spi_chip ad1836_spi_chip_info = {
.bits_per_word = 16,
};
#endif
#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
static struct bfin5xx_spi_chip spidev_chip_info = {
.enable_dma = 0,
.bits_per_word = 8,
};
#endif
#endif
/* SPI (0) */
......@@ -248,6 +317,15 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
.controller_data = &ad1836_spi_chip_info,
},
#endif
#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
{
.modalias = "spidev",
.max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
.bus_num = 0,
.chip_select = 1,
.controller_data = &spidev_chip_info,
},
#endif
};
#if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE)
......@@ -340,6 +418,10 @@ static struct platform_device *ezkit_devices[] __initdata = {
&ax88180_device,
#endif
#if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE)
&net2272_bfin_device,
#endif
#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
&bfin_spi0_device,
#endif
......@@ -359,6 +441,11 @@ static struct platform_device *ezkit_devices[] __initdata = {
#if defined(CONFIG_I2C_GPIO) || defined(CONFIG_I2C_GPIO_MODULE)
&i2c_gpio_device,
#endif
#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
&isp1362_hcd_device,
#endif
&ezkit_flash_device,
};
......
arch/blackfin/mach-common/Makefile
View file @ 04a94bab
......@@ -4,8 +4,6 @@
obj-y := \
cache.o cacheinit.o entry.o \
interrupt.o lock.o irqpanic.o arch_checks.o
interrupt.o lock.o irqpanic.o arch_checks.o ints-priority.o
obj-$(CONFIG_BFIN_SINGLE_CORE) += ints-priority-sc.o
obj-$(CONFIG_BFIN_DUAL_CORE) += ints-priority-dc.o
obj-$(CONFIG_PM) += pm.o dpmc.o
arch/blackfin/mach-common/dpmc.S
View file @ 04a94bab
......@@ -191,6 +191,9 @@ ENTRY(_sleep_mode)
call _test_pll_locked;
R0 = IWR_ENABLE(0);
R1 = IWR_DISABLE_ALL;
R2 = IWR_DISABLE_ALL;
call _set_sic_iwr;
P0.H = hi(PLL_CTL);
......@@ -237,6 +240,10 @@ ENTRY(_deep_sleep)
CLI R4;
R0 = IWR_ENABLE(0);
R1 = IWR_DISABLE_ALL;
R2 = IWR_DISABLE_ALL;
call _set_sic_iwr;
call _set_dram_srfs;
......@@ -261,6 +268,9 @@ ENTRY(_deep_sleep)
call _test_pll_locked;
R0 = IWR_ENABLE(0);
R1 = IWR_DISABLE_ALL;
R2 = IWR_DISABLE_ALL;
call _set_sic_iwr;
P0.H = hi(PLL_CTL);
......@@ -286,7 +296,13 @@ ENTRY(_sleep_deeper)
CLI R4;
P3 = R0;
P4 = R1;
P5 = R2;
R0 = IWR_ENABLE(0);
R1 = IWR_DISABLE_ALL;
R2 = IWR_DISABLE_ALL;
call _set_sic_iwr;
call _set_dram_srfs; /* Set SDRAM Self Refresh */
......@@ -327,6 +343,8 @@ ENTRY(_sleep_deeper)
call _test_pll_locked;
R0 = P3;
R1 = P4;
R3 = P5;
call _set_sic_iwr; /* Set Awake from IDLE */
P0.H = hi(PLL_CTL);
......@@ -340,6 +358,9 @@ ENTRY(_sleep_deeper)
call _test_pll_locked;
R0 = IWR_ENABLE(0);
R1 = IWR_DISABLE_ALL;
R2 = IWR_DISABLE_ALL;
call _set_sic_iwr; /* Set Awake from IDLE PLL */
P0.H = hi(VR_CTL);
......@@ -417,14 +438,23 @@ ENTRY(_unset_dram_srfs)
RTS;
ENTRY(_set_sic_iwr)
#if defined(CONFIG_BF54x) || defined(CONFIG_BF52x)
#if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561)
P0.H = hi(SIC_IWR0);
P0.L = lo(SIC_IWR0);
P1.H = hi(SIC_IWR1);
P1.L = lo(SIC_IWR1);
[P1] = R1;
#if defined(CONFIG_BF54x)
P1.H = hi(SIC_IWR2);
P1.L = lo(SIC_IWR2);
[P1] = R2;
#endif
#else
P0.H = hi(SIC_IWR);
P0.L = lo(SIC_IWR);
#endif
[P0] = R0;
SSYNC;
RTS;
......
arch/blackfin/mach-common/entry.S
View file @ 04a94bab
......@@ -121,6 +121,7 @@ ENTRY(_ex_icplb_miss)
(R7:6,P5:4) = [sp++];
ASTAT = [sp++];
SAVE_ALL_SYS
DEBUG_HWTRACE_SAVE(p5, r7)
#ifdef CONFIG_MPU
R0 = SEQSTAT;
R1 = SP;
......@@ -132,14 +133,13 @@ ENTRY(_ex_icplb_miss)
#else
call __cplb_hdr;
#endif
DEBUG_START_HWTRACE(p5, r7)
DEBUG_HWTRACE_RESTORE(p5, r7)
RESTORE_ALL_SYS
SP = EX_SCRATCH_REG;
rtx;
ENDPROC(_ex_icplb_miss)
ENTRY(_ex_syscall)
DEBUG_START_HWTRACE(p5, r7)
(R7:6,P5:4) = [sp++];
ASTAT = [sp++];
raise 15; /* invoked by TRAP #0, for sys call */
......@@ -178,7 +178,6 @@ ENTRY(_ex_single_step)
ENDPROC(_ex_single_step)
ENTRY(_bfin_return_from_exception)
DEBUG_START_HWTRACE(p5, r7)
#if ANOMALY_05000257
R7=LC0;
LC0=R7;
......@@ -200,10 +199,9 @@ ENTRY(_handle_bad_cplb)
* need to make a CPLB exception look like a normal exception
*/
DEBUG_START_HWTRACE(p5, r7)
RESTORE_ALL_SYS
[--sp] = ASTAT;
[--sp] = (R7:6, P5:4);
[--sp] = (R7:6,P5:4);
ENTRY(_ex_replaceable)
nop;
......@@ -253,7 +251,6 @@ ENTRY(_ex_trap_c)
R6 = SEQSTAT;
[P5] = R6;
DEBUG_START_HWTRACE(p5, r7)
(R7:6,P5:4) = [sp++];
ASTAT = [sp++];
SP = EX_SCRATCH_REG;
......@@ -382,8 +379,7 @@ ENTRY(_trap) /* Exception: 4th entry into system event table(supervisor mode)*/
sp.h = _exception_stack_top;
/* Try to deal with syscalls quickly. */
[--sp] = ASTAT;
[--sp] = (R7:6, P5:4);
DEBUG_STOP_HWTRACE(p5, r7)
[--sp] = (R7:6,P5:4);
r7 = SEQSTAT; /* reason code is in bit 5:0 */
r6.l = lo(SEQSTAT_EXCAUSE);
r6.h = hi(SEQSTAT_EXCAUSE);
......
arch/blackfin/mach-common/ints-priority-dc.c deleted 100644 → 0
View file @ 765cdb6c
/*
* File: arch/blackfin/mach-common/ints-priority-dc.c
* Based on:
* Author:
*
* Created: ?
* Description: Set up the interrupt priorities
*
* Modified:
* 1996 Roman Zippel
* 1999 D. Jeff Dionne <jeff@uclinux.org>
* 2000-2001 Lineo, Inc. D. Jefff Dionne <jeff@lineo.ca>
* 2002 Arcturus Networks Inc. MaTed <mated@sympatico.ca>
* 2003 Metrowerks/Motorola
* 2003 Bas Vermeulen <bas@buyways.nl>
* Copyright 2004-2006 Analog Devices Inc.
*
* Bugs: Enter bugs at http://blackfin.uclinux.org/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, see the file COPYING, or write
* to the Free Software Foundation, Inc.,
* 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <linux/module.h>
#include <linux/kernel_stat.h>
#include <linux/seq_file.h>
#include <linux/irq.h>
#ifdef CONFIG_KGDB
#include <linux/kgdb.h>
#endif
#include <asm/traps.h>
#include <asm/blackfin.h>
#include <asm/gpio.h>
#include <asm/irq_handler.h>
/*
* NOTES:
* - we have separated the physical Hardware interrupt from the
* levels that the LINUX kernel sees (see the description in irq.h)
* -
*/
/* Initialize this to an actual value to force it into the .data
* section so that we know it is properly initialized at entry into
* the kernel but before bss is initialized to zero (which is where
* it would live otherwise). The 0x1f magic represents the IRQs we
* cannot actually mask out in hardware.
*/
unsigned long irq_flags = 0x1f;
/* The number of spurious interrupts */
atomic_t num_spurious;
struct ivgx {
/* irq number for request_irq, available in mach-bf561/irq.h */
int irqno;
/* corresponding bit in the SICA_ISR0 register */
int isrflag0;
/* corresponding bit in the SICA_ISR1 register */
int isrflag1;
} ivg_table[NR_PERI_INTS];
struct ivg_slice {
/* position of first irq in ivg_table for given ivg */
struct ivgx *ifirst;
struct ivgx *istop;
} ivg7_13[IVG13 - IVG7 + 1];
static void search_IAR(void);
/*
* Search SIC_IAR and fill tables with the irqvalues
* and their positions in the SIC_ISR register.
*/
static void __init search_IAR(void)
{
unsigned ivg, irq_pos = 0;
for (ivg = 0; ivg <= IVG13 - IVG7; ivg++) {
int irqn;
ivg7_13[ivg].istop = ivg7_13[ivg].ifirst = &ivg_table[irq_pos];
for (irqn = 0; irqn < NR_PERI_INTS; irqn++) {
int iar_shift = (irqn & 7) * 4;
if (ivg ==
(0xf &
bfin_read32((unsigned long *)SICA_IAR0 +
(irqn >> 3)) >> iar_shift)) {
ivg_table[irq_pos].irqno = IVG7 + irqn;
ivg_table[irq_pos].isrflag0 =
(irqn < 32 ? (1 << irqn) : 0);
ivg_table[irq_pos].isrflag1 =
(irqn < 32 ? 0 : (1 << (irqn - 32)));
ivg7_13[ivg].istop++;
irq_pos++;
}
}
}
}
/*
* This is for BF561 internal IRQs
*/
static void ack_noop(unsigned int irq)
{
/* Dummy function. */
}
static void bf561_core_mask_irq(unsigned int irq)
{
irq_flags &= ~(1 << irq);
if (!irqs_disabled())
local_irq_enable();
}
static void bf561_core_unmask_irq(unsigned int irq)
{
irq_flags |= 1 << irq;
/*
* If interrupts are enabled, IMASK must contain the same value
* as irq_flags. Make sure that invariant holds. If interrupts
* are currently disabled we need not do anything; one of the
* callers will take care of setting IMASK to the proper value
* when reenabling interrupts.
* local_irq_enable just does "STI irq_flags", so it's exactly
* what we need.
*/
if (!irqs_disabled())
local_irq_enable();
return;
}
static void bf561_internal_mask_irq(unsigned int irq)
{
unsigned long irq_mask;
if ((irq - (IRQ_CORETMR + 1)) < 32) {
irq_mask = (1 << (irq - (IRQ_CORETMR + 1)));
bfin_write_SICA_IMASK0(bfin_read_SICA_IMASK0() & ~irq_mask);
} else {
irq_mask = (1 << (irq - (IRQ_CORETMR + 1) - 32));
bfin_write_SICA_IMASK1(bfin_read_SICA_IMASK1() & ~irq_mask);
}
}
static void bf561_internal_unmask_irq(unsigned int irq)
{
unsigned long irq_mask;
if ((irq - (IRQ_CORETMR + 1)) < 32) {
irq_mask = (1 << (irq - (IRQ_CORETMR + 1)));
bfin_write_SICA_IMASK0(bfin_read_SICA_IMASK0() | irq_mask);
} else {
irq_mask = (1 << (irq - (IRQ_CORETMR + 1) - 32));
bfin_write_SICA_IMASK1(bfin_read_SICA_IMASK1() | irq_mask);
}
SSYNC();
}
static struct irq_chip bf561_core_irqchip = {
.ack = ack_noop,
.mask = bf561_core_mask_irq,
.unmask = bf561_core_unmask_irq,
};
static struct irq_chip bf561_internal_irqchip = {
.ack = ack_noop,
.mask = bf561_internal_mask_irq,
.unmask = bf561_internal_unmask_irq,
};
static unsigned short gpio_enabled[gpio_bank(MAX_BLACKFIN_GPIOS)];
static unsigned short gpio_edge_triggered[gpio_bank(MAX_BLACKFIN_GPIOS)];
static void bf561_gpio_ack_irq(unsigned int irq)
{
u16 gpionr = irq - IRQ_PF0;
if (gpio_edge_triggered[gpio_bank(gpionr)] & gpio_bit(gpionr)) {
set_gpio_data(gpionr, 0);
SSYNC();
}
}
static void bf561_gpio_mask_ack_irq(unsigned int irq)
{
u16 gpionr = irq - IRQ_PF0;
if (gpio_edge_triggered[gpio_bank(gpionr)] & gpio_bit(gpionr)) {
set_gpio_data(gpionr, 0);
SSYNC();
}
set_gpio_maska(gpionr, 0);
SSYNC();
}
static void bf561_gpio_mask_irq(unsigned int irq)
{
set_gpio_maska(irq - IRQ_PF0, 0);
SSYNC();
}
static void bf561_gpio_unmask_irq(unsigned int irq)
{
set_gpio_maska(irq - IRQ_PF0, 1);
SSYNC();
}
static unsigned int bf561_gpio_irq_startup(unsigned int irq)
{
unsigned int ret;
char buf[8];
u16 gpionr = irq - IRQ_PF0;
if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))) {
snprintf(buf, sizeof buf, "IRQ %d", irq);
ret = gpio_request(gpionr, buf);
if (ret)
return ret;
}
gpio_enabled[gpio_bank(gpionr)] |= gpio_bit(gpionr);
bf561_gpio_unmask_irq(irq);
return ret;
}
static void bf561_gpio_irq_shutdown(unsigned int irq)
{
bf561_gpio_mask_irq(irq);
gpio_free(irq - IRQ_PF0);
gpio_enabled[gpio_bank(irq - IRQ_PF0)] &= ~gpio_bit(irq - IRQ_PF0);
}
static int bf561_gpio_irq_type(unsigned int irq, unsigned int type)
{
unsigned int ret;
char buf[8];
u16 gpionr = irq - IRQ_PF0;
if (type == IRQ_TYPE_PROBE) {
/* only probe unenabled GPIO interrupt lines */
if (gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))
return 0;
type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
}
if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING |
IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))) {
snprintf(buf, sizeof buf, "IRQ %d", irq);
ret = gpio_request(gpionr, buf);
if (ret)
return ret;
}
gpio_enabled[gpio_bank(gpionr)] |= gpio_bit(gpionr);
} else {
gpio_enabled[gpio_bank(gpionr)] &= ~gpio_bit(gpionr);
return 0;
}
set_gpio_dir(gpionr, 0);
set_gpio_inen(gpionr, 1);
if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
gpio_edge_triggered[gpio_bank(gpionr)] |= gpio_bit(gpionr);
set_gpio_edge(gpionr, 1);
} else {
set_gpio_edge(gpionr, 0);
gpio_edge_triggered[gpio_bank(gpionr)] &= ~gpio_bit(gpionr);
}
if ((type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
== (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
set_gpio_both(gpionr, 1);
else
set_gpio_both(gpionr, 0);
if ((type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW)))
set_gpio_polar(gpionr, 1); /* low or falling edge denoted by one */
else
set_gpio_polar(gpionr, 0); /* high or rising edge denoted by zero */
SSYNC();
if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
set_irq_handler(irq, handle_edge_irq);
else
set_irq_handler(irq, handle_level_irq);
return 0;
}
static struct irq_chip bf561_gpio_irqchip = {
.ack = bf561_gpio_ack_irq,
.mask = bf561_gpio_mask_irq,
.mask_ack = bf561_gpio_mask_ack_irq,
.unmask = bf561_gpio_unmask_irq,
.set_type = bf561_gpio_irq_type,
.startup = bf561_gpio_irq_startup,
.shutdown = bf561_gpio_irq_shutdown
};
static void bf561_demux_gpio_irq(unsigned int inta_irq,
struct irq_desc *intb_desc)
{
int irq, flag_d, mask;
u16 gpio;
switch (inta_irq) {
case IRQ_PROG0_INTA:
irq = IRQ_PF0;
break;
case IRQ_PROG1_INTA:
irq = IRQ_PF16;
break;
case IRQ_PROG2_INTA:
irq = IRQ_PF32;
break;
default:
dump_stack();
return;
}
gpio = irq - IRQ_PF0;
flag_d = get_gpiop_data(gpio);
mask = flag_d & (gpio_enabled[gpio_bank(gpio)] &
get_gpiop_maska(gpio));
do {
if (mask & 1) {
struct irq_desc *desc = irq_desc + irq;
desc->handle_irq(irq, desc);
}
irq++;
mask >>= 1;
} while (mask);
}
void __init init_exception_vectors(void)
{
SSYNC();
/* cannot program in software:
* evt0 - emulation (jtag)
* evt1 - reset
*/
bfin_write_EVT2(evt_nmi);
bfin_write_EVT3(trap);
bfin_write_EVT5(evt_ivhw);
bfin_write_EVT6(evt_timer);
bfin_write_EVT7(evt_evt7);
bfin_write_EVT8(evt_evt8);
bfin_write_EVT9(evt_evt9);
bfin_write_EVT10(evt_evt10);
bfin_write_EVT11(evt_evt11);
bfin_write_EVT12(evt_evt12);
bfin_write_EVT13(evt_evt13);
bfin_write_EVT14(evt14_softirq);
bfin_write_EVT15(evt_system_call);
CSYNC();
}
/*
* This function should be called during kernel startup to initialize
* the BFin IRQ handling routines.
*/
int __init init_arch_irq(void)
{
int irq;
unsigned long ilat = 0;
/* Disable all the peripheral intrs - page 4-29 HW Ref manual */
bfin_write_SICA_IMASK0(SIC_UNMASK_ALL);
bfin_write_SICA_IMASK1(SIC_UNMASK_ALL);
SSYNC();
bfin_write_SICA_IWR0(IWR_ENABLE_ALL);
bfin_write_SICA_IWR1(IWR_ENABLE_ALL);
local_irq_disable();
init_exception_buff();
for (irq = 0; irq <= SYS_IRQS; irq++) {
if (irq <= IRQ_CORETMR)
set_irq_chip(irq, &bf561_core_irqchip);
else
set_irq_chip(irq, &bf561_internal_irqchip);
if ((irq != IRQ_PROG0_INTA) &&
(irq != IRQ_PROG1_INTA) &&
(irq != IRQ_PROG2_INTA))
set_irq_handler(irq, handle_simple_irq);
else
set_irq_chained_handler(irq, bf561_demux_gpio_irq);
}
for (irq = IRQ_PF0; irq <= IRQ_PF47; irq++) {
set_irq_chip(irq, &bf561_gpio_irqchip);
/* if configured as edge, then will be changed to do_edge_IRQ */
set_irq_handler(irq, handle_level_irq);
}
bfin_write_IMASK(0);
CSYNC();
ilat = bfin_read_ILAT();
CSYNC();
bfin_write_ILAT(ilat);
CSYNC();
printk(KERN_INFO "Configuring Blackfin Priority Driven Interrupts\n");
/* IMASK=xxx is equivalent to STI xx or irq_flags=xx,
* local_irq_enable()
*/
program_IAR();
/* Therefore it's better to setup IARs before interrupts enabled */
search_IAR();
/* Enable interrupts IVG7-15 */
irq_flags = irq_flags | IMASK_IVG15 |
IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 |
IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW;
return 0;
}
#ifdef CONFIG_DO_IRQ_L1
__attribute__((l1_text))
#endif
void do_irq(int vec, struct pt_regs *fp)
{
if (vec == EVT_IVTMR_P) {
vec = IRQ_CORETMR;
} else {
struct ivgx *ivg = ivg7_13[vec - IVG7].ifirst;
struct ivgx *ivg_stop = ivg7_13[vec - IVG7].istop;
unsigned long sic_status0, sic_status1;
SSYNC();
sic_status0 = bfin_read_SICA_IMASK0() & bfin_read_SICA_ISR0();
sic_status1 = bfin_read_SICA_IMASK1() & bfin_read_SICA_ISR1();
for (;; ivg++) {
if (ivg >= ivg_stop) {
atomic_inc(&num_spurious);
return;
} else if ((sic_status0 & ivg->isrflag0) ||
(sic_status1 & ivg->isrflag1))
break;
}
vec = ivg->irqno;
}
asm_do_IRQ(vec, fp);
#ifdef CONFIG_KGDB
kgdb_process_breakpoint();
#endif
}
arch/blackfin/mach-common/ints-priority-sc.c → arch/blackfin/mach-common/ints-priority.c
View file @ 04a94bab
/*
* File: arch/blackfin/mach-common/ints-priority-sc.c
* File: arch/blackfin/mach-common/ints-priority.c
* Based on:
* Author:
*
......@@ -13,7 +13,7 @@
* 2002 Arcturus Networks Inc. MaTed <mated@sympatico.ca>
* 2003 Metrowerks/Motorola
* 2003 Bas Vermeulen <bas@buyways.nl>
* Copyright 2004-2007 Analog Devices Inc.
* Copyright 2004-2008 Analog Devices Inc.
*
* Bugs: Enter bugs at http://blackfin.uclinux.org/
*
......@@ -69,6 +69,10 @@ unsigned long irq_flags = 0x1f;
/* The number of spurious interrupts */
atomic_t num_spurious;
#ifdef CONFIG_PM
unsigned long bfin_sic_iwr[3]; /* Up to 3 SIC_IWRx registers */
#endif
struct ivgx {
/* irq number for request_irq, available in mach-bf533/irq.h */
unsigned int irqno;
......@@ -98,8 +102,7 @@ static void __init search_IAR(void)
for (irqn = 0; irqn < NR_PERI_INTS; irqn++) {
int iar_shift = (irqn & 7) * 4;
if (ivg ==
(0xf &
if (ivg == (0xf &
#ifndef CONFIG_BF52x
bfin_read32((unsigned long *)SIC_IAR0 +
(irqn >> 3)) >> iar_shift)) {
......@@ -179,6 +182,27 @@ static void bfin_internal_unmask_irq(unsigned int irq)
SSYNC();
}
#ifdef CONFIG_PM
int bfin_internal_set_wake(unsigned int irq, unsigned int state)
{
unsigned bank, bit;
unsigned long flags;
bank = (irq - (IRQ_CORETMR + 1)) / 32;
bit = (irq - (IRQ_CORETMR + 1)) % 32;
local_irq_save(flags);
if (state)
bfin_sic_iwr[bank] |= (1 << bit);
else
bfin_sic_iwr[bank] &= ~(1 << bit);
local_irq_restore(flags);
return 0;
}
#endif
static struct irq_chip bfin_core_irqchip = {
.ack = ack_noop,
.mask = bfin_core_mask_irq,
......@@ -189,6 +213,9 @@ static struct irq_chip bfin_internal_irqchip = {
.ack = ack_noop,
.mask = bfin_internal_mask_irq,
.unmask = bfin_internal_unmask_irq,
#ifdef CONFIG_PM
.set_wake = bfin_internal_set_wake,
#endif
};
#ifdef BF537_GENERIC_ERROR_INT_DEMUX
......@@ -206,8 +233,7 @@ static void bfin_generic_error_mask_irq(unsigned int irq)
if (!error_int_mask) {
local_irq_disable();
bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() &
~(1 <<
(IRQ_GENERIC_ERROR -
~(1 << (IRQ_GENERIC_ERROR -
(IRQ_CORETMR + 1))));
SSYNC();
local_irq_enable();
......@@ -232,7 +258,7 @@ static struct irq_chip bfin_generic_error_irqchip = {
};
static void bfin_demux_error_irq(unsigned int int_err_irq,
struct irq_desc *intb_desc)
struct irq_desc *inta_desc)
{
int irq = 0;
......@@ -404,16 +430,8 @@ static int bfin_gpio_irq_type(unsigned int irq, unsigned int type)
return 0;
}
set_gpio_inen(gpionr, 0);
set_gpio_dir(gpionr, 0);
set_gpio_inen(gpionr, 1);
if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
gpio_edge_triggered[gpio_bank(gpionr)] |= gpio_bit(gpionr);
set_gpio_edge(gpionr, 1);
} else {
set_gpio_edge(gpionr, 0);
gpio_edge_triggered[gpio_bank(gpionr)] &= ~gpio_bit(gpionr);
}
if ((type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
== (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
......@@ -426,6 +444,18 @@ static int bfin_gpio_irq_type(unsigned int irq, unsigned int type)
else
set_gpio_polar(gpionr, 0); /* high or rising edge denoted by zero */
if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
set_gpio_edge(gpionr, 1);
set_gpio_inen(gpionr, 1);
gpio_edge_triggered[gpio_bank(gpionr)] |= gpio_bit(gpionr);
set_gpio_data(gpionr, 0);
} else {
set_gpio_edge(gpionr, 0);
gpio_edge_triggered[gpio_bank(gpionr)] &= ~gpio_bit(gpionr);
set_gpio_inen(gpionr, 1);
}
SSYNC();
if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
......@@ -436,6 +466,20 @@ static int bfin_gpio_irq_type(unsigned int irq, unsigned int type)
return 0;
}
#ifdef CONFIG_PM
int bfin_gpio_set_wake(unsigned int irq, unsigned int state)
{
unsigned gpio = irq_to_gpio(irq);
if (state)
gpio_pm_wakeup_request(gpio, PM_WAKE_IGNORE);
else
gpio_pm_wakeup_free(gpio);
return 0;
}
#endif
static struct irq_chip bfin_gpio_irqchip = {
.ack = bfin_gpio_ack_irq,
.mask = bfin_gpio_mask_irq,
......@@ -443,30 +487,87 @@ static struct irq_chip bfin_gpio_irqchip = {
.unmask = bfin_gpio_unmask_irq,
.set_type = bfin_gpio_irq_type,
.startup = bfin_gpio_irq_startup,
.shutdown = bfin_gpio_irq_shutdown
.shutdown = bfin_gpio_irq_shutdown,
#ifdef CONFIG_PM
.set_wake = bfin_gpio_set_wake,
#endif
};
static void bfin_demux_gpio_irq(unsigned int intb_irq,
struct irq_desc *intb_desc)
static void bfin_demux_gpio_irq(unsigned int inta_irq,
struct irq_desc *desc)
{
u16 i;
struct irq_desc *desc;
unsigned int i, gpio, mask, irq, search = 0;
for (i = 0; i < MAX_BLACKFIN_GPIOS; i += 16) {
int irq = IRQ_PF0 + i;
int flag_d = get_gpiop_data(i);
int mask =
flag_d & (gpio_enabled[gpio_bank(i)] & get_gpiop_maska(i));
switch (inta_irq) {
#if defined(CONFIG_BF53x)
case IRQ_PROG_INTA:
irq = IRQ_PF0;
search = 1;
break;
# if defined(BF537_FAMILY) && !(defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE))
case IRQ_MAC_RX:
irq = IRQ_PH0;
break;
# endif
#elif defined(CONFIG_BF52x)
case IRQ_PORTF_INTA:
irq = IRQ_PF0;
break;
case IRQ_PORTG_INTA:
irq = IRQ_PG0;
break;
case IRQ_PORTH_INTA:
irq = IRQ_PH0;
break;
#elif defined(CONFIG_BF561)
case IRQ_PROG0_INTA:
irq = IRQ_PF0;
break;
case IRQ_PROG1_INTA:
irq = IRQ_PF16;
break;
case IRQ_PROG2_INTA:
irq = IRQ_PF32;
break;
#endif
default:
BUG();
return;
}
while (mask) {
if (mask & 1) {
desc = irq_desc + irq;
desc->handle_irq(irq, desc);
if (search) {
for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE) {
irq += i;
mask = get_gpiop_data(i) &
(gpio_enabled[gpio_bank(i)] &
get_gpiop_maska(i));
while (mask) {
if (mask & 1) {
desc = irq_desc + irq;
desc->handle_irq(irq, desc);
}
irq++;
mask >>= 1;
}
irq++;
mask >>= 1;
}
} else {
gpio = irq_to_gpio(irq);
mask = get_gpiop_data(gpio) &
(gpio_enabled[gpio_bank(gpio)] &
get_gpiop_maska(gpio));
do {
if (mask & 1) {
desc = irq_desc + irq;
desc->handle_irq(irq, desc);
}
irq++;
mask >>= 1;
} while (mask);
}
}
#else /* CONFIG_BF54x */
......@@ -711,6 +812,74 @@ static int bfin_gpio_irq_type(unsigned int irq, unsigned int type)
return 0;
}
#ifdef CONFIG_PM
u32 pint_saved_masks[NR_PINT_SYS_IRQS];
u32 pint_wakeup_masks[NR_PINT_SYS_IRQS];
int bfin_gpio_set_wake(unsigned int irq, unsigned int state)
{
u32 pint_irq;
u8 pint_val = irq2pint_lut[irq - SYS_IRQS];
u32 bank = PINT_2_BANK(pint_val);
u32 pintbit = PINT_BIT(pint_val);
switch (bank) {
case 0:
pint_irq = IRQ_PINT0;
break;
case 2:
pint_irq = IRQ_PINT2;
break;
case 3:
pint_irq = IRQ_PINT3;
break;
case 1:
pint_irq = IRQ_PINT1;
break;
default:
return -EINVAL;
}
bfin_internal_set_wake(pint_irq, state);
if (state)
pint_wakeup_masks[bank] |= pintbit;
else
pint_wakeup_masks[bank] &= ~pintbit;
return 0;
}
u32 bfin_pm_setup(void)
{
u32 val, i;
for (i = 0; i < NR_PINT_SYS_IRQS; i++) {
val = pint[i]->mask_clear;
pint_saved_masks[i] = val;
if (val ^ pint_wakeup_masks[i]) {
pint[i]->mask_clear = val;
pint[i]->mask_set = pint_wakeup_masks[i];
}
}
return 0;
}
void bfin_pm_restore(void)
{
u32 i, val;
for (i = 0; i < NR_PINT_SYS_IRQS; i++) {
val = pint_saved_masks[i];
if (val ^ pint_wakeup_masks[i]) {
pint[i]->mask_clear = pint[i]->mask_clear;
pint[i]->mask_set = val;
}
}
}
#endif
static struct irq_chip bfin_gpio_irqchip = {
.ack = bfin_gpio_ack_irq,
.mask = bfin_gpio_mask_irq,
......@@ -718,17 +887,19 @@ static struct irq_chip bfin_gpio_irqchip = {
.unmask = bfin_gpio_unmask_irq,
.set_type = bfin_gpio_irq_type,
.startup = bfin_gpio_irq_startup,
.shutdown = bfin_gpio_irq_shutdown
.shutdown = bfin_gpio_irq_shutdown,
#ifdef CONFIG_PM
.set_wake = bfin_gpio_set_wake,
#endif
};
static void bfin_demux_gpio_irq(unsigned int intb_irq,
struct irq_desc *intb_desc)
static void bfin_demux_gpio_irq(unsigned int inta_irq,
struct irq_desc *desc)
{
u8 bank, pint_val;
u32 request, irq;
struct irq_desc *desc;
switch (intb_irq) {
switch (inta_irq) {
case IRQ_PINT0:
bank = 0;
break;
......@@ -795,7 +966,7 @@ int __init init_arch_irq(void)
int irq;
unsigned long ilat = 0;
/* Disable all the peripheral intrs - page 4-29 HW Ref manual */
#if defined(CONFIG_BF54x) || defined(CONFIG_BF52x)
#if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561)
bfin_write_SIC_IMASK0(SIC_UNMASK_ALL);
bfin_write_SIC_IMASK1(SIC_UNMASK_ALL);
bfin_write_SIC_IWR0(IWR_ENABLE_ALL);
......@@ -812,6 +983,8 @@ int __init init_arch_irq(void)
local_irq_disable();
init_exception_buff();
#ifdef CONFIG_BF54x
# ifdef CONFIG_PINTx_REASSIGN
pint[0]->assign = CONFIG_PINT0_ASSIGN;
......@@ -874,6 +1047,19 @@ int __init init_arch_irq(void)
set_irq_chained_handler(irq,
bfin_demux_gpio_irq);
break;
#elif defined(CONFIG_BF561)
case IRQ_PROG0_INTA:
set_irq_chained_handler(irq,
bfin_demux_gpio_irq);
break;
case IRQ_PROG1_INTA:
set_irq_chained_handler(irq,
bfin_demux_gpio_irq);
break;
case IRQ_PROG2_INTA:
set_irq_chained_handler(irq,
bfin_demux_gpio_irq);
break;
#endif
default:
set_irq_handler(irq, handle_simple_irq);
......@@ -893,11 +1079,8 @@ int __init init_arch_irq(void)
}
#endif
#ifndef CONFIG_BF54x
for (irq = IRQ_PF0; irq < NR_IRQS; irq++) {
#else
for (irq = IRQ_PA0; irq < NR_IRQS; irq++) {
#endif
for (irq = GPIO_IRQ_BASE; irq < NR_IRQS; irq++) {
set_irq_chip(irq, &bfin_gpio_irqchip);
/* if configured as edge, then will be changed to do_edge_IRQ */
set_irq_handler(irq, handle_level_irq);
......@@ -936,7 +1119,7 @@ void do_irq(int vec, struct pt_regs *fp)
} else {
struct ivgx *ivg = ivg7_13[vec - IVG7].ifirst;
struct ivgx *ivg_stop = ivg7_13[vec - IVG7].istop;
#if defined(CONFIG_BF54x) || defined(CONFIG_BF52x)
#if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561)
unsigned long sic_status[3];
SSYNC();
......
arch/blackfin/mach-common/pm.c
View file @ 04a94bab
......@@ -4,7 +4,7 @@
* Author: Cliff Brake <cbrake@accelent.com> Copyright (c) 2001
*
* Created: 2001
* Description: Power management for the bfin
* Description: Blackfin power management
*
* Modified: Nicolas Pitre - PXA250 support
* Copyright (c) 2002 Monta Vista Software, Inc.
......@@ -12,7 +12,7 @@
* Copyright (c) 2002 Monta Vista Software, Inc.
* Dirk Behme <dirk.behme@de.bosch.com> - OMAP1510/1610
* Copyright 2004
* Copyright 2004-2006 Analog Devices Inc.
* Copyright 2004-2008 Analog Devices Inc.
*
* Bugs: Enter bugs at http://blackfin.uclinux.org/
*
......@@ -67,42 +67,30 @@ void bfin_pm_suspend_standby_enter(void)
gpio_pm_wakeup_request(CONFIG_PM_WAKEUP_GPIO_NUMBER, WAKEUP_TYPE);
#endif
#if defined(CONFIG_PM_WAKEUP_BY_GPIO) || defined(CONFIG_PM_WAKEUP_GPIO_API)
{
u32 flags;
u32 flags;
local_irq_save(flags);
local_irq_save(flags);
bfin_pm_setup();
sleep_deeper(gpio_pm_setup()); /*Goto Sleep*/
gpio_pm_restore();
#if defined(CONFIG_BF54x) || defined(CONFIG_BF52x)
bfin_write_SIC_IWR0(IWR_ENABLE_ALL);
bfin_write_SIC_IWR1(IWR_ENABLE_ALL);
# ifdef CONFIG_BF54x
bfin_write_SIC_IWR2(IWR_ENABLE_ALL);
# endif
#ifdef CONFIG_PM_BFIN_SLEEP_DEEPER
sleep_deeper(bfin_sic_iwr[0], bfin_sic_iwr[1], bfin_sic_iwr[2]);
#else
bfin_write_SIC_IWR(IWR_ENABLE_ALL);
sleep_mode(bfin_sic_iwr[0], bfin_sic_iwr[1], bfin_sic_iwr[2]);
#endif
local_irq_restore(flags);
}
#endif
bfin_pm_restore();
#if defined(CONFIG_PM_WAKEUP_GPIO_BY_SIC_IWR)
sleep_deeper(CONFIG_PM_WAKEUP_SIC_IWR);
# if defined(CONFIG_BF54x) || defined(CONFIG_BF52x)
#if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561)
bfin_write_SIC_IWR0(IWR_ENABLE_ALL);
bfin_write_SIC_IWR1(IWR_ENABLE_ALL);
# ifdef CONFIG_BF54x
# ifdef CONFIG_BF54x
bfin_write_SIC_IWR2(IWR_ENABLE_ALL);
# endif
# else
bfin_write_SIC_IWR(IWR_ENABLE_ALL);
# endif
#endif /* CONFIG_PM_WAKEUP_GPIO_BY_SIC_IWR */
#else
bfin_write_SIC_IWR(IWR_ENABLE_ALL);
#endif
local_irq_restore(flags);
}
/*
......
arch/blackfin/mm/init.c
View file @ 04a94bab
......@@ -138,8 +138,7 @@ void __init mem_init(void)
start_mem = PAGE_ALIGN(start_mem);
max_mapnr = num_physpages = MAP_NR(high_memory);
printk(KERN_INFO "Kernel managed physical pages: %lu\n",
num_physpages);
printk(KERN_DEBUG "Kernel managed physical pages: %lu\n", num_physpages);
/* This will put all memory onto the freelists. */
totalram_pages = free_all_bootmem();
......@@ -153,8 +152,7 @@ void __init mem_init(void)
/* do not count in kernel image between _rambase and _ramstart */
reservedpages -= (_ramstart - _rambase) >> PAGE_SHIFT;
#if (defined(CONFIG_BFIN_ICACHE) && ANOMALY_05000263)
reservedpages += (_ramend - memory_end - DMA_UNCACHED_REGION) >>
PAGE_SHIFT;
reservedpages += (_ramend - memory_end - DMA_UNCACHED_REGION) >> PAGE_SHIFT;
#endif
codek = (_etext - _stext) >> 10;
......@@ -163,11 +161,9 @@ void __init mem_init(void)
printk(KERN_INFO
"Memory available: %luk/%luk RAM, "
"(%uk init code, %uk kernel code, "
"%uk data, %uk dma, %uk reserved)\n",
"(%uk init code, %uk kernel code, %uk data, %uk dma, %uk reserved)\n",
(unsigned long) freepages << (PAGE_SHIFT-10), _ramend >> 10,
initk, codek, datak, DMA_UNCACHED_REGION >> 10,
(reservedpages << (PAGE_SHIFT-10)));
initk, codek, datak, DMA_UNCACHED_REGION >> 10, (reservedpages << (PAGE_SHIFT-10)));
/* Initialize the blackfin L1 Memory. */
l1sram_init();
......
include/asm-blackfin/bfin-global.h
View file @ 04a94bab
......@@ -70,6 +70,7 @@ extern void program_IAR(void);
extern void evt14_softirq(void);
extern asmlinkage void asm_do_IRQ(unsigned int irq, struct pt_regs *regs);
extern void bfin_gpio_interrupt_setup(int irq, int irq_pfx, int type);
extern int bfin_internal_set_wake(unsigned int irq, unsigned int state);
extern asmlinkage void finish_atomic_sections (struct pt_regs *regs);
extern char fixed_code_start;
......@@ -121,6 +122,7 @@ extern unsigned long dpdt_swapcount_table[];
extern unsigned long table_start, table_end;
extern unsigned long bfin_sic_iwr[];
extern u16 _bfin_swrst; /* shadow for Software Reset Register (SWRST) */
extern struct file_operations dpmc_fops;
extern char _start;
......
include/asm-blackfin/bfin5xx_spi.h
View file @ 04a94bab
/************************************************************
*
* Copyright (C) 2004, Analog Devices. All Rights Reserved
* Copyright (C) 2006-2008, Analog Devices. All Rights Reserved
*
* FILE bfin5xx_spi.h
* PROGRAMMER(S): Luke Yang (Analog Devices Inc.)
......@@ -32,42 +32,6 @@
#define SPI_BAUD_OFF 0x14
#define SPI_SHAW_OFF 0x18
#define CMD_SPI_OUT_ENABLE 1
#define CMD_SPI_SET_BAUDRATE 2
#define CMD_SPI_SET_POLAR 3
#define CMD_SPI_SET_PHASE 4
#define CMD_SPI_SET_MASTER 5
#define CMD_SPI_SET_SENDOPT 6
#define CMD_SPI_SET_RECVOPT 7
#define CMD_SPI_SET_ORDER 8
#define CMD_SPI_SET_LENGTH16 9
#define CMD_SPI_GET_STAT 11
#define CMD_SPI_GET_CFG 12
#define CMD_SPI_SET_CSAVAIL 13
#define CMD_SPI_SET_CSHIGH 14 /* CS unavail */
#define CMD_SPI_SET_CSLOW 15 /* CS avail */
#define CMD_SPI_MISO_ENABLE 16
#define CMD_SPI_SET_CSENABLE 17
#define CMD_SPI_SET_CSDISABLE 18
#define CMD_SPI_SET_TRIGGER_MODE 19
#define CMD_SPI_SET_TRIGGER_SENSE 20
#define CMD_SPI_SET_TRIGGER_EDGE 21
#define CMD_SPI_SET_TRIGGER_LEVEL 22
#define CMD_SPI_SET_TIME_SPS 23
#define CMD_SPI_SET_TIME_SAMPLES 24
#define CMD_SPI_GET_SYSTEMCLOCK 25
#define CMD_SPI_SET_WRITECONTINUOUS 26
#define CMD_SPI_SET_SKFS 27
#define CMD_SPI_GET_ALLCONFIG 32 /* For debug */
#define SPI_DEFAULT_BARD 0x0100
#define SPI0_IRQ_NUM IRQ_SPI
#define SPI_ERR_TRIG -1
#define BIT_CTL_ENABLE 0x4000
#define BIT_CTL_OPENDRAIN 0x2000
......@@ -148,6 +112,10 @@
#define CFG_SPI_CS6VALUE 6
#define CFG_SPI_CS7VALUE 7
#define CMD_SPI_SET_BAUDRATE 2
#define CMD_SPI_GET_SYSTEMCLOCK 25
#define CMD_SPI_SET_WRITECONTINUOUS 26
/* device.platform_data for SSP controller devices */
struct bfin5xx_spi_master {
u16 num_chipselect;
......
include/asm-blackfin/dpmc.h
View file @ 04a94bab
......@@ -53,10 +53,10 @@ unsigned long get_pll_status(void);
void change_baud(int baud);
void fullon_mode(void);
void active_mode(void);
void sleep_mode(u32 sic_iwr);
void deep_sleep(u32 sic_iwr);
void hibernate_mode(u32 sic_iwr);
void sleep_deeper(u32 sic_iwr);
void sleep_mode(u32 sic_iwr0, u32 sic_iwr1, u32 sic_iwr2);
void deep_sleep(u32 sic_iwr0, u32 sic_iwr1, u32 sic_iwr2);
void hibernate_mode(u32 sic_iwr0, u32 sic_iwr1, u32 sic_iwr2);
void sleep_deeper(u32 sic_iwr0, u32 sic_iwr1, u32 sic_iwr2);
void program_wdog_timer(unsigned long);
void unmask_wdog_wakeup_evt(void);
void clear_wdog_wakeup_evt(void);
......
include/asm-blackfin/gpio.h
View file @ 04a94bab
......@@ -376,16 +376,19 @@ struct gpio_port_t {
#endif
#ifdef CONFIG_PM
unsigned int bfin_pm_setup(void);
void bfin_pm_restore(void);
#ifndef CONFIG_BF54x
#define PM_WAKE_RISING 0x1
#define PM_WAKE_FALLING 0x2
#define PM_WAKE_HIGH 0x4
#define PM_WAKE_LOW 0x8
#define PM_WAKE_BOTH_EDGES (PM_WAKE_RISING | PM_WAKE_FALLING)
#define PM_WAKE_IGNORE 0xF0
int gpio_pm_wakeup_request(unsigned gpio, unsigned char type);
void gpio_pm_wakeup_free(unsigned gpio);
unsigned int gpio_pm_setup(void);
void gpio_pm_restore(void);
struct gpio_port_s {
unsigned short data;
......@@ -409,6 +412,7 @@ struct gpio_port_s {
unsigned short fer;
unsigned short reserved;
};
#endif /*CONFIG_BF54x*/
#endif /*CONFIG_PM*/
/***********************************************************
......
include/asm-blackfin/mach-bf548/blackfin.h
View file @ 04a94bab
......@@ -46,6 +46,10 @@
#include "defBF544.h"
#endif
#ifdef CONFIG_BF547
#include "defBF547.h"
#endif
#ifdef CONFIG_BF548
#include "defBF548.h"
#endif
......@@ -58,10 +62,12 @@
#ifdef CONFIG_BF542
#include "cdefBF542.h"
#endif
#ifdef CONFIG_BF544
#include "cdefBF544.h"
#endif
#ifdef CONFIG_BF547
#include "cdefBF547.h"
#endif
#ifdef CONFIG_BF548
#include "cdefBF548.h"
#endif
......
include/asm-blackfin/mach-bf548/cdefBF547.h 0 → 100644
View file @ 04a94bab
/*
* File: include/asm-blackfin/mach-bf548/cdefBF547.h
* Based on:
* Author:
*
* Created:
* Description:
*
* Rev:
*
* Modified:
*
* Bugs: Enter bugs at http://blackfin.uclinux.org/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; see the file COPYING.
* If not, write to the Free Software Foundation,
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
#ifndef _CDEF_BF548_H
#define _CDEF_BF548_H
/* include all Core registers and bit definitions */
#include "defBF548.h"
/* include core sbfin_read_()ecific register pointer definitions */
#include <asm/mach-common/cdef_LPBlackfin.h>
/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF548 */
/* include cdefBF54x_base.h for the set of #defines that are common to all ADSP-BF54x bfin_read_()rocessors */
#include "cdefBF54x_base.h"
/* The following are the #defines needed by ADSP-BF548 that are not in the common header */
/* Timer Registers */
#define bfin_read_TIMER8_CONFIG() bfin_read16(TIMER8_CONFIG)
#define bfin_write_TIMER8_CONFIG(val) bfin_write16(TIMER8_CONFIG, val)
#define bfin_read_TIMER8_COUNTER() bfin_read32(TIMER8_COUNTER)
#define bfin_write_TIMER8_COUNTER(val) bfin_write32(TIMER8_COUNTER, val)
#define bfin_read_TIMER8_PERIOD() bfin_read32(TIMER8_PERIOD)
#define bfin_write_TIMER8_PERIOD(val) bfin_write32(TIMER8_PERIOD, val)
#define bfin_read_TIMER8_WIDTH() bfin_read32(TIMER8_WIDTH)
#define bfin_write_TIMER8_WIDTH(val) bfin_write32(TIMER8_WIDTH, val)
#define bfin_read_TIMER9_CONFIG() bfin_read16(TIMER9_CONFIG)
#define bfin_write_TIMER9_CONFIG(val) bfin_write16(TIMER9_CONFIG, val)
#define bfin_read_TIMER9_COUNTER() bfin_read32(TIMER9_COUNTER)
#define bfin_write_TIMER9_COUNTER(val) bfin_write32(TIMER9_COUNTER, val)
#define bfin_read_TIMER9_PERIOD() bfin_read32(TIMER9_PERIOD)
#define bfin_write_TIMER9_PERIOD(val) bfin_write32(TIMER9_PERIOD, val)
#define bfin_read_TIMER9_WIDTH() bfin_read32(TIMER9_WIDTH)
#define bfin_write_TIMER9_WIDTH(val) bfin_write32(TIMER9_WIDTH, val)
#define bfin_read_TIMER10_CONFIG() bfin_read16(TIMER10_CONFIG)
#define bfin_write_TIMER10_CONFIG(val) bfin_write16(TIMER10_CONFIG, val)
#define bfin_read_TIMER10_COUNTER() bfin_read32(TIMER10_COUNTER)
#define bfin_write_TIMER10_COUNTER(val) bfin_write32(TIMER10_COUNTER, val)
#define bfin_read_TIMER10_PERIOD() bfin_read32(TIMER10_PERIOD)
#define bfin_write_TIMER10_PERIOD(val) bfin_write32(TIMER10_PERIOD, val)
#define bfin_read_TIMER10_WIDTH() bfin_read32(TIMER10_WIDTH)
#define bfin_write_TIMER10_WIDTH(val) bfin_write32(TIMER10_WIDTH, val)
/* Timer Groubfin_read_() of 3 */
#define bfin_read_TIMER_ENABLE1() bfin_read16(TIMER_ENABLE1)
#define bfin_write_TIMER_ENABLE1(val) bfin_write16(TIMER_ENABLE1, val)
#define bfin_read_TIMER_DISABLE1() bfin_read16(TIMER_DISABLE1)
#define bfin_write_TIMER_DISABLE1(val) bfin_write16(TIMER_DISABLE1, val)
#define bfin_read_TIMER_STATUS1() bfin_read32(TIMER_STATUS1)
#define bfin_write_TIMER_STATUS1(val) bfin_write32(TIMER_STATUS1, val)
/* SPORT0 Registers */
#define bfin_read_SPORT0_TCR1() bfin_read16(SPORT0_TCR1)
#define bfin_write_SPORT0_TCR1(val) bfin_write16(SPORT0_TCR1, val)
#define bfin_read_SPORT0_TCR2() bfin_read16(SPORT0_TCR2)
#define bfin_write_SPORT0_TCR2(val) bfin_write16(SPORT0_TCR2, val)
#define bfin_read_SPORT0_TCLKDIV() bfin_read16(SPORT0_TCLKDIV)
#define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV, val)
#define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV)
#define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV, val)
#define bfin_read_SPORT0_TX() bfin_read32(SPORT0_TX)
#define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX, val)
#define bfin_read_SPORT0_RX() bfin_read32(SPORT0_RX)
#define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX, val)
#define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1)
#define bfin_write_SPORT0_RCR1(val) bfin_write16(SPORT0_RCR1, val)
#define bfin_read_SPORT0_RCR2() bfin_read16(SPORT0_RCR2)
#define bfin_write_SPORT0_RCR2(val) bfin_write16(SPORT0_RCR2, val)
#define bfin_read_SPORT0_RCLKDIV() bfin_read16(SPORT0_RCLKDIV)
#define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV, val)
#define bfin_read_SPORT0_RFSDIV() bfin_read16(SPORT0_RFSDIV)
#define bfin_write_SPORT0_RFSDIV(val) bfin_write16(SPORT0_RFSDIV, val)
#define bfin_read_SPORT0_STAT() bfin_read16(SPORT0_STAT)
#define bfin_write_SPORT0_STAT(val) bfin_write16(SPORT0_STAT, val)
#define bfin_read_SPORT0_CHNL() bfin_read16(SPORT0_CHNL)
#define bfin_write_SPORT0_CHNL(val) bfin_write16(SPORT0_CHNL, val)
#define bfin_read_SPORT0_MCMC1() bfin_read16(SPORT0_MCMC1)
#define bfin_write_SPORT0_MCMC1(val) bfin_write16(SPORT0_MCMC1, val)
#define bfin_read_SPORT0_MCMC2() bfin_read16(SPORT0_MCMC2)
#define bfin_write_SPORT0_MCMC2(val) bfin_write16(SPORT0_MCMC2, val)
#define bfin_read_SPORT0_MTCS0() bfin_read32(SPORT0_MTCS0)
#define bfin_write_SPORT0_MTCS0(val) bfin_write32(SPORT0_MTCS0, val)
#define bfin_read_SPORT0_MTCS1() bfin_read32(SPORT0_MTCS1)
#define bfin_write_SPORT0_MTCS1(val) bfin_write32(SPORT0_MTCS1, val)
#define bfin_read_SPORT0_MTCS2() bfin_read32(SPORT0_MTCS2)
#define bfin_write_SPORT0_MTCS2(val) bfin_write32(SPORT0_MTCS2, val)
#define bfin_read_SPORT0_MTCS3() bfin_read32(SPORT0_MTCS3)
#define bfin_write_SPORT0_MTCS3(val) bfin_write32(SPORT0_MTCS3, val)
#define bfin_read_SPORT0_MRCS0() bfin_read32(SPORT0_MRCS0)
#define bfin_write_SPORT0_MRCS0(val) bfin_write32(SPORT0_MRCS0, val)
#define bfin_read_SPORT0_MRCS1() bfin_read32(SPORT0_MRCS1)
#define bfin_write_SPORT0_MRCS1(val) bfin_write32(SPORT0_MRCS1, val)
#define bfin_read_SPORT0_MRCS2() bfin_read32(SPORT0_MRCS2)
#define bfin_write_SPORT0_MRCS2(val) bfin_write32(SPORT0_MRCS2, val)
#define bfin_read_SPORT0_MRCS3() bfin_read32(SPORT0_MRCS3)
#define bfin_write_SPORT0_MRCS3(val) bfin_write32(SPORT0_MRCS3, val)
/* EPPI0 Registers */
#define bfin_read_EPPI0_STATUS() bfin_read16(EPPI0_STATUS)
#define bfin_write_EPPI0_STATUS(val) bfin_write16(EPPI0_STATUS, val)
#define bfin_read_EPPI0_HCOUNT() bfin_read16(EPPI0_HCOUNT)
#define bfin_write_EPPI0_HCOUNT(val) bfin_write16(EPPI0_HCOUNT, val)
#define bfin_read_EPPI0_HDELAY() bfin_read16(EPPI0_HDELAY)
#define bfin_write_EPPI0_HDELAY(val) bfin_write16(EPPI0_HDELAY, val)
#define bfin_read_EPPI0_VCOUNT() bfin_read16(EPPI0_VCOUNT)
#define bfin_write_EPPI0_VCOUNT(val) bfin_write16(EPPI0_VCOUNT, val)
#define bfin_read_EPPI0_VDELAY() bfin_read16(EPPI0_VDELAY)
#define bfin_write_EPPI0_VDELAY(val) bfin_write16(EPPI0_VDELAY, val)
#define bfin_read_EPPI0_FRAME() bfin_read16(EPPI0_FRAME)
#define bfin_write_EPPI0_FRAME(val) bfin_write16(EPPI0_FRAME, val)
#define bfin_read_EPPI0_LINE() bfin_read16(EPPI0_LINE)
#define bfin_write_EPPI0_LINE(val) bfin_write16(EPPI0_LINE, val)
#define bfin_read_EPPI0_CLKDIV() bfin_read16(EPPI0_CLKDIV)
#define bfin_write_EPPI0_CLKDIV(val) bfin_write16(EPPI0_CLKDIV, val)
#define bfin_read_EPPI0_CONTROL() bfin_read32(EPPI0_CONTROL)
#define bfin_write_EPPI0_CONTROL(val) bfin_write32(EPPI0_CONTROL, val)
#define bfin_read_EPPI0_FS1W_HBL() bfin_read32(EPPI0_FS1W_HBL)
#define bfin_write_EPPI0_FS1W_HBL(val) bfin_write32(EPPI0_FS1W_HBL, val)
#define bfin_read_EPPI0_FS1P_AVPL() bfin_read32(EPPI0_FS1P_AVPL)
#define bfin_write_EPPI0_FS1P_AVPL(val) bfin_write32(EPPI0_FS1P_AVPL, val)
#define bfin_read_EPPI0_FS2W_LVB() bfin_read32(EPPI0_FS2W_LVB)
#define bfin_write_EPPI0_FS2W_LVB(val) bfin_write32(EPPI0_FS2W_LVB, val)
#define bfin_read_EPPI0_FS2P_LAVF() bfin_read32(EPPI0_FS2P_LAVF)
#define bfin_write_EPPI0_FS2P_LAVF(val) bfin_write32(EPPI0_FS2P_LAVF, val)
#define bfin_read_EPPI0_CLIP() bfin_read32(EPPI0_CLIP)
#define bfin_write_EPPI0_CLIP(val) bfin_write32(EPPI0_CLIP, val)
/* UART2 Registers */
#define bfin_read_UART2_DLL() bfin_read16(UART2_DLL)
#define bfin_write_UART2_DLL(val) bfin_write16(UART2_DLL, val)
#define bfin_read_UART2_DLH() bfin_read16(UART2_DLH)
#define bfin_write_UART2_DLH(val) bfin_write16(UART2_DLH, val)
#define bfin_read_UART2_GCTL() bfin_read16(UART2_GCTL)
#define bfin_write_UART2_GCTL(val) bfin_write16(UART2_GCTL, val)
#define bfin_read_UART2_LCR() bfin_read16(UART2_LCR)
#define bfin_write_UART2_LCR(val) bfin_write16(UART2_LCR, val)
#define bfin_read_UART2_MCR() bfin_read16(UART2_MCR)
#define bfin_write_UART2_MCR(val) bfin_write16(UART2_MCR, val)
#define bfin_read_UART2_LSR() bfin_read16(UART2_LSR)
#define bfin_write_UART2_LSR(val) bfin_write16(UART2_LSR, val)
#define bfin_read_UART2_MSR() bfin_read16(UART2_MSR)
#define bfin_write_UART2_MSR(val) bfin_write16(UART2_MSR, val)
#define bfin_read_UART2_SCR() bfin_read16(UART2_SCR)
#define bfin_write_UART2_SCR(val) bfin_write16(UART2_SCR, val)
#define bfin_read_UART2_IER_SET() bfin_read16(UART2_IER_SET)
#define bfin_write_UART2_IER_SET(val) bfin_write16(UART2_IER_SET, val)
#define bfin_read_UART2_IER_CLEAR() bfin_read16(UART2_IER_CLEAR)
#define bfin_write_UART2_IER_CLEAR(val) bfin_write16(UART2_IER_CLEAR, val)
#define bfin_read_UART2_RBR() bfin_read16(UART2_RBR)
#define bfin_write_UART2_RBR(val) bfin_write16(UART2_RBR, val)
/* Two Wire Interface Registers (TWI1) */
#define bfin_read_TWI1_CLKDIV() bfin_read16(TWI1_CLKDIV)
#define bfin_write_TWI1_CLKDIV(val) bfin_write16(TWI1_CLKDIV, val)
#define bfin_read_TWI1_CONTROL() bfin_read16(TWI1_CONTROL)
#define bfin_write_TWI1_CONTROL(val) bfin_write16(TWI1_CONTROL, val)
#define bfin_read_TWI1_SLAVE_CTRL() bfin_read16(TWI1_SLAVE_CTRL)
#define bfin_write_TWI1_SLAVE_CTRL(val) bfin_write16(TWI1_SLAVE_CTRL, val)
#define bfin_read_TWI1_SLAVE_STAT() bfin_read16(TWI1_SLAVE_STAT)
#define bfin_write_TWI1_SLAVE_STAT(val) bfin_write16(TWI1_SLAVE_STAT, val)
#define bfin_read_TWI1_SLAVE_ADDR() bfin_read16(TWI1_SLAVE_ADDR)
#define bfin_write_TWI1_SLAVE_ADDR(val) bfin_write16(TWI1_SLAVE_ADDR, val)
#define bfin_read_TWI1_MASTER_CTRL() bfin_read16(TWI1_MASTER_CTRL)
#define bfin_write_TWI1_MASTER_CTRL(val) bfin_write16(TWI1_MASTER_CTRL, val)
#define bfin_read_TWI1_MASTER_STAT() bfin_read16(TWI1_MASTER_STAT)
#define bfin_write_TWI1_MASTER_STAT(val) bfin_write16(TWI1_MASTER_STAT, val)
#define bfin_read_TWI1_MASTER_ADDR() bfin_read16(TWI1_MASTER_ADDR)
#define bfin_write_TWI1_MASTER_ADDR(val) bfin_write16(TWI1_MASTER_ADDR, val)
#define bfin_read_TWI1_INT_STAT() bfin_read16(TWI1_INT_STAT)
#define bfin_write_TWI1_INT_STAT(val) bfin_write16(TWI1_INT_STAT, val)
#define bfin_read_TWI1_INT_MASK() bfin_read16(TWI1_INT_MASK)
#define bfin_write_TWI1_INT_MASK(val) bfin_write16(TWI1_INT_MASK, val)
#define bfin_read_TWI1_FIFO_CTRL() bfin_read16(TWI1_FIFO_CTRL)
#define bfin_write_TWI1_FIFO_CTRL(val) bfin_write16(TWI1_FIFO_CTRL, val)
#define bfin_read_TWI1_FIFO_STAT() bfin_read16(TWI1_FIFO_STAT)
#define bfin_write_TWI1_FIFO_STAT(val) bfin_write16(TWI1_FIFO_STAT, val)
#define bfin_read_TWI1_XMT_DATA8() bfin_read16(TWI1_XMT_DATA8)
#define bfin_write_TWI1_XMT_DATA8(val) bfin_write16(TWI1_XMT_DATA8, val)
#define bfin_read_TWI1_XMT_DATA16() bfin_read16(TWI1_XMT_DATA16)
#define bfin_write_TWI1_XMT_DATA16(val) bfin_write16(TWI1_XMT_DATA16, val)
#define bfin_read_TWI1_RCV_DATA8() bfin_read16(TWI1_RCV_DATA8)
#define bfin_write_TWI1_RCV_DATA8(val) bfin_write16(TWI1_RCV_DATA8, val)
#define bfin_read_TWI1_RCV_DATA16() bfin_read16(TWI1_RCV_DATA16)
#define bfin_write_TWI1_RCV_DATA16(val) bfin_write16(TWI1_RCV_DATA16, val)
/* SPI2 Registers */
#define bfin_read_SPI2_CTL() bfin_read16(SPI2_CTL)
#define bfin_write_SPI2_CTL(val) bfin_write16(SPI2_CTL, val)
#define bfin_read_SPI2_FLG() bfin_read16(SPI2_FLG)
#define bfin_write_SPI2_FLG(val) bfin_write16(SPI2_FLG, val)
#define bfin_read_SPI2_STAT() bfin_read16(SPI2_STAT)
#define bfin_write_SPI2_STAT(val) bfin_write16(SPI2_STAT, val)
#define bfin_read_SPI2_TDBR() bfin_read16(SPI2_TDBR)
#define bfin_write_SPI2_TDBR(val) bfin_write16(SPI2_TDBR, val)
#define bfin_read_SPI2_RDBR() bfin_read16(SPI2_RDBR)
#define bfin_write_SPI2_RDBR(val) bfin_write16(SPI2_RDBR, val)
#define bfin_read_SPI2_BAUD() bfin_read16(SPI2_BAUD)
#define bfin_write_SPI2_BAUD(val) bfin_write16(SPI2_BAUD, val)
#define bfin_read_SPI2_SHADOW() bfin_read16(SPI2_SHADOW)
#define bfin_write_SPI2_SHADOW(val) bfin_write16(SPI2_SHADOW, val)
/* ATAPI Registers */
#define bfin_read_ATAPI_CONTROL() bfin_read16(ATAPI_CONTROL)
#define bfin_write_ATAPI_CONTROL(val) bfin_write16(ATAPI_CONTROL, val)
#define bfin_read_ATAPI_STATUS() bfin_read16(ATAPI_STATUS)
#define bfin_write_ATAPI_STATUS(val) bfin_write16(ATAPI_STATUS, val)
#define bfin_read_ATAPI_DEV_ADDR() bfin_read16(ATAPI_DEV_ADDR)
#define bfin_write_ATAPI_DEV_ADDR(val) bfin_write16(ATAPI_DEV_ADDR, val)
#define bfin_read_ATAPI_DEV_TXBUF() bfin_read16(ATAPI_DEV_TXBUF)
#define bfin_write_ATAPI_DEV_TXBUF(val) bfin_write16(ATAPI_DEV_TXBUF, val)
#define bfin_read_ATAPI_DEV_RXBUF() bfin_read16(ATAPI_DEV_RXBUF)
#define bfin_write_ATAPI_DEV_RXBUF(val) bfin_write16(ATAPI_DEV_RXBUF, val)
#define bfin_read_ATAPI_INT_MASK() bfin_read16(ATAPI_INT_MASK)
#define bfin_write_ATAPI_INT_MASK(val) bfin_write16(ATAPI_INT_MASK, val)
#define bfin_read_ATAPI_INT_STATUS() bfin_read16(ATAPI_INT_STATUS)
#define bfin_write_ATAPI_INT_STATUS(val) bfin_write16(ATAPI_INT_STATUS, val)
#define bfin_read_ATAPI_XFER_LEN() bfin_read16(ATAPI_XFER_LEN)
#define bfin_write_ATAPI_XFER_LEN(val) bfin_write16(ATAPI_XFER_LEN, val)
#define bfin_read_ATAPI_LINE_STATUS() bfin_read16(ATAPI_LINE_STATUS)
#define bfin_write_ATAPI_LINE_STATUS(val) bfin_write16(ATAPI_LINE_STATUS, val)
#define bfin_read_ATAPI_SM_STATE() bfin_read16(ATAPI_SM_STATE)
#define bfin_write_ATAPI_SM_STATE(val) bfin_write16(ATAPI_SM_STATE, val)
#define bfin_read_ATAPI_TERMINATE() bfin_read16(ATAPI_TERMINATE)
#define bfin_write_ATAPI_TERMINATE(val) bfin_write16(ATAPI_TERMINATE, val)
#define bfin_read_ATAPI_PIO_TFRCNT() bfin_read16(ATAPI_PIO_TFRCNT)
#define bfin_write_ATAPI_PIO_TFRCNT(val) bfin_write16(ATAPI_PIO_TFRCNT, val)
#define bfin_read_ATAPI_DMA_TFRCNT() bfin_read16(ATAPI_DMA_TFRCNT)
#define bfin_write_ATAPI_DMA_TFRCNT(val) bfin_write16(ATAPI_DMA_TFRCNT, val)
#define bfin_read_ATAPI_UMAIN_TFRCNT() bfin_read16(ATAPI_UMAIN_TFRCNT)
#define bfin_write_ATAPI_UMAIN_TFRCNT(val) bfin_write16(ATAPI_UMAIN_TFRCNT, val)
#define bfin_read_ATAPI_UDMAOUT_TFRCNT() bfin_read16(ATAPI_UDMAOUT_TFRCNT)
#define bfin_write_ATAPI_UDMAOUT_TFRCNT(val) bfin_write16(ATAPI_UDMAOUT_TFRCNT, val)
#define bfin_read_ATAPI_REG_TIM_0() bfin_read16(ATAPI_REG_TIM_0)
#define bfin_write_ATAPI_REG_TIM_0(val) bfin_write16(ATAPI_REG_TIM_0, val)
#define bfin_read_ATAPI_PIO_TIM_0() bfin_read16(ATAPI_PIO_TIM_0)
#define bfin_write_ATAPI_PIO_TIM_0(val) bfin_write16(ATAPI_PIO_TIM_0, val)
#define bfin_read_ATAPI_PIO_TIM_1() bfin_read16(ATAPI_PIO_TIM_1)
#define bfin_write_ATAPI_PIO_TIM_1(val) bfin_write16(ATAPI_PIO_TIM_1, val)
#define bfin_read_ATAPI_MULTI_TIM_0() bfin_read16(ATAPI_MULTI_TIM_0)
#define bfin_write_ATAPI_MULTI_TIM_0(val) bfin_write16(ATAPI_MULTI_TIM_0, val)
#define bfin_read_ATAPI_MULTI_TIM_1() bfin_read16(ATAPI_MULTI_TIM_1)
#define bfin_write_ATAPI_MULTI_TIM_1(val) bfin_write16(ATAPI_MULTI_TIM_1, val)
#define bfin_read_ATAPI_MULTI_TIM_2() bfin_read16(ATAPI_MULTI_TIM_2)
#define bfin_write_ATAPI_MULTI_TIM_2(val) bfin_write16(ATAPI_MULTI_TIM_2, val)
#define bfin_read_ATAPI_ULTRA_TIM_0() bfin_read16(ATAPI_ULTRA_TIM_0)
#define bfin_write_ATAPI_ULTRA_TIM_0(val) bfin_write16(ATAPI_ULTRA_TIM_0, val)
#define bfin_read_ATAPI_ULTRA_TIM_1() bfin_read16(ATAPI_ULTRA_TIM_1)
#define bfin_write_ATAPI_ULTRA_TIM_1(val) bfin_write16(ATAPI_ULTRA_TIM_1, val)
#define bfin_read_ATAPI_ULTRA_TIM_2() bfin_read16(ATAPI_ULTRA_TIM_2)
#define bfin_write_ATAPI_ULTRA_TIM_2(val) bfin_write16(ATAPI_ULTRA_TIM_2, val)
#define bfin_read_ATAPI_ULTRA_TIM_3() bfin_read16(ATAPI_ULTRA_TIM_3)
#define bfin_write_ATAPI_ULTRA_TIM_3(val) bfin_write16(ATAPI_ULTRA_TIM_3, val)
/* SDH Registers */
#define bfin_read_SDH_PWR_CTL() bfin_read16(SDH_PWR_CTL)
#define bfin_write_SDH_PWR_CTL(val) bfin_write16(SDH_PWR_CTL, val)
#define bfin_read_SDH_CLK_CTL() bfin_read16(SDH_CLK_CTL)
#define bfin_write_SDH_CLK_CTL(val) bfin_write16(SDH_CLK_CTL, val)
#define bfin_read_SDH_ARGUMENT() bfin_read32(SDH_ARGUMENT)
#define bfin_write_SDH_ARGUMENT(val) bfin_write32(SDH_ARGUMENT, val)
#define bfin_read_SDH_COMMAND() bfin_read16(SDH_COMMAND)
#define bfin_write_SDH_COMMAND(val) bfin_write16(SDH_COMMAND, val)
#define bfin_read_SDH_RESP_CMD() bfin_read16(SDH_RESP_CMD)
#define bfin_write_SDH_RESP_CMD(val) bfin_write16(SDH_RESP_CMD, val)
#define bfin_read_SDH_RESPONSE0() bfin_read32(SDH_RESPONSE0)
#define bfin_write_SDH_RESPONSE0(val) bfin_write32(SDH_RESPONSE0, val)
#define bfin_read_SDH_RESPONSE1() bfin_read32(SDH_RESPONSE1)
#define bfin_write_SDH_RESPONSE1(val) bfin_write32(SDH_RESPONSE1, val)
#define bfin_read_SDH_RESPONSE2() bfin_read32(SDH_RESPONSE2)
#define bfin_write_SDH_RESPONSE2(val) bfin_write32(SDH_RESPONSE2, val)
#define bfin_read_SDH_RESPONSE3() bfin_read32(SDH_RESPONSE3)
#define bfin_write_SDH_RESPONSE3(val) bfin_write32(SDH_RESPONSE3, val)
#define bfin_read_SDH_DATA_TIMER() bfin_read32(SDH_DATA_TIMER)
#define bfin_write_SDH_DATA_TIMER(val) bfin_write32(SDH_DATA_TIMER, val)
#define bfin_read_SDH_DATA_LGTH() bfin_read16(SDH_DATA_LGTH)
#define bfin_write_SDH_DATA_LGTH(val) bfin_write16(SDH_DATA_LGTH, val)
#define bfin_read_SDH_DATA_CTL() bfin_read16(SDH_DATA_CTL)
#define bfin_write_SDH_DATA_CTL(val) bfin_write16(SDH_DATA_CTL, val)
#define bfin_read_SDH_DATA_CNT() bfin_read16(SDH_DATA_CNT)
#define bfin_write_SDH_DATA_CNT(val) bfin_write16(SDH_DATA_CNT, val)
#define bfin_read_SDH_STATUS() bfin_read32(SDH_STATUS)
#define bfin_write_SDH_STATUS(val) bfin_write32(SDH_STATUS, val)
#define bfin_read_SDH_STATUS_CLR() bfin_read16(SDH_STATUS_CLR)
#define bfin_write_SDH_STATUS_CLR(val) bfin_write16(SDH_STATUS_CLR, val)
#define bfin_read_SDH_MASK0() bfin_read32(SDH_MASK0)
#define bfin_write_SDH_MASK0(val) bfin_write32(SDH_MASK0, val)
#define bfin_read_SDH_MASK1() bfin_read32(SDH_MASK1)
#define bfin_write_SDH_MASK1(val) bfin_write32(SDH_MASK1, val)
#define bfin_read_SDH_FIFO_CNT() bfin_read16(SDH_FIFO_CNT)
#define bfin_write_SDH_FIFO_CNT(val) bfin_write16(SDH_FIFO_CNT, val)
#define bfin_read_SDH_FIFO() bfin_read32(SDH_FIFO)
#define bfin_write_SDH_FIFO(val) bfin_write32(SDH_FIFO, val)
#define bfin_read_SDH_E_STATUS() bfin_read16(SDH_E_STATUS)
#define bfin_write_SDH_E_STATUS(val) bfin_write16(SDH_E_STATUS, val)
#define bfin_read_SDH_E_MASK() bfin_read16(SDH_E_MASK)
#define bfin_write_SDH_E_MASK(val) bfin_write16(SDH_E_MASK, val)
#define bfin_read_SDH_CFG() bfin_read16(SDH_CFG)
#define bfin_write_SDH_CFG(val) bfin_write16(SDH_CFG, val)
#define bfin_read_SDH_RD_WAIT_EN() bfin_read16(SDH_RD_WAIT_EN)
#define bfin_write_SDH_RD_WAIT_EN(val) bfin_write16(SDH_RD_WAIT_EN, val)
#define bfin_read_SDH_PID0() bfin_read16(SDH_PID0)
#define bfin_write_SDH_PID0(val) bfin_write16(SDH_PID0, val)
#define bfin_read_SDH_PID1() bfin_read16(SDH_PID1)
#define bfin_write_SDH_PID1(val) bfin_write16(SDH_PID1, val)
#define bfin_read_SDH_PID2() bfin_read16(SDH_PID2)
#define bfin_write_SDH_PID2(val) bfin_write16(SDH_PID2, val)
#define bfin_read_SDH_PID3() bfin_read16(SDH_PID3)
#define bfin_write_SDH_PID3(val) bfin_write16(SDH_PID3, val)
#define bfin_read_SDH_PID4() bfin_read16(SDH_PID4)
#define bfin_write_SDH_PID4(val) bfin_write16(SDH_PID4, val)
#define bfin_read_SDH_PID5() bfin_read16(SDH_PID5)
#define bfin_write_SDH_PID5(val) bfin_write16(SDH_PID5, val)
#define bfin_read_SDH_PID6() bfin_read16(SDH_PID6)
#define bfin_write_SDH_PID6(val) bfin_write16(SDH_PID6, val)
#define bfin_read_SDH_PID7() bfin_read16(SDH_PID7)
#define bfin_write_SDH_PID7(val) bfin_write16(SDH_PID7, val)
/* HOST Port Registers */
#define bfin_read_HOST_CONTROL() bfin_read16(HOST_CONTROL)
#define bfin_write_HOST_CONTROL(val) bfin_write16(HOST_CONTROL, val)
#define bfin_read_HOST_STATUS() bfin_read16(HOST_STATUS)
#define bfin_write_HOST_STATUS(val) bfin_write16(HOST_STATUS, val)
#define bfin_read_HOST_TIMEOUT() bfin_read16(HOST_TIMEOUT)
#define bfin_write_HOST_TIMEOUT(val) bfin_write16(HOST_TIMEOUT, val)
/* USB Control Registers */
#define bfin_read_USB_FADDR() bfin_read16(USB_FADDR)
#define bfin_write_USB_FADDR(val) bfin_write16(USB_FADDR, val)
#define bfin_read_USB_POWER() bfin_read16(USB_POWER)
#define bfin_write_USB_POWER(val) bfin_write16(USB_POWER, val)
#define bfin_read_USB_INTRTX() bfin_read16(USB_INTRTX)
#define bfin_write_USB_INTRTX(val) bfin_write16(USB_INTRTX, val)
#define bfin_read_USB_INTRRX() bfin_read16(USB_INTRRX)
#define bfin_write_USB_INTRRX(val) bfin_write16(USB_INTRRX, val)
#define bfin_read_USB_INTRTXE() bfin_read16(USB_INTRTXE)
#define bfin_write_USB_INTRTXE(val) bfin_write16(USB_INTRTXE, val)
#define bfin_read_USB_INTRRXE() bfin_read16(USB_INTRRXE)
#define bfin_write_USB_INTRRXE(val) bfin_write16(USB_INTRRXE, val)
#define bfin_read_USB_INTRUSB() bfin_read16(USB_INTRUSB)
#define bfin_write_USB_INTRUSB(val) bfin_write16(USB_INTRUSB, val)
#define bfin_read_USB_INTRUSBE() bfin_read16(USB_INTRUSBE)
#define bfin_write_USB_INTRUSBE(val) bfin_write16(USB_INTRUSBE, val)
#define bfin_read_USB_FRAME() bfin_read16(USB_FRAME)
#define bfin_write_USB_FRAME(val) bfin_write16(USB_FRAME, val)
#define bfin_read_USB_INDEX() bfin_read16(USB_INDEX)
#define bfin_write_USB_INDEX(val) bfin_write16(USB_INDEX, val)
#define bfin_read_USB_TESTMODE() bfin_read16(USB_TESTMODE)
#define bfin_write_USB_TESTMODE(val) bfin_write16(USB_TESTMODE, val)
#define bfin_read_USB_GLOBINTR() bfin_read16(USB_GLOBINTR)
#define bfin_write_USB_GLOBINTR(val) bfin_write16(USB_GLOBINTR, val)
#define bfin_read_USB_GLOBAL_CTL() bfin_read16(USB_GLOBAL_CTL)
#define bfin_write_USB_GLOBAL_CTL(val) bfin_write16(USB_GLOBAL_CTL, val)
/* USB Packet Control Registers */
#define bfin_read_USB_TX_MAX_PACKET() bfin_read16(USB_TX_MAX_PACKET)
#define bfin_write_USB_TX_MAX_PACKET(val) bfin_write16(USB_TX_MAX_PACKET, val)
#define bfin_read_USB_CSR0() bfin_read16(USB_CSR0)
#define bfin_write_USB_CSR0(val) bfin_write16(USB_CSR0, val)
#define bfin_read_USB_TXCSR() bfin_read16(USB_TXCSR)
#define bfin_write_USB_TXCSR(val) bfin_write16(USB_TXCSR, val)
#define bfin_read_USB_RX_MAX_PACKET() bfin_read16(USB_RX_MAX_PACKET)
#define bfin_write_USB_RX_MAX_PACKET(val) bfin_write16(USB_RX_MAX_PACKET, val)
#define bfin_read_USB_RXCSR() bfin_read16(USB_RXCSR)
#define bfin_write_USB_RXCSR(val) bfin_write16(USB_RXCSR, val)
#define bfin_read_USB_COUNT0() bfin_read16(USB_COUNT0)
#define bfin_write_USB_COUNT0(val) bfin_write16(USB_COUNT0, val)
#define bfin_read_USB_RXCOUNT() bfin_read16(USB_RXCOUNT)
#define bfin_write_USB_RXCOUNT(val) bfin_write16(USB_RXCOUNT, val)
#define bfin_read_USB_TXTYPE() bfin_read16(USB_TXTYPE)
#define bfin_write_USB_TXTYPE(val) bfin_write16(USB_TXTYPE, val)
#define bfin_read_USB_NAKLIMIT0() bfin_read16(USB_NAKLIMIT0)
#define bfin_write_USB_NAKLIMIT0(val) bfin_write16(USB_NAKLIMIT0, val)
#define bfin_read_USB_TXINTERVAL() bfin_read16(USB_TXINTERVAL)
#define bfin_write_USB_TXINTERVAL(val) bfin_write16(USB_TXINTERVAL, val)
#define bfin_read_USB_RXTYPE() bfin_read16(USB_RXTYPE)
#define bfin_write_USB_RXTYPE(val) bfin_write16(USB_RXTYPE, val)
#define bfin_read_USB_RXINTERVAL() bfin_read16(USB_RXINTERVAL)
#define bfin_write_USB_RXINTERVAL(val) bfin_write16(USB_RXINTERVAL, val)
#define bfin_read_USB_TXCOUNT() bfin_read16(USB_TXCOUNT)
#define bfin_write_USB_TXCOUNT(val) bfin_write16(USB_TXCOUNT, val)
/* USB Endbfin_read_()oint FIFO Registers */
#define bfin_read_USB_EP0_FIFO() bfin_read16(USB_EP0_FIFO)
#define bfin_write_USB_EP0_FIFO(val) bfin_write16(USB_EP0_FIFO, val)
#define bfin_read_USB_EP1_FIFO() bfin_read16(USB_EP1_FIFO)
#define bfin_write_USB_EP1_FIFO(val) bfin_write16(USB_EP1_FIFO, val)
#define bfin_read_USB_EP2_FIFO() bfin_read16(USB_EP2_FIFO)
#define bfin_write_USB_EP2_FIFO(val) bfin_write16(USB_EP2_FIFO, val)
#define bfin_read_USB_EP3_FIFO() bfin_read16(USB_EP3_FIFO)
#define bfin_write_USB_EP3_FIFO(val) bfin_write16(USB_EP3_FIFO, val)
#define bfin_read_USB_EP4_FIFO() bfin_read16(USB_EP4_FIFO)
#define bfin_write_USB_EP4_FIFO(val) bfin_write16(USB_EP4_FIFO, val)
#define bfin_read_USB_EP5_FIFO() bfin_read16(USB_EP5_FIFO)
#define bfin_write_USB_EP5_FIFO(val) bfin_write16(USB_EP5_FIFO, val)
#define bfin_read_USB_EP6_FIFO() bfin_read16(USB_EP6_FIFO)
#define bfin_write_USB_EP6_FIFO(val) bfin_write16(USB_EP6_FIFO, val)
#define bfin_read_USB_EP7_FIFO() bfin_read16(USB_EP7_FIFO)
#define bfin_write_USB_EP7_FIFO(val) bfin_write16(USB_EP7_FIFO, val)
/* USB OTG Control Registers */
#define bfin_read_USB_OTG_DEV_CTL() bfin_read16(USB_OTG_DEV_CTL)
#define bfin_write_USB_OTG_DEV_CTL(val) bfin_write16(USB_OTG_DEV_CTL, val)
#define bfin_read_USB_OTG_VBUS_IRQ() bfin_read16(USB_OTG_VBUS_IRQ)
#define bfin_write_USB_OTG_VBUS_IRQ(val) bfin_write16(USB_OTG_VBUS_IRQ, val)
#define bfin_read_USB_OTG_VBUS_MASK() bfin_read16(USB_OTG_VBUS_MASK)
#define bfin_write_USB_OTG_VBUS_MASK(val) bfin_write16(USB_OTG_VBUS_MASK, val)
/* USB Phy Control Registers */
#define bfin_read_USB_LINKINFO() bfin_read16(USB_LINKINFO)
#define bfin_write_USB_LINKINFO(val) bfin_write16(USB_LINKINFO, val)
#define bfin_read_USB_VPLEN() bfin_read16(USB_VPLEN)
#define bfin_write_USB_VPLEN(val) bfin_write16(USB_VPLEN, val)
#define bfin_read_USB_HS_EOF1() bfin_read16(USB_HS_EOF1)
#define bfin_write_USB_HS_EOF1(val) bfin_write16(USB_HS_EOF1, val)
#define bfin_read_USB_FS_EOF1() bfin_read16(USB_FS_EOF1)
#define bfin_write_USB_FS_EOF1(val) bfin_write16(USB_FS_EOF1, val)
#define bfin_read_USB_LS_EOF1() bfin_read16(USB_LS_EOF1)
#define bfin_write_USB_LS_EOF1(val) bfin_write16(USB_LS_EOF1, val)
/* (APHY_CNTRL is for ADI usage only) */
#define bfin_read_USB_APHY_CNTRL() bfin_read16(USB_APHY_CNTRL)
#define bfin_write_USB_APHY_CNTRL(val) bfin_write16(USB_APHY_CNTRL, val)
/* (APHY_CALIB is for ADI usage only) */
#define bfin_read_USB_APHY_CALIB() bfin_read16(USB_APHY_CALIB)
#define bfin_write_USB_APHY_CALIB(val) bfin_write16(USB_APHY_CALIB, val)
#define bfin_read_USB_APHY_CNTRL2() bfin_read16(USB_APHY_CNTRL2)
#define bfin_write_USB_APHY_CNTRL2(val) bfin_write16(USB_APHY_CNTRL2, val)
/* (PHY_TEST is for ADI usage only) */
#define bfin_read_USB_PHY_TEST() bfin_read16(USB_PHY_TEST)
#define bfin_write_USB_PHY_TEST(val) bfin_write16(USB_PHY_TEST, val)
#define bfin_read_USB_PLLOSC_CTRL() bfin_read16(USB_PLLOSC_CTRL)
#define bfin_write_USB_PLLOSC_CTRL(val) bfin_write16(USB_PLLOSC_CTRL, val)
#define bfin_read_USB_SRP_CLKDIV() bfin_read16(USB_SRP_CLKDIV)
#define bfin_write_USB_SRP_CLKDIV(val) bfin_write16(USB_SRP_CLKDIV, val)
/* USB Endbfin_read_()oint 0 Control Registers */
#define bfin_read_USB_EP_NI0_TXMAXP() bfin_read16(USB_EP_NI0_TXMAXP)
#define bfin_write_USB_EP_NI0_TXMAXP(val) bfin_write16(USB_EP_NI0_TXMAXP, val)
#define bfin_read_USB_EP_NI0_TXCSR() bfin_read16(USB_EP_NI0_TXCSR)
#define bfin_write_USB_EP_NI0_TXCSR(val) bfin_write16(USB_EP_NI0_TXCSR, val)
#define bfin_read_USB_EP_NI0_RXMAXP() bfin_read16(USB_EP_NI0_RXMAXP)
#define bfin_write_USB_EP_NI0_RXMAXP(val) bfin_write16(USB_EP_NI0_RXMAXP, val)
#define bfin_read_USB_EP_NI0_RXCSR() bfin_read16(USB_EP_NI0_RXCSR)
#define bfin_write_USB_EP_NI0_RXCSR(val) bfin_write16(USB_EP_NI0_RXCSR, val)
#define bfin_read_USB_EP_NI0_RXCOUNT() bfin_read16(USB_EP_NI0_RXCOUNT)
#define bfin_write_USB_EP_NI0_RXCOUNT(val) bfin_write16(USB_EP_NI0_RXCOUNT, val)
#define bfin_read_USB_EP_NI0_TXTYPE() bfin_read16(USB_EP_NI0_TXTYPE)
#define bfin_write_USB_EP_NI0_TXTYPE(val) bfin_write16(USB_EP_NI0_TXTYPE, val)
#define bfin_read_USB_EP_NI0_TXINTERVAL() bfin_read16(USB_EP_NI0_TXINTERVAL)
#define bfin_write_USB_EP_NI0_TXINTERVAL(val) bfin_write16(USB_EP_NI0_TXINTERVAL, val)
#define bfin_read_USB_EP_NI0_RXTYPE() bfin_read16(USB_EP_NI0_RXTYPE)
#define bfin_write_USB_EP_NI0_RXTYPE(val) bfin_write16(USB_EP_NI0_RXTYPE, val)
#define bfin_read_USB_EP_NI0_RXINTERVAL() bfin_read16(USB_EP_NI0_RXINTERVAL)
#define bfin_write_USB_EP_NI0_RXINTERVAL(val) bfin_write16(USB_EP_NI0_RXINTERVAL, val)
/* USB Endbfin_read_()oint 1 Control Registers */
#define bfin_read_USB_EP_NI0_TXCOUNT() bfin_read16(USB_EP_NI0_TXCOUNT)
#define bfin_write_USB_EP_NI0_TXCOUNT(val) bfin_write16(USB_EP_NI0_TXCOUNT, val)
#define bfin_read_USB_EP_NI1_TXMAXP() bfin_read16(USB_EP_NI1_TXMAXP)
#define bfin_write_USB_EP_NI1_TXMAXP(val) bfin_write16(USB_EP_NI1_TXMAXP, val)
#define bfin_read_USB_EP_NI1_TXCSR() bfin_read16(USB_EP_NI1_TXCSR)
#define bfin_write_USB_EP_NI1_TXCSR(val) bfin_write16(USB_EP_NI1_TXCSR, val)
#define bfin_read_USB_EP_NI1_RXMAXP() bfin_read16(USB_EP_NI1_RXMAXP)
#define bfin_write_USB_EP_NI1_RXMAXP(val) bfin_write16(USB_EP_NI1_RXMAXP, val)
#define bfin_read_USB_EP_NI1_RXCSR() bfin_read16(USB_EP_NI1_RXCSR)
#define bfin_write_USB_EP_NI1_RXCSR(val) bfin_write16(USB_EP_NI1_RXCSR, val)
#define bfin_read_USB_EP_NI1_RXCOUNT() bfin_read16(USB_EP_NI1_RXCOUNT)
#define bfin_write_USB_EP_NI1_RXCOUNT(val) bfin_write16(USB_EP_NI1_RXCOUNT, val)
#define bfin_read_USB_EP_NI1_TXTYPE() bfin_read16(USB_EP_NI1_TXTYPE)
#define bfin_write_USB_EP_NI1_TXTYPE(val) bfin_write16(USB_EP_NI1_TXTYPE, val)
#define bfin_read_USB_EP_NI1_TXINTERVAL() bfin_read16(USB_EP_NI1_TXINTERVAL)
#define bfin_write_USB_EP_NI1_TXINTERVAL(val) bfin_write16(USB_EP_NI1_TXINTERVAL, val)
#define bfin_read_USB_EP_NI1_RXTYPE() bfin_read16(USB_EP_NI1_RXTYPE)
#define bfin_write_USB_EP_NI1_RXTYPE(val) bfin_write16(USB_EP_NI1_RXTYPE, val)
#define bfin_read_USB_EP_NI1_RXINTERVAL() bfin_read16(USB_EP_NI1_RXINTERVAL)
#define bfin_write_USB_EP_NI1_RXINTERVAL(val) bfin_write16(USB_EP_NI1_RXINTERVAL, val)
/* USB Endbfin_read_()oint 2 Control Registers */
#define bfin_read_USB_EP_NI1_TXCOUNT() bfin_read16(USB_EP_NI1_TXCOUNT)
#define bfin_write_USB_EP_NI1_TXCOUNT(val) bfin_write16(USB_EP_NI1_TXCOUNT, val)
#define bfin_read_USB_EP_NI2_TXMAXP() bfin_read16(USB_EP_NI2_TXMAXP)
#define bfin_write_USB_EP_NI2_TXMAXP(val) bfin_write16(USB_EP_NI2_TXMAXP, val)
#define bfin_read_USB_EP_NI2_TXCSR() bfin_read16(USB_EP_NI2_TXCSR)
#define bfin_write_USB_EP_NI2_TXCSR(val) bfin_write16(USB_EP_NI2_TXCSR, val)
#define bfin_read_USB_EP_NI2_RXMAXP() bfin_read16(USB_EP_NI2_RXMAXP)
#define bfin_write_USB_EP_NI2_RXMAXP(val) bfin_write16(USB_EP_NI2_RXMAXP, val)
#define bfin_read_USB_EP_NI2_RXCSR() bfin_read16(USB_EP_NI2_RXCSR)
#define bfin_write_USB_EP_NI2_RXCSR(val) bfin_write16(USB_EP_NI2_RXCSR, val)
#define bfin_read_USB_EP_NI2_RXCOUNT() bfin_read16(USB_EP_NI2_RXCOUNT)
#define bfin_write_USB_EP_NI2_RXCOUNT(val) bfin_write16(USB_EP_NI2_RXCOUNT, val)
#define bfin_read_USB_EP_NI2_TXTYPE() bfin_read16(USB_EP_NI2_TXTYPE)
#define bfin_write_USB_EP_NI2_TXTYPE(val) bfin_write16(USB_EP_NI2_TXTYPE, val)
#define bfin_read_USB_EP_NI2_TXINTERVAL() bfin_read16(USB_EP_NI2_TXINTERVAL)
#define bfin_write_USB_EP_NI2_TXINTERVAL(val) bfin_write16(USB_EP_NI2_TXINTERVAL, val)
#define bfin_read_USB_EP_NI2_RXTYPE() bfin_read16(USB_EP_NI2_RXTYPE)
#define bfin_write_USB_EP_NI2_RXTYPE(val) bfin_write16(USB_EP_NI2_RXTYPE, val)
#define bfin_read_USB_EP_NI2_RXINTERVAL() bfin_read16(USB_EP_NI2_RXINTERVAL)
#define bfin_write_USB_EP_NI2_RXINTERVAL(val) bfin_write16(USB_EP_NI2_RXINTERVAL, val)
/* USB Endbfin_read_()oint 3 Control Registers */
#define bfin_read_USB_EP_NI2_TXCOUNT() bfin_read16(USB_EP_NI2_TXCOUNT)
#define bfin_write_USB_EP_NI2_TXCOUNT(val) bfin_write16(USB_EP_NI2_TXCOUNT, val)
#define bfin_read_USB_EP_NI3_TXMAXP() bfin_read16(USB_EP_NI3_TXMAXP)
#define bfin_write_USB_EP_NI3_TXMAXP(val) bfin_write16(USB_EP_NI3_TXMAXP, val)
#define bfin_read_USB_EP_NI3_TXCSR() bfin_read16(USB_EP_NI3_TXCSR)
#define bfin_write_USB_EP_NI3_TXCSR(val) bfin_write16(USB_EP_NI3_TXCSR, val)
#define bfin_read_USB_EP_NI3_RXMAXP() bfin_read16(USB_EP_NI3_RXMAXP)
#define bfin_write_USB_EP_NI3_RXMAXP(val) bfin_write16(USB_EP_NI3_RXMAXP, val)
#define bfin_read_USB_EP_NI3_RXCSR() bfin_read16(USB_EP_NI3_RXCSR)
#define bfin_write_USB_EP_NI3_RXCSR(val) bfin_write16(USB_EP_NI3_RXCSR, val)
#define bfin_read_USB_EP_NI3_RXCOUNT() bfin_read16(USB_EP_NI3_RXCOUNT)
#define bfin_write_USB_EP_NI3_RXCOUNT(val) bfin_write16(USB_EP_NI3_RXCOUNT, val)
#define bfin_read_USB_EP_NI3_TXTYPE() bfin_read16(USB_EP_NI3_TXTYPE)
#define bfin_write_USB_EP_NI3_TXTYPE(val) bfin_write16(USB_EP_NI3_TXTYPE, val)
#define bfin_read_USB_EP_NI3_TXINTERVAL() bfin_read16(USB_EP_NI3_TXINTERVAL)
#define bfin_write_USB_EP_NI3_TXINTERVAL(val) bfin_write16(USB_EP_NI3_TXINTERVAL, val)
#define bfin_read_USB_EP_NI3_RXTYPE() bfin_read16(USB_EP_NI3_RXTYPE)
#define bfin_write_USB_EP_NI3_RXTYPE(val) bfin_write16(USB_EP_NI3_RXTYPE, val)
#define bfin_read_USB_EP_NI3_RXINTERVAL() bfin_read16(USB_EP_NI3_RXINTERVAL)
#define bfin_write_USB_EP_NI3_RXINTERVAL(val) bfin_write16(USB_EP_NI3_RXINTERVAL, val)
/* USB Endbfin_read_()oint 4 Control Registers */
#define bfin_read_USB_EP_NI3_TXCOUNT() bfin_read16(USB_EP_NI3_TXCOUNT)
#define bfin_write_USB_EP_NI3_TXCOUNT(val) bfin_write16(USB_EP_NI3_TXCOUNT, val)
#define bfin_read_USB_EP_NI4_TXMAXP() bfin_read16(USB_EP_NI4_TXMAXP)
#define bfin_write_USB_EP_NI4_TXMAXP(val) bfin_write16(USB_EP_NI4_TXMAXP, val)
#define bfin_read_USB_EP_NI4_TXCSR() bfin_read16(USB_EP_NI4_TXCSR)
#define bfin_write_USB_EP_NI4_TXCSR(val) bfin_write16(USB_EP_NI4_TXCSR, val)
#define bfin_read_USB_EP_NI4_RXMAXP() bfin_read16(USB_EP_NI4_RXMAXP)
#define bfin_write_USB_EP_NI4_RXMAXP(val) bfin_write16(USB_EP_NI4_RXMAXP, val)
#define bfin_read_USB_EP_NI4_RXCSR() bfin_read16(USB_EP_NI4_RXCSR)
#define bfin_write_USB_EP_NI4_RXCSR(val) bfin_write16(USB_EP_NI4_RXCSR, val)
#define bfin_read_USB_EP_NI4_RXCOUNT() bfin_read16(USB_EP_NI4_RXCOUNT)
#define bfin_write_USB_EP_NI4_RXCOUNT(val) bfin_write16(USB_EP_NI4_RXCOUNT, val)
#define bfin_read_USB_EP_NI4_TXTYPE() bfin_read16(USB_EP_NI4_TXTYPE)
#define bfin_write_USB_EP_NI4_TXTYPE(val) bfin_write16(USB_EP_NI4_TXTYPE, val)
#define bfin_read_USB_EP_NI4_TXINTERVAL() bfin_read16(USB_EP_NI4_TXINTERVAL)
#define bfin_write_USB_EP_NI4_TXINTERVAL(val) bfin_write16(USB_EP_NI4_TXINTERVAL, val)
#define bfin_read_USB_EP_NI4_RXTYPE() bfin_read16(USB_EP_NI4_RXTYPE)
#define bfin_write_USB_EP_NI4_RXTYPE(val) bfin_write16(USB_EP_NI4_RXTYPE, val)
#define bfin_read_USB_EP_NI4_RXINTERVAL() bfin_read16(USB_EP_NI4_RXINTERVAL)
#define bfin_write_USB_EP_NI4_RXINTERVAL(val) bfin_write16(USB_EP_NI4_RXINTERVAL, val)
/* USB Endbfin_read_()oint 5 Control Registers */
#define bfin_read_USB_EP_NI4_TXCOUNT() bfin_read16(USB_EP_NI4_TXCOUNT)
#define bfin_write_USB_EP_NI4_TXCOUNT(val) bfin_write16(USB_EP_NI4_TXCOUNT, val)
#define bfin_read_USB_EP_NI5_TXMAXP() bfin_read16(USB_EP_NI5_TXMAXP)
#define bfin_write_USB_EP_NI5_TXMAXP(val) bfin_write16(USB_EP_NI5_TXMAXP, val)
#define bfin_read_USB_EP_NI5_TXCSR() bfin_read16(USB_EP_NI5_TXCSR)
#define bfin_write_USB_EP_NI5_TXCSR(val) bfin_write16(USB_EP_NI5_TXCSR, val)
#define bfin_read_USB_EP_NI5_RXMAXP() bfin_read16(USB_EP_NI5_RXMAXP)
#define bfin_write_USB_EP_NI5_RXMAXP(val) bfin_write16(USB_EP_NI5_RXMAXP, val)
#define bfin_read_USB_EP_NI5_RXCSR() bfin_read16(USB_EP_NI5_RXCSR)
#define bfin_write_USB_EP_NI5_RXCSR(val) bfin_write16(USB_EP_NI5_RXCSR, val)
#define bfin_read_USB_EP_NI5_RXCOUNT() bfin_read16(USB_EP_NI5_RXCOUNT)
#define bfin_write_USB_EP_NI5_RXCOUNT(val) bfin_write16(USB_EP_NI5_RXCOUNT, val)
#define bfin_read_USB_EP_NI5_TXTYPE() bfin_read16(USB_EP_NI5_TXTYPE)
#define bfin_write_USB_EP_NI5_TXTYPE(val) bfin_write16(USB_EP_NI5_TXTYPE, val)
#define bfin_read_USB_EP_NI5_TXINTERVAL() bfin_read16(USB_EP_NI5_TXINTERVAL)
#define bfin_write_USB_EP_NI5_TXINTERVAL(val) bfin_write16(USB_EP_NI5_TXINTERVAL, val)
#define bfin_read_USB_EP_NI5_RXTYPE() bfin_read16(USB_EP_NI5_RXTYPE)
#define bfin_write_USB_EP_NI5_RXTYPE(val) bfin_write16(USB_EP_NI5_RXTYPE, val)
#define bfin_read_USB_EP_NI5_RXINTERVAL() bfin_read16(USB_EP_NI5_RXINTERVAL)
#define bfin_write_USB_EP_NI5_RXINTERVAL(val) bfin_write16(USB_EP_NI5_RXINTERVAL, val)
/* USB Endbfin_read_()oint 6 Control Registers */
#define bfin_read_USB_EP_NI5_TXCOUNT() bfin_read16(USB_EP_NI5_TXCOUNT)
#define bfin_write_USB_EP_NI5_TXCOUNT(val) bfin_write16(USB_EP_NI5_TXCOUNT, val)
#define bfin_read_USB_EP_NI6_TXMAXP() bfin_read16(USB_EP_NI6_TXMAXP)
#define bfin_write_USB_EP_NI6_TXMAXP(val) bfin_write16(USB_EP_NI6_TXMAXP, val)
#define bfin_read_USB_EP_NI6_TXCSR() bfin_read16(USB_EP_NI6_TXCSR)
#define bfin_write_USB_EP_NI6_TXCSR(val) bfin_write16(USB_EP_NI6_TXCSR, val)
#define bfin_read_USB_EP_NI6_RXMAXP() bfin_read16(USB_EP_NI6_RXMAXP)
#define bfin_write_USB_EP_NI6_RXMAXP(val) bfin_write16(USB_EP_NI6_RXMAXP, val)
#define bfin_read_USB_EP_NI6_RXCSR() bfin_read16(USB_EP_NI6_RXCSR)
#define bfin_write_USB_EP_NI6_RXCSR(val) bfin_write16(USB_EP_NI6_RXCSR, val)
#define bfin_read_USB_EP_NI6_RXCOUNT() bfin_read16(USB_EP_NI6_RXCOUNT)
#define bfin_write_USB_EP_NI6_RXCOUNT(val) bfin_write16(USB_EP_NI6_RXCOUNT, val)
#define bfin_read_USB_EP_NI6_TXTYPE() bfin_read16(USB_EP_NI6_TXTYPE)
#define bfin_write_USB_EP_NI6_TXTYPE(val) bfin_write16(USB_EP_NI6_TXTYPE, val)
#define bfin_read_USB_EP_NI6_TXINTERVAL() bfin_read16(USB_EP_NI6_TXINTERVAL)
#define bfin_write_USB_EP_NI6_TXINTERVAL(val) bfin_write16(USB_EP_NI6_TXINTERVAL, val)
#define bfin_read_USB_EP_NI6_RXTYPE() bfin_read16(USB_EP_NI6_RXTYPE)
#define bfin_write_USB_EP_NI6_RXTYPE(val) bfin_write16(USB_EP_NI6_RXTYPE, val)
#define bfin_read_USB_EP_NI6_RXINTERVAL() bfin_read16(USB_EP_NI6_RXINTERVAL)
#define bfin_write_USB_EP_NI6_RXINTERVAL(val) bfin_write16(USB_EP_NI6_RXINTERVAL, val)
/* USB Endbfin_read_()oint 7 Control Registers */
#define bfin_read_USB_EP_NI6_TXCOUNT() bfin_read16(USB_EP_NI6_TXCOUNT)
#define bfin_write_USB_EP_NI6_TXCOUNT(val) bfin_write16(USB_EP_NI6_TXCOUNT, val)
#define bfin_read_USB_EP_NI7_TXMAXP() bfin_read16(USB_EP_NI7_TXMAXP)
#define bfin_write_USB_EP_NI7_TXMAXP(val) bfin_write16(USB_EP_NI7_TXMAXP, val)
#define bfin_read_USB_EP_NI7_TXCSR() bfin_read16(USB_EP_NI7_TXCSR)
#define bfin_write_USB_EP_NI7_TXCSR(val) bfin_write16(USB_EP_NI7_TXCSR, val)
#define bfin_read_USB_EP_NI7_RXMAXP() bfin_read16(USB_EP_NI7_RXMAXP)
#define bfin_write_USB_EP_NI7_RXMAXP(val) bfin_write16(USB_EP_NI7_RXMAXP, val)
#define bfin_read_USB_EP_NI7_RXCSR() bfin_read16(USB_EP_NI7_RXCSR)
#define bfin_write_USB_EP_NI7_RXCSR(val) bfin_write16(USB_EP_NI7_RXCSR, val)
#define bfin_read_USB_EP_NI7_RXCOUNT() bfin_read16(USB_EP_NI7_RXCOUNT)
#define bfin_write_USB_EP_NI7_RXCOUNT(val) bfin_write16(USB_EP_NI7_RXCOUNT, val)
#define bfin_read_USB_EP_NI7_TXTYPE() bfin_read16(USB_EP_NI7_TXTYPE)
#define bfin_write_USB_EP_NI7_TXTYPE(val) bfin_write16(USB_EP_NI7_TXTYPE, val)
#define bfin_read_USB_EP_NI7_TXINTERVAL() bfin_read16(USB_EP_NI7_TXINTERVAL)
#define bfin_write_USB_EP_NI7_TXINTERVAL(val) bfin_write16(USB_EP_NI7_TXINTERVAL, val)
#define bfin_read_USB_EP_NI7_RXTYPE() bfin_read16(USB_EP_NI7_RXTYPE)
#define bfin_write_USB_EP_NI7_RXTYPE(val) bfin_write16(USB_EP_NI7_RXTYPE, val)
#define bfin_read_USB_EP_NI7_RXINTERVAL() bfin_read16(USB_EP_NI7_RXINTERVAL)
#define bfin_write_USB_EP_NI7_RXINTERVAL(val) bfin_write16(USB_EP_NI7_RXINTERVAL, val)
#define bfin_read_USB_EP_NI7_TXCOUNT() bfin_read16(USB_EP_NI7_TXCOUNT)
#define bfin_write_USB_EP_NI7_TXCOUNT(val) bfin_write16(USB_EP_NI7_TXCOUNT, val)
#define bfin_read_USB_DMA_INTERRUPT() bfin_read16(USB_DMA_INTERRUPT)
#define bfin_write_USB_DMA_INTERRUPT(val) bfin_write16(USB_DMA_INTERRUPT, val)
/* USB Channel 0 Config Registers */
#define bfin_read_USB_DMA0CONTROL() bfin_read16(USB_DMA0CONTROL)
#define bfin_write_USB_DMA0CONTROL(val) bfin_write16(USB_DMA0CONTROL, val)
#define bfin_read_USB_DMA0ADDRLOW() bfin_read16(USB_DMA0ADDRLOW)
#define bfin_write_USB_DMA0ADDRLOW(val) bfin_write16(USB_DMA0ADDRLOW, val)
#define bfin_read_USB_DMA0ADDRHIGH() bfin_read16(USB_DMA0ADDRHIGH)
#define bfin_write_USB_DMA0ADDRHIGH(val) bfin_write16(USB_DMA0ADDRHIGH, val)
#define bfin_read_USB_DMA0COUNTLOW() bfin_read16(USB_DMA0COUNTLOW)
#define bfin_write_USB_DMA0COUNTLOW(val) bfin_write16(USB_DMA0COUNTLOW, val)
#define bfin_read_USB_DMA0COUNTHIGH() bfin_read16(USB_DMA0COUNTHIGH)
#define bfin_write_USB_DMA0COUNTHIGH(val) bfin_write16(USB_DMA0COUNTHIGH, val)
/* USB Channel 1 Config Registers */
#define bfin_read_USB_DMA1CONTROL() bfin_read16(USB_DMA1CONTROL)
#define bfin_write_USB_DMA1CONTROL(val) bfin_write16(USB_DMA1CONTROL, val)
#define bfin_read_USB_DMA1ADDRLOW() bfin_read16(USB_DMA1ADDRLOW)
#define bfin_write_USB_DMA1ADDRLOW(val) bfin_write16(USB_DMA1ADDRLOW, val)
#define bfin_read_USB_DMA1ADDRHIGH() bfin_read16(USB_DMA1ADDRHIGH)
#define bfin_write_USB_DMA1ADDRHIGH(val) bfin_write16(USB_DMA1ADDRHIGH, val)
#define bfin_read_USB_DMA1COUNTLOW() bfin_read16(USB_DMA1COUNTLOW)
#define bfin_write_USB_DMA1COUNTLOW(val) bfin_write16(USB_DMA1COUNTLOW, val)
#define bfin_read_USB_DMA1COUNTHIGH() bfin_read16(USB_DMA1COUNTHIGH)
#define bfin_write_USB_DMA1COUNTHIGH(val) bfin_write16(USB_DMA1COUNTHIGH, val)
/* USB Channel 2 Config Registers */
#define bfin_read_USB_DMA2CONTROL() bfin_read16(USB_DMA2CONTROL)
#define bfin_write_USB_DMA2CONTROL(val) bfin_write16(USB_DMA2CONTROL, val)
#define bfin_read_USB_DMA2ADDRLOW() bfin_read16(USB_DMA2ADDRLOW)
#define bfin_write_USB_DMA2ADDRLOW(val) bfin_write16(USB_DMA2ADDRLOW, val)
#define bfin_read_USB_DMA2ADDRHIGH() bfin_read16(USB_DMA2ADDRHIGH)
#define bfin_write_USB_DMA2ADDRHIGH(val) bfin_write16(USB_DMA2ADDRHIGH, val)
#define bfin_read_USB_DMA2COUNTLOW() bfin_read16(USB_DMA2COUNTLOW)
#define bfin_write_USB_DMA2COUNTLOW(val) bfin_write16(USB_DMA2COUNTLOW, val)
#define bfin_read_USB_DMA2COUNTHIGH() bfin_read16(USB_DMA2COUNTHIGH)
#define bfin_write_USB_DMA2COUNTHIGH(val) bfin_write16(USB_DMA2COUNTHIGH, val)
/* USB Channel 3 Config Registers */
#define bfin_read_USB_DMA3CONTROL() bfin_read16(USB_DMA3CONTROL)
#define bfin_write_USB_DMA3CONTROL(val) bfin_write16(USB_DMA3CONTROL, val)
#define bfin_read_USB_DMA3ADDRLOW() bfin_read16(USB_DMA3ADDRLOW)
#define bfin_write_USB_DMA3ADDRLOW(val) bfin_write16(USB_DMA3ADDRLOW, val)
#define bfin_read_USB_DMA3ADDRHIGH() bfin_read16(USB_DMA3ADDRHIGH)
#define bfin_write_USB_DMA3ADDRHIGH(val) bfin_write16(USB_DMA3ADDRHIGH, val)
#define bfin_read_USB_DMA3COUNTLOW() bfin_read16(USB_DMA3COUNTLOW)
#define bfin_write_USB_DMA3COUNTLOW(val) bfin_write16(USB_DMA3COUNTLOW, val)
#define bfin_read_USB_DMA3COUNTHIGH() bfin_read16(USB_DMA3COUNTHIGH)
#define bfin_write_USB_DMA3COUNTHIGH(val) bfin_write16(USB_DMA3COUNTHIGH, val)
/* USB Channel 4 Config Registers */
#define bfin_read_USB_DMA4CONTROL() bfin_read16(USB_DMA4CONTROL)
#define bfin_write_USB_DMA4CONTROL(val) bfin_write16(USB_DMA4CONTROL, val)
#define bfin_read_USB_DMA4ADDRLOW() bfin_read16(USB_DMA4ADDRLOW)
#define bfin_write_USB_DMA4ADDRLOW(val) bfin_write16(USB_DMA4ADDRLOW, val)
#define bfin_read_USB_DMA4ADDRHIGH() bfin_read16(USB_DMA4ADDRHIGH)
#define bfin_write_USB_DMA4ADDRHIGH(val) bfin_write16(USB_DMA4ADDRHIGH, val)
#define bfin_read_USB_DMA4COUNTLOW() bfin_read16(USB_DMA4COUNTLOW)
#define bfin_write_USB_DMA4COUNTLOW(val) bfin_write16(USB_DMA4COUNTLOW, val)
#define bfin_read_USB_DMA4COUNTHIGH() bfin_read16(USB_DMA4COUNTHIGH)
#define bfin_write_USB_DMA4COUNTHIGH(val) bfin_write16(USB_DMA4COUNTHIGH, val)
/* USB Channel 5 Config Registers */
#define bfin_read_USB_DMA5CONTROL() bfin_read16(USB_DMA5CONTROL)
#define bfin_write_USB_DMA5CONTROL(val) bfin_write16(USB_DMA5CONTROL, val)
#define bfin_read_USB_DMA5ADDRLOW() bfin_read16(USB_DMA5ADDRLOW)
#define bfin_write_USB_DMA5ADDRLOW(val) bfin_write16(USB_DMA5ADDRLOW, val)
#define bfin_read_USB_DMA5ADDRHIGH() bfin_read16(USB_DMA5ADDRHIGH)
#define bfin_write_USB_DMA5ADDRHIGH(val) bfin_write16(USB_DMA5ADDRHIGH, val)
#define bfin_read_USB_DMA5COUNTLOW() bfin_read16(USB_DMA5COUNTLOW)
#define bfin_write_USB_DMA5COUNTLOW(val) bfin_write16(USB_DMA5COUNTLOW, val)
#define bfin_read_USB_DMA5COUNTHIGH() bfin_read16(USB_DMA5COUNTHIGH)
#define bfin_write_USB_DMA5COUNTHIGH(val) bfin_write16(USB_DMA5COUNTHIGH, val)
/* USB Channel 6 Config Registers */
#define bfin_read_USB_DMA6CONTROL() bfin_read16(USB_DMA6CONTROL)
#define bfin_write_USB_DMA6CONTROL(val) bfin_write16(USB_DMA6CONTROL, val)
#define bfin_read_USB_DMA6ADDRLOW() bfin_read16(USB_DMA6ADDRLOW)
#define bfin_write_USB_DMA6ADDRLOW(val) bfin_write16(USB_DMA6ADDRLOW, val)
#define bfin_read_USB_DMA6ADDRHIGH() bfin_read16(USB_DMA6ADDRHIGH)
#define bfin_write_USB_DMA6ADDRHIGH(val) bfin_write16(USB_DMA6ADDRHIGH, val)
#define bfin_read_USB_DMA6COUNTLOW() bfin_read16(USB_DMA6COUNTLOW)
#define bfin_write_USB_DMA6COUNTLOW(val) bfin_write16(USB_DMA6COUNTLOW, val)
#define bfin_read_USB_DMA6COUNTHIGH() bfin_read16(USB_DMA6COUNTHIGH)
#define bfin_write_USB_DMA6COUNTHIGH(val) bfin_write16(USB_DMA6COUNTHIGH, val)
/* USB Channel 7 Config Registers */
#define bfin_read_USB_DMA7CONTROL() bfin_read16(USB_DMA7CONTROL)
#define bfin_write_USB_DMA7CONTROL(val) bfin_write16(USB_DMA7CONTROL, val)
#define bfin_read_USB_DMA7ADDRLOW() bfin_read16(USB_DMA7ADDRLOW)
#define bfin_write_USB_DMA7ADDRLOW(val) bfin_write16(USB_DMA7ADDRLOW, val)
#define bfin_read_USB_DMA7ADDRHIGH() bfin_read16(USB_DMA7ADDRHIGH)
#define bfin_write_USB_DMA7ADDRHIGH(val) bfin_write16(USB_DMA7ADDRHIGH, val)
#define bfin_read_USB_DMA7COUNTLOW() bfin_read16(USB_DMA7COUNTLOW)
#define bfin_write_USB_DMA7COUNTLOW(val) bfin_write16(USB_DMA7COUNTLOW, val)
#define bfin_read_USB_DMA7COUNTHIGH() bfin_read16(USB_DMA7COUNTHIGH)
#define bfin_write_USB_DMA7COUNTHIGH(val) bfin_write16(USB_DMA7COUNTHIGH, val)
/* Keybfin_read_()ad Registers */
#define bfin_read_KPAD_CTL() bfin_read16(KPAD_CTL)
#define bfin_write_KPAD_CTL(val) bfin_write16(KPAD_CTL, val)
#define bfin_read_KPAD_PRESCALE() bfin_read16(KPAD_PRESCALE)
#define bfin_write_KPAD_PRESCALE(val) bfin_write16(KPAD_PRESCALE, val)
#define bfin_read_KPAD_MSEL() bfin_read16(KPAD_MSEL)
#define bfin_write_KPAD_MSEL(val) bfin_write16(KPAD_MSEL, val)
#define bfin_read_KPAD_ROWCOL() bfin_read16(KPAD_ROWCOL)
#define bfin_write_KPAD_ROWCOL(val) bfin_write16(KPAD_ROWCOL, val)
#define bfin_read_KPAD_STAT() bfin_read16(KPAD_STAT)
#define bfin_write_KPAD_STAT(val) bfin_write16(KPAD_STAT, val)
#define bfin_read_KPAD_SOFTEVAL() bfin_read16(KPAD_SOFTEVAL)
#define bfin_write_KPAD_SOFTEVAL(val) bfin_write16(KPAD_SOFTEVAL, val)
/* Pixel Combfin_read_()ositor (PIXC) Registers */
#define bfin_read_PIXC_CTL() bfin_read16(PIXC_CTL)
#define bfin_write_PIXC_CTL(val) bfin_write16(PIXC_CTL, val)
#define bfin_read_PIXC_PPL() bfin_read16(PIXC_PPL)
#define bfin_write_PIXC_PPL(val) bfin_write16(PIXC_PPL, val)
#define bfin_read_PIXC_LPF() bfin_read16(PIXC_LPF)
#define bfin_write_PIXC_LPF(val) bfin_write16(PIXC_LPF, val)
#define bfin_read_PIXC_AHSTART() bfin_read16(PIXC_AHSTART)
#define bfin_write_PIXC_AHSTART(val) bfin_write16(PIXC_AHSTART, val)
#define bfin_read_PIXC_AHEND() bfin_read16(PIXC_AHEND)
#define bfin_write_PIXC_AHEND(val) bfin_write16(PIXC_AHEND, val)
#define bfin_read_PIXC_AVSTART() bfin_read16(PIXC_AVSTART)
#define bfin_write_PIXC_AVSTART(val) bfin_write16(PIXC_AVSTART, val)
#define bfin_read_PIXC_AVEND() bfin_read16(PIXC_AVEND)
#define bfin_write_PIXC_AVEND(val) bfin_write16(PIXC_AVEND, val)
#define bfin_read_PIXC_ATRANSP() bfin_read16(PIXC_ATRANSP)
#define bfin_write_PIXC_ATRANSP(val) bfin_write16(PIXC_ATRANSP, val)
#define bfin_read_PIXC_BHSTART() bfin_read16(PIXC_BHSTART)
#define bfin_write_PIXC_BHSTART(val) bfin_write16(PIXC_BHSTART, val)
#define bfin_read_PIXC_BHEND() bfin_read16(PIXC_BHEND)
#define bfin_write_PIXC_BHEND(val) bfin_write16(PIXC_BHEND, val)
#define bfin_read_PIXC_BVSTART() bfin_read16(PIXC_BVSTART)
#define bfin_write_PIXC_BVSTART(val) bfin_write16(PIXC_BVSTART, val)
#define bfin_read_PIXC_BVEND() bfin_read16(PIXC_BVEND)
#define bfin_write_PIXC_BVEND(val) bfin_write16(PIXC_BVEND, val)
#define bfin_read_PIXC_BTRANSP() bfin_read16(PIXC_BTRANSP)
#define bfin_write_PIXC_BTRANSP(val) bfin_write16(PIXC_BTRANSP, val)
#define bfin_read_PIXC_INTRSTAT() bfin_read16(PIXC_INTRSTAT)
#define bfin_write_PIXC_INTRSTAT(val) bfin_write16(PIXC_INTRSTAT, val)
#define bfin_read_PIXC_RYCON() bfin_read32(PIXC_RYCON)
#define bfin_write_PIXC_RYCON(val) bfin_write32(PIXC_RYCON, val)
#define bfin_read_PIXC_GUCON() bfin_read32(PIXC_GUCON)
#define bfin_write_PIXC_GUCON(val) bfin_write32(PIXC_GUCON, val)
#define bfin_read_PIXC_BVCON() bfin_read32(PIXC_BVCON)
#define bfin_write_PIXC_BVCON(val) bfin_write32(PIXC_BVCON, val)
#define bfin_read_PIXC_CCBIAS() bfin_read32(PIXC_CCBIAS)
#define bfin_write_PIXC_CCBIAS(val) bfin_write32(PIXC_CCBIAS, val)
#define bfin_read_PIXC_TC() bfin_read32(PIXC_TC)
#define bfin_write_PIXC_TC(val) bfin_write32(PIXC_TC, val)
/* Handshake MDMA 0 Registers */
#define bfin_read_HMDMA0_CONTROL() bfin_read16(HMDMA0_CONTROL)
#define bfin_write_HMDMA0_CONTROL(val) bfin_write16(HMDMA0_CONTROL, val)
#define bfin_read_HMDMA0_ECINIT() bfin_read16(HMDMA0_ECINIT)
#define bfin_write_HMDMA0_ECINIT(val) bfin_write16(HMDMA0_ECINIT, val)
#define bfin_read_HMDMA0_BCINIT() bfin_read16(HMDMA0_BCINIT)
#define bfin_write_HMDMA0_BCINIT(val) bfin_write16(HMDMA0_BCINIT, val)
#define bfin_read_HMDMA0_ECURGENT() bfin_read16(HMDMA0_ECURGENT)
#define bfin_write_HMDMA0_ECURGENT(val) bfin_write16(HMDMA0_ECURGENT, val)
#define bfin_read_HMDMA0_ECOVERFLOW() bfin_read16(HMDMA0_ECOVERFLOW)
#define bfin_write_HMDMA0_ECOVERFLOW(val) bfin_write16(HMDMA0_ECOVERFLOW, val)
#define bfin_read_HMDMA0_ECOUNT() bfin_read16(HMDMA0_ECOUNT)
#define bfin_write_HMDMA0_ECOUNT(val) bfin_write16(HMDMA0_ECOUNT, val)
#define bfin_read_HMDMA0_BCOUNT() bfin_read16(HMDMA0_BCOUNT)
#define bfin_write_HMDMA0_BCOUNT(val) bfin_write16(HMDMA0_BCOUNT, val)
/* Handshake MDMA 1 Registers */
#define bfin_read_HMDMA1_CONTROL() bfin_read16(HMDMA1_CONTROL)
#define bfin_write_HMDMA1_CONTROL(val) bfin_write16(HMDMA1_CONTROL, val)
#define bfin_read_HMDMA1_ECINIT() bfin_read16(HMDMA1_ECINIT)
#define bfin_write_HMDMA1_ECINIT(val) bfin_write16(HMDMA1_ECINIT, val)
#define bfin_read_HMDMA1_BCINIT() bfin_read16(HMDMA1_BCINIT)
#define bfin_write_HMDMA1_BCINIT(val) bfin_write16(HMDMA1_BCINIT, val)
#define bfin_read_HMDMA1_ECURGENT() bfin_read16(HMDMA1_ECURGENT)
#define bfin_write_HMDMA1_ECURGENT(val) bfin_write16(HMDMA1_ECURGENT, val)
#define bfin_read_HMDMA1_ECOVERFLOW() bfin_read16(HMDMA1_ECOVERFLOW)
#define bfin_write_HMDMA1_ECOVERFLOW(val) bfin_write16(HMDMA1_ECOVERFLOW, val)
#define bfin_read_HMDMA1_ECOUNT() bfin_read16(HMDMA1_ECOUNT)
#define bfin_write_HMDMA1_ECOUNT(val) bfin_write16(HMDMA1_ECOUNT, val)
#define bfin_read_HMDMA1_BCOUNT() bfin_read16(HMDMA1_BCOUNT)
#define bfin_write_HMDMA1_BCOUNT(val) bfin_write16(HMDMA1_BCOUNT, val)
#endif /* _CDEF_BF548_H */
include/asm-blackfin/mach-bf548/defBF547.h 0 → 100644
View file @ 04a94bab
/*
* File: include/asm-blackfin/mach-bf548/defBF547.h
* Based on:
* Author:
*
* Created:
* Description:
*
* Rev:
*
* Modified:
*
* Bugs: Enter bugs at http://blackfin.uclinux.org/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; see the file COPYING.
* If not, write to the Free Software Foundation,
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
#ifndef _DEF_BF548_H
#define _DEF_BF548_H
/* Include all Core registers and bit definitions */
#include <asm/mach-common/def_LPBlackfin.h>
/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF548 */
/* Include defBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */
#include "defBF54x_base.h"
/* The following are the #defines needed by ADSP-BF548 that are not in the common header */
/* Timer Registers */
#define TIMER8_CONFIG 0xffc00600 /* Timer 8 Configuration Register */
#define TIMER8_COUNTER 0xffc00604 /* Timer 8 Counter Register */
#define TIMER8_PERIOD 0xffc00608 /* Timer 8 Period Register */
#define TIMER8_WIDTH 0xffc0060c /* Timer 8 Width Register */
#define TIMER9_CONFIG 0xffc00610 /* Timer 9 Configuration Register */
#define TIMER9_COUNTER 0xffc00614 /* Timer 9 Counter Register */
#define TIMER9_PERIOD 0xffc00618 /* Timer 9 Period Register */
#define TIMER9_WIDTH 0xffc0061c /* Timer 9 Width Register */
#define TIMER10_CONFIG 0xffc00620 /* Timer 10 Configuration Register */
#define TIMER10_COUNTER 0xffc00624 /* Timer 10 Counter Register */
#define TIMER10_PERIOD 0xffc00628 /* Timer 10 Period Register */
#define TIMER10_WIDTH 0xffc0062c /* Timer 10 Width Register */
/* Timer Group of 3 Registers */
#define TIMER_ENABLE1 0xffc00640 /* Timer Group of 3 Enable Register */
#define TIMER_DISABLE1 0xffc00644 /* Timer Group of 3 Disable Register */
#define TIMER_STATUS1 0xffc00648 /* Timer Group of 3 Status Register */
/* SPORT0 Registers */
#define SPORT0_TCR1 0xffc00800 /* SPORT0 Transmit Configuration 1 Register */
#define SPORT0_TCR2 0xffc00804 /* SPORT0 Transmit Configuration 2 Register */
#define SPORT0_TCLKDIV 0xffc00808 /* SPORT0 Transmit Serial Clock Divider Register */
#define SPORT0_TFSDIV 0xffc0080c /* SPORT0 Transmit Frame Sync Divider Register */
#define SPORT0_TX 0xffc00810 /* SPORT0 Transmit Data Register */
#define SPORT0_RX 0xffc00818 /* SPORT0 Receive Data Register */
#define SPORT0_RCR1 0xffc00820 /* SPORT0 Receive Configuration 1 Register */
#define SPORT0_RCR2 0xffc00824 /* SPORT0 Receive Configuration 2 Register */
#define SPORT0_RCLKDIV 0xffc00828 /* SPORT0 Receive Serial Clock Divider Register */
#define SPORT0_RFSDIV 0xffc0082c /* SPORT0 Receive Frame Sync Divider Register */
#define SPORT0_STAT 0xffc00830 /* SPORT0 Status Register */
#define SPORT0_CHNL 0xffc00834 /* SPORT0 Current Channel Register */
#define SPORT0_MCMC1 0xffc00838 /* SPORT0 Multi channel Configuration Register 1 */
#define SPORT0_MCMC2 0xffc0083c /* SPORT0 Multi channel Configuration Register 2 */
#define SPORT0_MTCS0 0xffc00840 /* SPORT0 Multi channel Transmit Select Register 0 */
#define SPORT0_MTCS1 0xffc00844 /* SPORT0 Multi channel Transmit Select Register 1 */
#define SPORT0_MTCS2 0xffc00848 /* SPORT0 Multi channel Transmit Select Register 2 */
#define SPORT0_MTCS3 0xffc0084c /* SPORT0 Multi channel Transmit Select Register 3 */
#define SPORT0_MRCS0 0xffc00850 /* SPORT0 Multi channel Receive Select Register 0 */
#define SPORT0_MRCS1 0xffc00854 /* SPORT0 Multi channel Receive Select Register 1 */
#define SPORT0_MRCS2 0xffc00858 /* SPORT0 Multi channel Receive Select Register 2 */
#define SPORT0_MRCS3 0xffc0085c /* SPORT0 Multi channel Receive Select Register 3 */
/* EPPI0 Registers */
#define EPPI0_STATUS 0xffc01000 /* EPPI0 Status Register */
#define EPPI0_HCOUNT 0xffc01004 /* EPPI0 Horizontal Transfer Count Register */
#define EPPI0_HDELAY 0xffc01008 /* EPPI0 Horizontal Delay Count Register */
#define EPPI0_VCOUNT 0xffc0100c /* EPPI0 Vertical Transfer Count Register */
#define EPPI0_VDELAY 0xffc01010 /* EPPI0 Vertical Delay Count Register */
#define EPPI0_FRAME 0xffc01014 /* EPPI0 Lines per Frame Register */
#define EPPI0_LINE 0xffc01018 /* EPPI0 Samples per Line Register */
#define EPPI0_CLKDIV 0xffc0101c /* EPPI0 Clock Divide Register */
#define EPPI0_CONTROL 0xffc01020 /* EPPI0 Control Register */
#define EPPI0_FS1W_HBL 0xffc01024 /* EPPI0 FS1 Width Register / EPPI0 Horizontal Blanking Samples Per Line Register */
#define EPPI0_FS1P_AVPL 0xffc01028 /* EPPI0 FS1 Period Register / EPPI0 Active Video Samples Per Line Register */
#define EPPI0_FS2W_LVB 0xffc0102c /* EPPI0 FS2 Width Register / EPPI0 Lines of Vertical Blanking Register */
#define EPPI0_FS2P_LAVF 0xffc01030 /* EPPI0 FS2 Period Register/ EPPI0 Lines of Active Video Per Field Register */
#define EPPI0_CLIP 0xffc01034 /* EPPI0 Clipping Register */
/* UART2 Registers */
#define UART2_DLL 0xffc02100 /* Divisor Latch Low Byte */
#define UART2_DLH 0xffc02104 /* Divisor Latch High Byte */
#define UART2_GCTL 0xffc02108 /* Global Control Register */
#define UART2_LCR 0xffc0210c /* Line Control Register */
#define UART2_MCR 0xffc02110 /* Modem Control Register */
#define UART2_LSR 0xffc02114 /* Line Status Register */
#define UART2_MSR 0xffc02118 /* Modem Status Register */
#define UART2_SCR 0xffc0211c /* Scratch Register */
#define UART2_IER_SET 0xffc02120 /* Interrupt Enable Register Set */
#define UART2_IER_CLEAR 0xffc02124 /* Interrupt Enable Register Clear */
#define UART2_RBR 0xffc0212c /* Receive Buffer Register */
/* Two Wire Interface Registers (TWI1) */
#define TWI1_REGBASE 0xffc02200
#define TWI1_CLKDIV 0xffc02200 /* Clock Divider Register */
#define TWI1_CONTROL 0xffc02204 /* TWI Control Register */
#define TWI1_SLAVE_CTRL 0xffc02208 /* TWI Slave Mode Control Register */
#define TWI1_SLAVE_STAT 0xffc0220c /* TWI Slave Mode Status Register */
#define TWI1_SLAVE_ADDR 0xffc02210 /* TWI Slave Mode Address Register */
#define TWI1_MASTER_CTRL 0xffc02214 /* TWI Master Mode Control Register */
#define TWI1_MASTER_STAT 0xffc02218 /* TWI Master Mode Status Register */
#define TWI1_MASTER_ADDR 0xffc0221c /* TWI Master Mode Address Register */
#define TWI1_INT_STAT 0xffc02220 /* TWI Interrupt Status Register */
#define TWI1_INT_MASK 0xffc02224 /* TWI Interrupt Mask Register */
#define TWI1_FIFO_CTRL 0xffc02228 /* TWI FIFO Control Register */
#define TWI1_FIFO_STAT 0xffc0222c /* TWI FIFO Status Register */
#define TWI1_XMT_DATA8 0xffc02280 /* TWI FIFO Transmit Data Single Byte Register */
#define TWI1_XMT_DATA16 0xffc02284 /* TWI FIFO Transmit Data Double Byte Register */
#define TWI1_RCV_DATA8 0xffc02288 /* TWI FIFO Receive Data Single Byte Register */
#define TWI1_RCV_DATA16 0xffc0228c /* TWI FIFO Receive Data Double Byte Register */
/* SPI2 Registers */
#define SPI2_REGBASE 0xffc02400
#define SPI2_CTL 0xffc02400 /* SPI2 Control Register */
#define SPI2_FLG 0xffc02404 /* SPI2 Flag Register */
#define SPI2_STAT 0xffc02408 /* SPI2 Status Register */
#define SPI2_TDBR 0xffc0240c /* SPI2 Transmit Data Buffer Register */
#define SPI2_RDBR 0xffc02410 /* SPI2 Receive Data Buffer Register */
#define SPI2_BAUD 0xffc02414 /* SPI2 Baud Rate Register */
#define SPI2_SHADOW 0xffc02418 /* SPI2 Receive Data Buffer Shadow Register */
/* ATAPI Registers */
#define ATAPI_CONTROL 0xffc03800 /* ATAPI Control Register */
#define ATAPI_STATUS 0xffc03804 /* ATAPI Status Register */
#define ATAPI_DEV_ADDR 0xffc03808 /* ATAPI Device Register Address */
#define ATAPI_DEV_TXBUF 0xffc0380c /* ATAPI Device Register Write Data */
#define ATAPI_DEV_RXBUF 0xffc03810 /* ATAPI Device Register Read Data */
#define ATAPI_INT_MASK 0xffc03814 /* ATAPI Interrupt Mask Register */
#define ATAPI_INT_STATUS 0xffc03818 /* ATAPI Interrupt Status Register */
#define ATAPI_XFER_LEN 0xffc0381c /* ATAPI Length of Transfer */
#define ATAPI_LINE_STATUS 0xffc03820 /* ATAPI Line Status */
#define ATAPI_SM_STATE 0xffc03824 /* ATAPI State Machine Status */
#define ATAPI_TERMINATE 0xffc03828 /* ATAPI Host Terminate */
#define ATAPI_PIO_TFRCNT 0xffc0382c /* ATAPI PIO mode transfer count */
#define ATAPI_DMA_TFRCNT 0xffc03830 /* ATAPI DMA mode transfer count */
#define ATAPI_UMAIN_TFRCNT 0xffc03834 /* ATAPI UDMAIN transfer count */
#define ATAPI_UDMAOUT_TFRCNT 0xffc03838 /* ATAPI UDMAOUT transfer count */
#define ATAPI_REG_TIM_0 0xffc03840 /* ATAPI Register Transfer Timing 0 */
#define ATAPI_PIO_TIM_0 0xffc03844 /* ATAPI PIO Timing 0 Register */
#define ATAPI_PIO_TIM_1 0xffc03848 /* ATAPI PIO Timing 1 Register */
#define ATAPI_MULTI_TIM_0 0xffc03850 /* ATAPI Multi-DMA Timing 0 Register */
#define ATAPI_MULTI_TIM_1 0xffc03854 /* ATAPI Multi-DMA Timing 1 Register */
#define ATAPI_MULTI_TIM_2 0xffc03858 /* ATAPI Multi-DMA Timing 2 Register */
#define ATAPI_ULTRA_TIM_0 0xffc03860 /* ATAPI Ultra-DMA Timing 0 Register */
#define ATAPI_ULTRA_TIM_1 0xffc03864 /* ATAPI Ultra-DMA Timing 1 Register */
#define ATAPI_ULTRA_TIM_2 0xffc03868 /* ATAPI Ultra-DMA Timing 2 Register */
#define ATAPI_ULTRA_TIM_3 0xffc0386c /* ATAPI Ultra-DMA Timing 3 Register */
/* SDH Registers */
#define SDH_PWR_CTL 0xffc03900 /* SDH Power Control */
#define SDH_CLK_CTL 0xffc03904 /* SDH Clock Control */
#define SDH_ARGUMENT 0xffc03908 /* SDH Argument */
#define SDH_COMMAND 0xffc0390c /* SDH Command */
#define SDH_RESP_CMD 0xffc03910 /* SDH Response Command */
#define SDH_RESPONSE0 0xffc03914 /* SDH Response0 */
#define SDH_RESPONSE1 0xffc03918 /* SDH Response1 */
#define SDH_RESPONSE2 0xffc0391c /* SDH Response2 */
#define SDH_RESPONSE3 0xffc03920 /* SDH Response3 */
#define SDH_DATA_TIMER 0xffc03924 /* SDH Data Timer */
#define SDH_DATA_LGTH 0xffc03928 /* SDH Data Length */
#define SDH_DATA_CTL 0xffc0392c /* SDH Data Control */
#define SDH_DATA_CNT 0xffc03930 /* SDH Data Counter */
#define SDH_STATUS 0xffc03934 /* SDH Status */
#define SDH_STATUS_CLR 0xffc03938 /* SDH Status Clear */
#define SDH_MASK0 0xffc0393c /* SDH Interrupt0 Mask */
#define SDH_MASK1 0xffc03940 /* SDH Interrupt1 Mask */
#define SDH_FIFO_CNT 0xffc03948 /* SDH FIFO Counter */
#define SDH_FIFO 0xffc03980 /* SDH Data FIFO */
#define SDH_E_STATUS 0xffc039c0 /* SDH Exception Status */
#define SDH_E_MASK 0xffc039c4 /* SDH Exception Mask */
#define SDH_CFG 0xffc039c8 /* SDH Configuration */
#define SDH_RD_WAIT_EN 0xffc039cc /* SDH Read Wait Enable */
#define SDH_PID0 0xffc039d0 /* SDH Peripheral Identification0 */
#define SDH_PID1 0xffc039d4 /* SDH Peripheral Identification1 */
#define SDH_PID2 0xffc039d8 /* SDH Peripheral Identification2 */
#define SDH_PID3 0xffc039dc /* SDH Peripheral Identification3 */
#define SDH_PID4 0xffc039e0 /* SDH Peripheral Identification4 */
#define SDH_PID5 0xffc039e4 /* SDH Peripheral Identification5 */
#define SDH_PID6 0xffc039e8 /* SDH Peripheral Identification6 */
#define SDH_PID7 0xffc039ec /* SDH Peripheral Identification7 */
/* HOST Port Registers */
#define HOST_CONTROL 0xffc03a00 /* HOST Control Register */
#define HOST_STATUS 0xffc03a04 /* HOST Status Register */
#define HOST_TIMEOUT 0xffc03a08 /* HOST Acknowledge Mode Timeout Register */
/* USB Control Registers */
#define USB_FADDR 0xffc03c00 /* Function address register */
#define USB_POWER 0xffc03c04 /* Power management register */
#define USB_INTRTX 0xffc03c08 /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */
#define USB_INTRRX 0xffc03c0c /* Interrupt register for Rx endpoints 1 to 7 */
#define USB_INTRTXE 0xffc03c10 /* Interrupt enable register for IntrTx */
#define USB_INTRRXE 0xffc03c14 /* Interrupt enable register for IntrRx */
#define USB_INTRUSB 0xffc03c18 /* Interrupt register for common USB interrupts */
#define USB_INTRUSBE 0xffc03c1c /* Interrupt enable register for IntrUSB */
#define USB_FRAME 0xffc03c20 /* USB frame number */
#define USB_INDEX 0xffc03c24 /* Index register for selecting the indexed endpoint registers */
#define USB_TESTMODE 0xffc03c28 /* Enabled USB 20 test modes */
#define USB_GLOBINTR 0xffc03c2c /* Global Interrupt Mask register and Wakeup Exception Interrupt */
#define USB_GLOBAL_CTL 0xffc03c30 /* Global Clock Control for the core */
/* USB Packet Control Registers */
#define USB_TX_MAX_PACKET 0xffc03c40 /* Maximum packet size for Host Tx endpoint */
#define USB_CSR0 0xffc03c44 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
#define USB_TXCSR 0xffc03c44 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
#define USB_RX_MAX_PACKET 0xffc03c48 /* Maximum packet size for Host Rx endpoint */
#define USB_RXCSR 0xffc03c4c /* Control Status register for Host Rx endpoint */
#define USB_COUNT0 0xffc03c50 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
#define USB_RXCOUNT 0xffc03c50 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
#define USB_TXTYPE 0xffc03c54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */
#define USB_NAKLIMIT0 0xffc03c58 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
#define USB_TXINTERVAL 0xffc03c58 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
#define USB_RXTYPE 0xffc03c5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */
#define USB_RXINTERVAL 0xffc03c60 /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */
#define USB_TXCOUNT 0xffc03c68 /* Number of bytes to be written to the selected endpoint Tx FIFO */
/* USB Endpoint FIFO Registers */
#define USB_EP0_FIFO 0xffc03c80 /* Endpoint 0 FIFO */
#define USB_EP1_FIFO 0xffc03c88 /* Endpoint 1 FIFO */
#define USB_EP2_FIFO 0xffc03c90 /* Endpoint 2 FIFO */
#define USB_EP3_FIFO 0xffc03c98 /* Endpoint 3 FIFO */
#define USB_EP4_FIFO 0xffc03ca0 /* Endpoint 4 FIFO */
#define USB_EP5_FIFO 0xffc03ca8 /* Endpoint 5 FIFO */
#define USB_EP6_FIFO 0xffc03cb0 /* Endpoint 6 FIFO */
#define USB_EP7_FIFO 0xffc03cb8 /* Endpoint 7 FIFO */
/* USB OTG Control Registers */
#define USB_OTG_DEV_CTL 0xffc03d00 /* OTG Device Control Register */
#define USB_OTG_VBUS_IRQ 0xffc03d04 /* OTG VBUS Control Interrupts */
#define USB_OTG_VBUS_MASK 0xffc03d08 /* VBUS Control Interrupt Enable */
/* USB Phy Control Registers */
#define USB_LINKINFO 0xffc03d48 /* Enables programming of some PHY-side delays */
#define USB_VPLEN 0xffc03d4c /* Determines duration of VBUS pulse for VBUS charging */
#define USB_HS_EOF1 0xffc03d50 /* Time buffer for High-Speed transactions */
#define USB_FS_EOF1 0xffc03d54 /* Time buffer for Full-Speed transactions */
#define USB_LS_EOF1 0xffc03d58 /* Time buffer for Low-Speed transactions */
/* (APHY_CNTRL is for ADI usage only) */
#define USB_APHY_CNTRL 0xffc03de0 /* Register that increases visibility of Analog PHY */
/* (APHY_CALIB is for ADI usage only) */
#define USB_APHY_CALIB 0xffc03de4 /* Register used to set some calibration values */
#define USB_APHY_CNTRL2 0xffc03de8 /* Register used to prevent re-enumeration once Moab goes into hibernate mode */
/* (PHY_TEST is for ADI usage only) */
#define USB_PHY_TEST 0xffc03dec /* Used for reducing simulation time and simplifies FIFO testability */
#define USB_PLLOSC_CTRL 0xffc03df0 /* Used to program different parameters for USB PLL and Oscillator */
#define USB_SRP_CLKDIV 0xffc03df4 /* Used to program clock divide value for the clock fed to the SRP detection logic */
/* USB Endpoint 0 Control Registers */
#define USB_EP_NI0_TXMAXP 0xffc03e00 /* Maximum packet size for Host Tx endpoint0 */
#define USB_EP_NI0_TXCSR 0xffc03e04 /* Control Status register for endpoint 0 */
#define USB_EP_NI0_RXMAXP 0xffc03e08 /* Maximum packet size for Host Rx endpoint0 */
#define USB_EP_NI0_RXCSR 0xffc03e0c /* Control Status register for Host Rx endpoint0 */
#define USB_EP_NI0_RXCOUNT 0xffc03e10 /* Number of bytes received in endpoint 0 FIFO */
#define USB_EP_NI0_TXTYPE 0xffc03e14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */
#define USB_EP_NI0_TXINTERVAL 0xffc03e18 /* Sets the NAK response timeout on Endpoint 0 */
#define USB_EP_NI0_RXTYPE 0xffc03e1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */
#define USB_EP_NI0_RXINTERVAL 0xffc03e20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */
/* USB Endpoint 1 Control Registers */
#define USB_EP_NI0_TXCOUNT 0xffc03e28 /* Number of bytes to be written to the endpoint0 Tx FIFO */
#define USB_EP_NI1_TXMAXP 0xffc03e40 /* Maximum packet size for Host Tx endpoint1 */
#define USB_EP_NI1_TXCSR 0xffc03e44 /* Control Status register for endpoint1 */
#define USB_EP_NI1_RXMAXP 0xffc03e48 /* Maximum packet size for Host Rx endpoint1 */
#define USB_EP_NI1_RXCSR 0xffc03e4c /* Control Status register for Host Rx endpoint1 */
#define USB_EP_NI1_RXCOUNT 0xffc03e50 /* Number of bytes received in endpoint1 FIFO */
#define USB_EP_NI1_TXTYPE 0xffc03e54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */
#define USB_EP_NI1_TXINTERVAL 0xffc03e58 /* Sets the NAK response timeout on Endpoint1 */
#define USB_EP_NI1_RXTYPE 0xffc03e5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */
#define USB_EP_NI1_RXINTERVAL 0xffc03e60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */
/* USB Endpoint 2 Control Registers */
#define USB_EP_NI1_TXCOUNT 0xffc03e68 /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */
#define USB_EP_NI2_TXMAXP 0xffc03e80 /* Maximum packet size for Host Tx endpoint2 */
#define USB_EP_NI2_TXCSR 0xffc03e84 /* Control Status register for endpoint2 */
#define USB_EP_NI2_RXMAXP 0xffc03e88 /* Maximum packet size for Host Rx endpoint2 */
#define USB_EP_NI2_RXCSR 0xffc03e8c /* Control Status register for Host Rx endpoint2 */
#define USB_EP_NI2_RXCOUNT 0xffc03e90 /* Number of bytes received in endpoint2 FIFO */
#define USB_EP_NI2_TXTYPE 0xffc03e94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */
#define USB_EP_NI2_TXINTERVAL 0xffc03e98 /* Sets the NAK response timeout on Endpoint2 */
#define USB_EP_NI2_RXTYPE 0xffc03e9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */
#define USB_EP_NI2_RXINTERVAL 0xffc03ea0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */
/* USB Endpoint 3 Control Registers */
#define USB_EP_NI2_TXCOUNT 0xffc03ea8 /* Number of bytes to be written to the endpoint2 Tx FIFO */
#define USB_EP_NI3_TXMAXP 0xffc03ec0 /* Maximum packet size for Host Tx endpoint3 */
#define USB_EP_NI3_TXCSR 0xffc03ec4 /* Control Status register for endpoint3 */
#define USB_EP_NI3_RXMAXP 0xffc03ec8 /* Maximum packet size for Host Rx endpoint3 */
#define USB_EP_NI3_RXCSR 0xffc03ecc /* Control Status register for Host Rx endpoint3 */
#define USB_EP_NI3_RXCOUNT 0xffc03ed0 /* Number of bytes received in endpoint3 FIFO */
#define USB_EP_NI3_TXTYPE 0xffc03ed4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */
#define USB_EP_NI3_TXINTERVAL 0xffc03ed8 /* Sets the NAK response timeout on Endpoint3 */
#define USB_EP_NI3_RXTYPE 0xffc03edc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */
#define USB_EP_NI3_RXINTERVAL 0xffc03ee0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */
/* USB Endpoint 4 Control Registers */
#define USB_EP_NI3_TXCOUNT 0xffc03ee8 /* Number of bytes to be written to the H124endpoint3 Tx FIFO */
#define USB_EP_NI4_TXMAXP 0xffc03f00 /* Maximum packet size for Host Tx endpoint4 */
#define USB_EP_NI4_TXCSR 0xffc03f04 /* Control Status register for endpoint4 */
#define USB_EP_NI4_RXMAXP 0xffc03f08 /* Maximum packet size for Host Rx endpoint4 */
#define USB_EP_NI4_RXCSR 0xffc03f0c /* Control Status register for Host Rx endpoint4 */
#define USB_EP_NI4_RXCOUNT 0xffc03f10 /* Number of bytes received in endpoint4 FIFO */
#define USB_EP_NI4_TXTYPE 0xffc03f14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */
#define USB_EP_NI4_TXINTERVAL 0xffc03f18 /* Sets the NAK response timeout on Endpoint4 */
#define USB_EP_NI4_RXTYPE 0xffc03f1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */
#define USB_EP_NI4_RXINTERVAL 0xffc03f20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */
/* USB Endpoint 5 Control Registers */
#define USB_EP_NI4_TXCOUNT 0xffc03f28 /* Number of bytes to be written to the endpoint4 Tx FIFO */
#define USB_EP_NI5_TXMAXP 0xffc03f40 /* Maximum packet size for Host Tx endpoint5 */
#define USB_EP_NI5_TXCSR 0xffc03f44 /* Control Status register for endpoint5 */
#define USB_EP_NI5_RXMAXP 0xffc03f48 /* Maximum packet size for Host Rx endpoint5 */
#define USB_EP_NI5_RXCSR 0xffc03f4c /* Control Status register for Host Rx endpoint5 */
#define USB_EP_NI5_RXCOUNT 0xffc03f50 /* Number of bytes received in endpoint5 FIFO */
#define USB_EP_NI5_TXTYPE 0xffc03f54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */
#define USB_EP_NI5_TXINTERVAL 0xffc03f58 /* Sets the NAK response timeout on Endpoint5 */
#define USB_EP_NI5_RXTYPE 0xffc03f5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */
#define USB_EP_NI5_RXINTERVAL 0xffc03f60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */
/* USB Endpoint 6 Control Registers */
#define USB_EP_NI5_TXCOUNT 0xffc03f68 /* Number of bytes to be written to the H145endpoint5 Tx FIFO */
#define USB_EP_NI6_TXMAXP 0xffc03f80 /* Maximum packet size for Host Tx endpoint6 */
#define USB_EP_NI6_TXCSR 0xffc03f84 /* Control Status register for endpoint6 */
#define USB_EP_NI6_RXMAXP 0xffc03f88 /* Maximum packet size for Host Rx endpoint6 */
#define USB_EP_NI6_RXCSR 0xffc03f8c /* Control Status register for Host Rx endpoint6 */
#define USB_EP_NI6_RXCOUNT 0xffc03f90 /* Number of bytes received in endpoint6 FIFO */
#define USB_EP_NI6_TXTYPE 0xffc03f94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */
#define USB_EP_NI6_TXINTERVAL 0xffc03f98 /* Sets the NAK response timeout on Endpoint6 */
#define USB_EP_NI6_RXTYPE 0xffc03f9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */
#define USB_EP_NI6_RXINTERVAL 0xffc03fa0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */
/* USB Endpoint 7 Control Registers */
#define USB_EP_NI6_TXCOUNT 0xffc03fa8 /* Number of bytes to be written to the endpoint6 Tx FIFO */
#define USB_EP_NI7_TXMAXP 0xffc03fc0 /* Maximum packet size for Host Tx endpoint7 */
#define USB_EP_NI7_TXCSR 0xffc03fc4 /* Control Status register for endpoint7 */
#define USB_EP_NI7_RXMAXP 0xffc03fc8 /* Maximum packet size for Host Rx endpoint7 */
#define USB_EP_NI7_RXCSR 0xffc03fcc /* Control Status register for Host Rx endpoint7 */
#define USB_EP_NI7_RXCOUNT 0xffc03fd0 /* Number of bytes received in endpoint7 FIFO */
#define USB_EP_NI7_TXTYPE 0xffc03fd4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */
#define USB_EP_NI7_TXINTERVAL 0xffc03fd8 /* Sets the NAK response timeout on Endpoint7 */
#define USB_EP_NI7_RXTYPE 0xffc03fdc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */
#define USB_EP_NI7_RXINTERVAL 0xffc03ff0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */
#define USB_EP_NI7_TXCOUNT 0xffc03ff8 /* Number of bytes to be written to the endpoint7 Tx FIFO */
#define USB_DMA_INTERRUPT 0xffc04000 /* Indicates pending interrupts for the DMA channels */
/* USB Channel 0 Config Registers */
#define USB_DMA0CONTROL 0xffc04004 /* DMA master channel 0 configuration */
#define USB_DMA0ADDRLOW 0xffc04008 /* Lower 16-bits of memory source/destination address for DMA master channel 0 */
#define USB_DMA0ADDRHIGH 0xffc0400c /* Upper 16-bits of memory source/destination address for DMA master channel 0 */
#define USB_DMA0COUNTLOW 0xffc04010 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */
#define USB_DMA0COUNTHIGH 0xffc04014 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */
/* USB Channel 1 Config Registers */
#define USB_DMA1CONTROL 0xffc04024 /* DMA master channel 1 configuration */
#define USB_DMA1ADDRLOW 0xffc04028 /* Lower 16-bits of memory source/destination address for DMA master channel 1 */
#define USB_DMA1ADDRHIGH 0xffc0402c /* Upper 16-bits of memory source/destination address for DMA master channel 1 */
#define USB_DMA1COUNTLOW 0xffc04030 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */
#define USB_DMA1COUNTHIGH 0xffc04034 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */
/* USB Channel 2 Config Registers */
#define USB_DMA2CONTROL 0xffc04044 /* DMA master channel 2 configuration */
#define USB_DMA2ADDRLOW 0xffc04048 /* Lower 16-bits of memory source/destination address for DMA master channel 2 */
#define USB_DMA2ADDRHIGH 0xffc0404c /* Upper 16-bits of memory source/destination address for DMA master channel 2 */
#define USB_DMA2COUNTLOW 0xffc04050 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */
#define USB_DMA2COUNTHIGH 0xffc04054 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */
/* USB Channel 3 Config Registers */
#define USB_DMA3CONTROL 0xffc04064 /* DMA master channel 3 configuration */
#define USB_DMA3ADDRLOW 0xffc04068 /* Lower 16-bits of memory source/destination address for DMA master channel 3 */
#define USB_DMA3ADDRHIGH 0xffc0406c /* Upper 16-bits of memory source/destination address for DMA master channel 3 */
#define USB_DMA3COUNTLOW 0xffc04070 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */
#define USB_DMA3COUNTHIGH 0xffc04074 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */
/* USB Channel 4 Config Registers */
#define USB_DMA4CONTROL 0xffc04084 /* DMA master channel 4 configuration */
#define USB_DMA4ADDRLOW 0xffc04088 /* Lower 16-bits of memory source/destination address for DMA master channel 4 */
#define USB_DMA4ADDRHIGH 0xffc0408c /* Upper 16-bits of memory source/destination address for DMA master channel 4 */
#define USB_DMA4COUNTLOW 0xffc04090 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */
#define USB_DMA4COUNTHIGH 0xffc04094 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */
/* USB Channel 5 Config Registers */
#define USB_DMA5CONTROL 0xffc040a4 /* DMA master channel 5 configuration */
#define USB_DMA5ADDRLOW 0xffc040a8 /* Lower 16-bits of memory source/destination address for DMA master channel 5 */
#define USB_DMA5ADDRHIGH 0xffc040ac /* Upper 16-bits of memory source/destination address for DMA master channel 5 */
#define USB_DMA5COUNTLOW 0xffc040b0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */
#define USB_DMA5COUNTHIGH 0xffc040b4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */
/* USB Channel 6 Config Registers */
#define USB_DMA6CONTROL 0xffc040c4 /* DMA master channel 6 configuration */
#define USB_DMA6ADDRLOW 0xffc040c8 /* Lower 16-bits of memory source/destination address for DMA master channel 6 */
#define USB_DMA6ADDRHIGH 0xffc040cc /* Upper 16-bits of memory source/destination address for DMA master channel 6 */
#define USB_DMA6COUNTLOW 0xffc040d0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */
#define USB_DMA6COUNTHIGH 0xffc040d4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */
/* USB Channel 7 Config Registers */
#define USB_DMA7CONTROL 0xffc040e4 /* DMA master channel 7 configuration */
#define USB_DMA7ADDRLOW 0xffc040e8 /* Lower 16-bits of memory source/destination address for DMA master channel 7 */
#define USB_DMA7ADDRHIGH 0xffc040ec /* Upper 16-bits of memory source/destination address for DMA master channel 7 */
#define USB_DMA7COUNTLOW 0xffc040f0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */
#define USB_DMA7COUNTHIGH 0xffc040f4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */
/* Keypad Registers */
#define KPAD_CTL 0xffc04100 /* Controls keypad module enable and disable */
#define KPAD_PRESCALE 0xffc04104 /* Establish a time base for programing the KPAD_MSEL register */
#define KPAD_MSEL 0xffc04108 /* Selects delay parameters for keypad interface sensitivity */
#define KPAD_ROWCOL 0xffc0410c /* Captures the row and column output values of the keys pressed */
#define KPAD_STAT 0xffc04110 /* Holds and clears the status of the keypad interface interrupt */
#define KPAD_SOFTEVAL 0xffc04114 /* Lets software force keypad interface to check for keys being pressed */
/* Pixel Compositor (PIXC) Registers */
#define PIXC_CTL 0xffc04400 /* Overlay enable, resampling mode, I/O data format, transparency enable, watermark level, FIFO status */
#define PIXC_PPL 0xffc04404 /* Holds the number of pixels per line of the display */
#define PIXC_LPF 0xffc04408 /* Holds the number of lines per frame of the display */
#define PIXC_AHSTART 0xffc0440c /* Contains horizontal start pixel information of the overlay data (set A) */
#define PIXC_AHEND 0xffc04410 /* Contains horizontal end pixel information of the overlay data (set A) */
#define PIXC_AVSTART 0xffc04414 /* Contains vertical start pixel information of the overlay data (set A) */
#define PIXC_AVEND 0xffc04418 /* Contains vertical end pixel information of the overlay data (set A) */
#define PIXC_ATRANSP 0xffc0441c /* Contains the transparency ratio (set A) */
#define PIXC_BHSTART 0xffc04420 /* Contains horizontal start pixel information of the overlay data (set B) */
#define PIXC_BHEND 0xffc04424 /* Contains horizontal end pixel information of the overlay data (set B) */
#define PIXC_BVSTART 0xffc04428 /* Contains vertical start pixel information of the overlay data (set B) */
#define PIXC_BVEND 0xffc0442c /* Contains vertical end pixel information of the overlay data (set B) */
#define PIXC_BTRANSP 0xffc04430 /* Contains the transparency ratio (set B) */
#define PIXC_INTRSTAT 0xffc0443c /* Overlay interrupt configuration/status */
#define PIXC_RYCON 0xffc04440 /* Color space conversion matrix register. Contains the R/Y conversion coefficients */
#define PIXC_GUCON 0xffc04444 /* Color space conversion matrix register. Contains the G/U conversion coefficients */
#define PIXC_BVCON 0xffc04448 /* Color space conversion matrix register. Contains the B/V conversion coefficients */
#define PIXC_CCBIAS 0xffc0444c /* Bias values for the color space conversion matrix */
#define PIXC_TC 0xffc04450 /* Holds the transparent color value */
/* Handshake MDMA 0 Registers */
#define HMDMA0_CONTROL 0xffc04500 /* Handshake MDMA0 Control Register */
#define HMDMA0_ECINIT 0xffc04504 /* Handshake MDMA0 Initial Edge Count Register */
#define HMDMA0_BCINIT 0xffc04508 /* Handshake MDMA0 Initial Block Count Register */
#define HMDMA0_ECURGENT 0xffc0450c /* Handshake MDMA0 Urgent Edge Count Threshhold Register */
#define HMDMA0_ECOVERFLOW 0xffc04510 /* Handshake MDMA0 Edge Count Overflow Interrupt Register */
#define HMDMA0_ECOUNT 0xffc04514 /* Handshake MDMA0 Current Edge Count Register */
#define HMDMA0_BCOUNT 0xffc04518 /* Handshake MDMA0 Current Block Count Register */
/* Handshake MDMA 1 Registers */
#define HMDMA1_CONTROL 0xffc04540 /* Handshake MDMA1 Control Register */
#define HMDMA1_ECINIT 0xffc04544 /* Handshake MDMA1 Initial Edge Count Register */
#define HMDMA1_BCINIT 0xffc04548 /* Handshake MDMA1 Initial Block Count Register */
#define HMDMA1_ECURGENT 0xffc0454c /* Handshake MDMA1 Urgent Edge Count Threshhold Register */
#define HMDMA1_ECOVERFLOW 0xffc04550 /* Handshake MDMA1 Edge Count Overflow Interrupt Register */
#define HMDMA1_ECOUNT 0xffc04554 /* Handshake MDMA1 Current Edge Count Register */
#define HMDMA1_BCOUNT 0xffc04558 /* Handshake MDMA1 Current Block Count Register */
/* ********************************************************** */
/* SINGLE BIT MACRO PAIRS (bit mask and negated one) */
/* and MULTI BIT READ MACROS */
/* ********************************************************** */
/* Bit masks for PIXC_CTL */
#define PIXC_EN 0x1 /* Pixel Compositor Enable */
#define OVR_A_EN 0x2 /* Overlay A Enable */
#define OVR_B_EN 0x4 /* Overlay B Enable */
#define IMG_FORM 0x8 /* Image Data Format */
#define OVR_FORM 0x10 /* Overlay Data Format */
#define OUT_FORM 0x20 /* Output Data Format */
#define UDS_MOD 0x40 /* Resampling Mode */
#define TC_EN 0x80 /* Transparent Color Enable */
#define IMG_STAT 0x300 /* Image FIFO Status */
#define OVR_STAT 0xc00 /* Overlay FIFO Status */
#define WM_LVL 0x3000 /* FIFO Watermark Level */
/* Bit masks for PIXC_AHSTART */
#define A_HSTART 0xfff /* Horizontal Start Coordinates */
/* Bit masks for PIXC_AHEND */
#define A_HEND 0xfff /* Horizontal End Coordinates */
/* Bit masks for PIXC_AVSTART */
#define A_VSTART 0x3ff /* Vertical Start Coordinates */
/* Bit masks for PIXC_AVEND */
#define A_VEND 0x3ff /* Vertical End Coordinates */
/* Bit masks for PIXC_ATRANSP */
#define A_TRANSP 0xf /* Transparency Value */
/* Bit masks for PIXC_BHSTART */
#define B_HSTART 0xfff /* Horizontal Start Coordinates */
/* Bit masks for PIXC_BHEND */
#define B_HEND 0xfff /* Horizontal End Coordinates */
/* Bit masks for PIXC_BVSTART */
#define B_VSTART 0x3ff /* Vertical Start Coordinates */
/* Bit masks for PIXC_BVEND */
#define B_VEND 0x3ff /* Vertical End Coordinates */
/* Bit masks for PIXC_BTRANSP */
#define B_TRANSP 0xf /* Transparency Value */
/* Bit masks for PIXC_INTRSTAT */
#define OVR_INT_EN 0x1 /* Interrupt at End of Last Valid Overlay */
#define FRM_INT_EN 0x2 /* Interrupt at End of Frame */
#define OVR_INT_STAT 0x4 /* Overlay Interrupt Status */
#define FRM_INT_STAT 0x8 /* Frame Interrupt Status */
/* Bit masks for PIXC_RYCON */
#define A11 0x3ff /* A11 in the Coefficient Matrix */
#define A12 0xffc00 /* A12 in the Coefficient Matrix */
#define A13 0x3ff00000 /* A13 in the Coefficient Matrix */
#define RY_MULT4 0x40000000 /* Multiply Row by 4 */
/* Bit masks for PIXC_GUCON */
#define A21 0x3ff /* A21 in the Coefficient Matrix */
#define A22 0xffc00 /* A22 in the Coefficient Matrix */
#define A23 0x3ff00000 /* A23 in the Coefficient Matrix */
#define GU_MULT4 0x40000000 /* Multiply Row by 4 */
/* Bit masks for PIXC_BVCON */
#define A31 0x3ff /* A31 in the Coefficient Matrix */
#define A32 0xffc00 /* A32 in the Coefficient Matrix */
#define A33 0x3ff00000 /* A33 in the Coefficient Matrix */
#define BV_MULT4 0x40000000 /* Multiply Row by 4 */
/* Bit masks for PIXC_CCBIAS */
#define A14 0x3ff /* A14 in the Bias Vector */
#define A24 0xffc00 /* A24 in the Bias Vector */
#define A34 0x3ff00000 /* A34 in the Bias Vector */
/* Bit masks for PIXC_TC */
#define RY_TRANS 0xff /* Transparent Color - R/Y Component */
#define GU_TRANS 0xff00 /* Transparent Color - G/U Component */
#define BV_TRANS 0xff0000 /* Transparent Color - B/V Component */
/* Bit masks for HOST_CONTROL */
#define HOST_EN 0x1 /* Host Enable */
#define HOST_END 0x2 /* Host Endianess */
#define DATA_SIZE 0x4 /* Data Size */
#define HOST_RST 0x8 /* Host Reset */
#define HRDY_OVR 0x20 /* Host Ready Override */
#define INT_MODE 0x40 /* Interrupt Mode */
#define BT_EN 0x80 /* Bus Timeout Enable */
#define EHW 0x100 /* Enable Host Write */
#define EHR 0x200 /* Enable Host Read */
#define BDR 0x400 /* Burst DMA Requests */
/* Bit masks for HOST_STATUS */
#define DMA_READY 0x1 /* DMA Ready */
#define FIFOFULL 0x2 /* FIFO Full */
#define FIFOEMPTY 0x4 /* FIFO Empty */
#define DMA_COMPLETE 0x8 /* DMA Complete */
#define HSHK 0x10 /* Host Handshake */
#define HSTIMEOUT 0x20 /* Host Timeout */
#define HIRQ 0x40 /* Host Interrupt Request */
#define ALLOW_CNFG 0x80 /* Allow New Configuration */
#define DMA_DIR 0x100 /* DMA Direction */
#define BTE 0x200 /* Bus Timeout Enabled */
/* Bit masks for HOST_TIMEOUT */
#define COUNT_TIMEOUT 0x7ff /* Host Timeout count */
/* Bit masks for KPAD_CTL */
#define KPAD_EN 0x1 /* Keypad Enable */
#define KPAD_IRQMODE 0x6 /* Key Press Interrupt Enable */
#define KPAD_ROWEN 0x1c00 /* Row Enable Width */
#define KPAD_COLEN 0xe000 /* Column Enable Width */
/* Bit masks for KPAD_PRESCALE */
#define KPAD_PRESCALE_VAL 0x3f /* Key Prescale Value */
/* Bit masks for KPAD_MSEL */
#define DBON_SCALE 0xff /* Debounce Scale Value */
#define COLDRV_SCALE 0xff00 /* Column Driver Scale Value */
/* Bit masks for KPAD_ROWCOL */
#define KPAD_ROW 0xff /* Rows Pressed */
#define KPAD_COL 0xff00 /* Columns Pressed */
/* Bit masks for KPAD_STAT */
#define KPAD_IRQ 0x1 /* Keypad Interrupt Status */
#define KPAD_MROWCOL 0x6 /* Multiple Row/Column Keypress Status */
#define KPAD_PRESSED 0x8 /* Key press current status */
/* Bit masks for KPAD_SOFTEVAL */
#define KPAD_SOFTEVAL_E 0x2 /* Software Programmable Force Evaluate */
/* Bit masks for SDH_COMMAND */
#define CMD_IDX 0x3f /* Command Index */
#define CMD_RSP 0x40 /* Response */
#define CMD_L_RSP 0x80 /* Long Response */
#define CMD_INT_E 0x100 /* Command Interrupt */
#define CMD_PEND_E 0x200 /* Command Pending */
#define CMD_E 0x400 /* Command Enable */
/* Bit masks for SDH_PWR_CTL */
#define PWR_ON 0x3 /* Power On */
#if 0
#define TBD 0x3c /* TBD */
#endif
#define SD_CMD_OD 0x40 /* Open Drain Output */
#define ROD_CTL 0x80 /* Rod Control */
/* Bit masks for SDH_CLK_CTL */
#define CLKDIV 0xff /* MC_CLK Divisor */
#define CLK_E 0x100 /* MC_CLK Bus Clock Enable */
#define PWR_SV_E 0x200 /* Power Save Enable */
#define CLKDIV_BYPASS 0x400 /* Bypass Divisor */
#define WIDE_BUS 0x800 /* Wide Bus Mode Enable */
/* Bit masks for SDH_RESP_CMD */
#define RESP_CMD 0x3f /* Response Command */
/* Bit masks for SDH_DATA_CTL */
#define DTX_E 0x1 /* Data Transfer Enable */
#define DTX_DIR 0x2 /* Data Transfer Direction */
#define DTX_MODE 0x4 /* Data Transfer Mode */
#define DTX_DMA_E 0x8 /* Data Transfer DMA Enable */
#define DTX_BLK_LGTH 0xf0 /* Data Transfer Block Length */
/* Bit masks for SDH_STATUS */
#define CMD_CRC_FAIL 0x1 /* CMD CRC Fail */
#define DAT_CRC_FAIL 0x2 /* Data CRC Fail */
#define CMD_TIME_OUT 0x4 /* CMD Time Out */
#define DAT_TIME_OUT 0x8 /* Data Time Out */
#define TX_UNDERRUN 0x10 /* Transmit Underrun */
#define RX_OVERRUN 0x20 /* Receive Overrun */
#define CMD_RESP_END 0x40 /* CMD Response End */
#define CMD_SENT 0x80 /* CMD Sent */
#define DAT_END 0x100 /* Data End */
#define START_BIT_ERR 0x200 /* Start Bit Error */
#define DAT_BLK_END 0x400 /* Data Block End */
#define CMD_ACT 0x800 /* CMD Active */
#define TX_ACT 0x1000 /* Transmit Active */
#define RX_ACT 0x2000 /* Receive Active */
#define TX_FIFO_STAT 0x4000 /* Transmit FIFO Status */
#define RX_FIFO_STAT 0x8000 /* Receive FIFO Status */
#define TX_FIFO_FULL 0x10000 /* Transmit FIFO Full */
#define RX_FIFO_FULL 0x20000 /* Receive FIFO Full */
#define TX_FIFO_ZERO 0x40000 /* Transmit FIFO Empty */
#define RX_DAT_ZERO 0x80000 /* Receive FIFO Empty */
#define TX_DAT_RDY 0x100000 /* Transmit Data Available */
#define RX_FIFO_RDY 0x200000 /* Receive Data Available */
/* Bit masks for SDH_STATUS_CLR */
#define CMD_CRC_FAIL_STAT 0x1 /* CMD CRC Fail Status */
#define DAT_CRC_FAIL_STAT 0x2 /* Data CRC Fail Status */
#define CMD_TIMEOUT_STAT 0x4 /* CMD Time Out Status */
#define DAT_TIMEOUT_STAT 0x8 /* Data Time Out status */
#define TX_UNDERRUN_STAT 0x10 /* Transmit Underrun Status */
#define RX_OVERRUN_STAT 0x20 /* Receive Overrun Status */
#define CMD_RESP_END_STAT 0x40 /* CMD Response End Status */
#define CMD_SENT_STAT 0x80 /* CMD Sent Status */
#define DAT_END_STAT 0x100 /* Data End Status */
#define START_BIT_ERR_STAT 0x200 /* Start Bit Error Status */
#define DAT_BLK_END_STAT 0x400 /* Data Block End Status */
/* Bit masks for SDH_MASK0 */
#define CMD_CRC_FAIL_MASK 0x1 /* CMD CRC Fail Mask */
#define DAT_CRC_FAIL_MASK 0x2 /* Data CRC Fail Mask */
#define CMD_TIMEOUT_MASK 0x4 /* CMD Time Out Mask */
#define DAT_TIMEOUT_MASK 0x8 /* Data Time Out Mask */
#define TX_UNDERRUN_MASK 0x10 /* Transmit Underrun Mask */
#define RX_OVERRUN_MASK 0x20 /* Receive Overrun Mask */
#define CMD_RESP_END_MASK 0x40 /* CMD Response End Mask */
#define CMD_SENT_MASK 0x80 /* CMD Sent Mask */
#define DAT_END_MASK 0x100 /* Data End Mask */
#define START_BIT_ERR_MASK 0x200 /* Start Bit Error Mask */
#define DAT_BLK_END_MASK 0x400 /* Data Block End Mask */
#define CMD_ACT_MASK 0x800 /* CMD Active Mask */
#define TX_ACT_MASK 0x1000 /* Transmit Active Mask */
#define RX_ACT_MASK 0x2000 /* Receive Active Mask */
#define TX_FIFO_STAT_MASK 0x4000 /* Transmit FIFO Status Mask */
#define RX_FIFO_STAT_MASK 0x8000 /* Receive FIFO Status Mask */
#define TX_FIFO_FULL_MASK 0x10000 /* Transmit FIFO Full Mask */
#define RX_FIFO_FULL_MASK 0x20000 /* Receive FIFO Full Mask */
#define TX_FIFO_ZERO_MASK 0x40000 /* Transmit FIFO Empty Mask */
#define RX_DAT_ZERO_MASK 0x80000 /* Receive FIFO Empty Mask */
#define TX_DAT_RDY_MASK 0x100000 /* Transmit Data Available Mask */
#define RX_FIFO_RDY_MASK 0x200000 /* Receive Data Available Mask */
/* Bit masks for SDH_FIFO_CNT */
#define FIFO_COUNT 0x7fff /* FIFO Count */
/* Bit masks for SDH_E_STATUS */
#define SDIO_INT_DET 0x2 /* SDIO Int Detected */
#define SD_CARD_DET 0x10 /* SD Card Detect */
/* Bit masks for SDH_E_MASK */
#define SDIO_MSK 0x2 /* Mask SDIO Int Detected */
#define SCD_MSK 0x40 /* Mask Card Detect */
/* Bit masks for SDH_CFG */
#define CLKS_EN 0x1 /* Clocks Enable */
#define SD4E 0x4 /* SDIO 4-Bit Enable */
#define MWE 0x8 /* Moving Window Enable */
#define SD_RST 0x10 /* SDMMC Reset */
#define PUP_SDDAT 0x20 /* Pull-up SD_DAT */
#define PUP_SDDAT3 0x40 /* Pull-up SD_DAT3 */
#define PD_SDDAT3 0x80 /* Pull-down SD_DAT3 */
/* Bit masks for SDH_RD_WAIT_EN */
#define RWR 0x1 /* Read Wait Request */
/* Bit masks for ATAPI_CONTROL */
#define PIO_START 0x1 /* Start PIO/Reg Op */
#define MULTI_START 0x2 /* Start Multi-DMA Op */
#define ULTRA_START 0x4 /* Start Ultra-DMA Op */
#define XFER_DIR 0x8 /* Transfer Direction */
#define IORDY_EN 0x10 /* IORDY Enable */
#define FIFO_FLUSH 0x20 /* Flush FIFOs */
#define SOFT_RST 0x40 /* Soft Reset */
#define DEV_RST 0x80 /* Device Reset */
#define TFRCNT_RST 0x100 /* Trans Count Reset */
#define END_ON_TERM 0x200 /* End/Terminate Select */
#define PIO_USE_DMA 0x400 /* PIO-DMA Enable */
#define UDMAIN_FIFO_THRS 0xf000 /* Ultra DMA-IN FIFO Threshold */
/* Bit masks for ATAPI_STATUS */
#define PIO_XFER_ON 0x1 /* PIO transfer in progress */
#define MULTI_XFER_ON 0x2 /* Multi-word DMA transfer in progress */
#define ULTRA_XFER_ON 0x4 /* Ultra DMA transfer in progress */
#define ULTRA_IN_FL 0xf0 /* Ultra DMA Input FIFO Level */
/* Bit masks for ATAPI_DEV_ADDR */
#define DEV_ADDR 0x1f /* Device Address */
/* Bit masks for ATAPI_INT_MASK */
#define ATAPI_DEV_INT_MASK 0x1 /* Device interrupt mask */
#define PIO_DONE_MASK 0x2 /* PIO transfer done interrupt mask */
#define MULTI_DONE_MASK 0x4 /* Multi-DMA transfer done interrupt mask */
#define UDMAIN_DONE_MASK 0x8 /* Ultra-DMA in transfer done interrupt mask */
#define UDMAOUT_DONE_MASK 0x10 /* Ultra-DMA out transfer done interrupt mask */
#define HOST_TERM_XFER_MASK 0x20 /* Host terminate current transfer interrupt mask */
#define MULTI_TERM_MASK 0x40 /* Device terminate Multi-DMA transfer interrupt mask */
#define UDMAIN_TERM_MASK 0x80 /* Device terminate Ultra-DMA-in transfer interrupt mask */
#define UDMAOUT_TERM_MASK 0x100 /* Device terminate Ultra-DMA-out transfer interrupt mask */
/* Bit masks for ATAPI_INT_STATUS */
#define ATAPI_DEV_INT 0x1 /* Device interrupt status */
#define PIO_DONE_INT 0x2 /* PIO transfer done interrupt status */
#define MULTI_DONE_INT 0x4 /* Multi-DMA transfer done interrupt status */
#define UDMAIN_DONE_INT 0x8 /* Ultra-DMA in transfer done interrupt status */
#define UDMAOUT_DONE_INT 0x10 /* Ultra-DMA out transfer done interrupt status */
#define HOST_TERM_XFER_INT 0x20 /* Host terminate current transfer interrupt status */
#define MULTI_TERM_INT 0x40 /* Device terminate Multi-DMA transfer interrupt status */
#define UDMAIN_TERM_INT 0x80 /* Device terminate Ultra-DMA-in transfer interrupt status */
#define UDMAOUT_TERM_INT 0x100 /* Device terminate Ultra-DMA-out transfer interrupt status */
/* Bit masks for ATAPI_LINE_STATUS */
#define ATAPI_INTR 0x1 /* Device interrupt to host line status */
#define ATAPI_DASP 0x2 /* Device dasp to host line status */
#define ATAPI_CS0N 0x4 /* ATAPI chip select 0 line status */
#define ATAPI_CS1N 0x8 /* ATAPI chip select 1 line status */
#define ATAPI_ADDR 0x70 /* ATAPI address line status */
#define ATAPI_DMAREQ 0x80 /* ATAPI DMA request line status */
#define ATAPI_DMAACKN 0x100 /* ATAPI DMA acknowledge line status */
#define ATAPI_DIOWN 0x200 /* ATAPI write line status */
#define ATAPI_DIORN 0x400 /* ATAPI read line status */
#define ATAPI_IORDY 0x800 /* ATAPI IORDY line status */
/* Bit masks for ATAPI_SM_STATE */
#define PIO_CSTATE 0xf /* PIO mode state machine current state */
#define DMA_CSTATE 0xf0 /* DMA mode state machine current state */
#define UDMAIN_CSTATE 0xf00 /* Ultra DMA-In mode state machine current state */
#define UDMAOUT_CSTATE 0xf000 /* ATAPI IORDY line status */
/* Bit masks for ATAPI_TERMINATE */
#define ATAPI_HOST_TERM 0x1 /* Host terminationation */
/* Bit masks for ATAPI_REG_TIM_0 */
#define T2_REG 0xff /* End of cycle time for register access transfers */
#define TEOC_REG 0xff00 /* Selects DIOR/DIOW pulsewidth */
/* Bit masks for ATAPI_PIO_TIM_0 */
#define T1_REG 0xf /* Time from address valid to DIOR/DIOW */
#define T2_REG_PIO 0xff0 /* DIOR/DIOW pulsewidth */
#define T4_REG 0xf000 /* DIOW data hold */
/* Bit masks for ATAPI_PIO_TIM_1 */
#define TEOC_REG_PIO 0xff /* End of cycle time for PIO access transfers. */
/* Bit masks for ATAPI_MULTI_TIM_0 */
#define TD 0xff /* DIOR/DIOW asserted pulsewidth */
#define TM 0xff00 /* Time from address valid to DIOR/DIOW */
/* Bit masks for ATAPI_MULTI_TIM_1 */
#define TKW 0xff /* Selects DIOW negated pulsewidth */
#define TKR 0xff00 /* Selects DIOR negated pulsewidth */
/* Bit masks for ATAPI_MULTI_TIM_2 */
#define TH 0xff /* Selects DIOW data hold */
#define TEOC 0xff00 /* Selects end of cycle for DMA */
/* Bit masks for ATAPI_ULTRA_TIM_0 */
#define TACK 0xff /* Selects setup and hold times for TACK */
#define TENV 0xff00 /* Selects envelope time */
/* Bit masks for ATAPI_ULTRA_TIM_1 */
#define TDVS 0xff /* Selects data valid setup time */
#define TCYC_TDVS 0xff00 /* Selects cycle time - TDVS time */
/* Bit masks for ATAPI_ULTRA_TIM_2 */
#define TSS 0xff /* Selects time from STROBE edge to negation of DMARQ or assertion of STOP */
#define TMLI 0xff00 /* Selects interlock time */
/* Bit masks for ATAPI_ULTRA_TIM_3 */
#define TZAH 0xff /* Selects minimum delay required for output */
#define READY_PAUSE 0xff00 /* Selects ready to pause */
/* Bit masks for TIMER_ENABLE1 */
#define TIMEN8 0x1 /* Timer 8 Enable */
#define TIMEN9 0x2 /* Timer 9 Enable */
#define TIMEN10 0x4 /* Timer 10 Enable */
/* Bit masks for TIMER_DISABLE1 */
#define TIMDIS8 0x1 /* Timer 8 Disable */
#define TIMDIS9 0x2 /* Timer 9 Disable */
#define TIMDIS10 0x4 /* Timer 10 Disable */
/* Bit masks for TIMER_STATUS1 */
#define TIMIL8 0x1 /* Timer 8 Interrupt */
#define TIMIL9 0x2 /* Timer 9 Interrupt */
#define TIMIL10 0x4 /* Timer 10 Interrupt */
#define TOVF_ERR8 0x10 /* Timer 8 Counter Overflow */
#define TOVF_ERR9 0x20 /* Timer 9 Counter Overflow */
#define TOVF_ERR10 0x40 /* Timer 10 Counter Overflow */
#define TRUN8 0x1000 /* Timer 8 Slave Enable Status */
#define TRUN9 0x2000 /* Timer 9 Slave Enable Status */
#define TRUN10 0x4000 /* Timer 10 Slave Enable Status */
/* Bit masks for EPPI0 are obtained from common base header for EPPIx (EPPI1 and EPPI2) */
/* Bit masks for USB_FADDR */
#define FUNCTION_ADDRESS 0x7f /* Function address */
/* Bit masks for USB_POWER */
#define ENABLE_SUSPENDM 0x1 /* enable SuspendM output */
#define SUSPEND_MODE 0x2 /* Suspend Mode indicator */
#define RESUME_MODE 0x4 /* DMA Mode */
#define RESET 0x8 /* Reset indicator */
#define HS_MODE 0x10 /* High Speed mode indicator */
#define HS_ENABLE 0x20 /* high Speed Enable */
#define SOFT_CONN 0x40 /* Soft connect */
#define ISO_UPDATE 0x80 /* Isochronous update */
/* Bit masks for USB_INTRTX */
#define EP0_TX 0x1 /* Tx Endpoint 0 interrupt */
#define EP1_TX 0x2 /* Tx Endpoint 1 interrupt */
#define EP2_TX 0x4 /* Tx Endpoint 2 interrupt */
#define EP3_TX 0x8 /* Tx Endpoint 3 interrupt */
#define EP4_TX 0x10 /* Tx Endpoint 4 interrupt */
#define EP5_TX 0x20 /* Tx Endpoint 5 interrupt */
#define EP6_TX 0x40 /* Tx Endpoint 6 interrupt */
#define EP7_TX 0x80 /* Tx Endpoint 7 interrupt */
/* Bit masks for USB_INTRRX */
#define EP1_RX 0x2 /* Rx Endpoint 1 interrupt */
#define EP2_RX 0x4 /* Rx Endpoint 2 interrupt */
#define EP3_RX 0x8 /* Rx Endpoint 3 interrupt */
#define EP4_RX 0x10 /* Rx Endpoint 4 interrupt */
#define EP5_RX 0x20 /* Rx Endpoint 5 interrupt */
#define EP6_RX 0x40 /* Rx Endpoint 6 interrupt */
#define EP7_RX 0x80 /* Rx Endpoint 7 interrupt */
/* Bit masks for USB_INTRTXE */
#define EP0_TX_E 0x1 /* Endpoint 0 interrupt Enable */
#define EP1_TX_E 0x2 /* Tx Endpoint 1 interrupt Enable */
#define EP2_TX_E 0x4 /* Tx Endpoint 2 interrupt Enable */
#define EP3_TX_E 0x8 /* Tx Endpoint 3 interrupt Enable */
#define EP4_TX_E 0x10 /* Tx Endpoint 4 interrupt Enable */
#define EP5_TX_E 0x20 /* Tx Endpoint 5 interrupt Enable */
#define EP6_TX_E 0x40 /* Tx Endpoint 6 interrupt Enable */
#define EP7_TX_E 0x80 /* Tx Endpoint 7 interrupt Enable */
/* Bit masks for USB_INTRRXE */
#define EP1_RX_E 0x2 /* Rx Endpoint 1 interrupt Enable */
#define EP2_RX_E 0x4 /* Rx Endpoint 2 interrupt Enable */
#define EP3_RX_E 0x8 /* Rx Endpoint 3 interrupt Enable */
#define EP4_RX_E 0x10 /* Rx Endpoint 4 interrupt Enable */
#define EP5_RX_E 0x20 /* Rx Endpoint 5 interrupt Enable */
#define EP6_RX_E 0x40 /* Rx Endpoint 6 interrupt Enable */
#define EP7_RX_E 0x80 /* Rx Endpoint 7 interrupt Enable */
/* Bit masks for USB_INTRUSB */
#define SUSPEND_B 0x1 /* Suspend indicator */
#define RESUME_B 0x2 /* Resume indicator */
#define RESET_OR_BABLE_B 0x4 /* Reset/babble indicator */
#define SOF_B 0x8 /* Start of frame */
#define CONN_B 0x10 /* Connection indicator */
#define DISCON_B 0x20 /* Disconnect indicator */
#define SESSION_REQ_B 0x40 /* Session Request */
#define VBUS_ERROR_B 0x80 /* Vbus threshold indicator */
/* Bit masks for USB_INTRUSBE */
#define SUSPEND_BE 0x1 /* Suspend indicator int enable */
#define RESUME_BE 0x2 /* Resume indicator int enable */
#define RESET_OR_BABLE_BE 0x4 /* Reset/babble indicator int enable */
#define SOF_BE 0x8 /* Start of frame int enable */
#define CONN_BE 0x10 /* Connection indicator int enable */
#define DISCON_BE 0x20 /* Disconnect indicator int enable */
#define SESSION_REQ_BE 0x40 /* Session Request int enable */
#define VBUS_ERROR_BE 0x80 /* Vbus threshold indicator int enable */
/* Bit masks for USB_FRAME */
#define FRAME_NUMBER 0x7ff /* Frame number */
/* Bit masks for USB_INDEX */
#define SELECTED_ENDPOINT 0xf /* selected endpoint */
/* Bit masks for USB_GLOBAL_CTL */
#define GLOBAL_ENA 0x1 /* enables USB module */
#define EP1_TX_ENA 0x2 /* Transmit endpoint 1 enable */
#define EP2_TX_ENA 0x4 /* Transmit endpoint 2 enable */
#define EP3_TX_ENA 0x8 /* Transmit endpoint 3 enable */
#define EP4_TX_ENA 0x10 /* Transmit endpoint 4 enable */
#define EP5_TX_ENA 0x20 /* Transmit endpoint 5 enable */
#define EP6_TX_ENA 0x40 /* Transmit endpoint 6 enable */
#define EP7_TX_ENA 0x80 /* Transmit endpoint 7 enable */
#define EP1_RX_ENA 0x100 /* Receive endpoint 1 enable */
#define EP2_RX_ENA 0x200 /* Receive endpoint 2 enable */
#define EP3_RX_ENA 0x400 /* Receive endpoint 3 enable */
#define EP4_RX_ENA 0x800 /* Receive endpoint 4 enable */
#define EP5_RX_ENA 0x1000 /* Receive endpoint 5 enable */
#define EP6_RX_ENA 0x2000 /* Receive endpoint 6 enable */
#define EP7_RX_ENA 0x4000 /* Receive endpoint 7 enable */
/* Bit masks for USB_OTG_DEV_CTL */
#define SESSION 0x1 /* session indicator */
#define HOST_REQ 0x2 /* Host negotiation request */
#define HOST_MODE 0x4 /* indicates USBDRC is a host */
#define VBUS0 0x8 /* Vbus level indicator[0] */
#define VBUS1 0x10 /* Vbus level indicator[1] */
#define LSDEV 0x20 /* Low-speed indicator */
#define FSDEV 0x40 /* Full or High-speed indicator */
#define B_DEVICE 0x80 /* A' or 'B' device indicator */
/* Bit masks for USB_OTG_VBUS_IRQ */
#define DRIVE_VBUS_ON 0x1 /* indicator to drive VBUS control circuit */
#define DRIVE_VBUS_OFF 0x2 /* indicator to shut off charge pump */
#define CHRG_VBUS_START 0x4 /* indicator for external circuit to start charging VBUS */
#define CHRG_VBUS_END 0x8 /* indicator for external circuit to end charging VBUS */
#define DISCHRG_VBUS_START 0x10 /* indicator to start discharging VBUS */
#define DISCHRG_VBUS_END 0x20 /* indicator to stop discharging VBUS */
/* Bit masks for USB_OTG_VBUS_MASK */
#define DRIVE_VBUS_ON_ENA 0x1 /* enable DRIVE_VBUS_ON interrupt */
#define DRIVE_VBUS_OFF_ENA 0x2 /* enable DRIVE_VBUS_OFF interrupt */
#define CHRG_VBUS_START_ENA 0x4 /* enable CHRG_VBUS_START interrupt */
#define CHRG_VBUS_END_ENA 0x8 /* enable CHRG_VBUS_END interrupt */
#define DISCHRG_VBUS_START_ENA 0x10 /* enable DISCHRG_VBUS_START interrupt */
#define DISCHRG_VBUS_END_ENA 0x20 /* enable DISCHRG_VBUS_END interrupt */
/* Bit masks for USB_CSR0 */
#define RXPKTRDY 0x1 /* data packet receive indicator */
#define TXPKTRDY 0x2 /* data packet in FIFO indicator */
#define STALL_SENT 0x4 /* STALL handshake sent */
#define DATAEND 0x8 /* Data end indicator */
#define SETUPEND 0x10 /* Setup end */
#define SENDSTALL 0x20 /* Send STALL handshake */
#define SERVICED_RXPKTRDY 0x40 /* used to clear the RxPktRdy bit */
#define SERVICED_SETUPEND 0x80 /* used to clear the SetupEnd bit */
#define FLUSHFIFO 0x100 /* flush endpoint FIFO */
#define STALL_RECEIVED_H 0x4 /* STALL handshake received host mode */
#define SETUPPKT_H 0x8 /* send Setup token host mode */
#define ERROR_H 0x10 /* timeout error indicator host mode */
#define REQPKT_H 0x20 /* Request an IN transaction host mode */
#define STATUSPKT_H 0x40 /* Status stage transaction host mode */
#define NAK_TIMEOUT_H 0x80 /* EP0 halted after a NAK host mode */
/* Bit masks for USB_COUNT0 */
#define EP0_RX_COUNT 0x7f /* number of received bytes in EP0 FIFO */
/* Bit masks for USB_NAKLIMIT0 */
#define EP0_NAK_LIMIT 0x1f /* number of frames/micro frames after which EP0 timeouts */
/* Bit masks for USB_TX_MAX_PACKET */
#define MAX_PACKET_SIZE_T 0x7ff /* maximum data pay load in a frame */
/* Bit masks for USB_RX_MAX_PACKET */
#define MAX_PACKET_SIZE_R 0x7ff /* maximum data pay load in a frame */
/* Bit masks for USB_TXCSR */
#define TXPKTRDY_T 0x1 /* data packet in FIFO indicator */
#define FIFO_NOT_EMPTY_T 0x2 /* FIFO not empty */
#define UNDERRUN_T 0x4 /* TxPktRdy not set for an IN token */
#define FLUSHFIFO_T 0x8 /* flush endpoint FIFO */
#define STALL_SEND_T 0x10 /* issue a Stall handshake */
#define STALL_SENT_T 0x20 /* Stall handshake transmitted */
#define CLEAR_DATATOGGLE_T 0x40 /* clear endpoint data toggle */
#define INCOMPTX_T 0x80 /* indicates that a large packet is split */
#define DMAREQMODE_T 0x400 /* DMA mode (0 or 1) selection */
#define FORCE_DATATOGGLE_T 0x800 /* Force data toggle */
#define DMAREQ_ENA_T 0x1000 /* Enable DMA request for Tx EP */
#define ISO_T 0x4000 /* enable Isochronous transfers */
#define AUTOSET_T 0x8000 /* allows TxPktRdy to be set automatically */
#define ERROR_TH 0x4 /* error condition host mode */
#define STALL_RECEIVED_TH 0x20 /* Stall handshake received host mode */
#define NAK_TIMEOUT_TH 0x80 /* NAK timeout host mode */
/* Bit masks for USB_TXCOUNT */
#define TX_COUNT 0x1fff /* Number of bytes to be written to the selected endpoint Tx FIFO */
/* Bit masks for USB_RXCSR */
#define RXPKTRDY_R 0x1 /* data packet in FIFO indicator */
#define FIFO_FULL_R 0x2 /* FIFO not empty */
#define OVERRUN_R 0x4 /* TxPktRdy not set for an IN token */
#define DATAERROR_R 0x8 /* Out packet cannot be loaded into Rx FIFO */
#define FLUSHFIFO_R 0x10 /* flush endpoint FIFO */
#define STALL_SEND_R 0x20 /* issue a Stall handshake */
#define STALL_SENT_R 0x40 /* Stall handshake transmitted */
#define CLEAR_DATATOGGLE_R 0x80 /* clear endpoint data toggle */
#define INCOMPRX_R 0x100 /* indicates that a large packet is split */
#define DMAREQMODE_R 0x800 /* DMA mode (0 or 1) selection */
#define DISNYET_R 0x1000 /* disable Nyet handshakes */
#define DMAREQ_ENA_R 0x2000 /* Enable DMA request for Tx EP */
#define ISO_R 0x4000 /* enable Isochronous transfers */
#define AUTOCLEAR_R 0x8000 /* allows TxPktRdy to be set automatically */
#define ERROR_RH 0x4 /* TxPktRdy not set for an IN token host mode */
#define REQPKT_RH 0x20 /* request an IN transaction host mode */
#define STALL_RECEIVED_RH 0x40 /* Stall handshake received host mode */
#define INCOMPRX_RH 0x100 /* indicates that a large packet is split host mode */
#define DMAREQMODE_RH 0x800 /* DMA mode (0 or 1) selection host mode */
#define AUTOREQ_RH 0x4000 /* sets ReqPkt automatically host mode */
/* Bit masks for USB_RXCOUNT */
#define RX_COUNT 0x1fff /* Number of received bytes in the packet in the Rx FIFO */
/* Bit masks for USB_TXTYPE */
#define TARGET_EP_NO_T 0xf /* EP number */
#define PROTOCOL_T 0xc /* transfer type */
/* Bit masks for USB_TXINTERVAL */
#define TX_POLL_INTERVAL 0xff /* polling interval for selected Tx EP */
/* Bit masks for USB_RXTYPE */
#define TARGET_EP_NO_R 0xf /* EP number */
#define PROTOCOL_R 0xc /* transfer type */
/* Bit masks for USB_RXINTERVAL */
#define RX_POLL_INTERVAL 0xff /* polling interval for selected Rx EP */
/* Bit masks for USB_DMA_INTERRUPT */
#define DMA0_INT 0x1 /* DMA0 pending interrupt */
#define DMA1_INT 0x2 /* DMA1 pending interrupt */
#define DMA2_INT 0x4 /* DMA2 pending interrupt */
#define DMA3_INT 0x8 /* DMA3 pending interrupt */
#define DMA4_INT 0x10 /* DMA4 pending interrupt */
#define DMA5_INT 0x20 /* DMA5 pending interrupt */
#define DMA6_INT 0x40 /* DMA6 pending interrupt */
#define DMA7_INT 0x80 /* DMA7 pending interrupt */
/* Bit masks for USB_DMAxCONTROL */
#define DMA_ENA 0x1 /* DMA enable */
#define DIRECTION 0x2 /* direction of DMA transfer */
#define MODE 0x4 /* DMA Bus error */
#define INT_ENA 0x8 /* Interrupt enable */
#define EPNUM 0xf0 /* EP number */
#define BUSERROR 0x100 /* DMA Bus error */
/* Bit masks for USB_DMAxADDRHIGH */
#define DMA_ADDR_HIGH 0xffff /* Upper 16-bits of memory source/destination address for the DMA master channel */
/* Bit masks for USB_DMAxADDRLOW */
#define DMA_ADDR_LOW 0xffff /* Lower 16-bits of memory source/destination address for the DMA master channel */
/* Bit masks for USB_DMAxCOUNTHIGH */
#define DMA_COUNT_HIGH 0xffff /* Upper 16-bits of byte count of DMA transfer for DMA master channel */
/* Bit masks for USB_DMAxCOUNTLOW */
#define DMA_COUNT_LOW 0xffff /* Lower 16-bits of byte count of DMA transfer for DMA master channel */
/* Bit masks for HMDMAx_CONTROL */
#define HMDMAEN 0x1 /* Handshake MDMA Enable */
#define REP 0x2 /* Handshake MDMA Request Polarity */
#define UTE 0x8 /* Urgency Threshold Enable */
#define OIE 0x10 /* Overflow Interrupt Enable */
#define BDIE 0x20 /* Block Done Interrupt Enable */
#define MBDI 0x40 /* Mask Block Done Interrupt */
#define DRQ 0x300 /* Handshake MDMA Request Type */
#define RBC 0x1000 /* Force Reload of BCOUNT */
#define PS 0x2000 /* Pin Status */
#define OI 0x4000 /* Overflow Interrupt Generated */
#define BDI 0x8000 /* Block Done Interrupt Generated */
/* ******************************************* */
/* MULTI BIT MACRO ENUMERATIONS */
/* ******************************************* */
#endif /* _DEF_BF548_H */
include/asm-blackfin/mach-bf548/defBF548.h
View file @ 04a94bab
......@@ -1010,9 +1010,9 @@
#define DMA_READY 0x1 /* DMA Ready */
#define FIFOFULL 0x2 /* FIFO Full */
#define FIFOEMPTY 0x4 /* FIFO Empty */
#define COMPLETE 0x8 /* DMA Complete */
#define DMA_COMPLETE 0x8 /* DMA Complete */
#define HSHK 0x10 /* Host Handshake */
#define TIMEOUT 0x20 /* Host Timeout */
#define HSTIMEOUT 0x20 /* Host Timeout */
#define HIRQ 0x40 /* Host Interrupt Request */
#define ALLOW_CNFG 0x80 /* Allow New Configuration */
#define DMA_DIR 0x100 /* DMA Direction */
......
include/asm-blackfin/mach-bf548/dma.h
View file @ 04a94bab
......@@ -51,9 +51,13 @@
#define CH_PIXC_OVERLAY 16
#define CH_PIXC_OUTPUT 17
#define CH_SPORT2_RX 18
#define CH_UART2_RX 18
#define CH_SPORT2_TX 19
#define CH_UART2_TX 19
#define CH_SPORT3_RX 20
#define CH_UART3_RX 20
#define CH_SPORT3_TX 21
#define CH_UART3_TX 21
#define CH_SDH 22
#define CH_NFC 22
#define CH_SPI2 23
......
include/asm-blackfin/mach-bf548/irq.h
View file @ 04a94bab
......@@ -99,9 +99,13 @@ Events (highest priority) EMU 0
#define IRQ_UART2_ERROR BFIN_IRQ(31) /* UART2 Status (Error) Interrupt */
#define IRQ_CAN0_ERROR BFIN_IRQ(32) /* CAN0 Status (Error) Interrupt */
#define IRQ_SPORT2_RX BFIN_IRQ(33) /* SPORT2 RX (DMA18) Interrupt */
#define IRQ_UART2_RX BFIN_IRQ(33) /* UART2 RX (DMA18) Interrupt */
#define IRQ_SPORT2_TX BFIN_IRQ(34) /* SPORT2 TX (DMA19) Interrupt */
#define IRQ_UART2_TX BFIN_IRQ(34) /* UART2 TX (DMA19) Interrupt */
#define IRQ_SPORT3_RX BFIN_IRQ(35) /* SPORT3 RX (DMA20) Interrupt */
#define IRQ_UART3_RX BFIN_IRQ(35) /* UART3 RX (DMA20) Interrupt */
#define IRQ_SPORT3_TX BFIN_IRQ(36) /* SPORT3 TX (DMA21) Interrupt */
#define IRQ_UART3_TX BFIN_IRQ(36) /* UART3 TX (DMA21) Interrupt */
#define IRQ_EPPI1 BFIN_IRQ(37) /* EPP1 (DMA13) Interrupt */
#define IRQ_EPPI2 BFIN_IRQ(38) /* EPP2 (DMA14) Interrupt */
#define IRQ_SPI1 BFIN_IRQ(39) /* SPI1 (DMA5) Interrupt */
......@@ -421,9 +425,13 @@ Events (highest priority) EMU 0
/* IAR4 BIT FILEDS */
#define IRQ_CAN0_ERR_POS 0
#define IRQ_SPORT2_RX_POS 4
#define IRQ_UART2_RX_POS 4
#define IRQ_SPORT2_TX_POS 8
#define IRQ_UART2_TX_POS 8
#define IRQ_SPORT3_RX_POS 12
#define IRQ_UART3_RX_POS 12
#define IRQ_SPORT3_TX_POS 16
#define IRQ_UART3_TX_POS 16
#define IRQ_EPPI1_POS 20
#define IRQ_EPPI2_POS 24
#define IRQ_SPI1_POS 28
......
include/asm-blackfin/mach-bf561/blackfin.h
View file @ 04a94bab
......@@ -49,4 +49,24 @@
#define bfin_read_FIO_INEN() bfin_read_FIO0_INEN()
#define bfin_write_FIO_INEN(val) bfin_write_FIO0_INEN(val)
#define SIC_IAR0 SICA_IAR0
#define bfin_write_SIC_IMASK0 bfin_write_SICA_IMASK0
#define bfin_write_SIC_IMASK1 bfin_write_SICA_IMASK1
#define bfin_write_SIC_IWR0 bfin_write_SICA_IWR0
#define bfin_write_SIC_IWR1 bfin_write_SICA_IWR1
#define bfin_read_SIC_IMASK0 bfin_read_SICA_IMASK0
#define bfin_read_SIC_IMASK1 bfin_read_SICA_IMASK1
#define bfin_read_SIC_IWR0 bfin_read_SICA_IWR0
#define bfin_read_SIC_IWR1 bfin_read_SICA_IWR1
#define bfin_read_SIC_ISR0 bfin_read_SICA_ISR0
#define bfin_read_SIC_ISR1 bfin_read_SICA_ISR1
#define bfin_read_SIC_IMASK(x) bfin_read32(SICA_IMASK0 + (x << 2))
#define bfin_write_SIC_IMASK(x, val) bfin_write32((SICA_IMASK0 + (x << 2)), val)
#define bfin_read_SIC_ISR(x) bfin_read32(SICA_ISR0 + (x << 2))
#define bfin_write_SIC_ISR(x, val) bfin_write32((SICA_ISR0 + (x << 2)), val)
#endif /* _MACH_BLACKFIN_H_ */
include/asm-blackfin/termios.h
View file @ 04a94bab
......@@ -39,24 +39,6 @@ struct termio {
/* ioctl (fd, TIOCSERGETLSR, &result) where result may be as below */
/* line disciplines */
#define N_TTY 0
#define N_SLIP 1
#define N_MOUSE 2
#define N_PPP 3
#define N_STRIP 4
#define N_AX25 5
#define N_X25 6 /* X.25 async */
#define N_6PACK 7
#define N_MASC 8 /* Reserved for Mobitex module <kaz@cafe.net> */
#define N_R3964 9 /* Reserved for Simatic R3964 module */
#define N_PROFIBUS_FDL 10 /* Reserved for Profibus <Dave@mvhi.com> */
#define N_IRDA 11 /* Linux IR - http://irda.sourceforge.net/ */
#define N_SMSBLOCK 12 /* SMS block mode - for talking to GSM data cards about SMS messages */
#define N_HDLC 13 /* synchronous HDLC */
#define N_SYNC_PPP 14 /* synchronous PPP */
#define N_HCI 15 /* Bluetooth HCI UART */
#ifdef __KERNEL__
/* intr=^C quit=^\ erase=del kill=^U
......
include/asm-blackfin/trace.h
View file @ 04a94bab
......@@ -46,42 +46,47 @@ extern unsigned long software_trace_buff[];
#ifdef CONFIG_DEBUG_BFIN_HWTRACE_ON
#define TRACE_BUFFER_START(preg, dreg) trace_buffer_start(preg, dreg)
#define TRACE_BUFFER_STOP(preg, dreg) trace_buffer_stop(preg, dreg)
#define trace_buffer_stop(preg, dreg) \
preg.L = LO(TBUFCTL); \
preg.H = HI(TBUFCTL); \
dreg = 0x1; \
[preg] = dreg;
#define trace_buffer_start(preg, dreg) \
preg.L = LO(TBUFCTL); \
preg.H = HI(TBUFCTL); \
dreg = BFIN_TRACE_ON; \
[preg] = dreg;
#define trace_buffer_init(preg, dreg) \
preg.L = LO(TBUFCTL); \
preg.H = HI(TBUFCTL); \
dreg = BFIN_TRACE_INIT; \
[preg] = dreg;
#define trace_buffer_save(preg, dreg) \
preg.L = LO(TBUFCTL); \
preg.H = HI(TBUFCTL); \
dreg = [preg]; \
[sp++] = dreg; \
dreg = 0x1; \
[preg] = dreg;
#define trace_buffer_restore(preg, dreg) \
preg.L = LO(TBUFCTL); \
preg.H = HI(TBUFCTL); \
dreg = [sp--]; \
[preg] = dreg;
#else /* CONFIG_DEBUG_BFIN_HWTRACE_ON */
#define trace_buffer_stop(preg, dreg)
#define trace_buffer_start(preg, dreg)
#define trace_buffer_init(preg, dreg)
#define trace_buffer_save(preg, dreg)
#define trace_buffer_restore(preg, dreg)
#endif /* CONFIG_DEBUG_BFIN_HWTRACE_ON */
#ifdef CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE
# define DEBUG_START_HWTRACE(preg, dreg) trace_buffer_start(preg, dreg)
# define DEBUG_STOP_HWTRACE(preg, dreg) trace_buffer_stop(preg, dreg)
# define DEBUG_HWTRACE_SAVE(preg, dreg) trace_buffer_save(preg, dreg)
# define DEBUG_HWTRACE_RESTORE(preg, dreg) trace_buffer_restore(preg, dreg)
#else
# define DEBUG_START_HWTRACE(preg, dreg)
# define DEBUG_STOP_HWTRACE(preg, dreg)
# define DEBUG_HWTRACE_SAVE(preg, dreg)
# define DEBUG_HWTRACE_RESTORE(preg, dreg)
#endif
#endif /* __ASSEMBLY__ */
......
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