Skip to content

L
linux
Commit 051063b5 authored by Linus Torvalds's avatar Linus Torvalds
Browse files
Options

Merge bk://linux-scsi.bkbits.net/scsi-for-linus-2.6 

into home.osdl.org:/home/torvalds/v2.5/linux
parents 9430d91b 3b728486
Expand all Show whitespace changes
Inline Side-by-side
Showing with 3171 additions and 860 deletions
arch/v850/Kconfig
View file @ 051063b5
......@@ -48,20 +48,24 @@ menu "Processor type and features"
choice
prompt "Platform"
default GDB
config V850E_SIM
bool "GDB"
config RTE_CB_MA1
bool "RTE-V850E/MA1-CB"
config RTE_CB_NB85E
bool "RTE-V850E/NB85E-CB"
config V850E_SIM
bool "GDB"
config RTE_CB_ME2
bool "RTE-V850E/ME2-CB"
config V850E_AS85EP1
bool "AS85EP1"
config V850E2_SIM85E2C
bool "sim85e2c"
config V850E2_SIM85E2S
bool "sim85e2s"
config V850E2_FPGA85E2C
bool "NA85E2C-FPGA"
config V850E2_ANNA
bool "Anna"
config V850E_AS85EP1
bool "AS85EP1"
endchoice
......@@ -78,41 +82,32 @@ menu "Processor type and features"
bool
depends RTE_CB_MA1
default y
# Similarly for the RTE-V850E/MA1-CB - V850E/TEG
# Similarly for the RTE-V850E/NB85E-CB - V850E/TEG
config V850E_TEG
bool
depends RTE_CB_NB85E
default y
# NB85E processor core
config V850E_NB85E
# ... and the RTE-V850E/ME2-CB - V850E/ME2
config V850E_ME2
bool
depends V850E_MA1 || V850E_TEG
depends RTE_CB_ME2
default y
config V850E_MA1_HIGHRES_TIMER
bool "High resolution timer support"
depends V850E_MA1
#### sim85e2-specific config
#### V850E2 processor-specific config
# V850E2 processors
config V850E2
config V850E2_SIM85E2
bool
depends V850E2_SIM85E2C || V850E2_FPGA85E2C || V850E2_ANNA
depends V850E2_SIM85E2C || V850E2_SIM85E2S
default y
# Processors based on the NA85E2A core
config V850E2_NA85E2A
bool
depends V850E2_ANNA
default y
# Processors based on the NA85E2C core
config V850E2_NA85E2C
#### V850E2 processor-specific config
# V850E2 processors
config V850E2
bool
depends V850E2_SIM85E2C || V850E2_FPGA85E2C
depends V850E2_SIM85E2 || V850E2_FPGA85E2C || V850E2_ANNA
default y
......@@ -121,7 +116,7 @@ menu "Processor type and features"
# Boards in the RTE-x-CB series
config RTE_CB
bool
depends RTE_CB_MA1 || RTE_CB_NB85E
depends RTE_CB_MA1 || RTE_CB_NB85E || RTE_CB_ME2
default y
config RTE_CB_MULTI
......@@ -129,7 +124,7 @@ menu "Processor type and features"
# RTE_CB_NB85E can either have multi ROM support or not, but
# other platforms (currently only RTE_CB_MA1) require it.
prompt "Multi monitor ROM support" if RTE_CB_NB85E
depends RTE_CB
depends RTE_CB_MA1 || RTE_CB_NB85E
default y
config RTE_CB_MULTI_DBTRAP
......@@ -156,14 +151,42 @@ menu "Processor type and features"
# The only PCI bus we support is on the RTE-MOTHER-A board
config PCI
bool
default y if RTE_MB_A_PCI
default RTE_MB_A_PCI
#### Some feature-specific configs
# Everything except for the GDB simulator uses the same interrupt controller
config V850E_INTC
bool
default !V850E_SIM
# Everything except for the various simulators uses the "Timer D" unit
config V850E_TIMER_D
bool
default !V850E_SIM && !V850E2_SIM85E2
# Cache control used on some v850e1 processors
config V850E_CACHE
bool
default V850E_TEG || V850E_ME2
# Cache control used on v850e2 processors; I think this should
# actually apply to more, but currently only the SIM85E2S uses it
config V850E2_CACHE
bool
default V850E2_SIM85E2S
config NO_CACHE
bool
default !V850E_CACHE && !V850E2_CACHE
#### Misc config
config ROM_KERNEL
bool "Kernel in ROM"
depends V850E2_ANNA || (RTE_CB && !RTE_CB_MULTI)
depends V850E2_ANNA || V850E_AS85EP1 || RTE_CB_ME2
# Some platforms pre-zero memory, in which case the kernel doesn't need to
config ZERO_BSS
......@@ -177,9 +200,12 @@ menu "Processor type and features"
int
default 8 if V850E2_SIM85E2C || V850E2_FPGA85E2C
config V850E_HIGHRES_TIMER
bool "High resolution timer support"
depends V850E_TIMER_D
config TIME_BOOTUP
bool "Time bootup"
depends V850E_MA1_HIGHRES_TIMER
depends V850E_HIGHRES_TIMER
config RESET_GUARD
bool "Reset Guard"
......@@ -241,6 +267,7 @@ config KCORE_AOUT
default y
config KCORE_ELF
bool
default y
source "fs/Kconfig.binfmt"
......
arch/v850/kernel/Makefile
View file @ 051063b5
......@@ -15,24 +15,26 @@ obj-y += intv.o entry.o process.o syscalls.o time.o semaphore.o setup.o \
signal.o irq.o mach.o ptrace.o bug.o
obj-$(CONFIG_MODULES) += module.o v850_ksyms.o
# chip-specific code
obj-$(CONFIG_V850E_NB85E) += nb85e_intc.o
obj-$(CONFIG_V850E_MA1) += ma.o nb85e_utils.o nb85e_timer_d.o
obj-$(CONFIG_V850E_TEG) += teg.o nb85e_utils.o nb85e_cache.o \
nb85e_timer_d.o
obj-$(CONFIG_V850E2_ANNA) += anna.o nb85e_intc.o nb85e_utils.o \
nb85e_timer_d.o
obj-$(CONFIG_V850E_AS85EP1) += as85ep1.o nb85e_intc.o nb85e_utils.o \
nb85e_timer_d.o
obj-$(CONFIG_V850E_MA1) += ma.o
obj-$(CONFIG_V850E_ME2) += me2.o
obj-$(CONFIG_V850E_TEG) += teg.o
obj-$(CONFIG_V850E_AS85EP1) += as85ep1.o
obj-$(CONFIG_V850E2_ANNA) += anna.o
# platform-specific code
obj-$(CONFIG_V850E_SIM) += sim.o simcons.o
obj-$(CONFIG_V850E2_SIM85E2C) += sim85e2c.o nb85e_intc.o memcons.o
obj-$(CONFIG_V850E2_FPGA85E2C) += fpga85e2c.o nb85e_intc.o memcons.o
obj-$(CONFIG_V850E2_SIM85E2) += sim85e2.o memcons.o
obj-$(CONFIG_V850E2_FPGA85E2C) += fpga85e2c.o memcons.o
obj-$(CONFIG_RTE_CB) += rte_cb.o rte_cb_leds.o
obj-$(CONFIG_RTE_CB_MA1) += rte_ma1_cb.o
obj-$(CONFIG_RTE_CB_ME2) += rte_me2_cb.o
obj-$(CONFIG_RTE_CB_NB85E) += rte_nb85e_cb.o
obj-$(CONFIG_RTE_CB_MULTI) += rte_cb_multi.o
obj-$(CONFIG_RTE_MB_A_PCI) += rte_mb_a_pci.o
obj-$(CONFIG_RTE_GBUS_INT) += gbus_int.o
# feature-specific code
obj-$(CONFIG_V850E_MA1_HIGHRES_TIMER) += highres_timer.o
obj-$(CONFIG_V850E_INTC) += v850e_intc.o
obj-$(CONFIG_V850E_TIMER_D) += v850e_timer_d.o v850e_utils.o
obj-$(CONFIG_V850E_CACHE) += v850e_cache.o
obj-$(CONFIG_V850E2_CACHE) += v850e2_cache.o
obj-$(CONFIG_V850E_HIGHRES_TIMER) += highres_timer.o
obj-$(CONFIG_PROC_FS) += procfs.o
arch/v850/kernel/anna.c
View file @ 051063b5
/*
* arch/v850/kernel/anna.c -- Anna V850E2 evaluation chip/board
*
* Copyright (C) 2002 NEC Corporation
* Copyright (C) 2002 Miles Bader <miles@gnu.org>
* Copyright (C) 2002,03 NEC Electronics Corporation
* Copyright (C) 2002,03 Miles Bader <miles@gnu.org>
*
* This file is subject to the terms and conditions of the GNU General
* Public License. See the file COPYING in the main directory of this
......@@ -21,8 +21,8 @@
#include <asm/machdep.h>
#include <asm/atomic.h>
#include <asm/page.h>
#include <asm/nb85e_timer_d.h>
#include <asm/nb85e_uart.h>
#include <asm/v850e_timer_d.h>
#include <asm/v850e_uart.h>
#include "mach.h"
......@@ -42,31 +42,33 @@ static void anna_led_tick (void);
void __init mach_early_init (void)
{
ANNA_ILBEN = 0;
ANNA_CSC(0) = 0x402F;
ANNA_CSC(1) = 0x4000;
ANNA_BPC = 0;
ANNA_BSC = 0xAAAA;
ANNA_BEC = 0;
ANNA_BHC = 0xFFFF; /* icache all memory, dcache all */
ANNA_BCT(0) = 0xB088;
ANNA_BCT(1) = 0x0008;
ANNA_DWC(0) = 0x0027;
ANNA_DWC(1) = 0;
ANNA_BCC = 0x0006;
ANNA_ASC = 0;
ANNA_LBS = 0x0089;
ANNA_SCR3 = 0x21A9;
ANNA_RFS3 = 0x8121;
nb85e_intc_disable_irqs ();
V850E2_CSC(0) = 0x402F;
V850E2_CSC(1) = 0x4000;
V850E2_BPC = 0;
V850E2_BSC = 0xAAAA;
V850E2_BEC = 0;
#if 0
V850E2_BHC = 0xFFFF; /* icache all memory, dcache all */
#else
V850E2_BHC = 0; /* cache no memory */
#endif
V850E2_BCT(0) = 0xB088;
V850E2_BCT(1) = 0x0008;
V850E2_DWC(0) = 0x0027;
V850E2_DWC(1) = 0;
V850E2_BCC = 0x0006;
V850E2_ASC = 0;
V850E2_LBS = 0x0089;
V850E2_SCR(3) = 0x21A9;
V850E2_RFS(3) = 0x8121;
v850e_intc_disable_irqs ();
}
void __init mach_setup (char **cmdline)
{
#ifdef CONFIG_V850E_NB85E_UART_CONSOLE
nb85e_uart_cons_init (1);
#endif
ANNA_PORT_PM (LEDS_PORT) = 0; /* Make all LED pins output pins. */
mach_tick = anna_led_tick;
}
......@@ -95,12 +97,12 @@ void mach_gettimeofday (struct timespec *tv)
void __init mach_sched_init (struct irqaction *timer_action)
{
/* Start hardware timer. */
nb85e_timer_d_configure (0, HZ);
v850e_timer_d_configure (0, HZ);
/* Install timer interrupt handler. */
setup_irq (IRQ_INTCMD(0), timer_action);
}
static struct nb85e_intc_irq_init irq_inits[] = {
static struct v850e_intc_irq_init irq_inits[] = {
{ "IRQ", 0, NUM_MACH_IRQS, 1, 7 },
{ "PIN", IRQ_INTP(0), IRQ_INTP_NUM, 1, 4 },
{ "CCC", IRQ_INTCCC(0), IRQ_INTCCC_NUM, 1, 5 },
......@@ -118,7 +120,7 @@ static struct hw_interrupt_type hw_itypes[NUM_IRQ_INITS];
void __init mach_init_irqs (void)
{
nb85e_intc_init_irq_types (irq_inits, hw_itypes);
v850e_intc_init_irq_types (irq_inits, hw_itypes);
}
void machine_restart (char *__unused)
......
arch/v850/kernel/as85ep1.c
View file @ 051063b5
/*
* arch/v850/kernel/as85ep1.c -- AS85EP1 V850E evaluation chip/board
*
* Copyright (C) 2002 NEC Corporation
* Copyright (C) 2002 Miles Bader <miles@gnu.org>
* Copyright (C) 2002,03 NEC Electronics Corporation
* Copyright (C) 2002,03 Miles Bader <miles@gnu.org>
*
* This file is subject to the terms and conditions of the GNU General
* Public License. See the file COPYING in the main directory of this
......@@ -21,8 +21,8 @@
#include <asm/machdep.h>
#include <asm/atomic.h>
#include <asm/page.h>
#include <asm/nb85e_timer_d.h>
#include <asm/nb85e_uart.h>
#include <asm/v850e_timer_d.h>
#include <asm/v850e_uart.h>
#include "mach.h"
......@@ -90,20 +90,14 @@ void __init mach_early_init (void)
AS85EP1_IRAMM = 0x0; /* $BFbB"L?Na(BRAM$B$O!V(Bread-mode$B!W$K$J$j$^$9(B */
#endif /* !CONFIG_ROM_KERNEL */
nb85e_intc_disable_irqs ();
v850e_intc_disable_irqs ();
}
void __init mach_setup (char **cmdline)
{
#ifdef CONFIG_V850E_NB85E_UART_CONSOLE
nb85e_uart_cons_init (1);
#endif
AS85EP1_PORT_PMC (LEDS_PORT) = 0; /* Make the LEDs port an I/O port. */
AS85EP1_PORT_PM (LEDS_PORT) = 0; /* Make all the bits output pins. */
mach_tick = as85ep1_led_tick;
ROOT_DEV = MKDEV (BLKMEM_MAJOR, 0);
}
void __init mach_get_physical_ram (unsigned long *ram_start,
......@@ -137,21 +131,21 @@ void __init mach_reserve_bootmem ()
root_fs_image_end - root_fs_image_start);
}
void mach_gettimeofday (struct timeval *tv)
void mach_gettimeofday (struct timespec *tv)
{
tv->tv_sec = 0;
tv->tv_usec = 0;
tv->tv_nsec = 0;
}
void __init mach_sched_init (struct irqaction *timer_action)
{
/* Start hardware timer. */
nb85e_timer_d_configure (0, HZ);
v850e_timer_d_configure (0, HZ);
/* Install timer interrupt handler. */
setup_irq (IRQ_INTCMD(0), timer_action);
}
static struct nb85e_intc_irq_init irq_inits[] = {
static struct v850e_intc_irq_init irq_inits[] = {
{ "IRQ", 0, NUM_MACH_IRQS, 1, 7 },
{ "CCC", IRQ_INTCCC(0), IRQ_INTCCC_NUM, 1, 5 },
{ "CMD", IRQ_INTCMD(0), IRQ_INTCMD_NUM, 1, 5 },
......@@ -166,7 +160,7 @@ static struct hw_interrupt_type hw_itypes[NUM_IRQ_INITS];
void __init mach_init_irqs (void)
{
nb85e_intc_init_irq_types (irq_inits, hw_itypes);
v850e_intc_init_irq_types (irq_inits, hw_itypes);
}
void machine_restart (char *__unused)
......
arch/v850/kernel/fpga85e2c.c
View file @ 051063b5
......@@ -2,8 +2,8 @@
* arch/v850/kernel/fpga85e2c.h -- Machine-dependent defs for
* FPGA implementation of V850E2/NA85E2C
*
* Copyright (C) 2002 NEC Corporation
* Copyright (C) 2002 Miles Bader <miles@gnu.org>
* Copyright (C) 2002,03 NEC Electronics Corporation
* Copyright (C) 2002,03 Miles Bader <miles@gnu.org>
*
* This file is subject to the terms and conditions of the GNU General
* Public License. See the file COPYING in the main directory of this
......@@ -46,7 +46,7 @@ void __init mach_early_init (void)
/* Set bus sizes: CS0 32-bit, CS1 16-bit, CS7 8-bit,
everything else 32-bit. */
BSC = 0x2AA6;
V850E2_BSC = 0x2AA6;
for (i = 2; i <= 6; i++)
CSDEV(i) = 0; /* 32 bit */
......@@ -134,7 +134,7 @@ void machine_power_off (void)
/* Interrupts */
struct nb85e_intc_irq_init irq_inits[] = {
struct v850e_intc_irq_init irq_inits[] = {
{ "IRQ", 0, NUM_MACH_IRQS, 1, 7 },
{ "RPU", IRQ_RPU(0), IRQ_RPU_NUM, 1, 6 },
{ 0 }
......@@ -146,7 +146,7 @@ struct hw_interrupt_type hw_itypes[NUM_IRQ_INITS];
/* Initialize interrupts. */
void __init mach_init_irqs (void)
{
nb85e_intc_init_irq_types (irq_inits, hw_itypes);
v850e_intc_init_irq_types (irq_inits, hw_itypes);
}
......
arch/v850/kernel/gbus_int.c
View file @ 051063b5
......@@ -113,9 +113,7 @@ static irqreturn_t gbus_int_handle_irq (int irq, void *dev_id,
/* Only pay attention to enabled interrupts. */
status &= enable;
if (status) {
unsigned base_irq
= IRQ_GBUS_INT (w * GBUS_INT_BITS_PER_WORD);
irq = base_irq;
irq = IRQ_GBUS_INT (w * GBUS_INT_BITS_PER_WORD);
do {
/* There's an active interrupt in word
W, find out which one, and call its
......@@ -247,7 +245,7 @@ void __init gbus_int_init_irqs (void)
/* First initialize the shared gint interrupts. */
for (i = 0; i < NUM_USED_GINTS; i++) {
unsigned gint = used_gint[i].gint;
struct nb85e_intc_irq_init gint_irq_init[2];
struct v850e_intc_irq_init gint_irq_init[2];
/* We initialize one GINT interrupt at a time. */
gint_irq_init[0].name = "GINT";
......@@ -258,7 +256,7 @@ void __init gbus_int_init_irqs (void)
gint_irq_init[1].name = 0; /* Terminate the vector. */
nb85e_intc_init_irq_types (gint_irq_init, gint_hw_itypes);
v850e_intc_init_irq_types (gint_irq_init, gint_hw_itypes);
}
/* Then the GBUS interrupts. */
......
arch/v850/kernel/head.S
View file @ 051063b5
/*
* arch/v850/kernel/head.S -- Lowest-level startup code
*
* Copyright (C) 2001,02 NEC Corporation
* Copyright (C) 2001,02 Miles Bader <miles@gnu.org>
* Copyright (C) 2001,02,03 NEC Electronics Corporation
* Copyright (C) 2001,02,03 Miles Bader <miles@gnu.org>
*
* This file is subject to the terms and conditions of the GNU General
* Public License. See the file COPYING in the main directory of this
......@@ -115,7 +115,14 @@ C_ENTRY(start):
jarl CSYM(memset), lp
#endif
// Start Linux kernel.
// What happens if the main kernel function returns (it shouldn't)
mov hilo(CSYM(machine_halt)), lp
jr CSYM(start_kernel)
// Start the linux kernel. We use an indirect jump to get extra
// range, because on some platforms this initial startup code
// (and the associated platform-specific code in mach_early_init)
// are located far away from the main kernel, e.g. so that they
// can initialize RAM first and copy the kernel or something.
mov hilo(CSYM(start_kernel)), r12
jmp [r12]
C_END(start)
arch/v850/kernel/highres_timer.c
View file @ 051063b5
/*
* arch/v850/kernel/highres_timer.c -- High resolution timing routines
*
* Copyright (C) 2001,02 NEC Corporation
* Copyright (C) 2001,02 Miles Bader <miles@gnu.org>
* Copyright (C) 2001,02,03 NEC Electronics Corporation
* Copyright (C) 2001,02,03 Miles Bader <miles@gnu.org>
*
* This file is subject to the terms and conditions of the GNU General
* Public License. See the file COPYING in the main directory of this
......@@ -12,7 +12,7 @@
*/
#include <asm/system.h>
#include <asm/nb85e_timer_d.h>
#include <asm/v850e_timer_d.h>
#include <asm/highres_timer.h>
#define HIGHRES_TIMER_USEC_SHIFT 12
......@@ -42,7 +42,7 @@ void highres_timer_slow_tick_irq (void)
void highres_timer_reset (void)
{
NB85E_TIMER_D_TMD (HIGHRES_TIMER_TIMER_D_UNIT) = 0;
V850E_TIMER_D_TMD (HIGHRES_TIMER_TIMER_D_UNIT) = 0;
HIGHRES_TIMER_SLOW_TICKS = 0;
}
......@@ -51,12 +51,12 @@ void highres_timer_start (void)
u32 fast_tick_rate;
/* Start hardware timer. */
nb85e_timer_d_configure (HIGHRES_TIMER_TIMER_D_UNIT,
v850e_timer_d_configure (HIGHRES_TIMER_TIMER_D_UNIT,
HIGHRES_TIMER_SLOW_TICK_RATE);
fast_tick_rate =
(NB85E_TIMER_D_BASE_FREQ
>> NB85E_TIMER_D_DIVLOG2 (HIGHRES_TIMER_TIMER_D_UNIT));
(V850E_TIMER_D_BASE_FREQ
>> V850E_TIMER_D_DIVLOG2 (HIGHRES_TIMER_TIMER_D_UNIT));
/* The obvious way of calculating microseconds from fast ticks
is to do:
......@@ -77,16 +77,16 @@ void highres_timer_start (void)
/* Enable the interrupt (which is hardwired to this use), and
give it the highest priority. */
NB85E_INTC_IC (IRQ_INTCMD (HIGHRES_TIMER_TIMER_D_UNIT)) = 0;
V850E_INTC_IC (IRQ_INTCMD (HIGHRES_TIMER_TIMER_D_UNIT)) = 0;
}
void highres_timer_stop (void)
{
/* Stop the timer. */
NB85E_TIMER_D_TMCD (HIGHRES_TIMER_TIMER_D_UNIT) =
NB85E_TIMER_D_TMCD_CAE;
V850E_TIMER_D_TMCD (HIGHRES_TIMER_TIMER_D_UNIT) =
V850E_TIMER_D_TMCD_CAE;
/* Disable its interrupt, just in case. */
nb85e_intc_disable_irq (IRQ_INTCMD (HIGHRES_TIMER_TIMER_D_UNIT));
v850e_intc_disable_irq (IRQ_INTCMD (HIGHRES_TIMER_TIMER_D_UNIT));
}
inline void highres_timer_read_ticks (u32 *slow_ticks, u32 *fast_ticks)
......@@ -95,9 +95,9 @@ inline void highres_timer_read_ticks (u32 *slow_ticks, u32 *fast_ticks)
u32 fast_ticks_1, fast_ticks_2, _slow_ticks;
local_irq_save (flags);
fast_ticks_1 = NB85E_TIMER_D_TMD (HIGHRES_TIMER_TIMER_D_UNIT);
fast_ticks_1 = V850E_TIMER_D_TMD (HIGHRES_TIMER_TIMER_D_UNIT);
_slow_ticks = HIGHRES_TIMER_SLOW_TICKS;
fast_ticks_2 = NB85E_TIMER_D_TMD (HIGHRES_TIMER_TIMER_D_UNIT);
fast_ticks_2 = V850E_TIMER_D_TMD (HIGHRES_TIMER_TIMER_D_UNIT);
local_irq_restore (flags);
if (fast_ticks_2 < fast_ticks_1)
......
arch/v850/kernel/intv.S
View file @ 051063b5
......@@ -16,7 +16,7 @@
#include <asm/machdep.h>
#include <asm/entry.h>
#ifdef CONFIG_V850E_MA1_HIGHRES_TIMER
#ifdef CONFIG_V850E_HIGHRES_TIMER
#include <asm/highres_timer.h>
#endif
......@@ -59,7 +59,7 @@
.section .intv.mach, "ax"
.org 0x0
#if defined (CONFIG_V850E_MA1_HIGHRES_TIMER) && defined (IRQ_INTCMD)
#if defined (CONFIG_V850E_HIGHRES_TIMER) && defined (IRQ_INTCMD)
/* Interrupts before the highres timer interrupt. */
.rept IRQ_INTCMD (HIGHRES_TIMER_TIMER_D_UNIT)
......
arch/v850/kernel/ma.c
View file @ 051063b5
......@@ -22,19 +22,19 @@
#include <asm/atomic.h>
#include <asm/page.h>
#include <asm/machdep.h>
#include <asm/nb85e_timer_d.h>
#include <asm/v850e_timer_d.h>
#include "mach.h"
void __init mach_sched_init (struct irqaction *timer_action)
{
/* Start hardware timer. */
nb85e_timer_d_configure (0, HZ);
v850e_timer_d_configure (0, HZ);
/* Install timer interrupt handler. */
setup_irq (IRQ_INTCMD(0), timer_action);
}
static struct nb85e_intc_irq_init irq_inits[] = {
static struct v850e_intc_irq_init irq_inits[] = {
{ "IRQ", 0, NUM_MACH_IRQS, 1, 7 },
{ "CMD", IRQ_INTCMD(0), IRQ_INTCMD_NUM, 1, 5 },
{ "DMA", IRQ_INTDMA(0), IRQ_INTDMA_NUM, 1, 2 },
......@@ -51,7 +51,7 @@ static struct hw_interrupt_type hw_itypes[NUM_IRQ_INITS];
/* Initialize MA chip interrupts. */
void __init ma_init_irqs (void)
{
nb85e_intc_init_irq_types (irq_inits, hw_itypes);
v850e_intc_init_irq_types (irq_inits, hw_itypes);
}
/* Called before configuring an on-chip UART. */
......
arch/v850/kernel/me2.c 0 → 100644
View file @ 051063b5
/*
* arch/v850/kernel/me2.c -- V850E/ME2 chip-specific support
*
* Copyright (C) 2003 NEC Corporation
* Copyright (C) 2003 Miles Bader <miles@gnu.org>
*
* This file is subject to the terms and conditions of the GNU General
* Public License. See the file COPYING in the main directory of this
* archive for more details.
*
* Written by Miles Bader <miles@gnu.org>
*/
#include <linux/config.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/mm.h>
#include <linux/swap.h>
#include <linux/bootmem.h>
#include <linux/irq.h>
#include <asm/atomic.h>
#include <asm/page.h>
#include <asm/machdep.h>
#include <asm/v850e_timer_d.h>
#include "mach.h"
void __init mach_sched_init (struct irqaction *timer_action)
{
/* Start hardware timer. */
v850e_timer_d_configure (0, HZ);
/* Install timer interrupt handler. */
setup_irq (IRQ_INTCMD(0), timer_action);
}
static struct v850e_intc_irq_init irq_inits[] = {
{ "IRQ", 0, NUM_CPU_IRQS, 1, 7 },
{ "INTP", IRQ_INTP(0), IRQ_INTP_NUM, 1, 5 },
{ "CMD", IRQ_INTCMD(0), IRQ_INTCMD_NUM, 1, 3 },
{ "UBTIRE", IRQ_INTUBTIRE(0), IRQ_INTUBTIRE_NUM, 5, 4 },
{ "UBTIR", IRQ_INTUBTIR(0), IRQ_INTUBTIR_NUM, 5, 4 },
{ "UBTIT", IRQ_INTUBTIT(0), IRQ_INTUBTIT_NUM, 5, 4 },
{ "UBTIF", IRQ_INTUBTIF(0), IRQ_INTUBTIF_NUM, 5, 4 },
{ "UBTITO", IRQ_INTUBTITO(0), IRQ_INTUBTITO_NUM, 5, 4 },
{ 0 }
};
#define NUM_IRQ_INITS ((sizeof irq_inits / sizeof irq_inits[0]) - 1)
static struct hw_interrupt_type hw_itypes[NUM_IRQ_INITS];
/* Initialize V850E/ME2 chip interrupts. */
void __init me2_init_irqs (void)
{
v850e_intc_init_irq_types (irq_inits, hw_itypes);
}
/* Called before configuring an on-chip UART. */
void me2_uart_pre_configure (unsigned chan, unsigned cflags, unsigned baud)
{
if (chan == 0) {
/* Specify that the relevent pins on the chip should do
serial I/O, not direct I/O. */
ME2_PORT1_PMC |= 0xC;
/* Specify that we're using the UART, not the CSI device. */
ME2_PORT1_PFC |= 0xC;
} else if (chan == 1) {
/* Specify that the relevent pins on the chip should do
serial I/O, not direct I/O. */
ME2_PORT2_PMC |= 0x6;
/* Specify that we're using the UART, not the CSI device. */
ME2_PORT2_PFC |= 0x6;
}
}
arch/v850/kernel/rte_cb.c
View file @ 051063b5
......@@ -17,7 +17,7 @@
#include <linux/fs.h>
#include <asm/machdep.h>
#include <asm/nb85e_uart.h>
#include <asm/v850e_uart.h>
#include "mach.h"
......@@ -34,7 +34,7 @@ extern void multi_init (void);
void __init rte_cb_early_init (void)
{
nb85e_intc_disable_irqs ();
v850e_intc_disable_irqs ();
#ifdef CONFIG_RTE_CB_MULTI
multi_init ();
......@@ -43,6 +43,7 @@ void __init rte_cb_early_init (void)
void __init mach_setup (char **cmdline)
{
#ifdef CONFIG_RTE_MB_A_PCI
/* Probe for Mother-A, and print a message if we find it. */
*(volatile unsigned long *)MB_A_SRAM_ADDR = 0xDEADBEEF;
if (*(volatile unsigned long *)MB_A_SRAM_ADDR == 0xDEADBEEF) {
......@@ -52,23 +53,11 @@ void __init mach_setup (char **cmdline)
" NEC SolutionGear/Midas lab"
" RTE-MOTHER-A motherboard\n");
}
#if defined (CONFIG_V850E_NB85E_UART_CONSOLE) && !defined (CONFIG_TIME_BOOTUP)
nb85e_uart_cons_init (0);
#endif
#endif /* CONFIG_RTE_MB_A_PCI */
mach_tick = led_tick;
}
#ifdef CONFIG_TIME_BOOTUP
void initial_boot_done (void)
{
#ifdef CONFIG_V850E_NB85E_UART_CONSOLE
nb85e_uart_cons_init (0);
#endif
}
#endif
void machine_restart (char *__unused)
{
#ifdef CONFIG_RESET_GUARD
......@@ -194,6 +183,7 @@ static struct hw_interrupt_type gbus_hw_itypes[NUM_GBUS_IRQ_INITS];
#endif /* CONFIG_RTE_GBUS_INT */
void __init rte_cb_init_irqs (void)
{
#ifdef CONFIG_RTE_GBUS_INT
......
arch/v850/kernel/rte_ma1_cb.c
View file @ 051063b5
......@@ -20,7 +20,7 @@
#include <asm/page.h>
#include <asm/ma1.h>
#include <asm/rte_ma1_cb.h>
#include <asm/nb85e_timer_c.h>
#include <asm/v850e_timer_c.h>
#include "mach.h"
......@@ -89,14 +89,14 @@ void __init mach_init_irqs (void)
rte_cb_init_irqs ();
/* Use falling-edge-sensitivity for interrupts . */
NB85E_TIMER_C_SESC (0) &= ~0xC;
NB85E_TIMER_C_SESC (1) &= ~0xF;
V850E_TIMER_C_SESC (0) &= ~0xC;
V850E_TIMER_C_SESC (1) &= ~0xF;
/* INTP000-INTP011 are shared with `Timer C', so we have to set
up Timer C to pass them through as raw interrupts. */
for (tc = 0; tc < 2; tc++)
/* Turn on the timer. */
NB85E_TIMER_C_TMCC0 (tc) |= NB85E_TIMER_C_TMCC0_CAE;
V850E_TIMER_C_TMCC0 (tc) |= V850E_TIMER_C_TMCC0_CAE;
/* Make sure the relevant port0/port1 pins are assigned
interrupt duty. We used INTP001-INTP011 (don't screw with
......
arch/v850/kernel/rte_me2_cb.c 0 → 100644
View file @ 051063b5
/*
* arch/v850/kernel/rte_me2_cb.c -- Midas labs RTE-V850E/ME2-CB board
*
* Copyright (C) 2001,02,03 NEC Electronics Corporation
* Copyright (C) 2001,02,03 Miles Bader <miles@gnu.org>
*
* This file is subject to the terms and conditions of the GNU General
* Public License. See the file COPYING in the main directory of this
* archive for more details.
*
* Written by Miles Bader <miles@gnu.org>
*/
#include <linux/config.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/bootmem.h>
#include <linux/irq.h>
#include <linux/fs.h>
#include <linux/major.h>
#include <linux/sched.h>
#include <linux/delay.h>
#include <asm/atomic.h>
#include <asm/page.h>
#include <asm/me2.h>
#include <asm/rte_me2_cb.h>
#include <asm/machdep.h>
#include <asm/v850e_intc.h>
#include <asm/v850e_cache.h>
#include <asm/irq.h>
#include "mach.h"
extern unsigned long *_intv_start;
extern unsigned long *_intv_end;
/* LED access routines. */
extern unsigned read_leds (int pos, char *buf, int len);
extern unsigned write_leds (int pos, const char *buf, int len);
/* SDRAM are almost contiguous (with a small hole in between;
see mach_reserve_bootmem for details), so just use both as one big area. */
#define RAM_START SDRAM_ADDR
#define RAM_END (SDRAM_ADDR + SDRAM_SIZE)
void __init mach_get_physical_ram (unsigned long *ram_start,
unsigned long *ram_len)
{
*ram_start = RAM_START;
*ram_len = RAM_END - RAM_START;
}
void __init mach_reserve_bootmem ()
{
extern char _root_fs_image_start, _root_fs_image_end;
u32 root_fs_image_start = (u32)&_root_fs_image_start;
u32 root_fs_image_end = (u32)&_root_fs_image_end;
/* Reserve the memory used by the root filesystem image if it's
in RAM. */
if (root_fs_image_start >= RAM_START && root_fs_image_start < RAM_END)
reserve_bootmem (root_fs_image_start,
root_fs_image_end - root_fs_image_start);
}
void mach_gettimeofday (struct timespec *tv)
{
tv->tv_sec = 0;
tv->tv_nsec = 0;
}
/* Called before configuring an on-chip UART. */
void rte_me2_cb_uart_pre_configure (unsigned chan,
unsigned cflags, unsigned baud)
{
/* The RTE-V850E/ME2-CB connects some general-purpose I/O
pins on the CPU to the RTS/CTS lines of UARTB channel 0's
serial connection.
I/O pins P21 and P22 are RTS and CTS respectively. */
if (chan == 0) {
/* Put P21 & P22 in I/O port mode. */
ME2_PORT2_PMC &= ~0x6;
/* Make P21 and output, and P22 an input. */
ME2_PORT2_PM = (ME2_PORT2_PM & ~0xC) | 0x4;
}
me2_uart_pre_configure (chan, cflags, baud);
}
void __init mach_init_irqs (void)
{
/* Initialize interrupts. */
me2_init_irqs ();
rte_me2_cb_init_irqs ();
}
#ifdef CONFIG_ROM_KERNEL
/* Initialization for kernel in ROM. */
static inline rom_kernel_init (void)
{
/* If the kernel is in ROM, we have to copy any initialized data
from ROM into RAM. */
extern unsigned long _data_load_start, _sdata, _edata;
register unsigned long *src = &_data_load_start;
register unsigned long *dst = &_sdata, *end = &_edata;
while (dst != end)
*dst++ = *src++;
}
#endif /* CONFIG_ROM_KERNEL */
static void install_interrupt_vectors (void)
{
unsigned long *p1, *p2;
ME2_IRAMM = 0x03; /* V850E/ME2 iRAM write mode */
/* vector copy to iRAM */
p1 = (unsigned long *)0; /* v85x vector start */
p2 = (unsigned long *)&_intv_start;
while (p2 < (unsigned long *)&_intv_end)
*p1++ = *p2++;
ME2_IRAMM = 0x00; /* V850E/ME2 iRAM read mode */
}
/* CompactFlash */
static void cf_power_on (void)
{
/* CF card detected? */
if (CB_CF_STS0 & 0x0030)
return;
CB_CF_REG0 = 0x0002; /* reest on */
mdelay (10);
CB_CF_REG0 = 0x0003; /* power on */
mdelay (10);
CB_CF_REG0 = 0x0001; /* reset off */
mdelay (10);
}
static void cf_power_off (void)
{
CB_CF_REG0 = 0x0003; /* power on */
mdelay (10);
CB_CF_REG0 = 0x0002; /* reest on */
mdelay (10);
}
void __init mach_early_init (void)
{
install_interrupt_vectors ();
/* CS1 SDRAM instruction cache enable */
v850e_cache_enable (0x04, 0x03, 0);
rte_cb_early_init ();
/* CompactFlash power on */
cf_power_on ();
#if defined (CONFIG_ROM_KERNEL)
rom_kernel_init ();
#endif
}
/* RTE-V850E/ME2-CB Programmable Interrupt Controller. */
static struct cb_pic_irq_init cb_pic_irq_inits[] = {
{ "CB_EXTTM0", IRQ_CB_EXTTM0, 1, 1, 6 },
{ "CB_EXTSIO", IRQ_CB_EXTSIO, 1, 1, 6 },
{ "CB_TOVER", IRQ_CB_TOVER, 1, 1, 6 },
{ "CB_GINT0", IRQ_CB_GINT0, 1, 1, 6 },
{ "CB_USB", IRQ_CB_USB, 1, 1, 6 },
{ "CB_LANC", IRQ_CB_LANC, 1, 1, 6 },
{ "CB_USB_VBUS_ON", IRQ_CB_USB_VBUS_ON, 1, 1, 6 },
{ "CB_USB_VBUS_OFF", IRQ_CB_USB_VBUS_OFF, 1, 1, 6 },
{ "CB_EXTTM1", IRQ_CB_EXTTM1, 1, 1, 6 },
{ "CB_EXTTM2", IRQ_CB_EXTTM2, 1, 1, 6 },
{ 0 }
};
#define NUM_CB_PIC_IRQ_INITS \
((sizeof cb_pic_irq_inits / sizeof cb_pic_irq_inits[0]) - 1)
static struct hw_interrupt_type cb_pic_hw_itypes[NUM_CB_PIC_IRQ_INITS];
static unsigned char cb_pic_active_irqs = 0;
void __init rte_me2_cb_init_irqs (void)
{
cb_pic_init_irq_types (cb_pic_irq_inits, cb_pic_hw_itypes);
/* Initalize on board PIC1 (not PIC0) enable */
CB_PIC_INT0M = 0x0000;
CB_PIC_INT1M = 0x0000;
CB_PIC_INTR = 0x0000;
CB_PIC_INTEN |= CB_PIC_INT1EN;
ME2_PORT2_PMC |= 0x08; /* INTP23/SCK1 mode */
ME2_PORT2_PFC &= ~0x08; /* INTP23 mode */
ME2_INTR(2) &= ~0x08; /* INTP23 falling-edge detect */
ME2_INTF(2) &= ~0x08; /* " */
rte_cb_init_irqs (); /* gbus &c */
}
/* Enable interrupt handling for interrupt IRQ. */
void cb_pic_enable_irq (unsigned irq)
{
CB_PIC_INT1M |= 1 << (irq - CB_PIC_BASE_IRQ);
}
void cb_pic_disable_irq (unsigned irq)
{
CB_PIC_INT1M &= ~(1 << (irq - CB_PIC_BASE_IRQ));
}
void cb_pic_shutdown_irq (unsigned irq)
{
cb_pic_disable_irq (irq);
if (--cb_pic_active_irqs == 0)
free_irq (IRQ_CB_PIC, 0);
CB_PIC_INT1M &= ~(1 << (irq - CB_PIC_BASE_IRQ));
}
static void cb_pic_handle_irq (int irq, void *dev_id, struct pt_regs *regs)
{
unsigned status = CB_PIC_INTR;
unsigned enable = CB_PIC_INT1M;
/* Only pay attention to enabled interrupts. */
status &= enable;
CB_PIC_INTEN &= ~CB_PIC_INT1EN;
if (status) {
unsigned mask = 1;
irq = CB_PIC_BASE_IRQ;
do {
/* There's an active interrupt, find out which one,
and call its handler. */
while (! (status & mask)) {
irq++;
mask <<= 1;
}
status &= ~mask;
CB_PIC_INTR = mask;
/* Recursively call handle_irq to handle it. */
handle_irq (irq, regs);
} while (status);
}
CB_PIC_INTEN |= CB_PIC_INT1EN;
}
static void irq_nop (unsigned irq) { }
static unsigned cb_pic_startup_irq (unsigned irq)
{
int rval;
if (cb_pic_active_irqs == 0) {
rval = request_irq (IRQ_CB_PIC, cb_pic_handle_irq,
SA_INTERRUPT, "cb_pic_handler", 0);
if (rval != 0)
return rval;
}
cb_pic_active_irqs++;
cb_pic_enable_irq (irq);
return 0;
}
/* Initialize HW_IRQ_TYPES for INTC-controlled irqs described in array
INITS (which is terminated by an entry with the name field == 0). */
void __init cb_pic_init_irq_types (struct cb_pic_irq_init *inits,
struct hw_interrupt_type *hw_irq_types)
{
struct cb_pic_irq_init *init;
for (init = inits; init->name; init++) {
struct hw_interrupt_type *hwit = hw_irq_types++;
hwit->typename = init->name;
hwit->startup = cb_pic_startup_irq;
hwit->shutdown = cb_pic_shutdown_irq;
hwit->enable = cb_pic_enable_irq;
hwit->disable = cb_pic_disable_irq;
hwit->ack = irq_nop;
hwit->end = irq_nop;
/* Initialize kernel IRQ infrastructure for this interrupt. */
init_irq_handlers(init->base, init->num, init->interval, hwit);
}
}
arch/v850/kernel/rte_nb85e_cb.c
View file @ 051063b5
......@@ -21,7 +21,7 @@
#include <asm/atomic.h>
#include <asm/page.h>
#include <asm/nb85e.h>
#include <asm/v850e.h>
#include <asm/rte_nb85e_cb.h>
#include "mach.h"
......@@ -41,7 +41,7 @@ void __init mach_early_init (void)
Unfortunately, the dcache seems to be buggy, so we only use the
icache for now. */
nb85e_cache_enable (0x0040 /* BHC */, 0x0000 /* DCC */);
v850e_cache_enable (0x0040 /*BHC*/, 0x0003 /*ICC*/, 0x0000 /*DCC*/);
rte_cb_early_init ();
}
......
arch/v850/kernel/sim85e2c.c → arch/v850/kernel/sim85e2.c
View file @ 051063b5
/*
* arch/v850/kernel/sim85e2c.c -- Machine-specific stuff for
* arch/v850/kernel/sim85e2.c -- Machine-specific stuff for
* V850E2 RTL simulator
*
* Copyright (C) 2002 NEC Corporation
* Copyright (C) 2002 Miles Bader <miles@gnu.org>
* Copyright (C) 2002,03 NEC Electronics Corporation
* Copyright (C) 2002,03 Miles Bader <miles@gnu.org>
*
* This file is subject to the terms and conditions of the GNU General
* Public License. See the file COPYING in the main directory of this
......@@ -26,17 +26,47 @@
#include "mach.h"
/* There are 4 possible areas we can use:
IRAM (1MB) is fast for instruction fetches, but slow for data
DRAM (1020KB) is fast for data, but slow for instructions
ERAM is cached, so should be fast for both insns and data
SDRAM is external DRAM, similar to ERAM
*/
#define INIT_MEMC_FOR_SDRAM
#define USE_SDRAM_AREA
#define KERNEL_IN_SDRAM_AREA
#define DCACHE_MODE V850E2_CACHE_BTSC_DCM_WT
/*#define DCACHE_MODE V850E2_CACHE_BTSC_DCM_WB_ALLOC*/
#ifdef USE_SDRAM_AREA
#define RAM_START SDRAM_ADDR
#define RAM_END (SDRAM_ADDR + SDRAM_SIZE)
#else
/* When we use DRAM, we need to account for the fact that the end of it is
used for R0_RAM. */
#define RAM_START DRAM_ADDR
#define RAM_END R0_RAM_ADDR
#endif
extern void memcons_setup (void);
void __init mach_early_init (void)
#ifdef KERNEL_IN_SDRAM_AREA
#define EARLY_INIT_SECTION_ATTR __attribute__ ((section (".early.text")))
#else
#define EARLY_INIT_SECTION_ATTR __init
#endif
void EARLY_INIT_SECTION_ATTR mach_early_init (void)
{
extern int panic_timeout;
/* Don't stop the simulator at `halt' instructions. */
NOTHAL = 1;
/* The sim85e2c simulator tracks `undefined' values, so to make
/* The sim85e2 simulator tracks `undefined' values, so to make
debugging easier, we begin by zeroing out all otherwise
undefined registers. This is not strictly necessary.
......@@ -67,10 +97,41 @@ void __init mach_early_init (void)
asm volatile ("ldsr r0, 16; ldsr r0, 17; ldsr r0, 18; ldsr r0, 19");
asm volatile ("ldsr r0, 20");
#ifdef INIT_MEMC_FOR_SDRAM
/* Settings for SDRAM controller. */
V850E2_VSWC = 0x0042;
V850E2_BSC = 0x9286;
V850E2_BCT(0) = 0xb000; /* was: 0 */
V850E2_BCT(1) = 0x000b;
V850E2_ASC = 0;
V850E2_LBS = 0xa9aa; /* was: 0xaaaa */
V850E2_LBC(0) = 0;
V850E2_LBC(1) = 0; /* was: 0x3 */
V850E2_BCC = 0;
V850E2_RFS(4) = 0x800a; /* was: 0xf109 */
V850E2_SCR(4) = 0x2091; /* was: 0x20a1 */
V850E2_RFS(3) = 0x800c;
V850E2_SCR(3) = 0x20a1;
V850E2_DWC(0) = 0;
V850E2_DWC(1) = 0;
#endif
#if 0
#ifdef CONFIG_V850E2_SIM85E2S
/* Turn on the caches. */
NA85E2C_CACHE_BTSC
|= (NA85E2C_CACHE_BTSC_ICM | NA85E2C_CACHE_BTSC_DCM0);
NA85E2C_BUSM_BHC = 0xFFFF;
V850E2_CACHE_BTSC = V850E2_CACHE_BTSC_ICM | DCACHE_MODE;
V850E2_BHC = 0x1010;
#elif CONFIG_V850E2_SIM85E2C
V850E2_CACHE_BTSC |= (V850E2_CACHE_BTSC_ICM | V850E2_CACHE_BTSC_DCM0);
V850E2_BUSM_BHC = 0xFFFF;
#endif
#else
V850E2_BHC = 0;
#endif
/* Don't stop the simulator at `halt' instructions. */
SIM85E2_NOTHAL = 1;
/* Ensure that the simulator halts on a panic, instead of going
into an infinite loop inside the panic function. */
......@@ -84,18 +145,23 @@ void __init mach_setup (char **cmdline)
void mach_get_physical_ram (unsigned long *ram_start, unsigned long *ram_len)
{
/* There are 3 possible areas we can use:
IRAM (1MB) is fast for instruction fetches, but slow for data
DRAM (1020KB) is fast for data, but slow for instructions
ERAM is cached, so should be fast for both insns and data,
_but_ currently only supports write-through caching, so
writes are slow.
Since there's really no area that's good for general kernel
use, we use DRAM -- it won't be good for user programs
(which will be loaded into kernel allocated memory), but
currently we're more concerned with testing the kernel. */
*ram_start = DRAM_ADDR;
*ram_len = R0_RAM_ADDR - DRAM_ADDR;
*ram_start = RAM_START;
*ram_len = RAM_END - RAM_START;
}
void __init mach_reserve_bootmem ()
{
extern char _root_fs_image_start, _root_fs_image_end;
u32 root_fs_image_start = (u32)&_root_fs_image_start;
u32 root_fs_image_end = (u32)&_root_fs_image_end;
/* Reserve the memory used by the root filesystem image if it's
in RAM. */
if (root_fs_image_end > root_fs_image_start
&& root_fs_image_start >= RAM_START
&& root_fs_image_start < RAM_END)
reserve_bootmem (root_fs_image_start,
root_fs_image_end - root_fs_image_start);
}
void __init mach_sched_init (struct irqaction *timer_action)
......@@ -114,7 +180,7 @@ void mach_gettimeofday (struct timespec *tv)
/* Interrupts */
struct nb85e_intc_irq_init irq_inits[] = {
struct v850e_intc_irq_init irq_inits[] = {
{ "IRQ", 0, NUM_MACH_IRQS, 1, 7 },
{ 0 }
};
......@@ -123,14 +189,14 @@ struct hw_interrupt_type hw_itypes[1];
/* Initialize interrupts. */
void __init mach_init_irqs (void)
{
nb85e_intc_init_irq_types (irq_inits, hw_itypes);
v850e_intc_init_irq_types (irq_inits, hw_itypes);
}
void machine_halt (void) __attribute__ ((noreturn));
void machine_halt (void)
{
SIMFIN = 0; /* Halt immediately. */
SIM85E2_SIMFIN = 0; /* Halt immediately. */
for (;;) {}
}
......
arch/v850/kernel/teg.c
View file @ 051063b5
......@@ -22,7 +22,7 @@
#include <asm/atomic.h>
#include <asm/page.h>
#include <asm/machdep.h>
#include <asm/nb85e_timer_d.h>
#include <asm/v850e_timer_d.h>
#include "mach.h"
......@@ -31,12 +31,12 @@ void __init mach_sched_init (struct irqaction *timer_action)
/* Select timer interrupt instead of external pin. */
TEG_ISS |= 0x1;
/* Start hardware timer. */
nb85e_timer_d_configure (0, HZ);
v850e_timer_d_configure (0, HZ);
/* Install timer interrupt handler. */
setup_irq (IRQ_INTCMD(0), timer_action);
}
static struct nb85e_intc_irq_init irq_inits[] = {
static struct v850e_intc_irq_init irq_inits[] = {
{ "IRQ", 0, NUM_CPU_IRQS, 1, 7 },
{ "CMD", IRQ_INTCMD(0), IRQ_INTCMD_NUM, 1, 5 },
{ "SER", IRQ_INTSER(0), IRQ_INTSER_NUM, 1, 3 },
......@@ -51,7 +51,7 @@ static struct hw_interrupt_type hw_itypes[NUM_IRQ_INITS];
/* Initialize MA chip interrupts. */
void __init teg_init_irqs (void)
{
nb85e_intc_init_irq_types (irq_inits, hw_itypes);
v850e_intc_init_irq_types (irq_inits, hw_itypes);
}
/* Called before configuring an on-chip UART. */
......
arch/v850/kernel/v850e2_cache.c 0 → 100644
View file @ 051063b5
/*
* arch/v850/kernel/v850e2_cache.c -- Cache control for V850E2 cache
* memories
*
* Copyright (C) 2003 NEC Electronics Corporation
* Copyright (C) 2003 Miles Bader <miles@gnu.org>
*
* This file is subject to the terms and conditions of the GNU General
* Public License. See the file COPYING in the main directory of this
* archive for more details.
*
* Written by Miles Bader <miles@gnu.org>
*/
#include <linux/mm.h>
#include <asm/v850e2_cache.h>
/* Cache operations we can do. The encoding corresponds directly to the
value we need to write into the COPR register. */
enum cache_op {
OP_SYNC_IF_DIRTY = V850E2_CACHE_COPR_CFC(0), /* 000 */
OP_SYNC_IF_VALID = V850E2_CACHE_COPR_CFC(1), /* 001 */
OP_SYNC_IF_VALID_AND_CLEAR = V850E2_CACHE_COPR_CFC(3), /* 011 */
OP_WAY_CLEAR = V850E2_CACHE_COPR_CFC(4), /* 100 */
OP_FILL = V850E2_CACHE_COPR_CFC(5), /* 101 */
OP_CLEAR = V850E2_CACHE_COPR_CFC(6), /* 110 */
OP_CREATE_DIRTY = V850E2_CACHE_COPR_CFC(7) /* 111 */
};
/* Which cache to use. This encoding also corresponds directly to the
value we need to write into the COPR register. */
enum cache {
ICACHE = 0,
DCACHE = V850E2_CACHE_COPR_LBSL
};
/* Returns ADDR rounded down to the beginning of its cache-line. */
#define CACHE_LINE_ADDR(addr) \
((addr) & ~(V850E2_CACHE_LINE_SIZE - 1))
/* Returns END_ADDR rounded up to the `limit' of its cache-line. */
#define CACHE_LINE_END_ADDR(end_addr) \
CACHE_LINE_ADDR(end_addr + (V850E2_CACHE_LINE_SIZE - 1))
/* Low-level cache ops. */
/* Apply cache-op OP to all entries in CACHE. */
static inline void cache_op_all (enum cache_op op, enum cache cache)
{
int cmd = op | cache | V850E2_CACHE_COPR_WSLE | V850E2_CACHE_COPR_STRT;
if (op != OP_WAY_CLEAR) {
/* The WAY_CLEAR operation does the whole way, but other
ops take begin-index and count params; we just indicate
the entire cache. */
V850E2_CACHE_CADL = 0;
V850E2_CACHE_CADH = 0;
V850E2_CACHE_CCNT = V850E2_CACHE_WAY_SIZE - 1;
}
V850E2_CACHE_COPR = cmd | V850E2_CACHE_COPR_WSL(0); /* way 0 */
V850E2_CACHE_COPR = cmd | V850E2_CACHE_COPR_WSL(1); /* way 1 */
V850E2_CACHE_COPR = cmd | V850E2_CACHE_COPR_WSL(2); /* way 2 */
V850E2_CACHE_COPR = cmd | V850E2_CACHE_COPR_WSL(3); /* way 3 */
}
/* Apply cache-op OP to all entries in CACHE covering addresses ADDR
through ADDR+LEN. */
static inline void cache_op_range (enum cache_op op, u32 addr, u32 len,
enum cache cache)
{
u32 start = CACHE_LINE_ADDR (addr);
u32 end = CACHE_LINE_END_ADDR (addr + len);
u32 num_lines = (end - start) >> V850E2_CACHE_LINE_SIZE_BITS;
V850E2_CACHE_CADL = start & 0xFFFF;
V850E2_CACHE_CADH = start >> 16;
V850E2_CACHE_CCNT = num_lines - 1;
V850E2_CACHE_COPR = op | cache | V850E2_CACHE_COPR_STRT;
}
/* High-level ops. */
static void cache_exec_after_store_all (void)
{
cache_op_all (OP_SYNC_IF_DIRTY, DCACHE);
cache_op_all (OP_WAY_CLEAR, ICACHE);
}
static void cache_exec_after_store_range (u32 start, u32 len)
{
cache_op_range (OP_SYNC_IF_DIRTY, start, len, DCACHE);
cache_op_range (OP_CLEAR, start, len, ICACHE);
}
/* Exported functions. */
void flush_icache (void)
{
cache_exec_after_store_all ();
}
void flush_icache_range (unsigned long start, unsigned long end)
{
cache_exec_after_store_range (start, end - start);
}
void flush_icache_page (struct vm_area_struct *vma, struct page *page)
{
cache_exec_after_store_range (page_to_virt (page), PAGE_SIZE);
}
void flush_icache_user_range (struct vm_area_struct *vma, struct page *page,
unsigned long addr, int len)
{
cache_exec_after_store_range (addr, len);
}
void flush_cache_sigtramp (unsigned long addr)
{
/* For the exact size, see signal.c, but 16 bytes should be enough. */
cache_exec_after_store_range (addr, 16);
}
arch/v850/kernel/nb85e_cache.c → arch/v850/kernel/v850e_cache.c
View file @ 051063b5
/*
* arch/v850/kernel/nb85e_cache.c -- Cache control for NB85E_CACHE212 and
* NB85E_CACHE213 cache memories
* arch/v850/kernel/v850e_cache.c -- Cache control for V850E cache memories
*
* Copyright (C) 2003 NEC Electronics Corporation
* Copyright (C) 2003 Miles Bader <miles@gnu.org>
......@@ -12,19 +11,31 @@
* Written by Miles Bader <miles@gnu.org>
*/
/* This file implements cache control for the rather simple cache used on
some V850E CPUs, specifically the NB85E/TEG CPU-core and the V850E/ME2
CPU. V850E2 processors have their own (better) cache
implementation. */
#include <asm/entry.h>
#include <asm/nb85e_cache.h>
#include <asm/v850e_cache.h>
#define WAIT_UNTIL_CLEAR(value) while (value) {}
/* Set caching params via the BHC and DCC registers. */
void nb85e_cache_enable (u16 bhc, u16 dcc)
void v850e_cache_enable (u16 bhc, u16 icc, u16 dcc)
{
unsigned long *r0_ram = (unsigned long *)R0_RAM_ADDR;
register u16 bhc_val asm ("r6") = bhc;
/* Read the instruction cache control register (ICC) and confirm
that bits 0 and 1 (TCLR0, TCLR1) are all cleared. */
WAIT_UNTIL_CLEAR (V850E_CACHE_ICC & 0x3);
V850E_CACHE_ICC = icc;
#ifdef V850E_CACHE_DCC
/* Configure data-cache. */
NB85E_CACHE_DCC = dcc;
V850E_CACHE_DCC = dcc;
#endif /* V850E_CACHE_DCC */
/* Configure caching for various memory regions by writing the BHC
register. The documentation says that an instruction _cannot_
......@@ -32,9 +43,12 @@ void nb85e_cache_enable (u16 bhc, u16 dcc)
instruction itself exists; to work around this, we store
appropriate instructions into the on-chip RAM area (which is never
cached), and briefly jump there to do the work. */
r0_ram[0] = 0xf0720760; /* st.h r0, 0xfffff072[r0] */
r0_ram[1] = 0xf06a3760; /* st.h r6, 0xfffff06a[r0] */
r0_ram[2] = 0x5640006b; /* jmp [r11] */
#ifdef V850E_CACHE_WRITE_IBS
*r0_ram++ = 0xf0720760; /* st.h r0, 0xfffff072[r0] */
#endif
*r0_ram++ = 0xf06a3760; /* st.h r6, 0xfffff06a[r0] */
*r0_ram = 0x5640006b; /* jmp [r11] */
asm ("mov hilo(1f), r11; jmp [%1]; 1:;"
:: "r" (bhc_val), "r" (R0_RAM_ADDR) : "r11");
}
......@@ -43,11 +57,11 @@ static void clear_icache (void)
{
/* 1. Read the instruction cache control register (ICC) and confirm
that bits 0 and 1 (TCLR0, TCLR1) are all cleared. */
WAIT_UNTIL_CLEAR (NB85E_CACHE_ICC & 0x3);
WAIT_UNTIL_CLEAR (V850E_CACHE_ICC & 0x3);
/* 2. Read the ICC register and confirm that bit 12 (LOCK0) is
cleared. Bit 13 of the ICC register is always cleared. */
WAIT_UNTIL_CLEAR (NB85E_CACHE_ICC & 0x1000);
WAIT_UNTIL_CLEAR (V850E_CACHE_ICC & 0x1000);
/* 3. Set the TCLR0 and TCLR1 bits of the ICC register as follows,
when clearing way 0 and way 1 at the same time:
......@@ -55,13 +69,17 @@ static void clear_icache (void)
(b) Read the TCLR0 and TCLR1 bits to confirm that these bits
are cleared.
(c) Perform (a) and (b) above again. */
NB85E_CACHE_ICC |= 0x3;
WAIT_UNTIL_CLEAR (NB85E_CACHE_ICC & 0x3);
V850E_CACHE_ICC |= 0x3;
WAIT_UNTIL_CLEAR (V850E_CACHE_ICC & 0x3);
#ifdef V850E_CACHE_REPEAT_ICC_WRITE
/* Do it again. */
NB85E_CACHE_ICC |= 0x3;
WAIT_UNTIL_CLEAR (NB85E_CACHE_ICC & 0x3);
V850E_CACHE_ICC |= 0x3;
WAIT_UNTIL_CLEAR (V850E_CACHE_ICC & 0x3);
#endif
}
#ifdef V850E_CACHE_DCC
/* Flush or clear (or both) the data cache, depending on the value of FLAGS;
the procedure is the same for both, just the control bits used differ (and
both may be performed simultaneously). */
......@@ -69,47 +87,54 @@ static void dcache_op (unsigned short flags)
{
/* 1. Read the data cache control register (DCC) and confirm that bits
0, 1, 4, and 5 (DC00, DC01, DC04, DC05) are all cleared. */
WAIT_UNTIL_CLEAR (NB85E_CACHE_DCC & 0x33);
WAIT_UNTIL_CLEAR (V850E_CACHE_DCC & 0x33);
/* 2. Clear DCC register bit 12 (DC12), bit 13 (DC13), or both
depending on the way for which tags are to be cleared. */
NB85E_CACHE_DCC &= ~0xC000;
V850E_CACHE_DCC &= ~0xC000;
/* 3. Set DCC register bit 0 (DC00), bit 1 (DC01) or both depending on
the way for which tags are to be cleared.
...
Set DCC register bit 4 (DC04), bit 5 (DC05), or both depending
on the way to be data flushed. */
NB85E_CACHE_DCC |= flags;
V850E_CACHE_DCC |= flags;
/* 4. Read DCC register bit DC00, DC01 [DC04, DC05], or both depending
on the way for which tags were cleared [flushed] and confirm
that that bit is cleared. */
WAIT_UNTIL_CLEAR (NB85E_CACHE_DCC & flags);
WAIT_UNTIL_CLEAR (V850E_CACHE_DCC & flags);
}
#endif /* V850E_CACHE_DCC */
/* Flushes the contents of the dcache to memory. */
static inline void flush_dcache (void)
{
#ifdef V850E_CACHE_DCC
/* We only need to do something if in write-back mode. */
if (NB85E_CACHE_DCC & 0x0400)
if (V850E_CACHE_DCC & 0x0400)
dcache_op (0x30);
#endif /* V850E_CACHE_DCC */
}
/* Flushes the contents of the dcache to memory, and then clears it. */
static inline void clear_dcache (void)
{
#ifdef V850E_CACHE_DCC
/* We only need to do something if the dcache is enabled. */
if (NB85E_CACHE_DCC & 0x0C00)
if (V850E_CACHE_DCC & 0x0C00)
dcache_op (0x33);
#endif /* V850E_CACHE_DCC */
}
/* Clears the dcache without flushing to memory first. */
static inline void clear_dcache_no_flush (void)
{
#ifdef V850E_CACHE_DCC
/* We only need to do something if the dcache is enabled. */
if (NB85E_CACHE_DCC & 0x0C00)
if (V850E_CACHE_DCC & 0x0C00)
dcache_op (0x3);
#endif /* V850E_CACHE_DCC */
}
static inline void cache_exec_after_store (void)
......@@ -121,58 +146,28 @@ static inline void cache_exec_after_store (void)
/* Exported functions. */
void inline nb85e_cache_flush_all (void)
{
clear_icache ();
clear_dcache ();
}
void nb85e_cache_flush_mm (struct mm_struct *mm)
{
/* nothing */
}
void nb85e_cache_flush_range (struct mm_struct *mm,
unsigned long start, unsigned long end)
{
/* nothing */
}
void nb85e_cache_flush_page (struct vm_area_struct *vma,
unsigned long page_addr)
{
/* nothing */
}
void nb85e_cache_flush_dcache_page (struct page *page)
{
/* nothing */
}
void nb85e_cache_flush_icache (void)
void flush_icache (void)
{
cache_exec_after_store ();
}
void nb85e_cache_flush_icache_range (unsigned long start, unsigned long end)
void flush_icache_range (unsigned long start, unsigned long end)
{
cache_exec_after_store ();
}
void nb85e_cache_flush_icache_page (struct vm_area_struct *vma,
struct page *page)
void flush_icache_page (struct vm_area_struct *vma, struct page *page)
{
cache_exec_after_store ();
}
void nb85e_cache_flush_icache_user_range (struct vm_area_struct *vma,
struct page *page,
void flush_icache_user_range (struct vm_area_struct *vma, struct page *page,
unsigned long adr, int len)
{
cache_exec_after_store ();
}
void nb85e_cache_flush_sigtramp (unsigned long addr)
void flush_cache_sigtramp (unsigned long addr)
{
cache_exec_after_store ();
}
arch/v850/kernel/nb85e_intc.c → arch/v850/kernel/v850e_intc.c
View file @ 051063b5
/*
* arch/v850/kernel/nb85e_intc.c -- NB85E cpu core interrupt controller (INTC)
* arch/v850/kernel/v850e_intc.c -- V850E interrupt controller (INTC)
*
* Copyright (C) 2001,02,03 NEC Electronics Corporation
* Copyright (C) 2001,02,03 Miles Bader <miles@gnu.org>
......@@ -15,18 +15,18 @@
#include <linux/init.h>
#include <linux/irq.h>
#include <asm/nb85e_intc.h>
#include <asm/v850e_intc.h>
static void irq_nop (unsigned irq) { }
static unsigned nb85e_intc_irq_startup (unsigned irq)
static unsigned v850e_intc_irq_startup (unsigned irq)
{
nb85e_intc_clear_pending_irq (irq);
nb85e_intc_enable_irq (irq);
v850e_intc_clear_pending_irq (irq);
v850e_intc_enable_irq (irq);
return 0;
}
static void nb85e_intc_end_irq (unsigned irq)
static void v850e_intc_end_irq (unsigned irq)
{
unsigned long psw, temp;
......@@ -64,22 +64,22 @@ static void nb85e_intc_end_irq (unsigned irq)
/* Initialize HW_IRQ_TYPES for INTC-controlled irqs described in array
INITS (which is terminated by an entry with the name field == 0). */
void __init nb85e_intc_init_irq_types (struct nb85e_intc_irq_init *inits,
void __init v850e_intc_init_irq_types (struct v850e_intc_irq_init *inits,
struct hw_interrupt_type *hw_irq_types)
{
struct nb85e_intc_irq_init *init;
struct v850e_intc_irq_init *init;
for (init = inits; init->name; init++) {
unsigned i;
struct hw_interrupt_type *hwit = hw_irq_types++;
hwit->typename = init->name;
hwit->startup = nb85e_intc_irq_startup;
hwit->shutdown = nb85e_intc_disable_irq;
hwit->enable = nb85e_intc_enable_irq;
hwit->disable = nb85e_intc_disable_irq;
hwit->startup = v850e_intc_irq_startup;
hwit->shutdown = v850e_intc_disable_irq;
hwit->enable = v850e_intc_enable_irq;
hwit->disable = v850e_intc_disable_irq;
hwit->ack = irq_nop;
hwit->end = nb85e_intc_end_irq;
hwit->end = v850e_intc_end_irq;
/* Initialize kernel IRQ infrastructure for this interrupt. */
init_irq_handlers(init->base, init->num, init->interval, hwit);
......@@ -92,13 +92,13 @@ void __init nb85e_intc_init_irq_types (struct nb85e_intc_irq_init *inits,
interrupts are initially disabled), then
assume whoever enabled it has set things up
properly, and avoid messing with it. */
if (! nb85e_intc_irq_enabled (irq))
if (! v850e_intc_irq_enabled (irq))
/* This write also (1) disables the
interrupt, and (2) clears any pending
interrupts. */
NB85E_INTC_IC (irq)
= (NB85E_INTC_IC_PR (init->priority)
| NB85E_INTC_IC_MK);
V850E_INTC_IC (irq)
= (V850E_INTC_IC_PR (init->priority)
| V850E_INTC_IC_MK);
}
}
}
arch/v850/kernel/nb85e_timer_d.c → arch/v850/kernel/v850e_timer_d.c
View file @ 051063b5
/*
* include/asm-v850/nb85e_timer_d.c -- `Timer D' component often used
* with the NB85E cpu core
* include/asm-v850/v850e_timer_d.c -- `Timer D' component often used
* with V850E CPUs
*
* Copyright (C) 2001,02 NEC Corporation
* Copyright (C) 2001,02 Miles Bader <miles@gnu.org>
* Copyright (C) 2001,02,03 NEC Electronics Corporation
* Copyright (C) 2001,02,03 Miles Bader <miles@gnu.org>
*
* This file is subject to the terms and conditions of the GNU General
* Public License. See the file COPYING in the main directory of this
......@@ -14,41 +14,41 @@
#include <linux/kernel.h>
#include <asm/nb85e_utils.h>
#include <asm/nb85e_timer_d.h>
#include <asm/v850e_utils.h>
#include <asm/v850e_timer_d.h>
/* Start interval timer TIMER (0-3). The timer will issue the
corresponding INTCMD interrupt RATE times per second.
This function does not enable the interrupt. */
void nb85e_timer_d_configure (unsigned timer, unsigned rate)
void v850e_timer_d_configure (unsigned timer, unsigned rate)
{
unsigned divlog2, count;
/* Calculate params for timer. */
if (! calc_counter_params (
NB85E_TIMER_D_BASE_FREQ, rate,
NB85E_TIMER_D_TMCD_CS_MIN, NB85E_TIMER_D_TMCD_CS_MAX, 16,
V850E_TIMER_D_BASE_FREQ, rate,
V850E_TIMER_D_TMCD_CS_MIN, V850E_TIMER_D_TMCD_CS_MAX, 16,
&divlog2, &count))
printk (KERN_WARNING
"Cannot find interval timer %d setting suitable"
" for rate of %dHz.\n"
"Using rate of %dHz instead.\n",
timer, rate,
(NB85E_TIMER_D_BASE_FREQ >> divlog2) >> 16);
(V850E_TIMER_D_BASE_FREQ >> divlog2) >> 16);
/* Do the actual hardware timer initialization: */
/* Enable timer. */
NB85E_TIMER_D_TMCD(timer) = NB85E_TIMER_D_TMCD_CAE;
V850E_TIMER_D_TMCD(timer) = V850E_TIMER_D_TMCD_CAE;
/* Set clock divider. */
NB85E_TIMER_D_TMCD(timer)
= NB85E_TIMER_D_TMCD_CAE
| NB85E_TIMER_D_TMCD_CS(divlog2);
V850E_TIMER_D_TMCD(timer)
= V850E_TIMER_D_TMCD_CAE
| V850E_TIMER_D_TMCD_CS(divlog2);
/* Set timer compare register. */
NB85E_TIMER_D_CMD(timer) = count;
V850E_TIMER_D_CMD(timer) = count;
/* Start counting. */
NB85E_TIMER_D_TMCD(timer)
= NB85E_TIMER_D_TMCD_CAE
| NB85E_TIMER_D_TMCD_CS(divlog2)
| NB85E_TIMER_D_TMCD_CE;
V850E_TIMER_D_TMCD(timer)
= V850E_TIMER_D_TMCD_CAE
| V850E_TIMER_D_TMCD_CS(divlog2)
| V850E_TIMER_D_TMCD_CE;
}
arch/v850/kernel/nb85e_utils.c → arch/v850/kernel/v850e_utils.c
View file @ 051063b5
/*
* include/asm-v850/nb85e_utils.h -- Utility functions associated with
* the NB85E cpu core
* include/asm-v850/v850e_utils.h -- Utility functions associated with
* V850E CPUs
*
* Copyright (C) 2001,02 NEC Corporation
* Copyright (C) 2001,02 Miles Bader <miles@gnu.org>
* Copyright (C) 2001,02,03 NEC Electronics Corporation
* Copyright (C) 2001,02,03 Miles Bader <miles@gnu.org>
*
* This file is subject to the terms and conditions of the GNU General
* Public License. See the file COPYING in the main directory of this
......@@ -12,10 +12,7 @@
* Written by Miles Bader <miles@gnu.org>
*/
/* Note: these functions are often associated with the N85E cpu core,
but not always, which is why they're not in `nb85e.c'. */
#include <asm/nb85e_utils.h>
#include <asm/v850e_utils.h>
/* Calculate counter clock-divider and count values to attain the
desired frequency RATE from the base frequency BASE_FREQ. The
......
arch/v850/rte_me2_cb.ld 0 → 100644
View file @ 051063b5
/* Linker script for the Midas labs RTE-V850E/ME2-CB evaluation board
(CONFIG_RTE_CB_ME2), with kernel in SDRAM. */
MEMORY {
/* 128Kbyte of IRAM */
IRAM : ORIGIN = 0x00000000, LENGTH = 0x00020000
/* 32MB of SDRAM. */
SDRAM : ORIGIN = 0x00800000, LENGTH = 0x02000000
}
#define KRAM SDRAM
SECTIONS {
.text : {
__kram_start = . ;
TEXT_CONTENTS
INTV_CONTENTS /* copy to iRAM (0x0-0x620) */
} > KRAM
.data : {
DATA_CONTENTS
BSS_CONTENTS
RAMK_INIT_CONTENTS
__kram_end = . ;
BOOTMAP_CONTENTS
} > KRAM
.root ALIGN (4096) : { ROOT_FS_CONTENTS } > SDRAM
}
arch/v850/sim85e2c.ld → arch/v850/sim85e2.ld
View file @ 051063b5
......@@ -19,26 +19,26 @@ MEMORY {
/* `external ram' (CS1 area), comes after IRAM.
This should match ERAM_ADDR in "include/asm-v580/sim85e2c.h". */
ERAM : ORIGIN = 0x00100000, LENGTH = 0x07f00000
/* Dynamic RAM; uses memory controller. */
/* SDRAM : ORIGIN = 0x10000000, LENGTH = 0x01000000 */
SDRAM : ORIGIN = 0x10000000, LENGTH = 0x00200000/*use 2MB*/
}
SECTIONS {
.iram : {
INTV_CONTENTS
TEXT_CONTENTS
RAMK_INIT_CONTENTS
*arch/v850/kernel/head.o
*(.early.text)
} > IRAM
.data : {
__kram_start = . ;
DATA_CONTENTS
BSS_CONTENTS
ROOT_FS_CONTENTS
/* We stick console output into a buffer here. */
.dram : {
_memcons_output = . ;
. = . + 0x8000 ;
_memcons_output_end = . ;
__kram_end = . ;
BOOTMAP_CONTENTS
} > DRAM AT> DRAM_LOAD
} > DRAM
.sdram : {
/* We stick console output into a buffer here. */
RAMK_KRAM_CONTENTS
ROOT_FS_CONTENTS
} > SDRAM
}
arch/v850/vmlinux.lds.S
View file @ 051063b5
......@@ -206,8 +206,8 @@ _jiffies = _jiffies_64 ;
# include "sim.ld"
#endif
#ifdef CONFIG_V850E2_SIM85E2C
# include "sim85e2c.ld"
#ifdef CONFIG_V850E2_SIM85E2
# include "sim85e2.ld"
#endif
#ifdef CONFIG_V850E2_FPGA85E2C
......@@ -247,3 +247,8 @@ _jiffies = _jiffies_64 ;
# include "rte_nb85e_cb.ld"
# endif
#endif
#ifdef CONFIG_RTE_CB_ME2
# include "rte_me2_cb.ld"
#endif
drivers/serial/Kconfig
View file @ 051063b5
......@@ -404,14 +404,19 @@ config SERIAL_SUNSAB_CONSOLE
on your Sparc system as the console, you can do so by answering
Y to this option.
config V850E_NB85E_UART
config V850E_UART
bool "NEC V850E on-chip UART support"
depends on V850E_NB85E || V850E2_ANNA || V850E_AS85EP1
depends on V850E_MA1 || V850E_ME2 || V850E_TEG || V850E2_ANNA || V850E_AS85EP1
default y
config V850E_NB85E_UART_CONSOLE
config V850E_UARTB
bool
depends V850E_UART && V850E_ME2
default y
config V850E_UART_CONSOLE
bool "Use NEC V850E on-chip UART for console"
depends on V850E_NB85E_UART
depends on V850E_UART
config SERIAL98
tristate "PC-9800 8251-based primary serial port support"
......@@ -426,12 +431,12 @@ config SERIAL98_CONSOLE
config SERIAL_CORE
tristate
default m if SERIAL_AMBA!=y && SERIAL_CLPS711X!=y && SERIAL_21285!=y && !SERIAL_SA1100 && !SERIAL_ANAKIN && !SERIAL_UART00 && SERIAL_8250!=y && SERIAL_MUX!=y && !SERIAL_ROCKETPORT && !SERIAL_SUNCORE && !V850E_NB85E_UART && (SERIAL_AMBA=m || SERIAL_CLPS711X=m || SERIAL_21285=m || SERIAL_8250=m || SERIAL_MUX=m || SERIAL98=m)
default y if SERIAL_AMBA=y || SERIAL_CLPS711X=y || SERIAL_21285=y || SERIAL_SA1100 || SERIAL_ANAKIN || SERIAL_UART00 || SERIAL_8250=y || SERIAL_MUX=y || SERIAL_ROCKETPORT || SERIAL_SUNCORE || V850E_NB85E_UART || SERIAL98=y
default m if SERIAL_AMBA!=y && SERIAL_CLPS711X!=y && SERIAL_21285!=y && !SERIAL_SA1100 && !SERIAL_ANAKIN && !SERIAL_UART00 && SERIAL_8250!=y && SERIAL_MUX!=y && !SERIAL_ROCKETPORT && !SERIAL_SUNCORE && !V850E_UART && (SERIAL_AMBA=m || SERIAL_CLPS711X=m || SERIAL_21285=m || SERIAL_8250=m || SERIAL_MUX=m || SERIAL98=m)
default y if SERIAL_AMBA=y || SERIAL_CLPS711X=y || SERIAL_21285=y || SERIAL_SA1100 || SERIAL_ANAKIN || SERIAL_UART00 || SERIAL_8250=y || SERIAL_MUX=y || SERIAL_ROCKETPORT || SERIAL_SUNCORE || V850E_UART || SERIAL98=y
config SERIAL_CORE_CONSOLE
bool
depends on SERIAL_AMBA_CONSOLE || SERIAL_CLPS711X_CONSOLE || SERIAL_21285_CONSOLE || SERIAL_SA1100_CONSOLE || SERIAL_ANAKIN_CONSOLE || SERIAL_UART00_CONSOLE || SERIAL_8250_CONSOLE || SERIAL_MUX_CONSOLE || SERIAL_SUNZILOG_CONSOLE || SERIAL_SUNSU_CONSOLE || SERIAL_SUNSAB_CONSOLE || V850E_NB85E_UART_CONSOLE || SERIAL98_CONSOLE
depends on SERIAL_AMBA_CONSOLE || SERIAL_CLPS711X_CONSOLE || SERIAL_21285_CONSOLE || SERIAL_SA1100_CONSOLE || SERIAL_ANAKIN_CONSOLE || SERIAL_UART00_CONSOLE || SERIAL_8250_CONSOLE || SERIAL_MUX_CONSOLE || SERIAL_SUNZILOG_CONSOLE || SERIAL_SUNSU_CONSOLE || SERIAL_SUNSAB_CONSOLE || V850E_UART_CONSOLE || SERIAL98_CONSOLE
default y
config SERIAL_68328
......
drivers/serial/Makefile
View file @ 051063b5
......@@ -29,5 +29,5 @@ obj-$(CONFIG_SERIAL_MUX) += mux.o
obj-$(CONFIG_SERIAL_68328) += 68328serial.o
obj-$(CONFIG_SERIAL_68360) += 68360serial.o
obj-$(CONFIG_SERIAL_COLDFIRE) += mcfserial.o
obj-$(CONFIG_V850E_NB85E_UART) += nb85e_uart.o
obj-$(CONFIG_V850E_UART) += v850e_uart.o
obj-$(CONFIG_SERIAL98) += serial98.o
include/asm-v850/anna.h
View file @ 051063b5
/*
* include/asm-v850/anna.h -- Anna V850E2 evaluation cpu chip/board
*
* Copyright (C) 2001,2002 NEC Corporation
* Copyright (C) 2001,2002 Miles Bader <miles@gnu.org>
* Copyright (C) 2001,02,03 NEC Electronics Corporation
* Copyright (C) 2001,02,03 Miles Bader <miles@gnu.org>
*
* This file is subject to the terms and conditions of the GNU General
* Public License. See the file COPYING in the main directory of this
......@@ -14,8 +14,9 @@
#ifndef __V850_ANNA_H__
#define __V850_ANNA_H__
#include <asm/v850e2.h> /* Based on V850E2 core. */
#define CPU_ARCH "v850e2"
#define CPU_MODEL "v850e2/anna"
#define CPU_MODEL_LONG "NEC V850E2/Anna"
#define PLATFORM "anna"
......@@ -48,30 +49,6 @@
/* Anna specific control registers. */
#define ANNA_CSC_ADDR(n) (0xFFFFF060 + (n) * 2)
#define ANNA_CSC(n) (*(volatile u16 *)ANNA_CSC_ADDR(n))
#define ANNA_BPC_ADDR 0xFFFFF064
#define ANNA_BPC (*(volatile u16 *)ANNA_BPC_ADDR)
#define ANNA_BSC_ADDR 0xFFFFF066
#define ANNA_BSC (*(volatile u16 *)ANNA_BSC_ADDR)
#define ANNA_BEC_ADDR 0xFFFFF068
#define ANNA_BEC (*(volatile u16 *)ANNA_BEC_ADDR)
#define ANNA_BHC_ADDR 0xFFFFF06A
#define ANNA_BHC (*(volatile u16 *)ANNA_BHC_ADDR)
#define ANNA_BCT_ADDR(n) (0xFFFFF480 + (n) * 2)
#define ANNA_BCT(n) (*(volatile u16 *)ANNA_BCT_ADDR(n))
#define ANNA_DWC_ADDR(n) (0xFFFFF484 + (n) * 2)
#define ANNA_DWC(n) (*(volatile u16 *)ANNA_DWC_ADDR(n))
#define ANNA_BCC_ADDR 0xFFFFF488
#define ANNA_BCC (*(volatile u16 *)ANNA_BCC_ADDR)
#define ANNA_ASC_ADDR 0xFFFFF48A
#define ANNA_ASC (*(volatile u16 *)ANNA_ASC_ADDR)
#define ANNA_LBS_ADDR 0xFFFFF48E
#define ANNA_LBS (*(volatile u16 *)ANNA_LBS_ADDR)
#define ANNA_SCR3_ADDR 0xFFFFF4AC
#define ANNA_SCR3 (*(volatile u16 *)ANNA_SCR3_ADDR)
#define ANNA_RFS3_ADDR 0xFFFFF4AE
#define ANNA_RFS3 (*(volatile u16 *)ANNA_RFS3_ADDR)
#define ANNA_ILBEN_ADDR 0xFFFFF7F2
#define ANNA_ILBEN (*(volatile u16 *)ANNA_ILBEN_ADDR)
......@@ -85,9 +62,6 @@
#define ANNA_PORT_PM(n) (*(volatile u8 *)ANNA_PORT_PM_ADDR(n))
/* NB85E-style interrupt system. */
#include <asm/nb85e_intc.h>
/* Hardware-specific interrupt numbers (in the kernel IRQ namespace). */
#define IRQ_INTP(n) (n) /* Pnnn (pin) interrupts 0-15 */
#define IRQ_INTP_NUM 16
......@@ -116,12 +90,15 @@ extern void anna_init_irqs (void);
/* Anna UART details (basically the same as the V850E/MA1, but 2 channels). */
#define NB85E_UART_NUM_CHANNELS 2
#define NB85E_UART_BASE_FREQ (SYS_CLOCK_FREQ / 2)
#define NB85E_UART_CHIP_NAME "V850E2/NA85E2A"
#define V850E_UART_NUM_CHANNELS 2
#define V850E_UART_BASE_FREQ (SYS_CLOCK_FREQ / 2)
#define V850E_UART_CHIP_NAME "V850E2/NA85E2A"
/* This is the UART channel that's actually connected on the board. */
#define V850E_UART_CONSOLE_CHANNEL 1
/* This is a function that gets called before configuring the UART. */
#define NB85E_UART_PRE_CONFIGURE anna_uart_pre_configure
#define V850E_UART_PRE_CONFIGURE anna_uart_pre_configure
#ifndef __ASSEMBLY__
extern void anna_uart_pre_configure (unsigned chan,
unsigned cflags, unsigned baud);
......@@ -130,9 +107,9 @@ extern void anna_uart_pre_configure (unsigned chan,
/* This board supports RTS/CTS for the on-chip UART, but only for channel 1. */
/* CTS for UART channel 1 is pin P37 (bit 7 of port 3). */
#define NB85E_UART_CTS(chan) ((chan) == 1 ? !(ANNA_PORT_IO(3) & 0x80) : 1)
#define V850E_UART_CTS(chan) ((chan) == 1 ? !(ANNA_PORT_IO(3) & 0x80) : 1)
/* RTS for UART channel 1 is pin P07 (bit 7 of port 0). */
#define NB85E_UART_SET_RTS(chan, val) \
#define V850E_UART_SET_RTS(chan, val) \
do { \
if (chan == 1) { \
unsigned old = ANNA_PORT_IO(0); \
......@@ -145,16 +122,16 @@ extern void anna_uart_pre_configure (unsigned chan,
/* Timer C details. */
#define NB85E_TIMER_C_BASE_ADDR 0xFFFFF600
#define V850E_TIMER_C_BASE_ADDR 0xFFFFF600
/* Timer D details (the Anna actually has 5 of these; should change later). */
#define NB85E_TIMER_D_BASE_ADDR 0xFFFFF540
#define NB85E_TIMER_D_TMD_BASE_ADDR (NB85E_TIMER_D_BASE_ADDR + 0x0)
#define NB85E_TIMER_D_CMD_BASE_ADDR (NB85E_TIMER_D_BASE_ADDR + 0x2)
#define NB85E_TIMER_D_TMCD_BASE_ADDR (NB85E_TIMER_D_BASE_ADDR + 0x4)
#define V850E_TIMER_D_BASE_ADDR 0xFFFFF540
#define V850E_TIMER_D_TMD_BASE_ADDR (V850E_TIMER_D_BASE_ADDR + 0x0)
#define V850E_TIMER_D_CMD_BASE_ADDR (V850E_TIMER_D_BASE_ADDR + 0x2)
#define V850E_TIMER_D_TMCD_BASE_ADDR (V850E_TIMER_D_BASE_ADDR + 0x4)
#define NB85E_TIMER_D_BASE_FREQ SYS_CLOCK_FREQ
#define NB85E_TIMER_D_TMCD_CS_MIN 1 /* min 2^1 divider */
#define V850E_TIMER_D_BASE_FREQ SYS_CLOCK_FREQ
#define V850E_TIMER_D_TMCD_CS_MIN 1 /* min 2^1 divider */
/* For <asm/param.h> */
......
include/asm-v850/as85ep1.h
View file @ 051063b5
/*
* include/asm-v850/as85ep1.h -- AS85EP1 evaluation CPU chip/board
*
* Copyright (C) 2001,2002 NEC Corporation
* Copyright (C) 2001,2002 Miles Bader <miles@gnu.org>
* Copyright (C) 2001,02,03 NEC Electronics Corporation
* Copyright (C) 2001,02,03 Miles Bader <miles@gnu.org>
*
* This file is subject to the terms and conditions of the GNU General
* Public License. See the file COPYING in the main directory of this
......@@ -14,8 +14,9 @@
#ifndef __V850_AS85EP1_H__
#define __V850_AS85EP1_H__
#include <asm/v850e.h>
#define CPU_ARCH "v850e"
#define CPU_MODEL "as85ep1"
#define CPU_MODEL_LONG "NEC V850E/AS85EP1"
#define PLATFORM "AS85EP1"
......@@ -86,9 +87,6 @@
#define AS85EP1_PORT_PMC(n) (*(volatile u8 *)AS85EP1_PORT_PMC_ADDR(n))
/* NB85E-style interrupt system. */
#include <asm/nb85e_intc.h>
/* Hardware-specific interrupt numbers (in the kernel IRQ namespace). */
#define IRQ_INTCCC(n) (0x0C + (n))
#define IRQ_INTCCC_NUM 8
......@@ -110,12 +108,12 @@ extern void as85ep1_init_irqs (void);
/* AS85EP1 UART details (basically the same as the V850E/MA1, but 2 channels). */
#define NB85E_UART_NUM_CHANNELS 2
#define NB85E_UART_BASE_FREQ (SYS_CLOCK_FREQ / 4)
#define NB85E_UART_CHIP_NAME "V850E/NA85E"
#define V850E_UART_NUM_CHANNELS 2
#define V850E_UART_BASE_FREQ (SYS_CLOCK_FREQ / 4)
#define V850E_UART_CHIP_NAME "V850E/NA85E"
/* This is a function that gets called before configuring the UART. */
#define NB85E_UART_PRE_CONFIGURE as85ep1_uart_pre_configure
#define V850E_UART_PRE_CONFIGURE as85ep1_uart_pre_configure
#ifndef __ASSEMBLY__
extern void as85ep1_uart_pre_configure (unsigned chan,
unsigned cflags, unsigned baud);
......@@ -124,9 +122,9 @@ extern void as85ep1_uart_pre_configure (unsigned chan,
/* This board supports RTS/CTS for the on-chip UART, but only for channel 1. */
/* CTS for UART channel 1 is pin P54 (bit 4 of port 5). */
#define NB85E_UART_CTS(chan) ((chan) == 1 ? !(AS85EP1_PORT_IO(5) & 0x10) : 1)
#define V850E_UART_CTS(chan) ((chan) == 1 ? !(AS85EP1_PORT_IO(5) & 0x10) : 1)
/* RTS for UART channel 1 is pin P53 (bit 3 of port 5). */
#define NB85E_UART_SET_RTS(chan, val) \
#define V850E_UART_SET_RTS(chan, val) \
do { \
if (chan == 1) { \
unsigned old = AS85EP1_PORT_IO(5); \
......@@ -139,16 +137,16 @@ extern void as85ep1_uart_pre_configure (unsigned chan,
/* Timer C details. */
#define NB85E_TIMER_C_BASE_ADDR 0xFFFFF600
#define V850E_TIMER_C_BASE_ADDR 0xFFFFF600
/* Timer D details (the AS85EP1 actually has 5 of these; should change later). */
#define NB85E_TIMER_D_BASE_ADDR 0xFFFFF540
#define NB85E_TIMER_D_TMD_BASE_ADDR (NB85E_TIMER_D_BASE_ADDR + 0x0)
#define NB85E_TIMER_D_CMD_BASE_ADDR (NB85E_TIMER_D_BASE_ADDR + 0x2)
#define NB85E_TIMER_D_TMCD_BASE_ADDR (NB85E_TIMER_D_BASE_ADDR + 0x4)
#define V850E_TIMER_D_BASE_ADDR 0xFFFFF540
#define V850E_TIMER_D_TMD_BASE_ADDR (V850E_TIMER_D_BASE_ADDR + 0x0)
#define V850E_TIMER_D_CMD_BASE_ADDR (V850E_TIMER_D_BASE_ADDR + 0x2)
#define V850E_TIMER_D_TMCD_BASE_ADDR (V850E_TIMER_D_BASE_ADDR + 0x4)
#define NB85E_TIMER_D_BASE_FREQ SYS_CLOCK_FREQ
#define NB85E_TIMER_D_TMCD_CS_MIN 2 /* min 2^2 divider */
#define V850E_TIMER_D_BASE_FREQ SYS_CLOCK_FREQ
#define V850E_TIMER_D_TMCD_CS_MIN 2 /* min 2^2 divider */
/* For <asm/param.h> */
......
include/asm-v850/asm.h
View file @ 051063b5
/*
* include/asm-v850/asm.h -- Macros for writing assembly code
*
* Copyright (C) 2001,02,03 NEC Corporation
* Copyright (C) 2001,02,03 NEC Electronics Corporation
* Copyright (C) 2001,02,03 Miles Bader <miles@gnu.org>
*
* This file is subject to the terms and conditions of the GNU General
......
include/asm-v850/cacheflush.h
View file @ 051063b5
/*
* include/asm-v850/cacheflush.h
*
* Copyright (C) 2001,02 NEC Corporation
* Copyright (C) 2001,02 Miles Bader <miles@gnu.org>
* Copyright (C) 2001,02,03 NEC Electronics Corporation
* Copyright (C) 2001,02,03 Miles Bader <miles@gnu.org>
*
* This file is subject to the terms and conditions of the GNU General
* Public License. See the file COPYING in the main directory of this
......@@ -21,21 +21,40 @@
#include <asm/machdep.h>
#ifndef flush_cache_all
/* If there's no flush_cache_all macro defined by <asm/machdep.h>, then
this processor has no cache, so just define these as nops. */
/* The following are all used by the kernel in ways that only affect
systems with MMUs, so we don't need them. */
#define flush_cache_all() ((void)0)
#define flush_cache_mm(mm) ((void)0)
#define flush_cache_range(vma, start, end) ((void)0)
#define flush_cache_page(vma, vmaddr) ((void)0)
#define flush_dcache_page(page) ((void)0)
#ifdef CONFIG_NO_CACHE
/* Some systems have no cache at all, in which case we don't need these
either. */
#define flush_icache() ((void)0)
#define flush_icache_range(start, end) ((void)0)
#define flush_icache_page(vma,pg) ((void)0)
#define flush_icache_user_range(vma,pg,adr,len) ((void)0)
#define flush_cache_sigtramp(vaddr) ((void)0)
#endif /* !flush_cache_all */
#else /* !CONFIG_NO_CACHE */
struct page;
struct mm_struct;
struct vm_area_struct;
/* Otherwise, somebody had better define them. */
extern void flush_icache (void);
extern void flush_icache_range (unsigned long start, unsigned long end);
extern void flush_icache_page (struct vm_area_struct *vma, struct page *page);
extern void flush_icache_user_range (struct vm_area_struct *vma,
struct page *page,
unsigned long adr, int len);
extern void flush_cache_sigtramp (unsigned long addr);
#endif /* CONFIG_NO_CACHE */
#endif /* __V850_CACHEFLUSH_H__ */
include/asm-v850/entry.h
View file @ 051063b5
......@@ -65,10 +65,10 @@
#define RESET_GUARD_ACTIVE 0xFAB4BEEF
#endif /* CONFIG_RESET_GUARD */
#ifdef CONFIG_V850E_MA1_HIGHRES_TIMER
#ifdef CONFIG_V850E_HIGHRES_TIMER
#define HIGHRES_TIMER_SLOW_TICKS_ADDR (KERNEL_VAR_SPACE_ADDR + 32)
#define HIGHRES_TIMER_SLOW_TICKS KERNEL_VAR (HIGHRES_TIMER_SLOW_TICKS_ADDR)
#endif /* CONFIG_V850E_MA1_HIGHRES_TIMER */
#endif /* CONFIG_V850E_HIGHRES_TIMER */
#ifndef __ASSEMBLY__
......
include/asm-v850/fpga85e2c.h
View file @ 051063b5
......@@ -2,8 +2,8 @@
* include/asm-v850/fpga85e2c.h -- Machine-dependent defs for
* FPGA implementation of V850E2/NA85E2C
*
* Copyright (C) 2002 NEC Corporation
* Copyright (C) 2002 Miles Bader <miles@gnu.org>
* Copyright (C) 2002,03 NEC Electronics Corporation
* Copyright (C) 2002,03 Miles Bader <miles@gnu.org>
*
* This file is subject to the terms and conditions of the GNU General
* Public License. See the file COPYING in the main directory of this
......@@ -15,11 +15,10 @@
#ifndef __V850_FPGA85E2C_H__
#define __V850_FPGA85E2C_H__
#include <asm/v850e2.h>
#include <asm/clinkage.h>
#define CPU_ARCH "v850e2"
#define CPU_MODEL "v850e2/fpga85e2c"
#define CPU_MODEL_LONG "NEC V850E2/NA85E2C"
#define PLATFORM "fpga85e2c"
......@@ -42,27 +41,6 @@
#define CSDEV_ADDR(n) (0xFFE80110 + 2*(n))
#define CSDEV(n) (*(volatile unsigned char *)CSDEV_ADDR (n))
/* The BSC register controls bus-sizing. Each memory area CSn uses a pair
of bits N*2 and N*2+1, where 00 means an 8-bit bus size, 01 16-bit, and
10 32-bit. */
#define BSC_ADDR 0xFFFFF066
#define BSC (*(volatile unsigned short *)BSC_ADDR)
#define DWC_ADDR(n) (0xFFFFF484 + 2*(n))
#define DWC(n) (*(volatile unsigned short *)DWC_ADDR (n))
#define ASC_ADDR 0xFFFFF48A
#define ASC (*(volatile unsigned short *)ASC_ADDR)
#define BTSC_ADDR 0xFFFFF070
#define BTSC (*(volatile unsigned short *)BTSC_ADDR)
#define BHC_ADDR 0xFFFFF06A
#define BHC (*(volatile unsigned short *)BHC_ADDR)
/* NB85E-style interrupt system. */
#include <asm/nb85e_intc.h>
/* Timer interrupts 0-3, interrupt at intervals from CLK/4096 to CLK/16384. */
#define IRQ_RPU(n) (60 + (n))
......
include/asm-v850/highres_timer.h
View file @ 051063b5
/*
* include/asm-v850/highres_timer.h -- High resolution timing routines
*
* Copyright (C) 2001 NEC Corporation
* Copyright (C) 2001 Miles Bader <miles@gnu.org>
* Copyright (C) 2001,03 NEC Electronics Corporation
* Copyright (C) 2001,03 Miles Bader <miles@gnu.org>
*
* This file is subject to the terms and conditions of the GNU General
* Public License. See the file COPYING in the main directory of this
......@@ -25,7 +25,7 @@
counter overflows). */
#define HIGHRES_TIMER_SLOW_TICK_RATE 25
/* Which timer in the nb85e `Timer D' we use. */
/* Which timer in the V850E `Timer D' we use. */
#define HIGHRES_TIMER_TIMER_D_UNIT 3
......
include/asm-v850/ma.h
View file @ 051063b5
/*
* include/asm-v850/ma.h -- V850E/MA series of cpu chips
*
* Copyright (C) 2001,02 NEC Corporation
* Copyright (C) 2001,02 Miles Bader <miles@gnu.org>
* Copyright (C) 2001,02,03 NEC Electronics Corporation
* Copyright (C) 2001,02,03 Miles Bader <miles@gnu.org>
*
* This file is subject to the terms and conditions of the GNU General
* Public License. See the file COPYING in the main directory of this
......@@ -14,9 +14,8 @@
#ifndef __V850_MA_H__
#define __V850_MA_H__
/* The MA series uses the NB85E cpu core. */
#include <asm/nb85e.h>
/* The MA series uses the V850E cpu core. */
#include <asm/v850e.h>
/* For <asm/entry.h> */
......@@ -28,10 +27,10 @@
/* MA series UART details. */
#define NB85E_UART_BASE_FREQ CPU_CLOCK_FREQ
#define V850E_UART_BASE_FREQ CPU_CLOCK_FREQ
/* This is a function that gets called before configuring the UART. */
#define NB85E_UART_PRE_CONFIGURE ma_uart_pre_configure
#define V850E_UART_PRE_CONFIGURE ma_uart_pre_configure
#ifndef __ASSEMBLY__
extern void ma_uart_pre_configure (unsigned chan,
unsigned cflags, unsigned baud);
......@@ -39,16 +38,16 @@ extern void ma_uart_pre_configure (unsigned chan,
/* MA series timer C details. */
#define NB85E_TIMER_C_BASE_ADDR 0xFFFFF600
#define V850E_TIMER_C_BASE_ADDR 0xFFFFF600
/* MA series timer D details. */
#define NB85E_TIMER_D_BASE_ADDR 0xFFFFF540
#define NB85E_TIMER_D_TMD_BASE_ADDR (NB85E_TIMER_D_BASE_ADDR + 0x0)
#define NB85E_TIMER_D_CMD_BASE_ADDR (NB85E_TIMER_D_BASE_ADDR + 0x2)
#define NB85E_TIMER_D_TMCD_BASE_ADDR (NB85E_TIMER_D_BASE_ADDR + 0x4)
#define V850E_TIMER_D_BASE_ADDR 0xFFFFF540
#define V850E_TIMER_D_TMD_BASE_ADDR (V850E_TIMER_D_BASE_ADDR + 0x0)
#define V850E_TIMER_D_CMD_BASE_ADDR (V850E_TIMER_D_BASE_ADDR + 0x2)
#define V850E_TIMER_D_TMCD_BASE_ADDR (V850E_TIMER_D_BASE_ADDR + 0x4)
#define NB85E_TIMER_D_BASE_FREQ CPU_CLOCK_FREQ
#define V850E_TIMER_D_BASE_FREQ CPU_CLOCK_FREQ
/* Port 0 */
......
include/asm-v850/ma1.h
View file @ 051063b5
/*
* include/asm-v850/ma1.h -- V850E/MA1 cpu chip
*
* Copyright (C) 2001,02 NEC Corporation
* Copyright (C) 2001,02 Miles Bader <miles@gnu.org>
* Copyright (C) 2001,02,03 NEC Electronics Corporation
* Copyright (C) 2001,02,03 Miles Bader <miles@gnu.org>
*
* This file is subject to the terms and conditions of the GNU General
* Public License. See the file COPYING in the main directory of this
......@@ -40,12 +40,11 @@
#define IRQ_INTST(n) (0x27 + (n)*4) /* UART 0-2 transmission completion */
#define IRQ_INTST_NUM 3
/* For <asm/irq.h> */
#define NUM_CPU_IRQS 0x30
/* The MA1 has a UART with 3 channels. */
#define NB85E_UART_NUM_CHANNELS 3
#define V850E_UART_NUM_CHANNELS 3
#endif /* __V850_MA1_H__ */
include/asm-v850/machdep.h
View file @ 051063b5
/*
* include/asm-v850/machdep.h -- Machine-dependent definitions
*
* Copyright (C) 2001,02 NEC Corporation
* Copyright (C) 2001,02 Miles Bader <miles@gnu.org>
* Copyright (C) 2001,02,03 NEC Electronics Corporation
* Copyright (C) 2001,02,03 Miles Bader <miles@gnu.org>
*
* This file is subject to the terms and conditions of the GNU General
* Public License. See the file COPYING in the main directory of this
......@@ -20,6 +20,9 @@
#ifdef CONFIG_V850E_MA1
#include <asm/ma1.h>
#endif
#ifdef CONFIG_V850E_ME2
#include <asm/me2.h>
#endif
#ifdef CONFIG_V850E_TEG
#include <asm/teg.h>
#endif
......@@ -36,6 +39,9 @@
#ifdef CONFIG_RTE_CB_MA1
#include <asm/rte_ma1_cb.h>
#endif
#ifdef CONFIG_RTE_CB_ME2
#include <asm/rte_me2_cb.h>
#endif
#ifdef CONFIG_RTE_CB_NB85E
#include <asm/rte_nb85e_cb.h>
#endif
......@@ -45,6 +51,9 @@
#ifdef CONFIG_V850E2_SIM85E2C
#include <asm/sim85e2c.h>
#endif
#ifdef CONFIG_V850E2_SIM85E2S
#include <asm/sim85e2s.h>
#endif
#ifdef CONFIG_V850E2_FPGA85E2C
#include <asm/fpga85e2c.h>
#endif
......
include/asm-v850/me2.h 0 → 100644
View file @ 051063b5
/*
* include/asm-v850/me2.h -- V850E/ME2 cpu chip
*
* Copyright (C) 2001,02,03 NEC Electronics Corporation
* Copyright (C) 2001,02,03 Miles Bader <miles@gnu.org>
*
* This file is subject to the terms and conditions of the GNU General
* Public License. See the file COPYING in the main directory of this
* archive for more details.
*
* Written by Miles Bader <miles@gnu.org>
*/
#ifndef __V850_ME2_H__
#define __V850_ME2_H__
#include <asm/v850e.h>
#include <asm/v850e_cache.h>
#define CPU_MODEL "v850e/me2"
#define CPU_MODEL_LONG "NEC V850E/ME2"
/* Hardware-specific interrupt numbers (in the kernel IRQ namespace). */
#define IRQ_INTP(n) (n) /* Pnnn (pin) interrupts */
#define IRQ_INTP_NUM 31
#define IRQ_INTCMD(n) (0x31 + (n)) /* interval timer interrupts 0-3 */
#define IRQ_INTCMD_NUM 4
#define IRQ_INTDMA(n) (0x41 + (n)) /* DMA interrupts 0-3 */
#define IRQ_INTDMA_NUM 4
#define IRQ_INTUBTIRE(n) (0x49 + (n)*5)/* UARTB 0-1 reception error */
#define IRQ_INTUBTIRE_NUM 2
#define IRQ_INTUBTIR(n) (0x4a + (n)*5) /* UARTB 0-1 reception complete */
#define IRQ_INTUBTIR_NUM 2
#define IRQ_INTUBTIT(n) (0x4b + (n)*5) /* UARTB 0-1 transmission complete */
#define IRQ_INTUBTIT_NUM 2
#define IRQ_INTUBTIF(n) (0x4c + (n)*5) /* UARTB 0-1 FIFO trans. complete */
#define IRQ_INTUBTIF_NUM 2
#define IRQ_INTUBTITO(n) (0x4d + (n)*5) /* UARTB 0-1 reception timeout */
#define IRQ_INTUBTITO_NUM 2
/* For <asm/irq.h> */
#define NUM_CPU_IRQS 0x59 /* V850E/ME2 */
/* For <asm/entry.h> */
/* We use on-chip RAM, for a few miscellaneous variables that must be
accessible using a load instruction relative to R0. */
#define R0_RAM_ADDR 0xFFFFB000 /* V850E/ME2 */
/* V850E/ME2 UARTB details.*/
#define V850E_UART_NUM_CHANNELS 2
#define V850E_UARTB_BASE_FREQ (CPU_CLOCK_FREQ / 4)
/* This is a function that gets called before configuring the UART. */
#define V850E_UART_PRE_CONFIGURE me2_uart_pre_configure
#ifndef __ASSEMBLY__
extern void me2_uart_pre_configure (unsigned chan,
unsigned cflags, unsigned baud);
#endif /* __ASSEMBLY__ */
/* V850E/ME2 timer C details. */
#define V850E_TIMER_C_BASE_ADDR 0xFFFFF600
/* V850E/ME2 timer D details. */
#define V850E_TIMER_D_BASE_ADDR 0xFFFFF540
#define V850E_TIMER_D_TMD_BASE_ADDR (V850E_TIMER_D_BASE_ADDR + 0x0)
#define V850E_TIMER_D_CMD_BASE_ADDR (V850E_TIMER_D_BASE_ADDR + 0x2)
#define V850E_TIMER_D_TMCD_BASE_ADDR (V850E_TIMER_D_BASE_ADDR + 0x4)
#define V850E_TIMER_D_BASE_FREQ (CPU_CLOCK_FREQ / 2)
/* Select iRAM mode. */
#define ME2_IRAMM_ADDR 0xFFFFF80A
#define ME2_IRAMM (*(volatile u8*)ME2_IRAMM_ADDR)
/* Interrupt edge-detection configuration. INTF(n) and INTR(n) are only
valid for n == 1, 2, or 5. */
#define ME2_INTF_ADDR(n) (0xFFFFFC00 + (n) * 0x2)
#define ME2_INTF(n) (*(volatile u8*)ME2_INTF_ADDR(n))
#define ME2_INTR_ADDR(n) (0xFFFFFC20 + (n) * 0x2)
#define ME2_INTR(n) (*(volatile u8*)ME2_INTR_ADDR(n))
#define ME2_INTFAL_ADDR 0xFFFFFC10
#define ME2_INTFAL (*(volatile u8*)ME2_INTFAL_ADDR)
#define ME2_INTRAL_ADDR 0xFFFFFC30
#define ME2_INTRAL (*(volatile u8*)ME2_INTRAL_ADDR)
#define ME2_INTFDH_ADDR 0xFFFFFC16
#define ME2_INTFDH (*(volatile u16*)ME2_INTFDH_ADDR)
#define ME2_INTRDH_ADDR 0xFFFFFC36
#define ME2_INTRDH (*(volatile u16*)ME2_INTRDH_ADDR)
#define ME2_SESC_ADDR(n) (0xFFFFF609 + (n) * 0x10)
#define ME2_SESC(n) (*(volatile u8*)ME2_SESC_ADDR(n))
#define ME2_SESA10_ADDR 0xFFFFF5AD
#define ME2_SESA10 (*(volatile u8*)ME2_SESA10_ADDR)
#define ME2_SESA11_ADDR 0xFFFFF5DD
#define ME2_SESA11 (*(volatile u8*)ME2_SESA11_ADDR)
/* Port 1 */
/* Direct I/O. Bits 0-3 are pins P10-P13. */
#define ME2_PORT1_IO_ADDR 0xFFFFF402
#define ME2_PORT1_IO (*(volatile u8 *)ME2_PORT1_IO_ADDR)
/* Port mode (for direct I/O, 0 = output, 1 = input). */
#define ME2_PORT1_PM_ADDR 0xFFFFF422
#define ME2_PORT1_PM (*(volatile u8 *)ME2_PORT1_PM_ADDR)
/* Port mode control (0 = direct I/O mode, 1 = alternative I/O mode). */
#define ME2_PORT1_PMC_ADDR 0xFFFFF442
#define ME2_PORT1_PMC (*(volatile u8 *)ME2_PORT1_PMC_ADDR)
/* Port function control (for serial interfaces, 0 = CSI30, 1 = UARTB0 ). */
#define ME2_PORT1_PFC_ADDR 0xFFFFF462
#define ME2_PORT1_PFC (*(volatile u8 *)ME2_PORT1_PFC_ADDR)
/* Port 2 */
/* Direct I/O. Bits 0-3 are pins P20-P25. */
#define ME2_PORT2_IO_ADDR 0xFFFFF404
#define ME2_PORT2_IO (*(volatile u8 *)ME2_PORT2_IO_ADDR)
/* Port mode (for direct I/O, 0 = output, 1 = input). */
#define ME2_PORT2_PM_ADDR 0xFFFFF424
#define ME2_PORT2_PM (*(volatile u8 *)ME2_PORT2_PM_ADDR)
/* Port mode control (0 = direct I/O mode, 1 = alternative I/O mode). */
#define ME2_PORT2_PMC_ADDR 0xFFFFF444
#define ME2_PORT2_PMC (*(volatile u8 *)ME2_PORT2_PMC_ADDR)
/* Port function control (for serial interfaces, 0 = INTP2x, 1 = UARTB1 ). */
#define ME2_PORT2_PFC_ADDR 0xFFFFF464
#define ME2_PORT2_PFC (*(volatile u8 *)ME2_PORT2_PFC_ADDR)
/* Port 5 */
/* Direct I/O. Bits 0-5 are pins P50-P55. */
#define ME2_PORT5_IO_ADDR 0xFFFFF40A
#define ME2_PORT5_IO (*(volatile u8 *)ME2_PORT5_IO_ADDR)
/* Port mode (for direct I/O, 0 = output, 1 = input). */
#define ME2_PORT5_PM_ADDR 0xFFFFF42A
#define ME2_PORT5_PM (*(volatile u8 *)ME2_PORT5_PM_ADDR)
/* Port mode control (0 = direct I/O mode, 1 = alternative I/O mode). */
#define ME2_PORT5_PMC_ADDR 0xFFFFF44A
#define ME2_PORT5_PMC (*(volatile u8 *)ME2_PORT5_PMC_ADDR)
/* Port function control (). */
#define ME2_PORT5_PFC_ADDR 0xFFFFF46A
#define ME2_PORT5_PFC (*(volatile u8 *)ME2_PORT5_PFC_ADDR)
/* Port 6 */
/* Direct I/O. Bits 5-7 are pins P65-P67. */
#define ME2_PORT6_IO_ADDR 0xFFFFF40C
#define ME2_PORT6_IO (*(volatile u8 *)ME2_PORT6_IO_ADDR)
/* Port mode (for direct I/O, 0 = output, 1 = input). */
#define ME2_PORT6_PM_ADDR 0xFFFFF42C
#define ME2_PORT6_PM (*(volatile u8 *)ME2_PORT6_PM_ADDR)
/* Port mode control (0 = direct I/O mode, 1 = alternative I/O mode). */
#define ME2_PORT6_PMC_ADDR 0xFFFFF44C
#define ME2_PORT6_PMC (*(volatile u8 *)ME2_PORT6_PMC_ADDR)
/* Port function control (). */
#define ME2_PORT6_PFC_ADDR 0xFFFFF46C
#define ME2_PORT6_PFC (*(volatile u8 *)ME2_PORT6_PFC_ADDR)
/* Port 7 */
/* Direct I/O. Bits 2-7 are pins P72-P77. */
#define ME2_PORT7_IO_ADDR 0xFFFFF40E
#define ME2_PORT7_IO (*(volatile u8 *)ME2_PORT7_IO_ADDR)
/* Port mode (for direct I/O, 0 = output, 1 = input). */
#define ME2_PORT7_PM_ADDR 0xFFFFF42E
#define ME2_PORT7_PM (*(volatile u8 *)ME2_PORT7_PM_ADDR)
/* Port mode control (0 = direct I/O mode, 1 = alternative I/O mode). */
#define ME2_PORT7_PMC_ADDR 0xFFFFF44E
#define ME2_PORT7_PMC (*(volatile u8 *)ME2_PORT7_PMC_ADDR)
/* Port function control (). */
#define ME2_PORT7_PFC_ADDR 0xFFFFF46E
#define ME2_PORT7_PFC (*(volatile u8 *)ME2_PORT7_PFC_ADDR)
#ifndef __ASSEMBLY__
/* Initialize V850E/ME2 chip interrupts. */
extern void me2_init_irqs (void);
#endif /* !__ASSEMBLY__ */
#endif /* __V850_ME2_H__ */
include/asm-v850/nb85e_cache.h deleted 100644 → 0
View file @ 9430d91b
/*
* include/asm-v850/nb85e_cache_cache.h -- Cache control for NB85E_CACHE212 and
* NB85E_CACHE213 cache memories
*
* Copyright (C) 2001,03 NEC Electronics Corporation
* Copyright (C) 2001,03 Miles Bader <miles@gnu.org>
*
* This file is subject to the terms and conditions of the GNU General
* Public License. See the file COPYING in the main directory of this
* archive for more details.
*
* Written by Miles Bader <miles@gnu.org>
*/
#ifndef __V850_NB85E_CACHE_H__
#define __V850_NB85E_CACHE_H__
#include <asm/types.h>
/* Cache control registers. */
#define NB85E_CACHE_BHC_ADDR 0xFFFFF06A
#define NB85E_CACHE_BHC (*(volatile u16 *)NB85E_CACHE_BHC_ADDR)
#define NB85E_CACHE_ICC_ADDR 0xFFFFF070
#define NB85E_CACHE_ICC (*(volatile u16 *)NB85E_CACHE_ICC_ADDR)
#define NB85E_CACHE_ISI_ADDR 0xFFFFF072
#define NB85E_CACHE_ISI (*(volatile u16 *)NB85E_CACHE_ISI_ADDR)
#define NB85E_CACHE_DCC_ADDR 0xFFFFF078
#define NB85E_CACHE_DCC (*(volatile u16 *)NB85E_CACHE_DCC_ADDR)
/* Size of a cache line in bytes. */
#define NB85E_CACHE_LINE_SIZE 16
/* For <asm/cache.h> */
#define L1_CACHE_BYTES NB85E_CACHE_LINE_SIZE
#if defined(__KERNEL__) && !defined(__ASSEMBLY__)
/* Set caching params via the BHC and DCC registers. */
void nb85e_cache_enable (u16 bhc, u16 dcc);
struct page;
struct mm_struct;
struct vm_area_struct;
extern void nb85e_cache_flush_all (void);
extern void nb85e_cache_flush_mm (struct mm_struct *mm);
extern void nb85e_cache_flush_range (struct mm_struct *mm,
unsigned long start,
unsigned long end);
extern void nb85e_cache_flush_page (struct vm_area_struct *vma,
unsigned long page_addr);
extern void nb85e_cache_flush_dcache_page (struct page *page);
extern void nb85e_cache_flush_icache (void);
extern void nb85e_cache_flush_icache_range (unsigned long start,
unsigned long end);
extern void nb85e_cache_flush_icache_page (struct vm_area_struct *vma,
struct page *page);
extern void nb85e_cache_flush_icache_user_range (struct vm_area_struct *vma,
struct page *page,
unsigned long adr, int len);
extern void nb85e_cache_flush_sigtramp (unsigned long addr);
#define flush_cache_all nb85e_cache_flush_all
#define flush_cache_mm nb85e_cache_flush_mm
#define flush_cache_range nb85e_cache_flush_range
#define flush_cache_page nb85e_cache_flush_page
#define flush_dcache_page nb85e_cache_flush_dcache_page
#define flush_icache nb85e_cache_flush_icache
#define flush_icache_range nb85e_cache_flush_icache_range
#define flush_icache_page nb85e_cache_flush_icache_page
#define flush_icache_user_range nb85e_cache_flush_icache_user_range
#define flush_cache_sigtramp nb85e_cache_flush_sigtramp
#endif /* __KERNEL__ && !__ASSEMBLY__ */
#endif /* __V850_NB85E_CACHE_H__ */
include/asm-v850/nb85e_uart.h deleted 100644 → 0
View file @ 9430d91b
/*
* include/asm-v850/nb85e_uart.h -- On-chip UART often used with the
* NB85E cpu core
*
* Copyright (C) 2001,02 NEC Corporation
* Copyright (C) 2001,02 Miles Bader <miles@gnu.org>
*
* This file is subject to the terms and conditions of the GNU General
* Public License. See the file COPYING in the main directory of this
* archive for more details.
*
* Written by Miles Bader <miles@gnu.org>
*/
/* There's not actually a single UART implementation used by nb85e
derivatives, but rather a series of implementations that are all
`close' to one another. This file attempts to capture some
commonality between them. */
#ifndef __V850_NB85E_UART_H__
#define __V850_NB85E_UART_H__
#include <asm/types.h>
#include <asm/machdep.h> /* Pick up chip-specific defs. */
/* The base address of the UART control registers for channel N.
The default is the address used on the V850E/MA1. */
#ifndef NB85E_UART_BASE_ADDR
#define NB85E_UART_BASE_ADDR(n) (0xFFFFFA00 + 0x10 * (n))
#endif
/* Addresses of specific UART control registers for channel N.
The defaults are the addresses used on the V850E/MA1; if a platform
wants to redefine any of these, it must redefine them all. */
#ifndef NB85E_UART_ASIM_ADDR
#define NB85E_UART_ASIM_ADDR(n) (NB85E_UART_BASE_ADDR(n) + 0x0)
#define NB85E_UART_RXB_ADDR(n) (NB85E_UART_BASE_ADDR(n) + 0x2)
#define NB85E_UART_ASIS_ADDR(n) (NB85E_UART_BASE_ADDR(n) + 0x3)
#define NB85E_UART_TXB_ADDR(n) (NB85E_UART_BASE_ADDR(n) + 0x4)
#define NB85E_UART_ASIF_ADDR(n) (NB85E_UART_BASE_ADDR(n) + 0x5)
#define NB85E_UART_CKSR_ADDR(n) (NB85E_UART_BASE_ADDR(n) + 0x6)
#define NB85E_UART_BRGC_ADDR(n) (NB85E_UART_BASE_ADDR(n) + 0x7)
#endif
#ifndef NB85E_UART_CKSR_MAX_FREQ
#define NB85E_UART_CKSR_MAX_FREQ (25*1000*1000)
#endif
/* UART config registers. */
#define NB85E_UART_ASIM(n) (*(volatile u8 *)NB85E_UART_ASIM_ADDR(n))
/* Control bits for config registers. */
#define NB85E_UART_ASIM_CAE 0x80 /* clock enable */
#define NB85E_UART_ASIM_TXE 0x40 /* transmit enable */
#define NB85E_UART_ASIM_RXE 0x20 /* receive enable */
#define NB85E_UART_ASIM_PS_MASK 0x18 /* mask covering parity-select bits */
#define NB85E_UART_ASIM_PS_NONE 0x00 /* no parity */
#define NB85E_UART_ASIM_PS_ZERO 0x08 /* zero parity */
#define NB85E_UART_ASIM_PS_ODD 0x10 /* odd parity */
#define NB85E_UART_ASIM_PS_EVEN 0x18 /* even parity */
#define NB85E_UART_ASIM_CL_8 0x04 /* char len is 8 bits (otherwise, 7) */
#define NB85E_UART_ASIM_SL_2 0x02 /* 2 stop bits (otherwise, 1) */
#define NB85E_UART_ASIM_ISRM 0x01 /* generate INTSR interrupt on errors
(otherwise, generate INTSER) */
/* UART serial interface status registers. */
#define NB85E_UART_ASIS(n) (*(volatile u8 *)NB85E_UART_ASIS_ADDR(n))
/* Control bits for status registers. */
#define NB85E_UART_ASIS_PE 0x04 /* parity error */
#define NB85E_UART_ASIS_FE 0x02 /* framing error */
#define NB85E_UART_ASIS_OVE 0x01 /* overrun error */
/* UART serial interface transmission status registers. */
#define NB85E_UART_ASIF(n) (*(volatile u8 *)NB85E_UART_ASIF_ADDR(n))
#define NB85E_UART_ASIF_TXBF 0x02 /* transmit buffer flag (data in TXB) */
#define NB85E_UART_ASIF_TXSF 0x01 /* transmit shift flag (sending data) */
/* UART receive buffer register. */
#define NB85E_UART_RXB(n) (*(volatile u8 *)NB85E_UART_RXB_ADDR(n))
/* UART transmit buffer register. */
#define NB85E_UART_TXB(n) (*(volatile u8 *)NB85E_UART_TXB_ADDR(n))
/* UART baud-rate generator control registers. */
#define NB85E_UART_CKSR(n) (*(volatile u8 *)NB85E_UART_CKSR_ADDR(n))
#define NB85E_UART_CKSR_MAX 11
#define NB85E_UART_BRGC(n) (*(volatile u8 *)NB85E_UART_BRGC_ADDR(n))
/* This UART doesn't implement RTS/CTS by default, but some platforms
implement them externally, so check to see if <asm/machdep.h> defined
anything. */
#ifdef NB85E_UART_CTS
#define nb85e_uart_cts(n) NB85E_UART_CTS(n)
#else
#define nb85e_uart_cts(n) (1)
#endif
/* Do the same for RTS. */
#ifdef NB85E_UART_SET_RTS
#define nb85e_uart_set_rts(n,v) NB85E_UART_SET_RTS(n,v)
#else
#define nb85e_uart_set_rts(n,v) ((void)0)
#endif
/* Return true if all characters awaiting transmission on uart channel N
have been transmitted. */
#define nb85e_uart_xmit_done(n) \
(! (NB85E_UART_ASIF(n) & NB85E_UART_ASIF_TXBF))
/* Wait for this to be true. */
#define nb85e_uart_wait_for_xmit_done(n) \
do { } while (! nb85e_uart_xmit_done (n))
/* Return true if uart channel N is ready to transmit a character. */
#define nb85e_uart_xmit_ok(n) \
(nb85e_uart_xmit_done(n) && nb85e_uart_cts(n))
/* Wait for this to be true. */
#define nb85e_uart_wait_for_xmit_ok(n) \
do { } while (! nb85e_uart_xmit_ok (n))
/* Write character CH to uart channel N. */
#define nb85e_uart_putc(n, ch) (NB85E_UART_TXB(n) = (ch))
#define NB85E_UART_MINOR_BASE 64
#ifndef __ASSEMBLY__
/* Setup a console using channel 0 of the builtin uart. */
extern void nb85e_uart_cons_init (unsigned chan);
/* Configure and turn on uart channel CHAN, using the termios `control
modes' bits in CFLAGS, and a baud-rate of BAUD. */
void nb85e_uart_configure (unsigned chan, unsigned cflags, unsigned baud);
/* If the macro NB85E_UART_PRE_CONFIGURE is defined (presumably by a
<asm/machdep.h>), it is called from nb85e_uart_pre_configure before
anything else is done, with interrupts disabled. */
#endif /* !__ASSEMBLY__ */
#endif /* __V850_NB85E_UART_H__ */
include/asm-v850/processor.h
View file @ 051063b5
/*
* include/asm-v850/processor.h
*
* Copyright (C) 2001,02,03 NEC Corporation
* Copyright (C) 2001,02,03 NEC Electronics Corporation
* Copyright (C) 2001,02,03 Miles Bader <miles@gnu.org>
*
* This file is subject to the terms and conditions of the GNU General
......
include/asm-v850/ptrace.h
View file @ 051063b5
/*
* include/asm-v850/ptrace.h -- Access to CPU registers
*
* Copyright (C) 2001,02,03 NEC Corporation
* Copyright (C) 2001,02,03 NEC Electronics Corporation
* Copyright (C) 2001,02,03 Miles Bader <miles@gnu.org>
*
* This file is subject to the terms and conditions of the GNU General
......
include/asm-v850/rte_cb.h
View file @ 051063b5
/*
* include/asm-v850/rte_cb.h -- Midas labs RTE-CB series of evaluation boards
*
* Copyright (C) 2001,02,03 NEC Corporation
* Copyright (C) 2001,02,03 NEC Electronics Corporation
* Copyright (C) 2001,02,03 Miles Bader <miles@gnu.org>
*
* This file is subject to the terms and conditions of the GNU General
......@@ -20,42 +20,54 @@
#define MB_A_SRAM_SIZE 0x00200000 /* 2MB */
#ifdef CONFIG_RTE_GBUS_INT
/* GBUS interrupt support. */
#define GBUS_INT_BASE_IRQ NUM_CPU_IRQS
#define GBUS_INT_BASE_ADDR (GCS2_ADDR + 0x00006000)
#include <asm/gbus_int.h>
/* We define NUM_MACH_IRQS to include extra interrupts from the GBUS. */
#define NUM_MACH_IRQS (NUM_CPU_IRQS + IRQ_GBUS_INT_NUM)
# include <asm/gbus_int.h>
# define GBUS_INT_BASE_IRQ NUM_RTE_CB_IRQS
# define GBUS_INT_BASE_ADDR (GCS2_ADDR + 0x00006000)
/* Some specific interrupts. */
#define IRQ_MB_A_LAN IRQ_GBUS_INT(10)
#define IRQ_MB_A_PCI1(n) (IRQ_GBUS_INT(16) + (n))
#define IRQ_MB_A_PCI1_NUM 4
#define IRQ_MB_A_PCI2(n) (IRQ_GBUS_INT(20) + (n))
#define IRQ_MB_A_PCI2_NUM 4
#define IRQ_MB_A_EXT(n) (IRQ_GBUS_INT(24) + (n))
#define IRQ_MB_A_EXT_NUM 4
#define IRQ_MB_A_USB_OC(n) (IRQ_GBUS_INT(28) + (n))
#define IRQ_MB_A_USB_OC_NUM 2
#define IRQ_MB_A_PCMCIA_OC IRQ_GBUS_INT(30)
# define IRQ_MB_A_LAN IRQ_GBUS_INT(10)
# define IRQ_MB_A_PCI1(n) (IRQ_GBUS_INT(16) + (n))
# define IRQ_MB_A_PCI1_NUM 4
# define IRQ_MB_A_PCI2(n) (IRQ_GBUS_INT(20) + (n))
# define IRQ_MB_A_PCI2_NUM 4
# define IRQ_MB_A_EXT(n) (IRQ_GBUS_INT(24) + (n))
# define IRQ_MB_A_EXT_NUM 4
# define IRQ_MB_A_USB_OC(n) (IRQ_GBUS_INT(28) + (n))
# define IRQ_MB_A_USB_OC_NUM 2
# define IRQ_MB_A_PCMCIA_OC IRQ_GBUS_INT(30)
/* We define NUM_MACH_IRQS to include extra interrupts from the GBUS. */
# define NUM_MACH_IRQS (NUM_RTE_CB_IRQS + IRQ_GBUS_INT_NUM)
#else /* !CONFIG_RTE_GBUS_INT */
# define NUM_MACH_IRQS NUM_RTE_CB_IRQS
#endif /* CONFIG_RTE_GBUS_INT */
#ifdef CONFIG_RTE_MB_A_PCI
/* Mother-A PCI bus support. */
#include <asm/rte_mb_a_pci.h>
# include <asm/rte_mb_a_pci.h>
/* These are the base addresses used for allocating device address
space. 512K of the motherboard SRAM is in the same space, so we have
to be careful not to let it be allocated. */
#define PCIBIOS_MIN_MEM (MB_A_PCI_MEM_ADDR + 0x80000)
#define PCIBIOS_MIN_IO MB_A_PCI_IO_ADDR
# define PCIBIOS_MIN_MEM (MB_A_PCI_MEM_ADDR + 0x80000)
# define PCIBIOS_MIN_IO MB_A_PCI_IO_ADDR
/* As we don't really support PCI DMA to cpu memory, and use bounce-buffers
instead, perversely enough, this becomes always true! */
#define pci_dma_supported(dev, mask) 1
#define pci_dac_dma_supported(dev, mask) 0
#define pcibios_assign_all_busses() 1
# define pci_dma_supported(dev, mask) 1
# define pci_dac_dma_supported(dev, mask) 0
# define pcibios_assign_all_busses() 1
#endif /* CONFIG_RTE_MB_A_PCI */
/* For <asm/param.h> */
......
include/asm-v850/rte_ma1_cb.h
View file @ 051063b5
......@@ -17,25 +17,6 @@
#include <asm/rte_cb.h> /* Common defs for Midas RTE-CB boards. */
/* CPU addresses of GBUS memory spaces. */
#define GCS0_ADDR 0x05000000 /* GCS0 - Common SRAM (2MB) */
#define GCS0_SIZE 0x00200000 /* 2MB */
#define GCS1_ADDR 0x06000000 /* GCS1 - Flash ROM (8MB) */
#define GCS1_SIZE 0x00800000 /* 8MB */
#define GCS2_ADDR 0x07900000 /* GCS2 - I/O registers */
#define GCS2_SIZE 0x00400000 /* 4MB */
#define GCS5_ADDR 0x04000000 /* GCS5 - PCI bus space */
#define GCS5_SIZE 0x01000000 /* 16MB */
#define GCS6_ADDR 0x07980000 /* GCS6 - PCI control registers */
#define GCS6_SIZE 0x00000200 /* 512B */
/* The GBUS GINT0 - GINT4 interrupts are connected to the INTP000 - INTP011
pins on the CPU. These are shared among the GBUS interrupts. */
#define IRQ_GINT(n) IRQ_INTP(n)
#define IRQ_GINT_NUM 4
#define PLATFORM "rte-v850e/ma1-cb"
#define PLATFORM_LONG "Midas lab RTE-V850E/MA1-CB"
......@@ -53,10 +34,32 @@
#define SDRAM_SIZE 0x02000000 /* 32MB */
/* CPU addresses of GBUS memory spaces. */
#define GCS0_ADDR 0x05000000 /* GCS0 - Common SRAM (2MB) */
#define GCS0_SIZE 0x00200000 /* 2MB */
#define GCS1_ADDR 0x06000000 /* GCS1 - Flash ROM (8MB) */
#define GCS1_SIZE 0x00800000 /* 8MB */
#define GCS2_ADDR 0x07900000 /* GCS2 - I/O registers */
#define GCS2_SIZE 0x00400000 /* 4MB */
#define GCS5_ADDR 0x04000000 /* GCS5 - PCI bus space */
#define GCS5_SIZE 0x01000000 /* 16MB */
#define GCS6_ADDR 0x07980000 /* GCS6 - PCI control registers */
#define GCS6_SIZE 0x00000200 /* 512B */
/* For <asm/page.h> */
#define PAGE_OFFSET SRAM_ADDR
/* The GBUS GINT0 - GINT3 interrupts are connected to the INTP000 - INTP011
pins on the CPU. These are shared among the GBUS interrupts. */
#define IRQ_GINT(n) IRQ_INTP(n)
#define IRQ_GINT_NUM 4
/* Used by <asm/rte_cb.h> to derive NUM_MACH_IRQS. */
#define NUM_RTE_CB_IRQS NUM_CPU_IRQS
#ifdef CONFIG_ROM_KERNEL
/* Kernel is in ROM, starting at address 0. */
......@@ -98,8 +101,8 @@
/* Override the basic MA uart pre-initialization so that we can
initialize extra stuff. */
#undef NB85E_UART_PRE_CONFIGURE /* should be defined by <asm/ma.h> */
#define NB85E_UART_PRE_CONFIGURE rte_ma1_cb_uart_pre_configure
#undef V850E_UART_PRE_CONFIGURE /* should be defined by <asm/ma.h> */
#define V850E_UART_PRE_CONFIGURE rte_ma1_cb_uart_pre_configure
#ifndef __ASSEMBLY__
extern void rte_ma1_cb_uart_pre_configure (unsigned chan,
unsigned cflags, unsigned baud);
......@@ -108,9 +111,9 @@ extern void rte_ma1_cb_uart_pre_configure (unsigned chan,
/* This board supports RTS/CTS for the on-chip UART, but only for channel 0. */
/* CTS for UART channel 0 is pin P43 (bit 3 of port 4). */
#define NB85E_UART_CTS(chan) ((chan) == 0 ? !(MA_PORT4_IO & 0x8) : 1)
#define V850E_UART_CTS(chan) ((chan) == 0 ? !(MA_PORT4_IO & 0x8) : 1)
/* RTS for UART channel 0 is pin P42 (bit 2 of port 4). */
#define NB85E_UART_SET_RTS(chan, val) \
#define V850E_UART_SET_RTS(chan, val) \
do { \
if (chan == 0) { \
unsigned old = MA_PORT4_IO; \
......
include/asm-v850/rte_me2_cb.h 0 → 100644
View file @ 051063b5
/*
* include/asm-v850/rte_me2_cb.h -- Midas labs RTE-V850E/ME2-CB board
*
* Copyright (C) 2001,02,03 NEC Corporation
* Copyright (C) 2001,02,03 Miles Bader <miles@gnu.org>
*
* This file is subject to the terms and conditions of the GNU General
* Public License. See the file COPYING in the main directory of this
* archive for more details.
*
* Written by Miles Bader <miles@gnu.org>
*/
#ifndef __V850_RTE_ME2_CB_H__
#define __V850_RTE_ME2_CB_H__
#include <asm/rte_cb.h> /* Common defs for Midas RTE-CB boards. */
#define PLATFORM "rte-v850e/me2-cb"
#define PLATFORM_LONG "Midas lab RTE-V850E/ME2-CB"
#define CPU_CLOCK_FREQ 150000000 /* 150MHz */
#define FIXED_BOGOMIPS 50
/* 32MB of onbard SDRAM. */
#define SDRAM_ADDR 0x00800000
#define SDRAM_SIZE 0x02000000 /* 32MB */
/* CPU addresses of GBUS memory spaces. */
#define GCS0_ADDR 0x04000000 /* GCS0 - Common SRAM (2MB) */
#define GCS0_SIZE 0x00800000 /* 8MB */
#define GCS1_ADDR 0x04800000 /* GCS1 - Flash ROM (8MB) */
#define GCS1_SIZE 0x00800000 /* 8MB */
#define GCS2_ADDR 0x07000000 /* GCS2 - I/O registers */
#define GCS2_SIZE 0x00800000 /* 8MB */
#define GCS5_ADDR 0x08000000 /* GCS5 - PCI bus space */
#define GCS5_SIZE 0x02000000 /* 32MB */
#define GCS6_ADDR 0x07800000 /* GCS6 - PCI control registers */
#define GCS6_SIZE 0x00800000 /* 8MB */
/* For <asm/page.h> */
#define PAGE_OFFSET SDRAM_ADDR
#ifdef CONFIG_ROM_KERNEL
/* Kernel is in ROM, starting at address 0. */
#define INTV_BASE 0
#define ROOT_FS_IMAGE_RW 0
#else /* !CONFIG_ROM_KERNEL */
/* Using RAM-kernel. Assume some sort of boot-loader got us loaded at
address 0. */
#define INTV_BASE 0
#define ROOT_FS_IMAGE_RW 1
#endif /* CONFIG_ROM_KERNEL */
/* Some misc. on-board devices. */
/* Seven-segment LED display (four digits). */
#define LED_ADDR(n) (0x0FE02000 + (n))
#define LED(n) (*(volatile unsigned char *)LED_ADDR(n))
#define LED_NUM_DIGITS 4
/* On-board PIC. */
#define CB_PIC_BASE_ADDR 0x0FE04000
#define CB_PIC_INT0M_ADDR (CB_PIC_BASE_ADDR + 0x00)
#define CB_PIC_INT0M (*(volatile u16 *)CB_PIC_INT0M_ADDR)
#define CB_PIC_INT1M_ADDR (CB_PIC_BASE_ADDR + 0x10)
#define CB_PIC_INT1M (*(volatile u16 *)CB_PIC_INT1M_ADDR)
#define CB_PIC_INTR_ADDR (CB_PIC_BASE_ADDR + 0x20)
#define CB_PIC_INTR (*(volatile u16 *)CB_PIC_INTR_ADDR)
#define CB_PIC_INTEN_ADDR (CB_PIC_BASE_ADDR + 0x30)
#define CB_PIC_INTEN (*(volatile u16 *)CB_PIC_INTEN_ADDR)
#define CB_PIC_INT0EN 0x0001
#define CB_PIC_INT1EN 0x0002
#define CB_PIC_INT0SEL 0x0080
/* The PIC interrupts themselves. */
#define CB_PIC_BASE_IRQ NUM_CPU_IRQS
#define IRQ_CB_PIC_NUM 10
/* Some specific CB_PIC interrupts. */
#define IRQ_CB_EXTTM0 (CB_PIC_BASE_IRQ + 0)
#define IRQ_CB_EXTSIO (CB_PIC_BASE_IRQ + 1)
#define IRQ_CB_TOVER (CB_PIC_BASE_IRQ + 2)
#define IRQ_CB_GINT0 (CB_PIC_BASE_IRQ + 3)
#define IRQ_CB_USB (CB_PIC_BASE_IRQ + 4)
#define IRQ_CB_LANC (CB_PIC_BASE_IRQ + 5)
#define IRQ_CB_USB_VBUS_ON (CB_PIC_BASE_IRQ + 6)
#define IRQ_CB_USB_VBUS_OFF (CB_PIC_BASE_IRQ + 7)
#define IRQ_CB_EXTTM1 (CB_PIC_BASE_IRQ + 8)
#define IRQ_CB_EXTTM2 (CB_PIC_BASE_IRQ + 9)
/* The GBUS GINT1 - GINT3 (note, not GINT0!) interrupts are connected to
the INTP65 - INTP67 pins on the CPU. These are shared among the GBUS
interrupts. */
#define IRQ_GINT(n) IRQ_INTP((n) + 9) /* 0 is unused! */
#define IRQ_GINT_NUM 4 /* 0 is unused! */
/* The shared interrupt line from the PIC is connected to CPU pin INTP23. */
#define IRQ_CB_PIC IRQ_INTP(4) /* P23 */
/* Used by <asm/rte_cb.h> to derive NUM_MACH_IRQS. */
#define NUM_RTE_CB_IRQS (NUM_CPU_IRQS + IRQ_CB_PIC_NUM)
#ifndef __ASSEMBLY__
struct cb_pic_irq_init {
const char *name; /* name of interrupt type */
/* Range of kernel irq numbers for this type:
BASE, BASE+INTERVAL, ..., BASE+INTERVAL*NUM */
unsigned base, num, interval;
unsigned priority; /* interrupt priority to assign */
};
struct hw_interrupt_type; /* fwd decl */
/* Enable interrupt handling for interrupt IRQ. */
extern void cb_pic_enable_irq (unsigned irq);
/* Disable interrupt handling for interrupt IRQ. Note that any interrupts
received while disabled will be delivered once the interrupt is enabled
again, unless they are explicitly cleared using `cb_pic_clear_pending_irq'. */
extern void cb_pic_disable_irq (unsigned irq);
/* Initialize HW_IRQ_TYPES for PIC irqs described in array INITS (which is
terminated by an entry with the name field == 0). */
extern void cb_pic_init_irq_types (struct cb_pic_irq_init *inits,
struct hw_interrupt_type *hw_irq_types);
/* Initialize PIC interrupts. */
extern void cb_pic_init_irqs (void);
#endif /* __ASSEMBLY__ */
/* TL16C550C on board UART see also asm/serial.h */
#define CB_UART_BASE 0x0FE08000
#define CB_UART_REG_GAP 0x10
#define CB_UART_CLOCK 0x16000000
/* CompactFlash setting see also asm/ide.h, asm/hdreg.h. */
#define CB_CF_BASE 0x0FE0C000
#define CB_CF_CCR_ADDR (CB_CF_BASE+0x200)
#define CB_CF_CCR (*(volatile u8 *)CB_CF_CCR_ADDR)
#define CB_CF_REG0_ADDR (CB_CF_BASE+0x1000)
#define CB_CF_REG0 (*(volatile u16 *)CB_CF_REG0_ADDR)
#define CB_CF_STS0_ADDR (CB_CF_BASE+0x1004)
#define CB_CF_STS0 (*(volatile u16 *)CB_CF_STS0_ADDR)
#define CB_PCATA_BASE (CB_CF_BASE+0x800)
#define CB_IDE_BASE (CB_CF_BASE+0x9F0)
#define CB_IDE_CTRL (CB_CF_BASE+0xBF6)
#define CB_IDE_REG_OFFS 0x1
/* SMSC LAN91C111 setting */
#if defined(CONFIG_SMC91111)
#define CB_LANC_BASE 0x0FE10300
#define CONFIG_SMC16BITONLY
#define ETH0_ADDR CB_LANC_BASE
#define ETH0_IRQ IRQ_CB_LANC
#endif /* CONFIG_SMC16BITONLY */
#undef V850E_UART_PRE_CONFIGURE
#define V850E_UART_PRE_CONFIGURE rte_me2_cb_uart_pre_configure
#ifndef __ASSEMBLY__
extern void rte_me2_cb_uart_pre_configure (unsigned chan,
unsigned cflags, unsigned baud);
#endif /* __ASSEMBLY__ */
/* This board supports RTS/CTS for the on-chip UART, but only for channel 0. */
/* CTS for UART channel 0 is pin P22 (bit 2 of port 2). */
#define V850E_UART_CTS(chan) ((chan) == 0 ? !(ME2_PORT2_IO & 0x4) : 1)
/* RTS for UART channel 0 is pin P21 (bit 1 of port 2). */
#define V850E_UART_SET_RTS(chan, val) \
do { \
if (chan == 0) { \
unsigned old = ME2_PORT2_IO; \
if (val) \
ME2_PORT2_IO = old & ~0x2; \
else \
ME2_PORT2_IO = old | 0x2; \
} \
} while (0)
#ifndef __ASSEMBLY__
extern void rte_me2_cb_init_irqs (void);
#endif /* !__ASSEMBLY__ */
#endif /* __V850_RTE_ME2_CB_H__ */
include/asm-v850/rte_nb85e_cb.h
View file @ 051063b5
......@@ -17,6 +17,21 @@
#include <asm/rte_cb.h> /* Common defs for Midas RTE-CB boards. */
#define PLATFORM "rte-v850e/nb85e-cb"
#define PLATFORM_LONG "Midas lab RTE-V850E/NB85E-CB"
#define CPU_CLOCK_FREQ 50000000 /* 50MHz */
/* 1MB of onboard SRAM. Note that the monitor ROM uses parts of this
for its own purposes, so care must be taken. */
#define SRAM_ADDR 0x03C00000
#define SRAM_SIZE 0x00100000 /* 1MB */
/* 16MB of onbard SDRAM. */
#define SDRAM_ADDR 0x01000000
#define SDRAM_SIZE 0x01000000 /* 16MB */
/* CPU addresses of GBUS memory spaces. */
#define GCS0_ADDR 0x00400000 /* GCS0 - Common SRAM (2MB) */
#define GCS0_SIZE 0x00400000 /* 4MB */
......@@ -39,20 +54,8 @@
#define IRQ_GINT(n) (10 + (n))
#define IRQ_GINT_NUM 3
#define PLATFORM "rte-v850e/nb85e-cb"
#define PLATFORM_LONG "Midas lab RTE-V850E/NB85E-CB"
#define CPU_CLOCK_FREQ 50000000 /* 50MHz */
/* 1MB of onboard SRAM. Note that the monitor ROM uses parts of this
for its own purposes, so care must be taken. */
#define SRAM_ADDR 0x03C00000
#define SRAM_SIZE 0x00100000 /* 1MB */
/* 16MB of onbard SDRAM. */
#define SDRAM_ADDR 0x01000000
#define SDRAM_SIZE 0x01000000 /* 16MB */
/* Used by <asm/rte_cb.h> to derive NUM_MACH_IRQS. */
#define NUM_RTE_CB_IRQS NUM_CPU_IRQS
#ifdef CONFIG_ROM_KERNEL
......@@ -86,8 +89,8 @@
/* Override the basic TEG UART pre-initialization so that we can
initialize extra stuff. */
#undef NB85E_UART_PRE_CONFIGURE /* should be defined by <asm/teg.h> */
#define NB85E_UART_PRE_CONFIGURE rte_nb85e_cb_uart_pre_configure
#undef V850E_UART_PRE_CONFIGURE /* should be defined by <asm/teg.h> */
#define V850E_UART_PRE_CONFIGURE rte_nb85e_cb_uart_pre_configure
#ifndef __ASSEMBLY__
extern void rte_nb85e_cb_uart_pre_configure (unsigned chan,
unsigned cflags, unsigned baud);
......@@ -96,9 +99,9 @@ extern void rte_nb85e_cb_uart_pre_configure (unsigned chan,
/* This board supports RTS/CTS for the on-chip UART. */
/* CTS is pin P00. */
#define NB85E_UART_CTS(chan) (! (TEG_PORT0_IO & 0x1))
#define V850E_UART_CTS(chan) (! (TEG_PORT0_IO & 0x1))
/* RTS is pin P02. */
#define NB85E_UART_SET_RTS(chan, val) \
#define V850E_UART_SET_RTS(chan, val) \
do { \
unsigned old = TEG_PORT0_IO; \
TEG_PORT0_IO = val ? (old & ~0x4) : (old | 0x4); \
......
include/asm-v850/serial.h 0 → 100644
View file @ 051063b5
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 1999 by Ralf Baechle
* Copyright (C) 1999, 2000 Silicon Graphics, Inc.
*/
#include <linux/config.h>
#ifdef CONFIG_RTE_CB_ME2
#include <asm/rte_me2_cb.h>
#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST)
#define irq_cannonicalize(x) (x)
#define BASE_BAUD 250000 /* (16MHz / (16 * 38400)) * 9600 */
#define RS_TABLE_SIZE 1
#define SERIAL_PORT_DFNS \
{ 0, BASE_BAUD, CB_UART_BASE, IRQ_CB_EXTSIO, STD_COM_FLAGS },
/* Redefine UART register offsets. */
#undef UART_RX
#undef UART_TX
#undef UART_DLL
#undef UART_TRG
#undef UART_DLM
#undef UART_IER
#undef UART_FCTR
#undef UART_IIR
#undef UART_FCR
#undef UART_EFR
#undef UART_LCR
#undef UART_MCR
#undef UART_LSR
#undef UART_MSR
#undef UART_SCR
#undef UART_EMSR
#define UART_RX (0 * CB_UART_REG_GAP)
#define UART_TX (0 * CB_UART_REG_GAP)
#define UART_DLL (0 * CB_UART_REG_GAP)
#define UART_TRG (0 * CB_UART_REG_GAP)
#define UART_DLM (1 * CB_UART_REG_GAP)
#define UART_IER (1 * CB_UART_REG_GAP)
#define UART_FCTR (1 * CB_UART_REG_GAP)
#define UART_IIR (2 * CB_UART_REG_GAP)
#define UART_FCR (2 * CB_UART_REG_GAP)
#define UART_EFR (2 * CB_UART_REG_GAP)
#define UART_LCR (3 * CB_UART_REG_GAP)
#define UART_MCR (4 * CB_UART_REG_GAP)
#define UART_LSR (5 * CB_UART_REG_GAP)
#define UART_MSR (6 * CB_UART_REG_GAP)
#define UART_SCR (7 * CB_UART_REG_GAP)
#define UART_EMSR (7 * CB_UART_REG_GAP)
#endif /* CONFIG_RTE_CB_ME2 */
include/asm-v850/sim85e2.h 0 → 100644
View file @ 051063b5
/*
* include/asm-v850/sim85e2.h -- Machine-dependent defs for
* V850E2 RTL simulator
*
* Copyright (C) 2002,03 NEC Electronics Corporation
* Copyright (C) 2002,03 Miles Bader <miles@gnu.org>
*
* This file is subject to the terms and conditions of the GNU General
* Public License. See the file COPYING in the main directory of this
* archive for more details.
*
* Written by Miles Bader <miles@gnu.org>
*/
#ifndef __V850_SIM85E2_H__
#define __V850_SIM85E2_H__
#include <asm/v850e2.h> /* Based on V850E2 core. */
/* Various memory areas supported by the simulator.
These should match the corresponding definitions in the linker script. */
/* `instruction RAM'; instruction fetches are much faster from IRAM than
from DRAM. */
#define IRAM_ADDR 0
#define IRAM_SIZE 0x00100000 /* 1MB */
/* `data RAM', below and contiguous with the I/O space.
Data fetches are much faster from DRAM than from IRAM. */
#define DRAM_ADDR 0xfff00000
#define DRAM_SIZE 0x000ff000 /* 1020KB */
/* `external ram'. Unlike the above RAM areas, this memory is cached,
so both instruction and data fetches should be (mostly) fast --
however, currently only write-through caching is supported, so writes
to ERAM will be slow. */
#define ERAM_ADDR 0x00100000
#define ERAM_SIZE 0x07f00000 /* 127MB (max) */
/* Dynamic RAM; uses memory controller. */
#define SDRAM_ADDR 0x10000000
#if 0
#define SDRAM_SIZE 0x01000000 /* 16MB */
#else
#define SDRAM_SIZE 0x00200000 /* Only use 2MB for testing */
#endif
/* Simulator specific control registers. */
/* NOTHAL controls whether the simulator will stop at a `halt' insn. */
#define SIM85E2_NOTHAL_ADDR 0xffffff22
#define SIM85E2_NOTHAL (*(volatile u8 *)SIM85E2_NOTHAL_ADDR)
/* The simulator will stop N cycles after N is written to SIMFIN. */
#define SIM85E2_SIMFIN_ADDR 0xffffff24
#define SIM85E2_SIMFIN (*(volatile u16 *)SIM85E2_SIMFIN_ADDR)
/* For <asm/irq.h> */
#define NUM_CPU_IRQS 64
/* For <asm/page.h> */
#define PAGE_OFFSET SDRAM_ADDR
/* For <asm/entry.h> */
/* `R0 RAM', used for a few miscellaneous variables that must be accessible
using a load instruction relative to R0. The sim85e2 simulator
actually puts 1020K of RAM from FFF00000 to FFFFF000, so we arbitarily
choose a small portion at the end of that. */
#define R0_RAM_ADDR 0xFFFFE000
/* For <asm/param.h> */
#ifndef HZ
#define HZ 24 /* Minimum supported frequency. */
#endif
#endif /* __V850_SIM85E2_H__ */
include/asm-v850/sim85e2c.h
View file @ 051063b5
......@@ -15,78 +15,12 @@
#ifndef __V850_SIM85E2C_H__
#define __V850_SIM85E2C_H__
/* Use generic sim85e2 settings, other than the various names. */
#include <asm/sim85e2.h>
#define CPU_ARCH "v850e2"
#define CPU_MODEL "v850e2"
#define CPU_MODEL_LONG "NEC V850E2"
#define PLATFORM "sim85e2c"
#define PLATFORM_LONG "SIM85E2C V850E2 simulator"
/* Various memory areas supported by the simulator.
These should match the corresponding definitions in the linker script. */
/* `instruction RAM'; instruction fetches are much faster from IRAM than
from DRAM. */
#define IRAM_ADDR 0
#define IRAM_SIZE 0x00100000 /* 1MB */
/* `data RAM', below and contiguous with the I/O space.
Data fetches are much faster from DRAM than from IRAM. */
#define DRAM_ADDR 0xfff00000
#define DRAM_SIZE 0x000ff000 /* 1020KB */
/* `external ram'. Unlike the above RAM areas, this memory is cached,
so both instruction and data fetches should be (mostly) fast --
however, currently only write-through caching is supported, so writes
to ERAM will be slow. */
#define ERAM_ADDR 0x00100000
#define ERAM_SIZE 0x07f00000 /* 127MB (max) */
/* CPU core control registers; these should be expanded and moved into
separate header files when we support some other processors based on
the same E2 core. */
/* Bus Transaction Control Register */
#define NA85E2C_CACHE_BTSC_ADDR 0xfffff070
#define NA85E2C_CACHE_BTSC (*(volatile unsigned short *)NA85E2C_CACHE_BTSC_ADDR)
#define NA85E2C_CACHE_BTSC_ICM 0x1 /* icache enable */
#define NA85E2C_CACHE_BTSC_DCM0 0x4 /* dcache enable, bit 0 */
#define NA85E2C_CACHE_BTSC_DCM1 0x8 /* dcache enable, bit 1 */
/* Cache Configuration Register */
#define NA85E2C_BUSM_BHC_ADDR 0xfffff06a
#define NA85E2C_BUSM_BHC (*(volatile unsigned short *)NA85E2C_BUSM_BHC_ADDR)
/* Simulator specific control registers. */
/* NOTHAL controls whether the simulator will stop at a `halt' insn. */
#define NOTHAL_ADDR 0xffffff22
#define NOTHAL (*(volatile unsigned char *)NOTHAL_ADDR)
/* The simulator will stop N cycles after N is written to SIMFIN. */
#define SIMFIN_ADDR 0xffffff24
#define SIMFIN (*(volatile unsigned short *)SIMFIN_ADDR)
/* The simulator has an nb85e-style interrupt system. */
#include <asm/nb85e_intc.h>
/* For <asm/irq.h> */
#define NUM_CPU_IRQS 64
/* For <asm/page.h> */
#define PAGE_OFFSET DRAM_ADDR
/* For <asm/entry.h> */
/* `R0 RAM', used for a few miscellaneous variables that must be accessible
using a load instruction relative to R0. The sim85e2c simulator
actually puts 1020K of RAM from FFF00000 to FFFFF000, so we arbitarily
choose a small portion at the end of that. */
#define R0_RAM_ADDR 0xFFFFE000
/* For <asm/param.h> */
#ifndef HZ
#define HZ 24 /* Minimum supported frequency. */
#endif
#endif /* __V850_SIM85E2C_H__ */
include/asm-v850/sim85e2s.h 0 → 100644
View file @ 051063b5
/*
* include/asm-v850/sim85e2s.h -- Machine-dependent defs for
* V850E2 RTL simulator
*
* Copyright (C) 2003 NEC Electronics Corporation
* Copyright (C) 2003 Miles Bader <miles@gnu.org>
*
* This file is subject to the terms and conditions of the GNU General
* Public License. See the file COPYING in the main directory of this
* archive for more details.
*
* Written by Miles Bader <miles@gnu.org>
*/
#ifndef __V850_SIM85E2S_H__
#define __V850_SIM85E2S_H__
#include <asm/sim85e2.h> /* Use generic sim85e2 settings. */
#if 0
#include <asm/v850e2_cache.h> /* + cache */
#endif
#define CPU_MODEL "v850e2"
#define CPU_MODEL_LONG "NEC V850E2"
#define PLATFORM "sim85e2s"
#define PLATFORM_LONG "SIM85E2S V850E2 simulator"
#endif /* __V850_SIM85E2S_H__ */
include/asm-v850/stat.h
View file @ 051063b5
/*
* include/asm-v850/stat.h -- v850 stat structure
*
* Copyright (C) 2001,02,03 NEC Corporation
* Copyright (C) 2001,02,03 NEC Electronics Corporation
* Copyright (C) 2001,02,03 Miles Bader <miles@gnu.org>
*
* This file is subject to the terms and conditions of the GNU General
......
include/asm-v850/system.h
View file @ 051063b5
/*
* include/asm-v850/system.h -- Low-level interrupt/thread ops
*
* Copyright (C) 2001,02,03 NEC Corporation
* Copyright (C) 2001,02,03 NEC Electronics Corporation
* Copyright (C) 2001,02,03 Miles Bader <miles@gnu.org>
*
* This file is subject to the terms and conditions of the GNU General
......
include/asm-v850/teg.h
View file @ 051063b5
......@@ -15,9 +15,9 @@
#define __V850_TEG_H__
/* The TEG uses the NB85E cpu core. */
#include <asm/nb85e.h>
#include <asm/nb85e_cache.h>
/* The TEG uses the V850E cpu core. */
#include <asm/v850e.h>
#include <asm/v850e_cache.h>
#define CPU_MODEL "v850e/nb85e-teg"
......@@ -51,18 +51,18 @@
/* TEG UART details. */
#define NB85E_UART_BASE_ADDR(n) (0xFFFFF600 + 0x10 * (n))
#define NB85E_UART_ASIM_ADDR(n) (NB85E_UART_BASE_ADDR(n) + 0x0)
#define NB85E_UART_ASIS_ADDR(n) (NB85E_UART_BASE_ADDR(n) + 0x2)
#define NB85E_UART_ASIF_ADDR(n) (NB85E_UART_BASE_ADDR(n) + 0x4)
#define NB85E_UART_CKSR_ADDR(n) (NB85E_UART_BASE_ADDR(n) + 0x6)
#define NB85E_UART_BRGC_ADDR(n) (NB85E_UART_BASE_ADDR(n) + 0x8)
#define NB85E_UART_TXB_ADDR(n) (NB85E_UART_BASE_ADDR(n) + 0xA)
#define NB85E_UART_RXB_ADDR(n) (NB85E_UART_BASE_ADDR(n) + 0xC)
#define NB85E_UART_NUM_CHANNELS 1
#define NB85E_UART_BASE_FREQ CPU_CLOCK_FREQ
#define V850E_UART_BASE_ADDR(n) (0xFFFFF600 + 0x10 * (n))
#define V850E_UART_ASIM_ADDR(n) (V850E_UART_BASE_ADDR(n) + 0x0)
#define V850E_UART_ASIS_ADDR(n) (V850E_UART_BASE_ADDR(n) + 0x2)
#define V850E_UART_ASIF_ADDR(n) (V850E_UART_BASE_ADDR(n) + 0x4)
#define V850E_UART_CKSR_ADDR(n) (V850E_UART_BASE_ADDR(n) + 0x6)
#define V850E_UART_BRGC_ADDR(n) (V850E_UART_BASE_ADDR(n) + 0x8)
#define V850E_UART_TXB_ADDR(n) (V850E_UART_BASE_ADDR(n) + 0xA)
#define V850E_UART_RXB_ADDR(n) (V850E_UART_BASE_ADDR(n) + 0xC)
#define V850E_UART_NUM_CHANNELS 1
#define V850E_UART_BASE_FREQ CPU_CLOCK_FREQ
/* This is a function that gets called before configuring the UART. */
#define NB85E_UART_PRE_CONFIGURE teg_uart_pre_configure
#define V850E_UART_PRE_CONFIGURE teg_uart_pre_configure
#ifndef __ASSEMBLY__
extern void teg_uart_pre_configure (unsigned chan,
unsigned cflags, unsigned baud);
......@@ -70,15 +70,15 @@ extern void teg_uart_pre_configure (unsigned chan,
/* The TEG RTPU. */
#define NB85E_RTPU_BASE_ADDR 0xFFFFF210
#define V850E_RTPU_BASE_ADDR 0xFFFFF210
/* TEG series timer D details. */
#define NB85E_TIMER_D_BASE_ADDR 0xFFFFF210
#define NB85E_TIMER_D_TMCD_BASE_ADDR (NB85E_TIMER_D_BASE_ADDR + 0x0)
#define NB85E_TIMER_D_TMD_BASE_ADDR (NB85E_TIMER_D_BASE_ADDR + 0x4)
#define NB85E_TIMER_D_CMD_BASE_ADDR (NB85E_TIMER_D_BASE_ADDR + 0x8)
#define NB85E_TIMER_D_BASE_FREQ CPU_CLOCK_FREQ
#define V850E_TIMER_D_BASE_ADDR 0xFFFFF210
#define V850E_TIMER_D_TMCD_BASE_ADDR (V850E_TIMER_D_BASE_ADDR + 0x0)
#define V850E_TIMER_D_TMD_BASE_ADDR (V850E_TIMER_D_BASE_ADDR + 0x4)
#define V850E_TIMER_D_CMD_BASE_ADDR (V850E_TIMER_D_BASE_ADDR + 0x8)
#define V850E_TIMER_D_BASE_FREQ CPU_CLOCK_FREQ
/* `Interrupt Source Select' control register. */
......
include/asm-v850/nb85e.h → include/asm-v850/v850e.h
View file @ 051063b5
/*
* include/asm-v850/nb85e.h -- NB85E cpu core
* include/asm-v850/v850e.h -- V850E CPU
*
* Copyright (C) 2001,02 NEC Corporation
* Copyright (C) 2001,02 Miles Bader <miles@gnu.org>
* Copyright (C) 2001,02,03 NEC Electronics Corporation
* Copyright (C) 2001,02,03 Miles Bader <miles@gnu.org>
*
* This file is subject to the terms and conditions of the GNU General
* Public License. See the file COPYING in the main directory of this
......@@ -11,11 +11,11 @@
* Written by Miles Bader <miles@gnu.org>
*/
#ifndef __V850_NB85E_H__
#define __V850_NB85E_H__
#ifndef __V850_V850E_H__
#define __V850_V850E_H__
#include <asm/nb85e_intc.h>
#include <asm/v850e_intc.h>
#define CPU_ARCH "v850e"
#endif /* __V850_NB85E_H__ */
#endif /* __V850_V850E_H__ */
include/asm-v850/v850e2.h 0 → 100644
View file @ 051063b5
/*
* include/asm-v850/v850e2.h -- Machine-dependent defs for V850E2 CPUs
*
* Copyright (C) 2002,03 NEC Electronics Corporation
* Copyright (C) 2002,03 Miles Bader <miles@gnu.org>
*
* This file is subject to the terms and conditions of the GNU General
* Public License. See the file COPYING in the main directory of this
* archive for more details.
*
* Written by Miles Bader <miles@gnu.org>
*/
#ifndef __V850_V850E2_H__
#define __V850_V850E2_H__
#include <asm/v850e_intc.h> /* v850e-style interrupt system. */
#define CPU_ARCH "v850e2"
/* Control registers. */
/* Chip area select control */
#define V850E2_CSC_ADDR(n) (0xFFFFF060 + (n) * 2)
#define V850E2_CSC(n) (*(volatile u16 *)V850E2_CSC_ADDR(n))
/* I/O area select control */
#define V850E2_BPC_ADDR 0xFFFFF064
#define V850E2_BPC (*(volatile u16 *)V850E2_BPC_ADDR)
/* Bus size configuration */
#define V850E2_BSC_ADDR 0xFFFFF066
#define V850E2_BSC (*(volatile u16 *)V850E2_BSC_ADDR)
/* Endian configuration */
#define V850E2_BEC_ADDR 0xFFFFF068
#define V850E2_BEC (*(volatile u16 *)V850E2_BEC_ADDR)
/* Cache configuration */
#define V850E2_BHC_ADDR 0xFFFFF06A
#define V850E2_BHC (*(volatile u16 *)V850E2_BHC_ADDR)
/* NPB strobe-wait configuration */
#define V850E2_VSWC_ADDR 0xFFFFF06E
#define V850E2_VSWC (*(volatile u16 *)V850E2_VSWC_ADDR)
/* Bus cycle type */
#define V850E2_BCT_ADDR(n) (0xFFFFF480 + (n) * 2)
#define V850E2_BCT(n) (*(volatile u16 *)V850E2_BCT_ADDR(n))
/* Data wait control */
#define V850E2_DWC_ADDR(n) (0xFFFFF484 + (n) * 2)
#define V850E2_DWC(n) (*(volatile u16 *)V850E2_DWC_ADDR(n))
/* Bus cycle control */
#define V850E2_BCC_ADDR 0xFFFFF488
#define V850E2_BCC (*(volatile u16 *)V850E2_BCC_ADDR)
/* Address wait control */
#define V850E2_ASC_ADDR 0xFFFFF48A
#define V850E2_ASC (*(volatile u16 *)V850E2_ASC_ADDR)
/* Local bus sizing control */
#define V850E2_LBS_ADDR 0xFFFFF48E
#define V850E2_LBS (*(volatile u16 *)V850E2_LBS_ADDR)
/* Line buffer control */
#define V850E2_LBC_ADDR(n) (0xFFFFF490 + (n) * 2)
#define V850E2_LBC(n) (*(volatile u16 *)V850E2_LBC_ADDR(n))
/* SDRAM configuration */
#define V850E2_SCR_ADDR(n) (0xFFFFF4A0 + (n) * 4)
#define V850E2_SCR(n) (*(volatile u16 *)V850E2_SCR_ADDR(n))
/* SDRAM refresh cycle control */
#define V850E2_RFS_ADDR(n) (0xFFFFF4A2 + (n) * 4)
#define V850E2_RFS(n) (*(volatile u16 *)V850E2_RFS_ADDR(n))
#endif /* __V850_V850E2_H__ */
include/asm-v850/v850e2_cache.h 0 → 100644
View file @ 051063b5
/*
* include/asm-v850/v850e2_cache_cache.h -- Cache control for V850E2
* cache memories
*
* Copyright (C) 2003 NEC Electronics Corporation
* Copyright (C) 2003 Miles Bader <miles@gnu.org>
*
* This file is subject to the terms and conditions of the GNU General
* Public License. See the file COPYING in the main directory of this
* archive for more details.
*
* Written by Miles Bader <miles@gnu.org>
*/
#ifndef __V850_V850E2_CACHE_H__
#define __V850_V850E2_CACHE_H__
#include <asm/types.h>
/* Cache control registers. */
/* Bus Transaction Control */
#define V850E2_CACHE_BTSC_ADDR 0xFFFFF070
#define V850E2_CACHE_BTSC (*(volatile u16 *)V850E2_CACHE_BTSC_ADDR)
#define V850E2_CACHE_BTSC_ICM 0x0001 /* icache enable */
#define V850E2_CACHE_BTSC_DCM0 0x0004 /* dcache enable, bit 0 */
#define V850E2_CACHE_BTSC_DCM1 0x0008 /* dcache enable, bit 1 */
#define V850E2_CACHE_BTSC_DCM_WT /* write-through */ \
V850E2_CACHE_BTSC_DCM0
#ifdef CONFIG_V850E2_V850E2S
# define V850E2_CACHE_BTSC_DCM_WB_NO_ALLOC /* write-back, non-alloc */ \
V850E2_CACHE_BTSC_DCM1
# define V850E2_CACHE_BTSC_DCM_WB_ALLOC /* write-back, non-alloc */ \
(V850E2_CACHE_BTSC_DCM1 | V850E2_CACHE_BTSC_DCM0)
# define V850E2_CACHE_BTSC_ISEQ 0x0010 /* icache `address sequence mode' */
# define V850E2_CACHE_BTSC_DSEQ 0x0020 /* dcache `address sequence mode' */
# define V850E2_CACHE_BTSC_IRFC 0x0030
# define V850E2_CACHE_BTSC_ILCD 0x4000
# define V850E2_CACHE_BTSC_VABE 0x8000
#endif /* CONFIG_V850E2_V850E2S */
/* Cache operation start address register (low-bits). */
#define V850E2_CACHE_CADL_ADDR 0xFFFFF074
#define V850E2_CACHE_CADL (*(volatile u16 *)V850E2_CACHE_CADL_ADDR)
/* Cache operation start address register (high-bits). */
#define V850E2_CACHE_CADH_ADDR 0xFFFFF076
#define V850E2_CACHE_CADH (*(volatile u16 *)V850E2_CACHE_CADH_ADDR)
/* Cache operation count register. */
#define V850E2_CACHE_CCNT_ADDR 0xFFFFF078
#define V850E2_CACHE_CCNT (*(volatile u16 *)V850E2_CACHE_CCNT_ADDR)
/* Cache operation specification register. */
#define V850E2_CACHE_COPR_ADDR 0xFFFFF07A
#define V850E2_CACHE_COPR (*(volatile u16 *)V850E2_CACHE_COPR_ADDR)
#define V850E2_CACHE_COPR_STRT 0x0001 /* start cache operation */
#define V850E2_CACHE_COPR_LBSL 0x0100 /* 0 = icache, 1 = dcache */
#define V850E2_CACHE_COPR_WSLE 0x0200 /* operate on cache way */
#define V850E2_CACHE_COPR_WSL(way) ((way) * 0x0400) /* way select */
#define V850E2_CACHE_COPR_CFC(op) ((op) * 0x1000) /* cache function code */
/* Size of a cache line in bytes. */
#define V850E2_CACHE_LINE_SIZE_BITS 4
#define V850E2_CACHE_LINE_SIZE (1 << V850E2_CACHE_LINE_SIZE_BITS)
/* The size of each cache `way' in lines. */
#define V850E2_CACHE_WAY_SIZE 256
/* For <asm/cache.h> */
#define L1_CACHE_BYTES V850E2_CACHE_LINE_SIZE
#endif /* __V850_V850E2_CACHE_H__ */
include/asm-v850/v850e_cache.h 0 → 100644
View file @ 051063b5
/*
* include/asm-v850/v850e_cache.h -- Cache control for V850E cache memories
*
* Copyright (C) 2001,03 NEC Electronics Corporation
* Copyright (C) 2001,03 Miles Bader <miles@gnu.org>
*
* This file is subject to the terms and conditions of the GNU General
* Public License. See the file COPYING in the main directory of this
* archive for more details.
*
* Written by Miles Bader <miles@gnu.org>
*/
/* This file implements cache control for the rather simple cache used on
some V850E CPUs, specifically the NB85E/TEG CPU-core and the V850E/ME2
CPU. V850E2 processors have their own (better) cache
implementation. */
#ifndef __V850_V850E_CACHE_H__
#define __V850_V850E_CACHE_H__
#include <asm/types.h>
/* Cache control registers. */
#define V850E_CACHE_BHC_ADDR 0xFFFFF06A
#define V850E_CACHE_BHC (*(volatile u16 *)V850E_CACHE_BHC_ADDR)
#define V850E_CACHE_ICC_ADDR 0xFFFFF070
#define V850E_CACHE_ICC (*(volatile u16 *)V850E_CACHE_ICC_ADDR)
#define V850E_CACHE_ISI_ADDR 0xFFFFF072
#define V850E_CACHE_ISI (*(volatile u16 *)V850E_CACHE_ISI_ADDR)
#define V850E_CACHE_DCC_ADDR 0xFFFFF078
#define V850E_CACHE_DCC (*(volatile u16 *)V850E_CACHE_DCC_ADDR)
/* Size of a cache line in bytes. */
#define V850E_CACHE_LINE_SIZE 16
/* For <asm/cache.h> */
#define L1_CACHE_BYTES V850E_CACHE_LINE_SIZE
#if defined(__KERNEL__) && !defined(__ASSEMBLY__)
/* Set caching params via the BHC, ICC, and DCC registers. */
void v850e_cache_enable (u16 bhc, u16 icc, u16 dcc);
#endif /* __KERNEL__ && !__ASSEMBLY__ */
#endif /* __V850_V850E_CACHE_H__ */
include/asm-v850/nb85e_intc.h → include/asm-v850/v850e_intc.h
View file @ 051063b5
/*
* include/asm-v850/nb85e_intc.h -- NB85E cpu core interrupt controller (INTC)
* include/asm-v850/v850e_intc.h -- V850E CPU interrupt controller (INTC)
*
* Copyright (C) 2001,02,03 NEC Electronics Corporation
* Copyright (C) 2001,02,03 Miles Bader <miles@gnu.org>
......@@ -11,106 +11,106 @@
* Written by Miles Bader <miles@gnu.org>
*/
#ifndef __V850_NB85E_INTC_H__
#define __V850_NB85E_INTC_H__
#ifndef __V850_V850E_INTC_H__
#define __V850_V850E_INTC_H__
/* There are 4 16-bit `Interrupt Mask Registers' located contiguously
starting from this base. Each interrupt uses a single bit to
indicated enabled/disabled status. */
#define NB85E_INTC_IMR_BASE_ADDR 0xFFFFF100
#define NB85E_INTC_IMR_ADDR(irq) (NB85E_INTC_IMR_BASE_ADDR + ((irq) >> 3))
#define NB85E_INTC_IMR_BIT(irq) ((irq) & 0x7)
#define V850E_INTC_IMR_BASE_ADDR 0xFFFFF100
#define V850E_INTC_IMR_ADDR(irq) (V850E_INTC_IMR_BASE_ADDR + ((irq) >> 3))
#define V850E_INTC_IMR_BIT(irq) ((irq) & 0x7)
/* Each maskable interrupt has a single-byte control register at this
address. */
#define NB85E_INTC_IC_BASE_ADDR 0xFFFFF110
#define NB85E_INTC_IC_ADDR(irq) (NB85E_INTC_IC_BASE_ADDR + ((irq) << 1))
#define NB85E_INTC_IC(irq) (*(volatile u8 *)NB85E_INTC_IC_ADDR(irq))
#define V850E_INTC_IC_BASE_ADDR 0xFFFFF110
#define V850E_INTC_IC_ADDR(irq) (V850E_INTC_IC_BASE_ADDR + ((irq) << 1))
#define V850E_INTC_IC(irq) (*(volatile u8 *)V850E_INTC_IC_ADDR(irq))
/* Encode priority PR for storing in an interrupt control register. */
#define NB85E_INTC_IC_PR(pr) (pr)
#define V850E_INTC_IC_PR(pr) (pr)
/* Interrupt disable bit in an interrupt control register. */
#define NB85E_INTC_IC_MK_BIT 6
#define NB85E_INTC_IC_MK (1 << NB85E_INTC_IC_MK_BIT)
#define V850E_INTC_IC_MK_BIT 6
#define V850E_INTC_IC_MK (1 << V850E_INTC_IC_MK_BIT)
/* Interrupt pending flag in an interrupt control register. */
#define NB85E_INTC_IC_IF_BIT 7
#define NB85E_INTC_IC_IF (1 << NB85E_INTC_IC_IF_BIT)
#define V850E_INTC_IC_IF_BIT 7
#define V850E_INTC_IC_IF (1 << V850E_INTC_IC_IF_BIT)
/* The ISPR (In-service priority register) contains one bit for each interrupt
priority level, which is set to one when that level is currently being
serviced (and thus blocking any interrupts of equal or lesser level). */
#define NB85E_INTC_ISPR_ADDR 0xFFFFF1FA
#define NB85E_INTC_ISPR (*(volatile u8 *)NB85E_INTC_ISPR_ADDR)
#define V850E_INTC_ISPR_ADDR 0xFFFFF1FA
#define V850E_INTC_ISPR (*(volatile u8 *)V850E_INTC_ISPR_ADDR)
#ifndef __ASSEMBLY__
/* Enable interrupt handling for interrupt IRQ. */
static inline void nb85e_intc_enable_irq (unsigned irq)
static inline void v850e_intc_enable_irq (unsigned irq)
{
__asm__ __volatile__ ("clr1 %0, [%1]"
:: "r" (NB85E_INTC_IMR_BIT (irq)),
"r" (NB85E_INTC_IMR_ADDR (irq))
:: "r" (V850E_INTC_IMR_BIT (irq)),
"r" (V850E_INTC_IMR_ADDR (irq))
: "memory");
}
/* Disable interrupt handling for interrupt IRQ. Note that any
interrupts received while disabled will be delivered once the
interrupt is enabled again, unless they are explicitly cleared using
`nb85e_intc_clear_pending_irq'. */
static inline void nb85e_intc_disable_irq (unsigned irq)
`v850e_intc_clear_pending_irq'. */
static inline void v850e_intc_disable_irq (unsigned irq)
{
__asm__ __volatile__ ("set1 %0, [%1]"
:: "r" (NB85E_INTC_IMR_BIT (irq)),
"r" (NB85E_INTC_IMR_ADDR (irq))
:: "r" (V850E_INTC_IMR_BIT (irq)),
"r" (V850E_INTC_IMR_ADDR (irq))
: "memory");
}
/* Return true if interrupt handling for interrupt IRQ is enabled. */
static inline int nb85e_intc_irq_enabled (unsigned irq)
static inline int v850e_intc_irq_enabled (unsigned irq)
{
int rval;
__asm__ __volatile__ ("tst1 %1, [%2]; setf z, %0"
: "=r" (rval)
: "r" (NB85E_INTC_IMR_BIT (irq)),
"r" (NB85E_INTC_IMR_ADDR (irq)));
: "r" (V850E_INTC_IMR_BIT (irq)),
"r" (V850E_INTC_IMR_ADDR (irq)));
return rval;
}
/* Disable irqs from 0 until LIMIT. LIMIT must be a multiple of 8. */
static inline void _nb85e_intc_disable_irqs (unsigned limit)
static inline void _v850e_intc_disable_irqs (unsigned limit)
{
unsigned long addr;
for (addr = NB85E_INTC_IMR_BASE_ADDR; limit >= 8; addr++, limit -= 8)
for (addr = V850E_INTC_IMR_BASE_ADDR; limit >= 8; addr++, limit -= 8)
*(char *)addr = 0xFF;
}
/* Disable all irqs. This is purposely a macro, because NUM_MACH_IRQS
will be only be defined later. */
#define nb85e_intc_disable_irqs() _nb85e_intc_disable_irqs (NUM_MACH_IRQS)
#define v850e_intc_disable_irqs() _v850e_intc_disable_irqs (NUM_MACH_IRQS)
/* Clear any pending interrupts for IRQ. */
static inline void nb85e_intc_clear_pending_irq (unsigned irq)
static inline void v850e_intc_clear_pending_irq (unsigned irq)
{
__asm__ __volatile__ ("clr1 %0, 0[%1]"
:: "i" (NB85E_INTC_IC_IF_BIT),
"r" (NB85E_INTC_IC_ADDR (irq))
:: "i" (V850E_INTC_IC_IF_BIT),
"r" (V850E_INTC_IC_ADDR (irq))
: "memory");
}
/* Return true if interrupt IRQ is pending (but disabled). */
static inline int nb85e_intc_irq_pending (unsigned irq)
static inline int v850e_intc_irq_pending (unsigned irq)
{
int rval;
__asm__ __volatile__ ("tst1 %1, 0[%2]; setf nz, %0"
: "=r" (rval)
: "i" (NB85E_INTC_IC_IF_BIT),
"r" (NB85E_INTC_IC_ADDR (irq)));
: "i" (V850E_INTC_IC_IF_BIT),
"r" (V850E_INTC_IC_ADDR (irq)));
return rval;
}
struct nb85e_intc_irq_init {
struct v850e_intc_irq_init {
const char *name; /* name of interrupt type */
/* Range of kernel irq numbers for this type:
......@@ -123,11 +123,11 @@ struct hw_interrupt_type; /* fwd decl */
/* Initialize HW_IRQ_TYPES for INTC-controlled irqs described in array
INITS (which is terminated by an entry with the name field == 0). */
extern void nb85e_intc_init_irq_types (struct nb85e_intc_irq_init *inits,
extern void v850e_intc_init_irq_types (struct v850e_intc_irq_init *inits,
struct hw_interrupt_type *hw_irq_types);
#endif /* !__ASSEMBLY__ */
#endif /* __V850_NB85E_INTC_H__ */
#endif /* __V850_V850E_INTC_H__ */
include/asm-v850/nb85e_timer_c.h → include/asm-v850/v850e_timer_c.h
View file @ 051063b5
/*
* include/asm-v850/nb85e_timer_c.h -- `Timer C' component often used
* with the NB85E cpu core
* include/asm-v850/v850e_timer_c.h -- `Timer C' component often used
* with the V850E cpu core
*
* Copyright (C) 2001 NEC Corporation
* Copyright (C) 2001 Miles Bader <miles@gnu.org>
* Copyright (C) 2001,03 NEC Electronics Corporation
* Copyright (C) 2001,03 Miles Bader <miles@gnu.org>
*
* This file is subject to the terms and conditions of the GNU General
* Public License. See the file COPYING in the main directory of this
......@@ -15,8 +15,8 @@
/* NOTE: this include file currently contains only enough to allow us to
use timer C as an interrupt pass-through. */
#ifndef __V850_NB85E_TIMER_C_H__
#define __V850_NB85E_TIMER_C_H__
#ifndef __V850_V850E_TIMER_C_H__
#define __V850_V850E_TIMER_C_H__
#include <asm/types.h>
#include <asm/machdep.h> /* Pick up chip-specific defs. */
......@@ -25,24 +25,24 @@
/* Timer C (16-bit interval timers). */
/* Control register 0 for timer C. */
#define NB85E_TIMER_C_TMCC0_ADDR(n) (NB85E_TIMER_C_BASE_ADDR + 0x6 + 0x10 *(n))
#define NB85E_TIMER_C_TMCC0(n) (*(volatile u8 *)NB85E_TIMER_C_TMCC0_ADDR(n))
#define NB85E_TIMER_C_TMCC0_CAE 0x01 /* clock action enable */
#define NB85E_TIMER_C_TMCC0_CE 0x02 /* count enable */
#define V850E_TIMER_C_TMCC0_ADDR(n) (V850E_TIMER_C_BASE_ADDR + 0x6 + 0x10 *(n))
#define V850E_TIMER_C_TMCC0(n) (*(volatile u8 *)V850E_TIMER_C_TMCC0_ADDR(n))
#define V850E_TIMER_C_TMCC0_CAE 0x01 /* clock action enable */
#define V850E_TIMER_C_TMCC0_CE 0x02 /* count enable */
/* ... */
/* Control register 1 for timer C. */
#define NB85E_TIMER_C_TMCC1_ADDR(n) (NB85E_TIMER_C_BASE_ADDR + 0x8 + 0x10 *(n))
#define NB85E_TIMER_C_TMCC1(n) (*(volatile u8 *)NB85E_TIMER_C_TMCC1_ADDR(n))
#define NB85E_TIMER_C_TMCC1_CMS0 0x01 /* capture/compare mode select (ccc0) */
#define NB85E_TIMER_C_TMCC1_CMS1 0x02 /* capture/compare mode select (ccc1) */
#define V850E_TIMER_C_TMCC1_ADDR(n) (V850E_TIMER_C_BASE_ADDR + 0x8 + 0x10 *(n))
#define V850E_TIMER_C_TMCC1(n) (*(volatile u8 *)V850E_TIMER_C_TMCC1_ADDR(n))
#define V850E_TIMER_C_TMCC1_CMS0 0x01 /* capture/compare mode select (ccc0) */
#define V850E_TIMER_C_TMCC1_CMS1 0x02 /* capture/compare mode select (ccc1) */
/* ... */
/* Interrupt edge-sensitivity control for timer C. */
#define NB85E_TIMER_C_SESC_ADDR(n) (NB85E_TIMER_C_BASE_ADDR + 0x9 + 0x10 *(n))
#define NB85E_TIMER_C_SESC(n) (*(volatile u8 *)NB85E_TIMER_C_SESC_ADDR(n))
#define V850E_TIMER_C_SESC_ADDR(n) (V850E_TIMER_C_BASE_ADDR + 0x9 + 0x10 *(n))
#define V850E_TIMER_C_SESC(n) (*(volatile u8 *)V850E_TIMER_C_SESC_ADDR(n))
/* ...etc... */
#endif /* __V850_NB85E_TIMER_C_H__ */
#endif /* __V850_V850E_TIMER_C_H__ */
include/asm-v850/nb85e_timer_d.h → include/asm-v850/v850e_timer_d.h
View file @ 051063b5
/*
* include/asm-v850/nb85e_timer_d.h -- `Timer D' component often used
* with the NB85E cpu core
* include/asm-v850/v850e_timer_d.h -- `Timer D' component often used
* with the V850E cpu core
*
* Copyright (C) 2001,02,03 NEC Electronics Corporation
* Copyright (C) 2001,02,03 Miles Bader <miles@gnu.org>
......@@ -12,8 +12,8 @@
* Written by Miles Bader <miles@gnu.org>
*/
#ifndef __V850_NB85E_TIMER_D_H__
#define __V850_NB85E_TIMER_D_H__
#ifndef __V850_V850E_TIMER_D_H__
#define __V850_V850E_TIMER_D_H__
#include <asm/types.h>
#include <asm/machdep.h> /* Pick up chip-specific defs. */
......@@ -22,31 +22,31 @@
/* Timer D (16-bit interval timers). */
/* Count registers for timer D. */
#define NB85E_TIMER_D_TMD_ADDR(n) (NB85E_TIMER_D_TMD_BASE_ADDR + 0x10 * (n))
#define NB85E_TIMER_D_TMD(n) (*(volatile u16 *)NB85E_TIMER_D_TMD_ADDR(n))
#define V850E_TIMER_D_TMD_ADDR(n) (V850E_TIMER_D_TMD_BASE_ADDR + 0x10 * (n))
#define V850E_TIMER_D_TMD(n) (*(volatile u16 *)V850E_TIMER_D_TMD_ADDR(n))
/* Count compare registers for timer D. */
#define NB85E_TIMER_D_CMD_ADDR(n) (NB85E_TIMER_D_CMD_BASE_ADDR + 0x10 * (n))
#define NB85E_TIMER_D_CMD(n) (*(volatile u16 *)NB85E_TIMER_D_CMD_ADDR(n))
#define V850E_TIMER_D_CMD_ADDR(n) (V850E_TIMER_D_CMD_BASE_ADDR + 0x10 * (n))
#define V850E_TIMER_D_CMD(n) (*(volatile u16 *)V850E_TIMER_D_CMD_ADDR(n))
/* Control registers for timer D. */
#define NB85E_TIMER_D_TMCD_ADDR(n) (NB85E_TIMER_D_TMCD_BASE_ADDR + 0x10 * (n))
#define NB85E_TIMER_D_TMCD(n) (*(volatile u8 *)NB85E_TIMER_D_TMCD_ADDR(n))
#define V850E_TIMER_D_TMCD_ADDR(n) (V850E_TIMER_D_TMCD_BASE_ADDR + 0x10 * (n))
#define V850E_TIMER_D_TMCD(n) (*(volatile u8 *)V850E_TIMER_D_TMCD_ADDR(n))
/* Control bits for timer D. */
#define NB85E_TIMER_D_TMCD_CE 0x2 /* count enable */
#define NB85E_TIMER_D_TMCD_CAE 0x1 /* clock action enable */
#define V850E_TIMER_D_TMCD_CE 0x2 /* count enable */
#define V850E_TIMER_D_TMCD_CAE 0x1 /* clock action enable */
/* Clock divider setting (log2). */
#define NB85E_TIMER_D_TMCD_CS(divlog2) (((divlog2) - NB85E_TIMER_D_TMCD_CS_MIN) << 4)
#define V850E_TIMER_D_TMCD_CS(divlog2) (((divlog2) - V850E_TIMER_D_TMCD_CS_MIN) << 4)
/* Minimum clock divider setting (log2). */
#ifndef NB85E_TIMER_D_TMCD_CS_MIN /* Can be overridden by mach-specific hdrs */
#define NB85E_TIMER_D_TMCD_CS_MIN 2 /* Default is correct for the v850e/ma1 */
#ifndef V850E_TIMER_D_TMCD_CS_MIN /* Can be overridden by mach-specific hdrs */
#define V850E_TIMER_D_TMCD_CS_MIN 2 /* Default is correct for the v850e/ma1 */
#endif
/* Maximum clock divider setting (log2). */
#define NB85E_TIMER_D_TMCD_CS_MAX (NB85E_TIMER_D_TMCD_CS_MIN + 7)
#define V850E_TIMER_D_TMCD_CS_MAX (V850E_TIMER_D_TMCD_CS_MIN + 7)
/* Return the clock-divider (log2) of timer D unit N. */
#define NB85E_TIMER_D_DIVLOG2(n) \
(((NB85E_TIMER_D_TMCD(n) >> 4) & 0x7) + NB85E_TIMER_D_TMCD_CS_MIN)
#define V850E_TIMER_D_DIVLOG2(n) \
(((V850E_TIMER_D_TMCD(n) >> 4) & 0x7) + V850E_TIMER_D_TMCD_CS_MIN)
#ifndef __ASSEMBLY__
......@@ -54,9 +54,9 @@
/* Start interval timer TIMER (0-3). The timer will issue the
corresponding INTCMD interrupt RATE times per second. This function
does not enable the interrupt. */
extern void nb85e_timer_d_configure (unsigned timer, unsigned rate);
extern void v850e_timer_d_configure (unsigned timer, unsigned rate);
#endif /* !__ASSEMBLY__ */
#endif /* __V850_NB85E_TIMER_D_H__ */
#endif /* __V850_V850E_TIMER_D_H__ */
include/asm-v850/v850e_uart.h 0 → 100644
View file @ 051063b5
/*
* include/asm-v850/v850e_uart.h -- common V850E on-chip UART driver
*
* Copyright (C) 2001,02,03 NEC Electronics Corporation
* Copyright (C) 2001,02,03 Miles Bader <miles@gnu.org>
*
* This file is subject to the terms and conditions of the GNU General
* Public License. See the file COPYING in the main directory of this
* archive for more details.
*
* Written by Miles Bader <miles@gnu.org>
*/
/* There's not actually a single UART implementation used by V850E CPUs,
but rather a series of implementations that are all `close' to one
another. This file corresponds to the single driver which handles all
of them. */
#ifndef __V850_V850E_UART_H__
#define __V850_V850E_UART_H__
#include <linux/config.h>
#include <linux/termios.h>
#include <asm/v850e_utils.h>
#include <asm/types.h>
#include <asm/machdep.h> /* Pick up chip-specific defs. */
/* Include model-specific definitions. */
#ifdef CONFIG_V850E_UART
# ifdef CONFIG_V850E_UARTB
# include <asm-v850/v850e_uartb.h>
# else
# include <asm-v850/v850e_uarta.h> /* original V850E UART */
# endif
#endif
/* Optional capabilities some hardware provides. */
/* This UART doesn't implement RTS/CTS by default, but some platforms
implement them externally, so check to see if <asm/machdep.h> defined
anything. */
#ifdef V850E_UART_CTS
#define v850e_uart_cts(n) V850E_UART_CTS(n)
#else
#define v850e_uart_cts(n) (1)
#endif
/* Do the same for RTS. */
#ifdef V850E_UART_SET_RTS
#define v850e_uart_set_rts(n,v) V850E_UART_SET_RTS(n,v)
#else
#define v850e_uart_set_rts(n,v) ((void)0)
#endif
/* This is the serial channel to use for the boot console (if desired). */
#ifndef V850E_UART_CONSOLE_CHANNEL
# define V850E_UART_CONSOLE_CHANNEL 0
#endif
#ifndef __ASSEMBLY__
/* Setup a console using channel 0 of the builtin uart. */
extern void v850e_uart_cons_init (unsigned chan);
/* Configure and turn on uart channel CHAN, using the termios `control
modes' bits in CFLAGS, and a baud-rate of BAUD. */
void v850e_uart_configure (unsigned chan, unsigned cflags, unsigned baud);
#endif /* !__ASSEMBLY__ */
#endif /* __V850_V850E_UART_H__ */
include/asm-v850/v850e_uarta.h 0 → 100644
View file @ 051063b5
This diff is collapsed.
include/asm-v850/v850e_uartb.h 0 → 100644
View file @ 051063b5
This diff is collapsed.
include/asm-v850/nb85e_utils.h → include/asm-v850/v850e_utils.h
View file @ 051063b5
/*
* include/asm-v850/nb85e_utils.h -- Utility functions associated with
* the NB85E cpu core
* include/asm-v850/v850e_utils.h -- Utility functions associated with
* V850E CPUs
*
* Copyright (C) 2001 NEC Corporation
* Copyright (C) 2001 Miles Bader <miles@gnu.org>
* Copyright (C) 2001,03 NEC Electronics Corporation
* Copyright (C) 2001,03 Miles Bader <miles@gnu.org>
*
* This file is subject to the terms and conditions of the GNU General
* Public License. See the file COPYING in the main directory of this
......@@ -12,8 +12,8 @@
* Written by Miles Bader <miles@gnu.org>
*/
#ifndef __V850_NB85E_UTILS_H__
#define __V850_NB85E_UTILS_H__
#ifndef __V850_V850E_UTILS_H__
#define __V850_V850E_UTILS_H__
/* Calculate counter clock-divider and count values to attain the
desired frequency RATE from the base frequency BASE_FREQ. The
......@@ -32,4 +32,4 @@ extern int calc_counter_params (unsigned long base_freq,
unsigned counter_size,
unsigned *divlog2, unsigned *count);
#endif /* __V850_NB85E_UTILS_H__ */
#endif /* __V850_V850E_UTILS_H__ */
include/linux/serial_core.h
View file @ 051063b5
......@@ -57,7 +57,7 @@
#define PORT_SUNSAB 39
/* NEC v850. */
#define PORT_NB85E_UART 40
#define PORT_V850E_UART 40
/* NEC PC-9800 */
#define PORT_8251_PC98 41
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment
GitLab Nexedi Edition | About GitLab | About Nexedi | 沪ICP备2021021310号-2 | 沪ICP备2021021310号-7