Commit 055c9fa8 authored by Linus Torvalds's avatar Linus Torvalds

Merge tag 'fixes-for-v3.5' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio

Pull GPIO fixes from Linus Walleij:
 "Yes, this is a *LATE* GPIO pull request with fixes for v3.5.

  Grant moved across the planet and accidentally fell off the grid, so
  he asked me to take over the GPIO merges for a while 10 days ago.

  Since then I went over the archives and collected this pile of fixes,
  and pulled two of them from the TI maintainer Kevin Hilman.  Then
  waited for them to at least hit linux-next once or twice."

GPIO fixes for v3.5:
 - Invalid context restore on bank 0 for OMAP driver in runtime
   suspend/resume cycle
 - Check for NULL platform data in sta-2x11 driver
 - Constrain selection of the V1 MSM GPIO driver to applicable platforms
   (Kconfig issue)
 - Make sure the correct output value is set in the wm8994 driver
 - Export devm_gpio_request_one() so it can be used in modules.
   Apparently some in-kernel modules can be configured to use this
   leading to breakage.
 - Check that the GPIO is valid in the lantiq driver
 - Fix the flag bits introduced for v3.5, so they don't overlap
 - Fix a device tree intialization bug for imx21-compatible devices
 - Carry over the OF node to the TPS65910 GPIO chip struct

* tag 'fixes-for-v3.5' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio:
  gpio: tps65910: initialize of_node of gpio_chip
  gpio/mxc: make irqs work for fsl,imx21-gpio devices
  gpio: fix bits conflict for gpio flags
  mips: pci-lantiq: Fix check for valid gpio
  gpio: export devm_gpio_request_one
  gpiolib: wm8994: Pay attention to the value set when enabling as output
  gpio/msm_v1: CONFIG_GPIO_MSM_V1 is only available on three SoCs
  gpio-sta2x11: don't use pdata if null
  gpio/omap: fix invalid context restore of gpio bank-0
  gpio/omap: fix irq loss while in idle with debounce on
parents 310959e8 46bada60
......@@ -129,7 +129,7 @@ static int __devinit ltq_pci_startup(struct platform_device *pdev)
/* setup reset gpio used by pci */
reset_gpio = of_get_named_gpio(node, "gpio-reset", 0);
if (reset_gpio > 0)
if (gpio_is_valid(reset_gpio))
devm_gpio_request(&pdev->dev, reset_gpio, "pci-reset");
/* enable auto-switching between PCI and EBU */
......@@ -192,7 +192,7 @@ static int __devinit ltq_pci_startup(struct platform_device *pdev)
ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_PCC_IEN) | 0x10, LTQ_EBU_PCC_IEN);
/* toggle reset pin */
if (reset_gpio > 0) {
if (gpio_is_valid(reset_gpio)) {
__gpio_set_value(reset_gpio, 0);
wmb();
mdelay(1);
......
......@@ -136,7 +136,7 @@ config GPIO_MPC8XXX
config GPIO_MSM_V1
tristate "Qualcomm MSM GPIO v1"
depends on GPIOLIB && ARCH_MSM
depends on GPIOLIB && ARCH_MSM && (ARCH_MSM7X00A || ARCH_MSM7X30 || ARCH_QSD8X50)
help
Say yes here to support the GPIO interface on ARM v6 based
Qualcomm MSM chips. Most of the pins on the MSM can be
......
......@@ -98,6 +98,7 @@ int devm_gpio_request_one(struct device *dev, unsigned gpio,
return 0;
}
EXPORT_SYMBOL(devm_gpio_request_one);
/**
* devm_gpio_free - free an interrupt
......
......@@ -398,10 +398,12 @@ static int __devinit mxc_gpio_probe(struct platform_device *pdev)
writel(~0, port->base + GPIO_ISR);
if (mxc_gpio_hwtype == IMX21_GPIO) {
/* setup one handler for all GPIO interrupts */
if (pdev->id == 0)
irq_set_chained_handler(port->irq,
mx2_gpio_irq_handler);
/*
* Setup one handler for all GPIO interrupts. Actually setting
* the handler is needed only once, but doing it for every port
* is more robust and easier.
*/
irq_set_chained_handler(port->irq, mx2_gpio_irq_handler);
} else {
/* setup one handler for each entry */
irq_set_chained_handler(port->irq, mx3_gpio_irq_handler);
......
......@@ -174,12 +174,22 @@ static inline void _gpio_dbck_enable(struct gpio_bank *bank)
if (bank->dbck_enable_mask && !bank->dbck_enabled) {
clk_enable(bank->dbck);
bank->dbck_enabled = true;
__raw_writel(bank->dbck_enable_mask,
bank->base + bank->regs->debounce_en);
}
}
static inline void _gpio_dbck_disable(struct gpio_bank *bank)
{
if (bank->dbck_enable_mask && bank->dbck_enabled) {
/*
* Disable debounce before cutting it's clock. If debounce is
* enabled but the clock is not, GPIO module seems to be unable
* to detect events and generate interrupts at least on OMAP3.
*/
__raw_writel(0, bank->base + bank->regs->debounce_en);
clk_disable(bank->dbck);
bank->dbck_enabled = false;
}
......@@ -1081,7 +1091,6 @@ static int __devinit omap_gpio_probe(struct platform_device *pdev)
bank->is_mpuio = pdata->is_mpuio;
bank->non_wakeup_gpios = pdata->non_wakeup_gpios;
bank->loses_context = pdata->loses_context;
bank->get_context_loss_count = pdata->get_context_loss_count;
bank->regs = pdata->regs;
#ifdef CONFIG_OF_GPIO
bank->chip.of_node = of_node_get(node);
......@@ -1135,6 +1144,9 @@ static int __devinit omap_gpio_probe(struct platform_device *pdev)
omap_gpio_chip_init(bank);
omap_gpio_show_rev(bank);
if (bank->loses_context)
bank->get_context_loss_count = pdata->get_context_loss_count;
pm_runtime_put(bank->dev);
list_add_tail(&bank->node, &omap_gpio_list);
......
......@@ -383,6 +383,7 @@ static int __devinit gsta_probe(struct platform_device *dev)
}
spin_lock_init(&chip->lock);
gsta_gpio_setup(chip);
if (gpio_pdata)
for (i = 0; i < GSTA_NR_GPIO; i++)
gsta_set_config(chip, i, gpio_pdata->pinconfig[i]);
......
......@@ -149,6 +149,7 @@ static int __devinit tps65910_gpio_probe(struct platform_device *pdev)
tps65910_gpio->gpio_chip.set = tps65910_gpio_set;
tps65910_gpio->gpio_chip.get = tps65910_gpio_get;
tps65910_gpio->gpio_chip.dev = &pdev->dev;
tps65910_gpio->gpio_chip.of_node = tps65910->dev->of_node;
if (pdata && pdata->gpio_base)
tps65910_gpio->gpio_chip.base = pdata->gpio_base;
else
......
......@@ -89,8 +89,11 @@ static int wm8994_gpio_direction_out(struct gpio_chip *chip,
struct wm8994_gpio *wm8994_gpio = to_wm8994_gpio(chip);
struct wm8994 *wm8994 = wm8994_gpio->wm8994;
if (value)
value = WM8994_GPN_LVL;
return wm8994_set_bits(wm8994, WM8994_GPIO_1 + offset,
WM8994_GPN_DIR, 0);
WM8994_GPN_DIR | WM8994_GPN_LVL, value);
}
static void wm8994_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
......
......@@ -22,8 +22,8 @@
/* Gpio pin is open source */
#define GPIOF_OPEN_SOURCE (1 << 3)
#define GPIOF_EXPORT (1 << 2)
#define GPIOF_EXPORT_CHANGEABLE (1 << 3)
#define GPIOF_EXPORT (1 << 4)
#define GPIOF_EXPORT_CHANGEABLE (1 << 5)
#define GPIOF_EXPORT_DIR_FIXED (GPIOF_EXPORT)
#define GPIOF_EXPORT_DIR_CHANGEABLE (GPIOF_EXPORT | GPIOF_EXPORT_CHANGEABLE)
......
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