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Commit 0598e144 authored by Alexander Viro's avatar Alexander Viro Committed by Linus Torvalds
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[PATCH] iphase iomem annotations 

partially annotated
Signed-off-by: default avatarAl Viro <viro@parcelfarce.linux.theplanet.co.uk>
Signed-off-by: default avatarLinus Torvalds <torvalds@osdl.org>
parent 5b36b1f9
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Inline Side-by-side
Showing with 51 additions and 52 deletions
drivers/atm/iphase.c
View file @ 0598e144
......@@ -1010,7 +1010,8 @@ static struct atm_dev *ia_boards = NULL;
void desc_dbg(IADEV *iadev) {
u_short tcq_wr_ptr, tcq_st_ptr, tcq_ed_ptr;
u32 tmp, i;
u32 i;
void __iomem *tmp;
// regval = readl((u32)ia_cmds->maddr);
tcq_wr_ptr = readw(iadev->seg_reg+TCQ_WR_PTR);
printk("B_tcq_wr = 0x%x desc = %d last desc = %d\n",
......@@ -1024,7 +1025,7 @@ void desc_dbg(IADEV *iadev) {
i = 0;
while (tcq_st_ptr != tcq_ed_ptr) {
tmp = iadev->seg_ram+tcq_st_ptr;
printk("TCQ slot %d desc = %d Addr = 0x%x\n", i++, readw(tmp), tmp);
printk("TCQ slot %d desc = %d Addr = %p\n", i++, readw(tmp), tmp);
tcq_st_ptr += 2;
}
for(i=0; i <iadev->num_tx_desc; i++)
......@@ -1080,7 +1081,7 @@ static int rx_pkt(struct atm_dev *dev)
IADEV *iadev;
struct atm_vcc *vcc;
unsigned short status;
struct rx_buf_desc *buf_desc_ptr;
struct rx_buf_desc __iomem *buf_desc_ptr;
int desc;
struct dle* wr_ptr;
int len;
......@@ -1095,7 +1096,7 @@ static int rx_pkt(struct atm_dev *dev)
}
/* mask 1st 3 bits to get the actual descno. */
desc = readw(iadev->reass_ram+iadev->rfL.pcq_rd) & 0x1fff;
IF_RX(printk("reass_ram = 0x%x iadev->rfL.pcq_rd = 0x%x desc = %d\n",
IF_RX(printk("reass_ram = %p iadev->rfL.pcq_rd = 0x%x desc = %d\n",
iadev->reass_ram, iadev->rfL.pcq_rd, desc);
printk(" pcq_wr_ptr = 0x%x\n",
readw(iadev->reass_reg+PCQ_WR_PTR)&0xffff);)
......@@ -1109,7 +1110,7 @@ static int rx_pkt(struct atm_dev *dev)
/* get the buffer desc entry.
update stuff. - doesn't seem to be any update necessary
*/
buf_desc_ptr = (struct rx_buf_desc *)iadev->RX_DESC_BASE_ADDR;
buf_desc_ptr = iadev->RX_DESC_BASE_ADDR;
/* make the ptr point to the corresponding buffer desc entry */
buf_desc_ptr += desc;
if (!desc || (desc > iadev->num_rx_desc) ||
......@@ -1358,8 +1359,8 @@ static void rx_dle_intr(struct atm_dev *dev)
static int open_rx(struct atm_vcc *vcc)
{
IADEV *iadev;
u_short *vc_table;
u_short *reass_ptr;
u_short __iomem *vc_table;
u_short __iomem *reass_ptr;
IF_EVENT(printk("iadev: open_rx %d.%d\n", vcc->vpi, vcc->vci);)
if (vcc->qos.rxtp.traffic_class == ATM_NONE) return 0;
......@@ -1372,7 +1373,7 @@ static int open_rx(struct atm_vcc *vcc)
}
/* Make only this VCI in the vc table valid and let all
others be invalid entries */
vc_table = (u_short *)(iadev->reass_ram+RX_VC_TABLE*iadev->memSize);
vc_table = iadev->reass_ram+RX_VC_TABLE*iadev->memSize;
vc_table += vcc->vci;
/* mask the last 6 bits and OR it with 3 for 1K VCs */
......@@ -1387,8 +1388,7 @@ static int open_rx(struct atm_vcc *vcc)
ia_open_abr_vc(iadev, &srv_p, vcc, 0);
}
else { /* for UBR later may need to add CBR logic */
reass_ptr = (u_short *)
(iadev->reass_ram+REASS_TABLE*iadev->memSize);
reass_ptr = iadev->reass_ram+REASS_TABLE*iadev->memSize;
reass_ptr += vcc->vci;
*reass_ptr = NO_AAL5_PKT;
}
......@@ -1403,7 +1403,7 @@ static int open_rx(struct atm_vcc *vcc)
static int rx_init(struct atm_dev *dev)
{
IADEV *iadev;
struct rx_buf_desc *buf_desc_ptr;
struct rx_buf_desc __iomem *buf_desc_ptr;
unsigned long rx_pkt_start = 0;
void *dle_addr;
struct abr_vc_table *abr_vc_table;
......@@ -1465,13 +1465,13 @@ static int rx_init(struct atm_dev *dev)
/* Initialize each entry in the Buffer Descriptor Table */
iadev->RX_DESC_BASE_ADDR = iadev->reass_ram+RX_DESC_BASE*iadev->memSize;
buf_desc_ptr =(struct rx_buf_desc *)iadev->RX_DESC_BASE_ADDR;
memset((caddr_t)buf_desc_ptr, 0, sizeof(*buf_desc_ptr));
buf_desc_ptr = iadev->RX_DESC_BASE_ADDR;
memset_io(buf_desc_ptr, 0, sizeof(*buf_desc_ptr));
buf_desc_ptr++;
rx_pkt_start = iadev->rx_pkt_ram;
for(i=1; i<=iadev->num_rx_desc; i++)
{
memset((caddr_t)buf_desc_ptr, 0, sizeof(*buf_desc_ptr));
memset_io(buf_desc_ptr, 0, sizeof(*buf_desc_ptr));
buf_desc_ptr->buf_start_hi = rx_pkt_start >> 16;
buf_desc_ptr->buf_start_lo = rx_pkt_start & 0x0000ffff;
buf_desc_ptr++;
......@@ -2053,10 +2053,9 @@ static int tx_init(struct atm_dev *dev)
IF_INIT(printk("CBR_TAB_BEG = 0x%x, CBR_TAB_END = 0x%x, CBR_PTR = 0x%x\n",
readw(iadev->seg_reg+CBR_TAB_BEG), readw(iadev->seg_reg+CBR_TAB_END),
readw(iadev->seg_reg+CBR_TAB_END+1));)
tmp16 = (iadev->seg_ram+CBR_SCHED_TABLE*iadev->memSize);
/* Initialize the CBR Schedualing Table */
memset((caddr_t)(iadev->seg_ram+CBR_SCHED_TABLE*iadev->memSize),
memset_io(iadev->seg_ram+CBR_SCHED_TABLE*iadev->memSize,
0, iadev->num_vc*6);
iadev->CbrRemEntries = iadev->CbrTotEntries = iadev->num_vc*3;
iadev->CbrEntryPt = 0;
......@@ -2287,7 +2286,8 @@ static int reset_sar(struct atm_dev *dev)
static int __init ia_init(struct atm_dev *dev)
{
IADEV *iadev;
unsigned long real_base, base;
unsigned long real_base;
void __iomem *base;
unsigned short command;
unsigned char revision;
int error, i;
......@@ -2343,7 +2343,7 @@ static int __init ia_init(struct atm_dev *dev)
udelay(10);
/* mapping the physical address to a virtual address in address space */
base=(unsigned long)ioremap((unsigned long)real_base,iadev->pci_map_size); /* ioremap is not resolved ??? */
base = ioremap(real_base,iadev->pci_map_size); /* ioremap is not resolved ??? */
if (!base)
{
......@@ -2351,39 +2351,38 @@ static int __init ia_init(struct atm_dev *dev)
dev->number);
return error;
}
IF_INIT(printk(DEV_LABEL " (itf %d): rev.%d,base=0x%lx,irq=%d\n",
IF_INIT(printk(DEV_LABEL " (itf %d): rev.%d,base=%p,irq=%d\n",
dev->number, revision, base, iadev->irq);)
/* filling the iphase dev structure */
iadev->mem = iadev->pci_map_size /2;
iadev->base_diff = real_base - base;
iadev->real_base = real_base;
iadev->base = base;
/* Bus Interface Control Registers */
iadev->reg = (u32 *) (base + REG_BASE);
iadev->reg = base + REG_BASE;
/* Segmentation Control Registers */
iadev->seg_reg = (u32 *) (base + SEG_BASE);
iadev->seg_reg = base + SEG_BASE;
/* Reassembly Control Registers */
iadev->reass_reg = (u32 *) (base + REASS_BASE);
iadev->reass_reg = base + REASS_BASE;
/* Front end/ DMA control registers */
iadev->phy = (u32 *) (base + PHY_BASE);
iadev->dma = (u32 *) (base + PHY_BASE);
iadev->phy = base + PHY_BASE;
iadev->dma = base + PHY_BASE;
/* RAM - Segmentation RAm and Reassembly RAM */
iadev->ram = (u32 *) (base + ACTUAL_RAM_BASE);
iadev->seg_ram = (base + ACTUAL_SEG_RAM_BASE);
iadev->reass_ram = (base + ACTUAL_REASS_RAM_BASE);
iadev->ram = base + ACTUAL_RAM_BASE;
iadev->seg_ram = base + ACTUAL_SEG_RAM_BASE;
iadev->reass_ram = base + ACTUAL_REASS_RAM_BASE;
/* lets print out the above */
IF_INIT(printk("Base addrs: %08x %08x %08x \n %08x %08x %08x %08x\n",
(u32)iadev->reg,(u32)iadev->seg_reg,(u32)iadev->reass_reg,
(u32)iadev->phy, (u32)iadev->ram, (u32)iadev->seg_ram,
(u32)iadev->reass_ram);)
IF_INIT(printk("Base addrs: %p %p %p \n %p %p %p %p\n",
iadev->reg,iadev->seg_reg,iadev->reass_reg,
iadev->phy, iadev->ram, iadev->seg_ram,
iadev->reass_ram);)
/* lets try reading the MAC address */
error = get_esi(dev);
if (error) {
iounmap((void *) iadev->base);
iounmap(iadev->base);
return error;
}
printk("IA: ");
......@@ -2393,7 +2392,7 @@ static int __init ia_init(struct atm_dev *dev)
/* reset SAR */
if (reset_sar(dev)) {
iounmap((void *) iadev->base);
iounmap(iadev->base);
printk("IA: reset SAR fail, please try again\n");
return 1;
}
......@@ -2659,7 +2658,7 @@ static void ia_close(struct atm_vcc *vcc)
vc_table += vcc->vci;
*vc_table = (vcc->vci << 6) | 15;
if (vcc->qos.rxtp.traffic_class == ATM_ABR) {
struct abr_vc_table *abr_vc_table = (struct abr_vc_table *)
struct abr_vc_table __iomem *abr_vc_table =
(iadev->reass_ram+ABR_VC_TABLE*iadev->memSize);
abr_vc_table += vcc->vci;
abr_vc_table->rdf = 0x0003;
......@@ -2890,7 +2889,7 @@ static int ia_setsockopt(struct atm_vcc *vcc, int level, int optname,
static int ia_pkt_tx (struct atm_vcc *vcc, struct sk_buff *skb) {
IADEV *iadev;
struct dle *wr_ptr;
struct tx_buf_desc *buf_desc_ptr;
struct tx_buf_desc __iomem *buf_desc_ptr;
int desc;
int comp_code;
int total_len;
......@@ -2994,7 +2993,7 @@ static int ia_pkt_tx (struct atm_vcc *vcc, struct sk_buff *skb) {
printk("\n");)
/* Build the buffer descriptor */
buf_desc_ptr = (struct tx_buf_desc *)(iadev->seg_ram+TX_DESC_BASE);
buf_desc_ptr = iadev->seg_ram+TX_DESC_BASE;
buf_desc_ptr += desc; /* points to the corresponding entry */
buf_desc_ptr->desc_mode = AAL5 | EOM_EN | APP_CRC32 | CMPL_INT;
/* Huh ? p.115 of users guide describes this as a read-only register */
......@@ -3252,7 +3251,7 @@ static void __devexit ia_remove_one(struct pci_dev *pdev)
atm_dev_deregister(dev);
IF_EVENT(printk("iav deregistered at (itf:%d)\n", dev->number);)
iounmap((void *) iadev->base);
iounmap(iadev->base);
pci_disable_device(pdev);
ia_free_rx(iadev);
......
drivers/atm/iphase.h
View file @ 0598e144
......@@ -996,18 +996,18 @@ typedef struct _SUNI_STATS_
typedef struct iadev_t {
/*-----base pointers into (i)chipSAR+ address space */
u32 *phy; /* base pointer into phy(SUNI) */
u32 *dma; /* base pointer into DMA control
u32 __iomem *phy; /* base pointer into phy(SUNI) */
u32 __iomem *dma; /* base pointer into DMA control
registers */
u32 *reg; /* base pointer to SAR registers
u32 __iomem *reg; /* base pointer to SAR registers
- Bus Interface Control Regs */
u32 *seg_reg; /* base pointer to segmentation engine
u32 __iomem *seg_reg; /* base pointer to segmentation engine
internal registers */
u32 *reass_reg; /* base pointer to reassemble engine
u32 __iomem *reass_reg; /* base pointer to reassemble engine
internal registers */
u32 *ram; /* base pointer to SAR RAM */
unsigned int seg_ram;
unsigned int reass_ram;
u32 __iomem *ram; /* base pointer to SAR RAM */
void __iomem *seg_ram;
void __iomem *reass_ram;
struct dle_q tx_dle_q;
struct free_desc_q *tx_free_desc_qhead;
struct sk_buff_head tx_dma_q, tx_backlog;
......@@ -1019,7 +1019,7 @@ typedef struct iadev_t {
struct cpcs_trailer_desc *tx_buf;
u16 num_tx_desc, tx_buf_sz, rate_limit;
u32 tx_cell_cnt, tx_pkt_cnt;
u32 MAIN_VC_TABLE_ADDR, EXT_VC_TABLE_ADDR, ABR_SCHED_TABLE_ADDR;
void __iomem *MAIN_VC_TABLE_ADDR, *EXT_VC_TABLE_ADDR, *ABR_SCHED_TABLE_ADDR;
struct dle_q rx_dle_q;
struct free_desc_q *rx_free_desc_qhead;
struct sk_buff_head rx_dma_q;
......@@ -1027,13 +1027,13 @@ typedef struct iadev_t {
struct atm_vcc **rx_open; /* list of all open VCs */
u16 num_rx_desc, rx_buf_sz, rxing;
u32 rx_pkt_ram, rx_tmp_cnt, rx_tmp_jif;
u32 RX_DESC_BASE_ADDR;
void __iomem *RX_DESC_BASE_ADDR;
u32 drop_rxpkt, drop_rxcell, rx_cell_cnt, rx_pkt_cnt;
struct atm_dev *next_board; /* other iphase devices */
struct pci_dev *pci;
int mem;
unsigned long base_diff; /* virtual - real base address */
unsigned int real_base, base; /* real and virtual base address */
unsigned int real_base; /* real and virtual base address */
void __iomem *base;
unsigned int pci_map_size; /*pci map size of board */
unsigned char irq;
unsigned char bus;
......
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