Skip to content

L
linux
Commit 05fafbfb authored by Yuval Mintz's avatar Yuval Mintz Committed by David S. Miller
1 Browse files
Options

qed: utilize FW 8.10.10.0 

This new firmware for the qed* adpaters fixes several issues:
 - Better blocking of malicious VFs.
 - After FLR, Tx-switching [internal routing] of packets might
   be incorrect.
 - Deletion of unicast MAC filters would sometime have side-effect
   of corrupting the MAC filters configred for a device.
It also contains fixes for future qed* drivers that *hopefully* would be
sent for review in the near future.

In addition, it would allow driver some new functionality, including:
 - Allowing PF/VF driver compaitibility with old drivers [running
   pre-8.10.5.0 firmware].
 - Better debug facilities.

This would also bump the qed* driver versions to 8.10.9.20.
Signed-off-by: default avatarYuval Mintz <Yuval.Mintz@qlogic.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 75d67207
Hide whitespace changes
Inline Side-by-side
Showing with 1375 additions and 725 deletions
drivers/net/ethernet/qlogic/qed/qed.h
View file @ 05fafbfb
......@@ -26,7 +26,7 @@
#include "qed_hsi.h"
extern const struct qed_common_ops qed_common_ops_pass;
#define DRV_MODULE_VERSION "8.7.1.20"
#define DRV_MODULE_VERSION "8.10.9.20"
#define MAX_HWFNS_PER_DEVICE (4)
#define NAME_SIZE 16
......
drivers/net/ethernet/qlogic/qed/qed_dev.c
View file @ 05fafbfb
......@@ -772,6 +772,9 @@ static int qed_hw_init_common(struct qed_hwfn *p_hwfn,
concrete_fid = qed_vfid_to_concrete(p_hwfn, vf_id);
qed_fid_pretend(p_hwfn, p_ptt, (u16) concrete_fid);
qed_wr(p_hwfn, p_ptt, CCFC_REG_STRONG_ENABLE_VF, 0x1);
qed_wr(p_hwfn, p_ptt, CCFC_REG_WEAK_ENABLE_VF, 0x0);
qed_wr(p_hwfn, p_ptt, TCFC_REG_STRONG_ENABLE_VF, 0x1);
qed_wr(p_hwfn, p_ptt, TCFC_REG_WEAK_ENABLE_VF, 0x0);
}
/* pretend to original PF */
qed_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
......@@ -782,34 +785,8 @@ static int qed_hw_init_common(struct qed_hwfn *p_hwfn,
static int qed_hw_init_port(struct qed_hwfn *p_hwfn,
struct qed_ptt *p_ptt, int hw_mode)
{
int rc = 0;
rc = qed_init_run(p_hwfn, p_ptt, PHASE_PORT, p_hwfn->port_id, hw_mode);
if (rc)
return rc;
if (hw_mode & (1 << MODE_MF_SI)) {
u8 pf_id = 0;
if (!qed_hw_init_first_eth(p_hwfn, p_ptt, &pf_id)) {
DP_VERBOSE(p_hwfn, NETIF_MSG_IFUP,
"PF[%08x] is first eth on engine\n", pf_id);
/* We should have configured BIT for ppfid, i.e., the
* relative function number in the port. But there's a
* bug in LLH in BB where the ppfid is actually engine
* based, so we need to take this into account.
*/
qed_wr(p_hwfn, p_ptt,
NIG_REG_LLH_TAGMAC_DEF_PF_VECTOR, 1 << pf_id);
}
/* Take the protocol-based hit vector if there is a hit,
* otherwise take the other vector.
*/
qed_wr(p_hwfn, p_ptt, NIG_REG_LLH_CLS_TYPE_DUALMODE, 0x2);
}
return rc;
return qed_init_run(p_hwfn, p_ptt, PHASE_PORT,
p_hwfn->port_id, hw_mode);
}
static int qed_hw_init_pf(struct qed_hwfn *p_hwfn,
......@@ -878,21 +855,6 @@ static int qed_hw_init_pf(struct qed_hwfn *p_hwfn,
/* Pure runtime initializations - directly to the HW */
qed_int_igu_init_pure_rt(p_hwfn, p_ptt, true, true);
if (hw_mode & (1 << MODE_MF_SI)) {
u8 pf_id = 0;
u32 val = 0;
if (!qed_hw_init_first_eth(p_hwfn, p_ptt, &pf_id)) {
if (p_hwfn->rel_pf_id == pf_id) {
DP_VERBOSE(p_hwfn, NETIF_MSG_IFUP,
"PF[%d] is first ETH on engine\n",
pf_id);
val = 1;
}
qed_wr(p_hwfn, p_ptt, PRS_REG_MSG_INFO, val);
}
}
if (b_hw_start) {
/* enable interrupts */
qed_int_igu_enable(p_hwfn, p_ptt, int_mode);
......
drivers/net/ethernet/qlogic/qed/qed_hsi.h
View file @ 05fafbfb
......@@ -536,6 +536,244 @@ struct core_conn_context {
struct regpair ustorm_st_padding[2];
};
enum core_error_handle {
LL2_DROP_PACKET,
LL2_DO_NOTHING,
LL2_ASSERT,
MAX_CORE_ERROR_HANDLE
};
enum core_event_opcode {
CORE_EVENT_TX_QUEUE_START,
CORE_EVENT_TX_QUEUE_STOP,
CORE_EVENT_RX_QUEUE_START,
CORE_EVENT_RX_QUEUE_STOP,
MAX_CORE_EVENT_OPCODE
};
enum core_l4_pseudo_checksum_mode {
CORE_L4_PSEUDO_CSUM_CORRECT_LENGTH,
CORE_L4_PSEUDO_CSUM_ZERO_LENGTH,
MAX_CORE_L4_PSEUDO_CHECKSUM_MODE
};
struct core_ll2_port_stats {
struct regpair gsi_invalid_hdr;
struct regpair gsi_invalid_pkt_length;
struct regpair gsi_unsupported_pkt_typ;
struct regpair gsi_crcchksm_error;
};
struct core_ll2_pstorm_per_queue_stat {
struct regpair sent_ucast_bytes;
struct regpair sent_mcast_bytes;
struct regpair sent_bcast_bytes;
struct regpair sent_ucast_pkts;
struct regpair sent_mcast_pkts;
struct regpair sent_bcast_pkts;
};
struct core_ll2_rx_prod {
__le16 bd_prod;
__le16 cqe_prod;
__le32 reserved;
};
struct core_ll2_tstorm_per_queue_stat {
struct regpair packet_too_big_discard;
struct regpair no_buff_discard;
};
struct core_ll2_ustorm_per_queue_stat {
struct regpair rcv_ucast_bytes;
struct regpair rcv_mcast_bytes;
struct regpair rcv_bcast_bytes;
struct regpair rcv_ucast_pkts;
struct regpair rcv_mcast_pkts;
struct regpair rcv_bcast_pkts;
};
enum core_ramrod_cmd_id {
CORE_RAMROD_UNUSED,
CORE_RAMROD_RX_QUEUE_START,
CORE_RAMROD_TX_QUEUE_START,
CORE_RAMROD_RX_QUEUE_STOP,
CORE_RAMROD_TX_QUEUE_STOP,
MAX_CORE_RAMROD_CMD_ID
};
enum core_roce_flavor_type {
CORE_ROCE,
CORE_RROCE,
MAX_CORE_ROCE_FLAVOR_TYPE
};
struct core_rx_action_on_error {
u8 error_type;
#define CORE_RX_ACTION_ON_ERROR_PACKET_TOO_BIG_MASK 0x3
#define CORE_RX_ACTION_ON_ERROR_PACKET_TOO_BIG_SHIFT 0
#define CORE_RX_ACTION_ON_ERROR_NO_BUFF_MASK 0x3
#define CORE_RX_ACTION_ON_ERROR_NO_BUFF_SHIFT 2
#define CORE_RX_ACTION_ON_ERROR_RESERVED_MASK 0xF
#define CORE_RX_ACTION_ON_ERROR_RESERVED_SHIFT 4
};
struct core_rx_bd {
struct regpair addr;
__le16 reserved[4];
};
struct core_rx_bd_with_buff_len {
struct regpair addr;
__le16 buff_length;
__le16 reserved[3];
};
union core_rx_bd_union {
struct core_rx_bd rx_bd;
struct core_rx_bd_with_buff_len rx_bd_with_len;
};
struct core_rx_cqe_opaque_data {
__le32 data[2];
};
enum core_rx_cqe_type {
CORE_RX_CQE_ILLIGAL_TYPE,
CORE_RX_CQE_TYPE_REGULAR,
CORE_RX_CQE_TYPE_GSI_OFFLOAD,
CORE_RX_CQE_TYPE_SLOW_PATH,
MAX_CORE_RX_CQE_TYPE
};
struct core_rx_fast_path_cqe {
u8 type;
u8 placement_offset;
struct parsing_and_err_flags parse_flags;
__le16 packet_length;
__le16 vlan;
struct core_rx_cqe_opaque_data opaque_data;
__le32 reserved[4];
};
struct core_rx_gsi_offload_cqe {
u8 type;
u8 data_length_error;
struct parsing_and_err_flags parse_flags;
__le16 data_length;
__le16 vlan;
__le32 src_mac_addrhi;
__le16 src_mac_addrlo;
u8 reserved1[2];
__le32 gid_dst[4];
};
struct core_rx_slow_path_cqe {
u8 type;
u8 ramrod_cmd_id;
__le16 echo;
__le32 reserved1[7];
};
union core_rx_cqe_union {
struct core_rx_fast_path_cqe rx_cqe_fp;
struct core_rx_gsi_offload_cqe rx_cqe_gsi;
struct core_rx_slow_path_cqe rx_cqe_sp;
};
struct core_rx_start_ramrod_data {
struct regpair bd_base;
struct regpair cqe_pbl_addr;
__le16 mtu;
__le16 sb_id;
u8 sb_index;
u8 complete_cqe_flg;
u8 complete_event_flg;
u8 drop_ttl0_flg;
__le16 num_of_pbl_pages;
u8 inner_vlan_removal_en;
u8 queue_id;
u8 main_func_queue;
u8 mf_si_bcast_accept_all;
u8 mf_si_mcast_accept_all;
struct core_rx_action_on_error action_on_error;
u8 gsi_offload_flag;
u8 reserved[7];
};
struct core_rx_stop_ramrod_data {
u8 complete_cqe_flg;
u8 complete_event_flg;
u8 queue_id;
u8 reserved1;
__le16 reserved2[2];
};
struct core_tx_bd_flags {
u8 as_bitfield;
#define CORE_TX_BD_FLAGS_FORCE_VLAN_MODE_MASK 0x1
#define CORE_TX_BD_FLAGS_FORCE_VLAN_MODE_SHIFT 0
#define CORE_TX_BD_FLAGS_VLAN_INSERTION_MASK 0x1
#define CORE_TX_BD_FLAGS_VLAN_INSERTION_SHIFT 1
#define CORE_TX_BD_FLAGS_START_BD_MASK 0x1
#define CORE_TX_BD_FLAGS_START_BD_SHIFT 2
#define CORE_TX_BD_FLAGS_IP_CSUM_MASK 0x1
#define CORE_TX_BD_FLAGS_IP_CSUM_SHIFT 3
#define CORE_TX_BD_FLAGS_L4_CSUM_MASK 0x1
#define CORE_TX_BD_FLAGS_L4_CSUM_SHIFT 4
#define CORE_TX_BD_FLAGS_IPV6_EXT_MASK 0x1
#define CORE_TX_BD_FLAGS_IPV6_EXT_SHIFT 5
#define CORE_TX_BD_FLAGS_L4_PROTOCOL_MASK 0x1
#define CORE_TX_BD_FLAGS_L4_PROTOCOL_SHIFT 6
#define CORE_TX_BD_FLAGS_L4_PSEUDO_CSUM_MODE_MASK 0x1
#define CORE_TX_BD_FLAGS_L4_PSEUDO_CSUM_MODE_SHIFT 7
};
struct core_tx_bd {
struct regpair addr;
__le16 nbytes;
__le16 nw_vlan_or_lb_echo;
u8 bitfield0;
#define CORE_TX_BD_NBDS_MASK 0xF
#define CORE_TX_BD_NBDS_SHIFT 0
#define CORE_TX_BD_ROCE_FLAV_MASK 0x1
#define CORE_TX_BD_ROCE_FLAV_SHIFT 4
#define CORE_TX_BD_RESERVED0_MASK 0x7
#define CORE_TX_BD_RESERVED0_SHIFT 5
struct core_tx_bd_flags bd_flags;
__le16 bitfield1;
#define CORE_TX_BD_L4_HDR_OFFSET_W_MASK 0x3FFF
#define CORE_TX_BD_L4_HDR_OFFSET_W_SHIFT 0
#define CORE_TX_BD_TX_DST_MASK 0x1
#define CORE_TX_BD_TX_DST_SHIFT 14
#define CORE_TX_BD_RESERVED1_MASK 0x1
#define CORE_TX_BD_RESERVED1_SHIFT 15
};
enum core_tx_dest {
CORE_TX_DEST_NW,
CORE_TX_DEST_LB,
MAX_CORE_TX_DEST
};
struct core_tx_start_ramrod_data {
struct regpair pbl_base_addr;
__le16 mtu;
__le16 sb_id;
u8 sb_index;
u8 stats_en;
u8 stats_id;
u8 conn_type;
__le16 pbl_size;
__le16 qm_pq_id;
u8 gsi_offload_flag;
u8 resrved[3];
};
struct core_tx_stop_ramrod_data {
__le32 reserved0[2];
};
struct eth_mstorm_per_pf_stat {
struct regpair gre_discard_pkts;
struct regpair vxlan_discard_pkts;
......@@ -636,9 +874,33 @@ struct hsi_fp_ver_struct {
};
/* Mstorm non-triggering VF zone */
enum malicious_vf_error_id {
MALICIOUS_VF_NO_ERROR,
VF_PF_CHANNEL_NOT_READY,
VF_ZONE_MSG_NOT_VALID,
VF_ZONE_FUNC_NOT_ENABLED,
ETH_PACKET_TOO_SMALL,
ETH_ILLEGAL_VLAN_MODE,
ETH_MTU_VIOLATION,
ETH_ILLEGAL_INBAND_TAGS,
ETH_VLAN_INSERT_AND_INBAND_VLAN,
ETH_ILLEGAL_NBDS,
ETH_FIRST_BD_WO_SOP,
ETH_INSUFFICIENT_BDS,
ETH_ILLEGAL_LSO_HDR_NBDS,
ETH_ILLEGAL_LSO_MSS,
ETH_ZERO_SIZE_BD,
ETH_ILLEGAL_LSO_HDR_LEN,
ETH_INSUFFICIENT_PAYLOAD,
ETH_EDPM_OUT_OF_SYNC,
ETH_TUNN_IPV6_EXT_NBD_ERR,
ETH_CONTROL_PACKET_VIOLATION,
MAX_MALICIOUS_VF_ERROR_ID
};
struct mstorm_non_trigger_vf_zone {
struct eth_mstorm_per_queue_stat eth_queue_stat;
struct eth_rx_prod_data eth_rx_queue_producers[ETH_MAX_NUM_RX_QUEUES_PER_VF];
struct eth_rx_prod_data eth_rx_queue_producers[ETH_MAX_NUM_RX_QUEUES_PER_VF_QUAD];
};
/* Mstorm VF zone */
......@@ -705,13 +967,17 @@ struct pf_start_ramrod_data {
struct protocol_dcb_data {
u8 dcb_enable_flag;
u8 reserved_a;
u8 dcb_priority;
u8 dcb_tc;
u8 reserved;
u8 reserved_b;
u8 reserved0;
};
struct pf_update_tunnel_config {
u8 update_rx_pf_clss;
u8 update_rx_def_ucast_clss;
u8 update_rx_def_non_ucast_clss;
u8 update_tx_pf_clss;
u8 set_vxlan_udp_port_flg;
u8 set_geneve_udp_port_flg;
......@@ -727,7 +993,7 @@ struct pf_update_tunnel_config {
u8 tunnel_clss_ipgre;
__le16 vxlan_udp_port;
__le16 geneve_udp_port;
__le16 reserved[3];
__le16 reserved[2];
};
struct pf_update_ramrod_data {
......@@ -736,16 +1002,17 @@ struct pf_update_ramrod_data {
u8 update_fcoe_dcb_data_flag;
u8 update_iscsi_dcb_data_flag;
u8 update_roce_dcb_data_flag;
u8 update_rroce_dcb_data_flag;
u8 update_iwarp_dcb_data_flag;
u8 update_mf_vlan_flag;
u8 reserved;
struct protocol_dcb_data eth_dcb_data;
struct protocol_dcb_data fcoe_dcb_data;
struct protocol_dcb_data iscsi_dcb_data;
struct protocol_dcb_data roce_dcb_data;
struct protocol_dcb_data rroce_dcb_data;
struct protocol_dcb_data iwarp_dcb_data;
__le16 mf_vlan;
__le16 reserved2;
__le16 reserved;
struct pf_update_tunnel_config tunnel_config;
};
......@@ -766,10 +1033,14 @@ enum protocol_version_array_key {
MAX_PROTOCOL_VERSION_ARRAY_KEY
};
/* Pstorm non-triggering VF zone */
struct rdma_sent_stats {
struct regpair sent_bytes;
struct regpair sent_pkts;
};
struct pstorm_non_trigger_vf_zone {
struct eth_pstorm_per_queue_stat eth_queue_stat;
struct regpair reserved[2];
struct rdma_sent_stats rdma_stats;
};
/* Pstorm VF zone */
......@@ -786,7 +1057,11 @@ struct ramrod_header {
__le16 echo;
};
/* Slowpath Element (SPQE) */
struct rdma_rcv_stats {
struct regpair rcv_bytes;
struct regpair rcv_pkts;
};
struct slow_path_element {
struct ramrod_header hdr;
struct regpair data_ptr;
......@@ -794,7 +1069,7 @@ struct slow_path_element {
/* Tstorm non-triggering VF zone */
struct tstorm_non_trigger_vf_zone {
struct regpair reserved[2];
struct rdma_rcv_stats rdma_stats;
};
struct tstorm_per_port_stat {
......@@ -802,9 +1077,14 @@ struct tstorm_per_port_stat {
struct regpair mac_error_discard;
struct regpair mftag_filter_discard;
struct regpair eth_mac_filter_discard;
struct regpair reserved[5];
struct regpair ll2_mac_filter_discard;
struct regpair ll2_conn_disabled_discard;
struct regpair iscsi_irregular_pkt;
struct regpair reserved;
struct regpair roce_irregular_pkt;
struct regpair eth_irregular_pkt;
struct regpair reserved1[2];
struct regpair reserved1;
struct regpair preroce_irregular_pkt;
struct regpair eth_gre_tunn_filter_discard;
struct regpair eth_vxlan_tunn_filter_discard;
struct regpair eth_geneve_tunn_filter_discard;
......@@ -870,7 +1150,13 @@ struct vf_stop_ramrod_data {
__le32 reserved2;
};
/* Attentions status block */
enum vf_zone_size_mode {
VF_ZONE_SIZE_MODE_DEFAULT,
VF_ZONE_SIZE_MODE_DOUBLE,
VF_ZONE_SIZE_MODE_QUAD,
MAX_VF_ZONE_SIZE_MODE
};
struct atten_status_block {
__le32 atten_bits;
__le32 atten_ack;
......@@ -1579,6 +1865,7 @@ enum dbg_status {
DBG_STATUS_REG_FIFO_BAD_DATA,
DBG_STATUS_PROTECTION_OVERRIDE_BAD_DATA,
DBG_STATUS_DBG_ARRAY_NOT_SET,
DBG_STATUS_MULTI_BLOCKS_WITH_FILTER,
MAX_DBG_STATUS
};
......@@ -1589,7 +1876,41 @@ enum dbg_status {
/* Number of VLAN priorities */
#define NUM_OF_VLAN_PRIORITIES 8
/* QM per-port init parameters */
struct init_brb_ram_req {
__le32 guranteed_per_tc;
__le32 headroom_per_tc;
__le32 min_pkt_size;
__le32 max_ports_per_engine;
u8 num_active_tcs[MAX_NUM_PORTS];
};
struct init_ets_tc_req {
u8 use_sp;
u8 use_wfq;
__le16 weight;
};
struct init_ets_req {
__le32 mtu;
struct init_ets_tc_req tc_req[NUM_OF_TCS];
};
struct init_nig_lb_rl_req {
__le16 lb_mac_rate;
__le16 lb_rate;
__le32 mtu;
__le16 tc_rate[NUM_OF_PHYS_TCS];
};
struct init_nig_pri_tc_map_entry {
u8 tc_id;
u8 valid;
};
struct init_nig_pri_tc_map_req {
struct init_nig_pri_tc_map_entry pri[NUM_OF_VLAN_PRIORITIES];
};
struct init_qm_port_params {
u8 active;
u8 active_phys_tcs;
......@@ -1619,7 +1940,7 @@ struct init_qm_vport_params {
/* Width of GRC address in bits (addresses are specified in dwords) */
#define GRC_ADDR_BITS 23
#define MAX_GRC_ADDR ((1 << GRC_ADDR_BITS) - 1)
#define MAX_GRC_ADDR (BIT(GRC_ADDR_BITS) - 1)
/* indicates an init that should be applied to any phase ID */
#define ANY_PHASE_ID 0xffff
......@@ -1674,11 +1995,11 @@ struct bin_buffer_hdr {
/* binary init buffer types */
enum bin_init_buffer_type {
BIN_BUF_FW_VER_INFO,
BIN_BUF_INIT_FW_VER_INFO,
BIN_BUF_INIT_CMD,
BIN_BUF_INIT_VAL,
BIN_BUF_INIT_MODE_TREE,
BIN_BUF_IRO,
BIN_BUF_INIT_IRO,
MAX_BIN_INIT_BUFFER_TYPE
};
......@@ -1918,44 +2239,34 @@ enum dbg_status qed_dbg_print_attn(struct qed_hwfn *p_hwfn,
#define MAX_NAME_LEN 16
/* Win 2 */
#define GTT_BAR0_MAP_REG_IGU_CMD \
0x00f000UL
#define GTT_BAR0_MAP_REG_IGU_CMD 0x00f000UL
/* Win 3 */
#define GTT_BAR0_MAP_REG_TSDM_RAM \
0x010000UL
#define GTT_BAR0_MAP_REG_TSDM_RAM 0x010000UL
/* Win 4 */
#define GTT_BAR0_MAP_REG_MSDM_RAM \
0x011000UL
#define GTT_BAR0_MAP_REG_MSDM_RAM 0x011000UL
/* Win 5 */
#define GTT_BAR0_MAP_REG_MSDM_RAM_1024 \
0x012000UL
#define GTT_BAR0_MAP_REG_MSDM_RAM_1024 0x012000UL
/* Win 6 */
#define GTT_BAR0_MAP_REG_USDM_RAM \
0x013000UL
#define GTT_BAR0_MAP_REG_USDM_RAM 0x013000UL
/* Win 7 */
#define GTT_BAR0_MAP_REG_USDM_RAM_1024 \
0x014000UL
#define GTT_BAR0_MAP_REG_USDM_RAM_1024 0x014000UL
/* Win 8 */
#define GTT_BAR0_MAP_REG_USDM_RAM_2048 \
0x015000UL
#define GTT_BAR0_MAP_REG_USDM_RAM_2048 0x015000UL
/* Win 9 */
#define GTT_BAR0_MAP_REG_XSDM_RAM \
0x016000UL
#define GTT_BAR0_MAP_REG_XSDM_RAM 0x016000UL
/* Win 10 */
#define GTT_BAR0_MAP_REG_YSDM_RAM \
0x017000UL
#define GTT_BAR0_MAP_REG_YSDM_RAM 0x017000UL
/* Win 11 */
#define GTT_BAR0_MAP_REG_PSDM_RAM \
0x018000UL
#define GTT_BAR0_MAP_REG_PSDM_RAM 0x018000UL
/**
* @brief qed_qm_pf_mem_size - prepare QM ILT sizes
......@@ -2003,7 +2314,7 @@ struct qed_qm_pf_rt_init_params {
u16 num_vf_pqs;
u8 start_vport;
u8 num_vports;
u8 pf_wfq;
u16 pf_wfq;
u32 pf_rl;
struct init_qm_pq_params *pq_params;
struct init_qm_vport_params *vport_params;
......@@ -2138,6 +2449,9 @@ void qed_set_geneve_enable(struct qed_hwfn *p_hwfn,
#define TSTORM_PORT_STAT_OFFSET(port_id) \
(IRO[1].base + ((port_id) * IRO[1].m1))
#define TSTORM_PORT_STAT_SIZE (IRO[1].size)
#define TSTORM_LL2_PORT_STAT_OFFSET(port_id) \
(IRO[2].base + ((port_id) * IRO[2].m1))
#define TSTORM_LL2_PORT_STAT_SIZE (IRO[2].size)
#define USTORM_VF_PF_CHANNEL_READY_OFFSET(vf_id) \
(IRO[3].base + ((vf_id) * IRO[3].m1))
#define USTORM_VF_PF_CHANNEL_READY_SIZE (IRO[3].size)
......@@ -2153,42 +2467,90 @@ void qed_set_geneve_enable(struct qed_hwfn *p_hwfn,
#define USTORM_COMMON_QUEUE_CONS_OFFSET(queue_zone_id) \
(IRO[7].base + ((queue_zone_id) * IRO[7].m1))
#define USTORM_COMMON_QUEUE_CONS_SIZE (IRO[7].size)
#define TSTORM_LL2_RX_PRODS_OFFSET(core_rx_queue_id) \
(IRO[14].base + ((core_rx_queue_id) * IRO[14].m1))
#define TSTORM_LL2_RX_PRODS_SIZE (IRO[14].size)
#define CORE_LL2_TSTORM_PER_QUEUE_STAT_OFFSET(core_rx_queue_id) \
(IRO[15].base + ((core_rx_queue_id) * IRO[15].m1))
#define CORE_LL2_TSTORM_PER_QUEUE_STAT_SIZE (IRO[15].size)
#define CORE_LL2_USTORM_PER_QUEUE_STAT_OFFSET(core_rx_queue_id) \
(IRO[16].base + ((core_rx_queue_id) * IRO[16].m1))
#define CORE_LL2_USTORM_PER_QUEUE_STAT_SIZE (IRO[16].size)
#define CORE_LL2_PSTORM_PER_QUEUE_STAT_OFFSET(core_tx_stats_id) \
(IRO[17].base + ((core_tx_stats_id) * IRO[17].m1))
#define CORE_LL2_PSTORM_PER_QUEUE_STAT_SIZE (IRO[17]. size)
#define MSTORM_QUEUE_STAT_OFFSET(stat_counter_id) \
(IRO[18].base + ((stat_counter_id) * IRO[18].m1))
#define MSTORM_QUEUE_STAT_SIZE (IRO[18].size)
#define MSTORM_ETH_PF_PRODS_OFFSET(queue_id) \
(IRO[19].base + ((queue_id) * IRO[19].m1))
#define MSTORM_ETH_PF_PRODS_SIZE (IRO[19].size)
#define MSTORM_TPA_TIMEOUT_US_OFFSET (IRO[20].base)
#define MSTORM_TPA_TIMEOUT_US_SIZE (IRO[20].size)
#define MSTORM_ETH_VF_PRODS_OFFSET(vf_id, vf_queue_id) \
(IRO[20].base + ((vf_id) * IRO[20].m1) + ((vf_queue_id) * IRO[20].m2))
#define MSTORM_ETH_VF_PRODS_SIZE (IRO[20].size)
#define MSTORM_TPA_TIMEOUT_US_OFFSET (IRO[21].base)
#define MSTORM_TPA_TIMEOUT_US_SIZE (IRO[21].size)
#define MSTORM_ETH_PF_STAT_OFFSET(pf_id) \
(IRO[21].base + ((pf_id) * IRO[21].m1))
(IRO[22].base + ((pf_id) * IRO[22].m1))
#define MSTORM_ETH_PF_STAT_SIZE (IRO[21].size)
#define USTORM_QUEUE_STAT_OFFSET(stat_counter_id) \
(IRO[22].base + ((stat_counter_id) * IRO[22].m1))
#define USTORM_QUEUE_STAT_SIZE (IRO[22].size)
(IRO[23].base + ((stat_counter_id) * IRO[23].m1))
#define USTORM_QUEUE_STAT_SIZE (IRO[23].size)
#define USTORM_ETH_PF_STAT_OFFSET(pf_id) \
(IRO[23].base + ((pf_id) * IRO[23].m1))
#define USTORM_ETH_PF_STAT_SIZE (IRO[23].size)
(IRO[24].base + ((pf_id) * IRO[24].m1))
#define USTORM_ETH_PF_STAT_SIZE (IRO[24].size)
#define PSTORM_QUEUE_STAT_OFFSET(stat_counter_id) \
(IRO[24].base + ((stat_counter_id) * IRO[24].m1))
#define PSTORM_QUEUE_STAT_SIZE (IRO[24].size)
(IRO[25].base + ((stat_counter_id) * IRO[25].m1))
#define PSTORM_QUEUE_STAT_SIZE (IRO[25].size)
#define PSTORM_ETH_PF_STAT_OFFSET(pf_id) \
(IRO[25].base + ((pf_id) * IRO[25].m1))
#define PSTORM_ETH_PF_STAT_SIZE (IRO[25].size)
(IRO[26].base + ((pf_id) * IRO[26].m1))
#define PSTORM_ETH_PF_STAT_SIZE (IRO[26].size)
#define PSTORM_CTL_FRAME_ETHTYPE_OFFSET(ethtype) \
(IRO[26].base + ((ethtype) * IRO[26].m1))
#define PSTORM_CTL_FRAME_ETHTYPE_SIZE (IRO[26].size)
#define TSTORM_ETH_PRS_INPUT_OFFSET (IRO[27].base)
#define TSTORM_ETH_PRS_INPUT_SIZE (IRO[27].size)
(IRO[27].base + ((ethtype) * IRO[27].m1))
#define PSTORM_CTL_FRAME_ETHTYPE_SIZE (IRO[27].size)
#define TSTORM_ETH_PRS_INPUT_OFFSET (IRO[28].base)
#define TSTORM_ETH_PRS_INPUT_SIZE (IRO[28].size)
#define ETH_RX_RATE_LIMIT_OFFSET(pf_id) \
(IRO[28].base + ((pf_id) * IRO[28].m1))
#define ETH_RX_RATE_LIMIT_SIZE (IRO[28].size)
(IRO[29].base + ((pf_id) * IRO[29].m1))
#define ETH_RX_RATE_LIMIT_SIZE (IRO[29].size)
#define XSTORM_ETH_QUEUE_ZONE_OFFSET(queue_id) \
(IRO[29].base + ((queue_id) * IRO[29].m1))
#define XSTORM_ETH_QUEUE_ZONE_SIZE (IRO[29].size)
static const struct iro iro_arr[46] = {
(IRO[30].base + ((queue_id) * IRO[30].m1))
#define XSTORM_ETH_QUEUE_ZONE_SIZE (IRO[30].size)
#define TSTORM_SCSI_CMDQ_CONS_OFFSET(cmdq_queue_id) \
(IRO[34].base + ((cmdq_queue_id) * IRO[34].m1))
#define TSTORM_SCSI_CMDQ_CONS_SIZE (IRO[34].size)
#define TSTORM_SCSI_BDQ_EXT_PROD_OFFSET(func_id, bdq_id) \
(IRO[35].base + ((func_id) * IRO[35].m1) + ((bdq_id) * IRO[35].m2))
#define TSTORM_SCSI_BDQ_EXT_PROD_SIZE (IRO[35].size)
#define MSTORM_SCSI_BDQ_EXT_PROD_OFFSET(func_id, bdq_id) \
(IRO[36].base + ((func_id) * IRO[36].m1) + ((bdq_id) * IRO[36].m2))
#define MSTORM_SCSI_BDQ_EXT_PROD_SIZE (IRO[36].size)
#define TSTORM_ISCSI_RX_STATS_OFFSET(pf_id) \
(IRO[37].base + ((pf_id) * IRO[37].m1))
#define TSTORM_ISCSI_RX_STATS_SIZE (IRO[37].size)
#define MSTORM_ISCSI_RX_STATS_OFFSET(pf_id) \
(IRO[38].base + ((pf_id) * IRO[38].m1))
#define MSTORM_ISCSI_RX_STATS_SIZE (IRO[38].size)
#define USTORM_ISCSI_RX_STATS_OFFSET(pf_id) \
(IRO[39].base + ((pf_id) * IRO[39].m1))
#define USTORM_ISCSI_RX_STATS_SIZE (IRO[39].size)
#define XSTORM_ISCSI_TX_STATS_OFFSET(pf_id) \
(IRO[40].base + ((pf_id) * IRO[40].m1))
#define XSTORM_ISCSI_TX_STATS_SIZE (IRO[40].size)
#define YSTORM_ISCSI_TX_STATS_OFFSET(pf_id) \
(IRO[41].base + ((pf_id) * IRO[41].m1))
#define YSTORM_ISCSI_TX_STATS_SIZE (IRO[41].size)
#define PSTORM_ISCSI_TX_STATS_OFFSET(pf_id) \
(IRO[42].base + ((pf_id) * IRO[42].m1))
#define PSTORM_ISCSI_TX_STATS_SIZE (IRO[42].size)
#define PSTORM_RDMA_QUEUE_STAT_OFFSET(rdma_stat_counter_id) \
(IRO[45].base + ((rdma_stat_counter_id) * IRO[45].m1))
#define PSTORM_RDMA_QUEUE_STAT_SIZE (IRO[45].size)
#define TSTORM_RDMA_QUEUE_STAT_OFFSET(rdma_stat_counter_id) \
(IRO[46].base + ((rdma_stat_counter_id) * IRO[46].m1))
#define TSTORM_RDMA_QUEUE_STAT_SIZE (IRO[46].size)
static const struct iro iro_arr[47] = {
{0x0, 0x0, 0x0, 0x0, 0x8},
{0x4cb0, 0x78, 0x0, 0x0, 0x78},
{0x6318, 0x20, 0x0, 0x0, 0x20},
......@@ -2201,20 +2563,21 @@ static const struct iro iro_arr[46] = {
{0x3df0, 0x0, 0x0, 0x0, 0x78},
{0x29b0, 0x0, 0x0, 0x0, 0x78},
{0x4c38, 0x0, 0x0, 0x0, 0x78},
{0x4a48, 0x0, 0x0, 0x0, 0x78},
{0x4990, 0x0, 0x0, 0x0, 0x78},
{0x7e48, 0x0, 0x0, 0x0, 0x78},
{0xa28, 0x8, 0x0, 0x0, 0x8},
{0x60f8, 0x10, 0x0, 0x0, 0x10},
{0xb820, 0x30, 0x0, 0x0, 0x30},
{0x95b8, 0x30, 0x0, 0x0, 0x30},
{0x4c18, 0x80, 0x0, 0x0, 0x40},
{0x4b60, 0x80, 0x0, 0x0, 0x40},
{0x1f8, 0x4, 0x0, 0x0, 0x4},
{0xc9a8, 0x0, 0x0, 0x0, 0x4},
{0x4c58, 0x80, 0x0, 0x0, 0x20},
{0x53a0, 0x80, 0x4, 0x0, 0x4},
{0xc8f0, 0x0, 0x0, 0x0, 0x4},
{0x4ba0, 0x80, 0x0, 0x0, 0x20},
{0x8050, 0x40, 0x0, 0x0, 0x30},
{0xe770, 0x60, 0x0, 0x0, 0x60},
{0x2b48, 0x80, 0x0, 0x0, 0x38},
{0xdf88, 0x78, 0x0, 0x0, 0x78},
{0xf188, 0x78, 0x0, 0x0, 0x78},
{0x1f8, 0x4, 0x0, 0x0, 0x4},
{0xacf0, 0x0, 0x0, 0x0, 0xf0},
{0xade0, 0x8, 0x0, 0x0, 0x8},
......@@ -2226,455 +2589,457 @@ static const struct iro iro_arr[46] = {
{0x200, 0x10, 0x8, 0x0, 0x8},
{0xb78, 0x10, 0x8, 0x0, 0x2},
{0xd888, 0x38, 0x0, 0x0, 0x24},
{0x12120, 0x10, 0x0, 0x0, 0x8},
{0x11b20, 0x38, 0x0, 0x0, 0x18},
{0x12c38, 0x10, 0x0, 0x0, 0x8},
{0x11aa0, 0x38, 0x0, 0x0, 0x18},
{0xa8c0, 0x30, 0x0, 0x0, 0x10},
{0x86f8, 0x28, 0x0, 0x0, 0x18},
{0xeff8, 0x10, 0x0, 0x0, 0x10},
{0x101f8, 0x10, 0x0, 0x0, 0x10},
{0xdd08, 0x48, 0x0, 0x0, 0x38},
{0xf460, 0x20, 0x0, 0x0, 0x20},
{0x10660, 0x20, 0x0, 0x0, 0x20},
{0x2b80, 0x80, 0x0, 0x0, 0x10},
{0x5000, 0x10, 0x0, 0x0, 0x10},
};
/* Runtime array offsets */
#define DORQ_REG_PF_MAX_ICID_0_RT_OFFSET 0
#define DORQ_REG_PF_MAX_ICID_1_RT_OFFSET 1
#define DORQ_REG_PF_MAX_ICID_2_RT_OFFSET 2
#define DORQ_REG_PF_MAX_ICID_3_RT_OFFSET 3
#define DORQ_REG_PF_MAX_ICID_4_RT_OFFSET 4
#define DORQ_REG_PF_MAX_ICID_5_RT_OFFSET 5
#define DORQ_REG_PF_MAX_ICID_6_RT_OFFSET 6
#define DORQ_REG_PF_MAX_ICID_7_RT_OFFSET 7
#define DORQ_REG_VF_MAX_ICID_0_RT_OFFSET 8
#define DORQ_REG_VF_MAX_ICID_1_RT_OFFSET 9
#define DORQ_REG_VF_MAX_ICID_2_RT_OFFSET 10
#define DORQ_REG_VF_MAX_ICID_3_RT_OFFSET 11
#define DORQ_REG_VF_MAX_ICID_4_RT_OFFSET 12
#define DORQ_REG_VF_MAX_ICID_5_RT_OFFSET 13
#define DORQ_REG_VF_MAX_ICID_6_RT_OFFSET 14
#define DORQ_REG_VF_MAX_ICID_7_RT_OFFSET 15
#define DORQ_REG_PF_WAKE_ALL_RT_OFFSET 16
#define DORQ_REG_TAG1_ETHERTYPE_RT_OFFSET 17
#define IGU_REG_PF_CONFIGURATION_RT_OFFSET 18
#define IGU_REG_VF_CONFIGURATION_RT_OFFSET 19
#define IGU_REG_ATTN_MSG_ADDR_L_RT_OFFSET 20
#define IGU_REG_ATTN_MSG_ADDR_H_RT_OFFSET 21
#define IGU_REG_LEADING_EDGE_LATCH_RT_OFFSET 22
#define IGU_REG_TRAILING_EDGE_LATCH_RT_OFFSET 23
#define CAU_REG_CQE_AGG_UNIT_SIZE_RT_OFFSET 24
#define CAU_REG_SB_VAR_MEMORY_RT_OFFSET 761
#define CAU_REG_SB_VAR_MEMORY_RT_SIZE 736
#define CAU_REG_SB_VAR_MEMORY_RT_OFFSET 761
#define CAU_REG_SB_VAR_MEMORY_RT_SIZE 736
#define CAU_REG_SB_ADDR_MEMORY_RT_OFFSET 1497
#define CAU_REG_SB_ADDR_MEMORY_RT_SIZE 736
#define CAU_REG_PI_MEMORY_RT_OFFSET 2233
#define CAU_REG_PI_MEMORY_RT_SIZE 4416
#define PRS_REG_SEARCH_RESP_INITIATOR_TYPE_RT_OFFSET 6649
#define PRS_REG_TASK_ID_MAX_INITIATOR_PF_RT_OFFSET 6650
#define PRS_REG_TASK_ID_MAX_INITIATOR_VF_RT_OFFSET 6651
#define PRS_REG_TASK_ID_MAX_TARGET_PF_RT_OFFSET 6652
#define PRS_REG_TASK_ID_MAX_TARGET_VF_RT_OFFSET 6653
#define PRS_REG_SEARCH_TCP_RT_OFFSET 6654
#define PRS_REG_SEARCH_FCOE_RT_OFFSET 6655
#define PRS_REG_SEARCH_ROCE_RT_OFFSET 6656
#define PRS_REG_ROCE_DEST_QP_MAX_VF_RT_OFFSET 6657
#define PRS_REG_ROCE_DEST_QP_MAX_PF_RT_OFFSET 6658
#define PRS_REG_SEARCH_OPENFLOW_RT_OFFSET 6659
#define PRS_REG_SEARCH_NON_IP_AS_OPENFLOW_RT_OFFSET 6660
#define PRS_REG_OPENFLOW_SUPPORT_ONLY_KNOWN_OVER_IP_RT_OFFSET 6661
#define PRS_REG_OPENFLOW_SEARCH_KEY_MASK_RT_OFFSET 6662
#define PRS_REG_TAG_ETHERTYPE_0_RT_OFFSET 6663
#define PRS_REG_LIGHT_L2_ETHERTYPE_EN_RT_OFFSET 6664
#define SRC_REG_FIRSTFREE_RT_OFFSET 6665
#define SRC_REG_FIRSTFREE_RT_SIZE 2
#define SRC_REG_LASTFREE_RT_OFFSET 6667
#define SRC_REG_LASTFREE_RT_SIZE 2
#define SRC_REG_COUNTFREE_RT_OFFSET 6669
#define SRC_REG_NUMBER_HASH_BITS_RT_OFFSET 6670
#define PSWRQ2_REG_CDUT_P_SIZE_RT_OFFSET 6671
#define PSWRQ2_REG_CDUC_P_SIZE_RT_OFFSET 6672
#define PSWRQ2_REG_TM_P_SIZE_RT_OFFSET 6673
#define PSWRQ2_REG_QM_P_SIZE_RT_OFFSET 6674
#define PSWRQ2_REG_SRC_P_SIZE_RT_OFFSET 6675
#define PSWRQ2_REG_TSDM_P_SIZE_RT_OFFSET 6676
#define PSWRQ2_REG_TM_FIRST_ILT_RT_OFFSET 6677
#define PSWRQ2_REG_TM_LAST_ILT_RT_OFFSET 6678
#define PSWRQ2_REG_QM_FIRST_ILT_RT_OFFSET 6679
#define PSWRQ2_REG_QM_LAST_ILT_RT_OFFSET 6680
#define PSWRQ2_REG_SRC_FIRST_ILT_RT_OFFSET 6681
#define PSWRQ2_REG_SRC_LAST_ILT_RT_OFFSET 6682
#define PSWRQ2_REG_CDUC_FIRST_ILT_RT_OFFSET 6683
#define PSWRQ2_REG_CDUC_LAST_ILT_RT_OFFSET 6684
#define PSWRQ2_REG_CDUT_FIRST_ILT_RT_OFFSET 6685
#define PSWRQ2_REG_CDUT_LAST_ILT_RT_OFFSET 6686
#define PSWRQ2_REG_TSDM_FIRST_ILT_RT_OFFSET 6687
#define PSWRQ2_REG_TSDM_LAST_ILT_RT_OFFSET 6688
#define PSWRQ2_REG_TM_NUMBER_OF_PF_BLOCKS_RT_OFFSET 6689
#define PSWRQ2_REG_CDUT_NUMBER_OF_PF_BLOCKS_RT_OFFSET 6690
#define PSWRQ2_REG_CDUC_NUMBER_OF_PF_BLOCKS_RT_OFFSET 6691
#define PSWRQ2_REG_TM_VF_BLOCKS_RT_OFFSET 6692
#define PSWRQ2_REG_CDUT_VF_BLOCKS_RT_OFFSET 6693
#define PSWRQ2_REG_CDUC_VF_BLOCKS_RT_OFFSET 6694
#define PSWRQ2_REG_TM_BLOCKS_FACTOR_RT_OFFSET 6695
#define PSWRQ2_REG_CDUT_BLOCKS_FACTOR_RT_OFFSET 6696
#define PSWRQ2_REG_CDUC_BLOCKS_FACTOR_RT_OFFSET 6697
#define PSWRQ2_REG_VF_BASE_RT_OFFSET 6698
#define PSWRQ2_REG_VF_LAST_ILT_RT_OFFSET 6699
#define PSWRQ2_REG_WR_MBS0_RT_OFFSET 6700
#define PSWRQ2_REG_RD_MBS0_RT_OFFSET 6701
#define PSWRQ2_REG_DRAM_ALIGN_WR_RT_OFFSET 6702
#define PSWRQ2_REG_DRAM_ALIGN_RD_RT_OFFSET 6703
#define PSWRQ2_REG_ILT_MEMORY_RT_OFFSET 6704
#define PSWRQ2_REG_ILT_MEMORY_RT_SIZE 22000
#define PGLUE_REG_B_VF_BASE_RT_OFFSET 28704
#define PGLUE_REG_B_CACHE_LINE_SIZE_RT_OFFSET 28705
#define PGLUE_REG_B_PF_BAR0_SIZE_RT_OFFSET 28706
#define PGLUE_REG_B_PF_BAR1_SIZE_RT_OFFSET 28707
#define PGLUE_REG_B_VF_BAR1_SIZE_RT_OFFSET 28708
#define TM_REG_VF_ENABLE_CONN_RT_OFFSET 28709
#define TM_REG_PF_ENABLE_CONN_RT_OFFSET 28710
#define TM_REG_PF_ENABLE_TASK_RT_OFFSET 28711
#define TM_REG_GROUP_SIZE_RESOLUTION_CONN_RT_OFFSET 28712
#define TM_REG_GROUP_SIZE_RESOLUTION_TASK_RT_OFFSET 28713
#define TM_REG_CONFIG_CONN_MEM_RT_OFFSET 28714
#define TM_REG_CONFIG_CONN_MEM_RT_SIZE 416
#define TM_REG_CONFIG_TASK_MEM_RT_OFFSET 29130
#define TM_REG_CONFIG_TASK_MEM_RT_SIZE 512
#define QM_REG_MAXPQSIZE_0_RT_OFFSET 29642
#define QM_REG_MAXPQSIZE_1_RT_OFFSET 29643
#define QM_REG_MAXPQSIZE_2_RT_OFFSET 29644
#define QM_REG_MAXPQSIZETXSEL_0_RT_OFFSET 29645
#define QM_REG_MAXPQSIZETXSEL_1_RT_OFFSET 29646
#define QM_REG_MAXPQSIZETXSEL_2_RT_OFFSET 29647
#define QM_REG_MAXPQSIZETXSEL_3_RT_OFFSET 29648
#define QM_REG_MAXPQSIZETXSEL_4_RT_OFFSET 29649
#define QM_REG_MAXPQSIZETXSEL_5_RT_OFFSET 29650
#define QM_REG_MAXPQSIZETXSEL_6_RT_OFFSET 29651
#define QM_REG_MAXPQSIZETXSEL_7_RT_OFFSET 29652
#define QM_REG_MAXPQSIZETXSEL_8_RT_OFFSET 29653
#define QM_REG_MAXPQSIZETXSEL_9_RT_OFFSET 29654
#define QM_REG_MAXPQSIZETXSEL_10_RT_OFFSET 29655
#define QM_REG_MAXPQSIZETXSEL_11_RT_OFFSET 29656
#define QM_REG_MAXPQSIZETXSEL_12_RT_OFFSET 29657
#define QM_REG_MAXPQSIZETXSEL_13_RT_OFFSET 29658
#define QM_REG_MAXPQSIZETXSEL_14_RT_OFFSET 29659
#define QM_REG_MAXPQSIZETXSEL_15_RT_OFFSET 29660
#define QM_REG_MAXPQSIZETXSEL_16_RT_OFFSET 29661
#define QM_REG_MAXPQSIZETXSEL_17_RT_OFFSET 29662
#define QM_REG_MAXPQSIZETXSEL_18_RT_OFFSET 29663
#define QM_REG_MAXPQSIZETXSEL_19_RT_OFFSET 29664
#define QM_REG_MAXPQSIZETXSEL_20_RT_OFFSET 29665
#define QM_REG_MAXPQSIZETXSEL_21_RT_OFFSET 29666
#define QM_REG_MAXPQSIZETXSEL_22_RT_OFFSET 29667
#define QM_REG_MAXPQSIZETXSEL_23_RT_OFFSET 29668
#define QM_REG_MAXPQSIZETXSEL_24_RT_OFFSET 29669
#define QM_REG_MAXPQSIZETXSEL_25_RT_OFFSET 29670
#define QM_REG_MAXPQSIZETXSEL_26_RT_OFFSET 29671
#define QM_REG_MAXPQSIZETXSEL_27_RT_OFFSET 29672
#define QM_REG_MAXPQSIZETXSEL_28_RT_OFFSET 29673
#define QM_REG_MAXPQSIZETXSEL_29_RT_OFFSET 29674
#define QM_REG_MAXPQSIZETXSEL_30_RT_OFFSET 29675
#define QM_REG_MAXPQSIZETXSEL_31_RT_OFFSET 29676
#define QM_REG_MAXPQSIZETXSEL_32_RT_OFFSET 29677
#define QM_REG_MAXPQSIZETXSEL_33_RT_OFFSET 29678
#define QM_REG_MAXPQSIZETXSEL_34_RT_OFFSET 29679
#define QM_REG_MAXPQSIZETXSEL_35_RT_OFFSET 29680
#define QM_REG_MAXPQSIZETXSEL_36_RT_OFFSET 29681
#define QM_REG_MAXPQSIZETXSEL_37_RT_OFFSET 29682
#define QM_REG_MAXPQSIZETXSEL_38_RT_OFFSET 29683
#define QM_REG_MAXPQSIZETXSEL_39_RT_OFFSET 29684
#define QM_REG_MAXPQSIZETXSEL_40_RT_OFFSET 29685
#define QM_REG_MAXPQSIZETXSEL_41_RT_OFFSET 29686
#define QM_REG_MAXPQSIZETXSEL_42_RT_OFFSET 29687
#define QM_REG_MAXPQSIZETXSEL_43_RT_OFFSET 29688
#define QM_REG_MAXPQSIZETXSEL_44_RT_OFFSET 29689
#define QM_REG_MAXPQSIZETXSEL_45_RT_OFFSET 29690
#define QM_REG_MAXPQSIZETXSEL_46_RT_OFFSET 29691
#define QM_REG_MAXPQSIZETXSEL_47_RT_OFFSET 29692
#define QM_REG_MAXPQSIZETXSEL_48_RT_OFFSET 29693
#define QM_REG_MAXPQSIZETXSEL_49_RT_OFFSET 29694
#define QM_REG_MAXPQSIZETXSEL_50_RT_OFFSET 29695
#define QM_REG_MAXPQSIZETXSEL_51_RT_OFFSET 29696
#define QM_REG_MAXPQSIZETXSEL_52_RT_OFFSET 29697
#define QM_REG_MAXPQSIZETXSEL_53_RT_OFFSET 29698
#define QM_REG_MAXPQSIZETXSEL_54_RT_OFFSET 29699
#define QM_REG_MAXPQSIZETXSEL_55_RT_OFFSET 29700
#define QM_REG_MAXPQSIZETXSEL_56_RT_OFFSET 29701
#define QM_REG_MAXPQSIZETXSEL_57_RT_OFFSET 29702
#define QM_REG_MAXPQSIZETXSEL_58_RT_OFFSET 29703
#define QM_REG_MAXPQSIZETXSEL_59_RT_OFFSET 29704
#define QM_REG_MAXPQSIZETXSEL_60_RT_OFFSET 29705
#define QM_REG_MAXPQSIZETXSEL_61_RT_OFFSET 29706
#define QM_REG_MAXPQSIZETXSEL_62_RT_OFFSET 29707
#define QM_REG_MAXPQSIZETXSEL_63_RT_OFFSET 29708
#define QM_REG_BASEADDROTHERPQ_RT_OFFSET 29709
#define QM_REG_BASEADDROTHERPQ_RT_SIZE 128
#define QM_REG_VOQCRDLINE_RT_OFFSET 29837
#define QM_REG_VOQCRDLINE_RT_SIZE 20
#define QM_REG_VOQINITCRDLINE_RT_OFFSET 29857
#define QM_REG_VOQINITCRDLINE_RT_SIZE 20
#define QM_REG_AFULLQMBYPTHRPFWFQ_RT_OFFSET 29877
#define QM_REG_AFULLQMBYPTHRVPWFQ_RT_OFFSET 29878
#define QM_REG_AFULLQMBYPTHRPFRL_RT_OFFSET 29879
#define QM_REG_AFULLQMBYPTHRGLBLRL_RT_OFFSET 29880
#define QM_REG_AFULLOPRTNSTCCRDMASK_RT_OFFSET 29881
#define QM_REG_WRROTHERPQGRP_0_RT_OFFSET 29882
#define QM_REG_WRROTHERPQGRP_1_RT_OFFSET 29883
#define QM_REG_WRROTHERPQGRP_2_RT_OFFSET 29884
#define QM_REG_WRROTHERPQGRP_3_RT_OFFSET 29885
#define QM_REG_WRROTHERPQGRP_4_RT_OFFSET 29886
#define QM_REG_WRROTHERPQGRP_5_RT_OFFSET 29887
#define QM_REG_WRROTHERPQGRP_6_RT_OFFSET 29888
#define QM_REG_WRROTHERPQGRP_7_RT_OFFSET 29889
#define QM_REG_WRROTHERPQGRP_8_RT_OFFSET 29890
#define QM_REG_WRROTHERPQGRP_9_RT_OFFSET 29891
#define QM_REG_WRROTHERPQGRP_10_RT_OFFSET 29892
#define QM_REG_WRROTHERPQGRP_11_RT_OFFSET 29893
#define QM_REG_WRROTHERPQGRP_12_RT_OFFSET 29894
#define QM_REG_WRROTHERPQGRP_13_RT_OFFSET 29895
#define QM_REG_WRROTHERPQGRP_14_RT_OFFSET 29896
#define QM_REG_WRROTHERPQGRP_15_RT_OFFSET 29897
#define QM_REG_WRROTHERGRPWEIGHT_0_RT_OFFSET 29898
#define QM_REG_WRROTHERGRPWEIGHT_1_RT_OFFSET 29899
#define QM_REG_WRROTHERGRPWEIGHT_2_RT_OFFSET 29900
#define QM_REG_WRROTHERGRPWEIGHT_3_RT_OFFSET 29901
#define QM_REG_WRRTXGRPWEIGHT_0_RT_OFFSET 29902
#define QM_REG_WRRTXGRPWEIGHT_1_RT_OFFSET 29903
#define QM_REG_PQTX2PF_0_RT_OFFSET 29904
#define QM_REG_PQTX2PF_1_RT_OFFSET 29905
#define QM_REG_PQTX2PF_2_RT_OFFSET 29906
#define QM_REG_PQTX2PF_3_RT_OFFSET 29907
#define QM_REG_PQTX2PF_4_RT_OFFSET 29908
#define QM_REG_PQTX2PF_5_RT_OFFSET 29909
#define QM_REG_PQTX2PF_6_RT_OFFSET 29910
#define QM_REG_PQTX2PF_7_RT_OFFSET 29911
#define QM_REG_PQTX2PF_8_RT_OFFSET 29912
#define QM_REG_PQTX2PF_9_RT_OFFSET 29913
#define QM_REG_PQTX2PF_10_RT_OFFSET 29914
#define QM_REG_PQTX2PF_11_RT_OFFSET 29915
#define QM_REG_PQTX2PF_12_RT_OFFSET 29916
#define QM_REG_PQTX2PF_13_RT_OFFSET 29917
#define QM_REG_PQTX2PF_14_RT_OFFSET 29918
#define QM_REG_PQTX2PF_15_RT_OFFSET 29919
#define QM_REG_PQTX2PF_16_RT_OFFSET 29920
#define QM_REG_PQTX2PF_17_RT_OFFSET 29921
#define QM_REG_PQTX2PF_18_RT_OFFSET 29922
#define QM_REG_PQTX2PF_19_RT_OFFSET 29923
#define QM_REG_PQTX2PF_20_RT_OFFSET 29924
#define QM_REG_PQTX2PF_21_RT_OFFSET 29925
#define QM_REG_PQTX2PF_22_RT_OFFSET 29926
#define QM_REG_PQTX2PF_23_RT_OFFSET 29927
#define QM_REG_PQTX2PF_24_RT_OFFSET 29928
#define QM_REG_PQTX2PF_25_RT_OFFSET 29929
#define QM_REG_PQTX2PF_26_RT_OFFSET 29930
#define QM_REG_PQTX2PF_27_RT_OFFSET 29931
#define QM_REG_PQTX2PF_28_RT_OFFSET 29932
#define QM_REG_PQTX2PF_29_RT_OFFSET 29933
#define QM_REG_PQTX2PF_30_RT_OFFSET 29934
#define QM_REG_PQTX2PF_31_RT_OFFSET 29935
#define QM_REG_PQTX2PF_32_RT_OFFSET 29936
#define QM_REG_PQTX2PF_33_RT_OFFSET 29937
#define QM_REG_PQTX2PF_34_RT_OFFSET 29938
#define QM_REG_PQTX2PF_35_RT_OFFSET 29939
#define QM_REG_PQTX2PF_36_RT_OFFSET 29940
#define QM_REG_PQTX2PF_37_RT_OFFSET 29941
#define QM_REG_PQTX2PF_38_RT_OFFSET 29942
#define QM_REG_PQTX2PF_39_RT_OFFSET 29943
#define QM_REG_PQTX2PF_40_RT_OFFSET 29944
#define QM_REG_PQTX2PF_41_RT_OFFSET 29945
#define QM_REG_PQTX2PF_42_RT_OFFSET 29946
#define QM_REG_PQTX2PF_43_RT_OFFSET 29947
#define QM_REG_PQTX2PF_44_RT_OFFSET 29948
#define QM_REG_PQTX2PF_45_RT_OFFSET 29949
#define QM_REG_PQTX2PF_46_RT_OFFSET 29950
#define QM_REG_PQTX2PF_47_RT_OFFSET 29951
#define QM_REG_PQTX2PF_48_RT_OFFSET 29952
#define QM_REG_PQTX2PF_49_RT_OFFSET 29953
#define QM_REG_PQTX2PF_50_RT_OFFSET 29954
#define QM_REG_PQTX2PF_51_RT_OFFSET 29955
#define QM_REG_PQTX2PF_52_RT_OFFSET 29956
#define QM_REG_PQTX2PF_53_RT_OFFSET 29957
#define QM_REG_PQTX2PF_54_RT_OFFSET 29958
#define QM_REG_PQTX2PF_55_RT_OFFSET 29959
#define QM_REG_PQTX2PF_56_RT_OFFSET 29960
#define QM_REG_PQTX2PF_57_RT_OFFSET 29961
#define QM_REG_PQTX2PF_58_RT_OFFSET 29962
#define QM_REG_PQTX2PF_59_RT_OFFSET 29963
#define QM_REG_PQTX2PF_60_RT_OFFSET 29964
#define QM_REG_PQTX2PF_61_RT_OFFSET 29965
#define QM_REG_PQTX2PF_62_RT_OFFSET 29966
#define QM_REG_PQTX2PF_63_RT_OFFSET 29967
#define QM_REG_PQOTHER2PF_0_RT_OFFSET 29968
#define QM_REG_PQOTHER2PF_1_RT_OFFSET 29969
#define QM_REG_PQOTHER2PF_2_RT_OFFSET 29970
#define QM_REG_PQOTHER2PF_3_RT_OFFSET 29971
#define QM_REG_PQOTHER2PF_4_RT_OFFSET 29972
#define QM_REG_PQOTHER2PF_5_RT_OFFSET 29973
#define QM_REG_PQOTHER2PF_6_RT_OFFSET 29974
#define QM_REG_PQOTHER2PF_7_RT_OFFSET 29975
#define QM_REG_PQOTHER2PF_8_RT_OFFSET 29976
#define QM_REG_PQOTHER2PF_9_RT_OFFSET 29977
#define QM_REG_PQOTHER2PF_10_RT_OFFSET 29978
#define QM_REG_PQOTHER2PF_11_RT_OFFSET 29979
#define QM_REG_PQOTHER2PF_12_RT_OFFSET 29980
#define QM_REG_PQOTHER2PF_13_RT_OFFSET 29981
#define QM_REG_PQOTHER2PF_14_RT_OFFSET 29982
#define QM_REG_PQOTHER2PF_15_RT_OFFSET 29983
#define QM_REG_RLGLBLPERIOD_0_RT_OFFSET 29984
#define QM_REG_RLGLBLPERIOD_1_RT_OFFSET 29985
#define QM_REG_RLGLBLPERIODTIMER_0_RT_OFFSET 29986
#define QM_REG_RLGLBLPERIODTIMER_1_RT_OFFSET 29987
#define QM_REG_RLGLBLPERIODSEL_0_RT_OFFSET 29988
#define QM_REG_RLGLBLPERIODSEL_1_RT_OFFSET 29989
#define QM_REG_RLGLBLPERIODSEL_2_RT_OFFSET 29990
#define QM_REG_RLGLBLPERIODSEL_3_RT_OFFSET 29991
#define QM_REG_RLGLBLPERIODSEL_4_RT_OFFSET 29992
#define QM_REG_RLGLBLPERIODSEL_5_RT_OFFSET 29993
#define QM_REG_RLGLBLPERIODSEL_6_RT_OFFSET 29994
#define QM_REG_RLGLBLPERIODSEL_7_RT_OFFSET 29995
#define QM_REG_RLGLBLINCVAL_RT_OFFSET 29996
#define QM_REG_RLGLBLINCVAL_RT_SIZE 256
#define QM_REG_RLGLBLUPPERBOUND_RT_OFFSET 30252
#define QM_REG_RLGLBLUPPERBOUND_RT_SIZE 256
#define QM_REG_RLGLBLCRD_RT_OFFSET 30508
#define QM_REG_RLGLBLCRD_RT_SIZE 256
#define QM_REG_RLGLBLENABLE_RT_OFFSET 30764
#define QM_REG_RLPFPERIOD_RT_OFFSET 30765
#define QM_REG_RLPFPERIODTIMER_RT_OFFSET 30766
#define QM_REG_RLPFINCVAL_RT_OFFSET 30767
#define QM_REG_RLPFINCVAL_RT_SIZE 16
#define QM_REG_RLPFUPPERBOUND_RT_OFFSET 30783
#define QM_REG_RLPFUPPERBOUND_RT_SIZE 16
#define QM_REG_RLPFCRD_RT_OFFSET 30799
#define QM_REG_RLPFCRD_RT_SIZE 16
#define QM_REG_RLPFENABLE_RT_OFFSET 30815
#define QM_REG_RLPFVOQENABLE_RT_OFFSET 30816
#define QM_REG_WFQPFWEIGHT_RT_OFFSET 30817
#define QM_REG_WFQPFWEIGHT_RT_SIZE 16
#define QM_REG_WFQPFUPPERBOUND_RT_OFFSET 30833
#define QM_REG_WFQPFUPPERBOUND_RT_SIZE 16
#define QM_REG_WFQPFCRD_RT_OFFSET 30849
#define QM_REG_WFQPFCRD_RT_SIZE 160
#define QM_REG_WFQPFENABLE_RT_OFFSET 31009
#define QM_REG_WFQVPENABLE_RT_OFFSET 31010
#define QM_REG_BASEADDRTXPQ_RT_OFFSET 31011
#define QM_REG_BASEADDRTXPQ_RT_SIZE 512
#define QM_REG_TXPQMAP_RT_OFFSET 31523
#define QM_REG_TXPQMAP_RT_SIZE 512
#define QM_REG_WFQVPWEIGHT_RT_OFFSET 32035
#define QM_REG_WFQVPWEIGHT_RT_SIZE 512
#define QM_REG_WFQVPCRD_RT_OFFSET 32547
#define QM_REG_WFQVPCRD_RT_SIZE 512
#define QM_REG_WFQVPMAP_RT_OFFSET 33059
#define QM_REG_WFQVPMAP_RT_SIZE 512
#define QM_REG_WFQPFCRD_MSB_RT_OFFSET 33571
#define QM_REG_WFQPFCRD_MSB_RT_SIZE 160
#define NIG_REG_TAG_ETHERTYPE_0_RT_OFFSET 33731
#define NIG_REG_OUTER_TAG_VALUE_LIST0_RT_OFFSET 33732
#define NIG_REG_OUTER_TAG_VALUE_LIST1_RT_OFFSET 33733
#define NIG_REG_OUTER_TAG_VALUE_LIST2_RT_OFFSET 33734
#define NIG_REG_OUTER_TAG_VALUE_LIST3_RT_OFFSET 33735
#define NIG_REG_OUTER_TAG_VALUE_MASK_RT_OFFSET 33736
#define NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE_RT_OFFSET 33737
#define NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET 33738
#define NIG_REG_LLH_FUNC_TAG_EN_RT_SIZE 4
#define NIG_REG_LLH_FUNC_TAG_HDR_SEL_RT_OFFSET 33742
#define NIG_REG_LLH_FUNC_TAG_HDR_SEL_RT_SIZE 4
#define NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET 33746
#define NIG_REG_LLH_FUNC_TAG_VALUE_RT_SIZE 4
#define NIG_REG_LLH_FUNC_NO_TAG_RT_OFFSET 33750
#define NIG_REG_LLH_FUNC_FILTER_VALUE_RT_OFFSET 33751
#define NIG_REG_LLH_FUNC_FILTER_VALUE_RT_SIZE 32
#define NIG_REG_LLH_FUNC_FILTER_EN_RT_OFFSET 33783
#define NIG_REG_LLH_FUNC_FILTER_EN_RT_SIZE 16
#define NIG_REG_LLH_FUNC_FILTER_MODE_RT_OFFSET 33799
#define NIG_REG_LLH_FUNC_FILTER_MODE_RT_SIZE 16
#define NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_RT_OFFSET 33815
#define NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_RT_SIZE 16
#define NIG_REG_LLH_FUNC_FILTER_HDR_SEL_RT_OFFSET 33831
#define NIG_REG_LLH_FUNC_FILTER_HDR_SEL_RT_SIZE 16
#define NIG_REG_TX_EDPM_CTRL_RT_OFFSET 33847
#define NIG_REG_ROCE_DUPLICATE_TO_HOST_RT_OFFSET 33848
#define CDU_REG_CID_ADDR_PARAMS_RT_OFFSET 33849
#define CDU_REG_SEGMENT0_PARAMS_RT_OFFSET 33850
#define CDU_REG_SEGMENT1_PARAMS_RT_OFFSET 33851
#define CDU_REG_PF_SEG0_TYPE_OFFSET_RT_OFFSET 33852
#define CDU_REG_PF_SEG1_TYPE_OFFSET_RT_OFFSET 33853
#define CDU_REG_PF_SEG2_TYPE_OFFSET_RT_OFFSET 33854
#define CDU_REG_PF_SEG3_TYPE_OFFSET_RT_OFFSET 33855
#define CDU_REG_PF_FL_SEG0_TYPE_OFFSET_RT_OFFSET 33856
#define CDU_REG_PF_FL_SEG1_TYPE_OFFSET_RT_OFFSET 33857
#define CDU_REG_PF_FL_SEG2_TYPE_OFFSET_RT_OFFSET 33858
#define CDU_REG_PF_FL_SEG3_TYPE_OFFSET_RT_OFFSET 33859
#define CDU_REG_VF_SEG_TYPE_OFFSET_RT_OFFSET 33860
#define CDU_REG_VF_FL_SEG_TYPE_OFFSET_RT_OFFSET 33861
#define PBF_REG_TAG_ETHERTYPE_0_RT_OFFSET 33862
#define PBF_REG_BTB_SHARED_AREA_SIZE_RT_OFFSET 33863
#define PBF_REG_YCMD_QS_NUM_LINES_VOQ0_RT_OFFSET 33864
#define PBF_REG_BTB_GUARANTEED_VOQ0_RT_OFFSET 33865
#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ0_RT_OFFSET 33866
#define PBF_REG_YCMD_QS_NUM_LINES_VOQ1_RT_OFFSET 33867
#define PBF_REG_BTB_GUARANTEED_VOQ1_RT_OFFSET 33868
#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ1_RT_OFFSET 33869
#define PBF_REG_YCMD_QS_NUM_LINES_VOQ2_RT_OFFSET 33870
#define PBF_REG_BTB_GUARANTEED_VOQ2_RT_OFFSET 33871
#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ2_RT_OFFSET 33872
#define PBF_REG_YCMD_QS_NUM_LINES_VOQ3_RT_OFFSET 33873
#define PBF_REG_BTB_GUARANTEED_VOQ3_RT_OFFSET 33874
#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ3_RT_OFFSET 33875
#define PBF_REG_YCMD_QS_NUM_LINES_VOQ4_RT_OFFSET 33876
#define PBF_REG_BTB_GUARANTEED_VOQ4_RT_OFFSET 33877
#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ4_RT_OFFSET 33878
#define PBF_REG_YCMD_QS_NUM_LINES_VOQ5_RT_OFFSET 33879
#define PBF_REG_BTB_GUARANTEED_VOQ5_RT_OFFSET 33880
#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ5_RT_OFFSET 33881
#define PBF_REG_YCMD_QS_NUM_LINES_VOQ6_RT_OFFSET 33882
#define PBF_REG_BTB_GUARANTEED_VOQ6_RT_OFFSET 33883
#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ6_RT_OFFSET 33884
#define PBF_REG_YCMD_QS_NUM_LINES_VOQ7_RT_OFFSET 33885
#define PBF_REG_BTB_GUARANTEED_VOQ7_RT_OFFSET 33886
#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ7_RT_OFFSET 33887
#define PBF_REG_YCMD_QS_NUM_LINES_VOQ8_RT_OFFSET 33888
#define PBF_REG_BTB_GUARANTEED_VOQ8_RT_OFFSET 33889
#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ8_RT_OFFSET 33890
#define PBF_REG_YCMD_QS_NUM_LINES_VOQ9_RT_OFFSET 33891
#define PBF_REG_BTB_GUARANTEED_VOQ9_RT_OFFSET 33892
#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ9_RT_OFFSET 33893
#define PBF_REG_YCMD_QS_NUM_LINES_VOQ10_RT_OFFSET 33894
#define PBF_REG_BTB_GUARANTEED_VOQ10_RT_OFFSET 33895
#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ10_RT_OFFSET 33896
#define PBF_REG_YCMD_QS_NUM_LINES_VOQ11_RT_OFFSET 33897
#define PBF_REG_BTB_GUARANTEED_VOQ11_RT_OFFSET 33898
#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ11_RT_OFFSET 33899
#define PBF_REG_YCMD_QS_NUM_LINES_VOQ12_RT_OFFSET 33900
#define PBF_REG_BTB_GUARANTEED_VOQ12_RT_OFFSET 33901
#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ12_RT_OFFSET 33902
#define PBF_REG_YCMD_QS_NUM_LINES_VOQ13_RT_OFFSET 33903
#define PBF_REG_BTB_GUARANTEED_VOQ13_RT_OFFSET 33904
#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ13_RT_OFFSET 33905
#define PBF_REG_YCMD_QS_NUM_LINES_VOQ14_RT_OFFSET 33906
#define PBF_REG_BTB_GUARANTEED_VOQ14_RT_OFFSET 33907
#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ14_RT_OFFSET 33908
#define PBF_REG_YCMD_QS_NUM_LINES_VOQ15_RT_OFFSET 33909
#define PBF_REG_BTB_GUARANTEED_VOQ15_RT_OFFSET 33910
#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ15_RT_OFFSET 33911
#define PBF_REG_YCMD_QS_NUM_LINES_VOQ16_RT_OFFSET 33912
#define PBF_REG_BTB_GUARANTEED_VOQ16_RT_OFFSET 33913
#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ16_RT_OFFSET 33914
#define PBF_REG_YCMD_QS_NUM_LINES_VOQ17_RT_OFFSET 33915
#define PBF_REG_BTB_GUARANTEED_VOQ17_RT_OFFSET 33916
#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ17_RT_OFFSET 33917
#define PBF_REG_YCMD_QS_NUM_LINES_VOQ18_RT_OFFSET 33918
#define PBF_REG_BTB_GUARANTEED_VOQ18_RT_OFFSET 33919
#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ18_RT_OFFSET 33920
#define PBF_REG_YCMD_QS_NUM_LINES_VOQ19_RT_OFFSET 33921
#define PBF_REG_BTB_GUARANTEED_VOQ19_RT_OFFSET 33922
#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ19_RT_OFFSET 33923
#define XCM_REG_CON_PHY_Q3_RT_OFFSET 33924
#define RUNTIME_ARRAY_SIZE 33925
#define DORQ_REG_PF_MAX_ICID_0_RT_OFFSET 0
#define DORQ_REG_PF_MAX_ICID_1_RT_OFFSET 1
#define DORQ_REG_PF_MAX_ICID_2_RT_OFFSET 2
#define DORQ_REG_PF_MAX_ICID_3_RT_OFFSET 3
#define DORQ_REG_PF_MAX_ICID_4_RT_OFFSET 4
#define DORQ_REG_PF_MAX_ICID_5_RT_OFFSET 5
#define DORQ_REG_PF_MAX_ICID_6_RT_OFFSET 6
#define DORQ_REG_PF_MAX_ICID_7_RT_OFFSET 7
#define DORQ_REG_VF_MAX_ICID_0_RT_OFFSET 8
#define DORQ_REG_VF_MAX_ICID_1_RT_OFFSET 9
#define DORQ_REG_VF_MAX_ICID_2_RT_OFFSET 10
#define DORQ_REG_VF_MAX_ICID_3_RT_OFFSET 11
#define DORQ_REG_VF_MAX_ICID_4_RT_OFFSET 12
#define DORQ_REG_VF_MAX_ICID_5_RT_OFFSET 13
#define DORQ_REG_VF_MAX_ICID_6_RT_OFFSET 14
#define DORQ_REG_VF_MAX_ICID_7_RT_OFFSET 15
#define DORQ_REG_PF_WAKE_ALL_RT_OFFSET 16
#define DORQ_REG_TAG1_ETHERTYPE_RT_OFFSET 17
#define IGU_REG_PF_CONFIGURATION_RT_OFFSET 18
#define IGU_REG_VF_CONFIGURATION_RT_OFFSET 19
#define IGU_REG_ATTN_MSG_ADDR_L_RT_OFFSET 20
#define IGU_REG_ATTN_MSG_ADDR_H_RT_OFFSET 21
#define IGU_REG_LEADING_EDGE_LATCH_RT_OFFSET 22
#define IGU_REG_TRAILING_EDGE_LATCH_RT_OFFSET 23
#define CAU_REG_CQE_AGG_UNIT_SIZE_RT_OFFSET 24
#define CAU_REG_SB_VAR_MEMORY_RT_OFFSET 761
#define CAU_REG_SB_VAR_MEMORY_RT_SIZE 736
#define CAU_REG_SB_VAR_MEMORY_RT_OFFSET 761
#define CAU_REG_SB_VAR_MEMORY_RT_SIZE 736
#define CAU_REG_SB_ADDR_MEMORY_RT_OFFSET 1497
#define CAU_REG_SB_ADDR_MEMORY_RT_SIZE 736
#define CAU_REG_PI_MEMORY_RT_OFFSET 2233
#define CAU_REG_PI_MEMORY_RT_SIZE 4416
#define PRS_REG_SEARCH_RESP_INITIATOR_TYPE_RT_OFFSET 6649
#define PRS_REG_TASK_ID_MAX_INITIATOR_PF_RT_OFFSET 6650
#define PRS_REG_TASK_ID_MAX_INITIATOR_VF_RT_OFFSET 6651
#define PRS_REG_TASK_ID_MAX_TARGET_PF_RT_OFFSET 6652
#define PRS_REG_TASK_ID_MAX_TARGET_VF_RT_OFFSET 6653
#define PRS_REG_SEARCH_TCP_RT_OFFSET 6654
#define PRS_REG_SEARCH_FCOE_RT_OFFSET 6655
#define PRS_REG_SEARCH_ROCE_RT_OFFSET 6656
#define PRS_REG_ROCE_DEST_QP_MAX_VF_RT_OFFSET 6657
#define PRS_REG_ROCE_DEST_QP_MAX_PF_RT_OFFSET 6658
#define PRS_REG_SEARCH_OPENFLOW_RT_OFFSET 6659
#define PRS_REG_SEARCH_NON_IP_AS_OPENFLOW_RT_OFFSET 6660
#define PRS_REG_OPENFLOW_SUPPORT_ONLY_KNOWN_OVER_IP_RT_OFFSET 6661
#define PRS_REG_OPENFLOW_SEARCH_KEY_MASK_RT_OFFSET 6662
#define PRS_REG_TAG_ETHERTYPE_0_RT_OFFSET 6663
#define PRS_REG_LIGHT_L2_ETHERTYPE_EN_RT_OFFSET 6664
#define SRC_REG_FIRSTFREE_RT_OFFSET 6665
#define SRC_REG_FIRSTFREE_RT_SIZE 2
#define SRC_REG_LASTFREE_RT_OFFSET 6667
#define SRC_REG_LASTFREE_RT_SIZE 2
#define SRC_REG_COUNTFREE_RT_OFFSET 6669
#define SRC_REG_NUMBER_HASH_BITS_RT_OFFSET 6670
#define PSWRQ2_REG_CDUT_P_SIZE_RT_OFFSET 6671
#define PSWRQ2_REG_CDUC_P_SIZE_RT_OFFSET 6672
#define PSWRQ2_REG_TM_P_SIZE_RT_OFFSET 6673
#define PSWRQ2_REG_QM_P_SIZE_RT_OFFSET 6674
#define PSWRQ2_REG_SRC_P_SIZE_RT_OFFSET 6675
#define PSWRQ2_REG_TSDM_P_SIZE_RT_OFFSET 6676
#define PSWRQ2_REG_TM_FIRST_ILT_RT_OFFSET 6677
#define PSWRQ2_REG_TM_LAST_ILT_RT_OFFSET 6678
#define PSWRQ2_REG_QM_FIRST_ILT_RT_OFFSET 6679
#define PSWRQ2_REG_QM_LAST_ILT_RT_OFFSET 6680
#define PSWRQ2_REG_SRC_FIRST_ILT_RT_OFFSET 6681
#define PSWRQ2_REG_SRC_LAST_ILT_RT_OFFSET 6682
#define PSWRQ2_REG_CDUC_FIRST_ILT_RT_OFFSET 6683
#define PSWRQ2_REG_CDUC_LAST_ILT_RT_OFFSET 6684
#define PSWRQ2_REG_CDUT_FIRST_ILT_RT_OFFSET 6685
#define PSWRQ2_REG_CDUT_LAST_ILT_RT_OFFSET 6686
#define PSWRQ2_REG_TSDM_FIRST_ILT_RT_OFFSET 6687
#define PSWRQ2_REG_TSDM_LAST_ILT_RT_OFFSET 6688
#define PSWRQ2_REG_TM_NUMBER_OF_PF_BLOCKS_RT_OFFSET 6689
#define PSWRQ2_REG_CDUT_NUMBER_OF_PF_BLOCKS_RT_OFFSET 6690
#define PSWRQ2_REG_CDUC_NUMBER_OF_PF_BLOCKS_RT_OFFSET 6691
#define PSWRQ2_REG_TM_VF_BLOCKS_RT_OFFSET 6692
#define PSWRQ2_REG_CDUT_VF_BLOCKS_RT_OFFSET 6693
#define PSWRQ2_REG_CDUC_VF_BLOCKS_RT_OFFSET 6694
#define PSWRQ2_REG_TM_BLOCKS_FACTOR_RT_OFFSET 6695
#define PSWRQ2_REG_CDUT_BLOCKS_FACTOR_RT_OFFSET 6696
#define PSWRQ2_REG_CDUC_BLOCKS_FACTOR_RT_OFFSET 6697
#define PSWRQ2_REG_VF_BASE_RT_OFFSET 6698
#define PSWRQ2_REG_VF_LAST_ILT_RT_OFFSET 6699
#define PSWRQ2_REG_WR_MBS0_RT_OFFSET 6700
#define PSWRQ2_REG_RD_MBS0_RT_OFFSET 6701
#define PSWRQ2_REG_DRAM_ALIGN_WR_RT_OFFSET 6702
#define PSWRQ2_REG_DRAM_ALIGN_RD_RT_OFFSET 6703
#define PSWRQ2_REG_ILT_MEMORY_RT_OFFSET 6704
#define PSWRQ2_REG_ILT_MEMORY_RT_SIZE 22000
#define PGLUE_REG_B_VF_BASE_RT_OFFSET 28704
#define PGLUE_REG_B_MSDM_OFFSET_MASK_B_RT_OFFSET 28705
#define PGLUE_REG_B_MSDM_VF_SHIFT_B_RT_OFFSET 28706
#define PGLUE_REG_B_CACHE_LINE_SIZE_RT_OFFSET 28707
#define PGLUE_REG_B_PF_BAR0_SIZE_RT_OFFSET 28708
#define PGLUE_REG_B_PF_BAR1_SIZE_RT_OFFSET 28709
#define PGLUE_REG_B_VF_BAR1_SIZE_RT_OFFSET 28710
#define TM_REG_VF_ENABLE_CONN_RT_OFFSET 28711
#define TM_REG_PF_ENABLE_CONN_RT_OFFSET 28712
#define TM_REG_PF_ENABLE_TASK_RT_OFFSET 28713
#define TM_REG_GROUP_SIZE_RESOLUTION_CONN_RT_OFFSET 28714
#define TM_REG_GROUP_SIZE_RESOLUTION_TASK_RT_OFFSET 28715
#define TM_REG_CONFIG_CONN_MEM_RT_OFFSET 28716
#define TM_REG_CONFIG_CONN_MEM_RT_SIZE 416
#define TM_REG_CONFIG_TASK_MEM_RT_OFFSET 29132
#define TM_REG_CONFIG_TASK_MEM_RT_SIZE 512
#define QM_REG_MAXPQSIZE_0_RT_OFFSET 29644
#define QM_REG_MAXPQSIZE_1_RT_OFFSET 29645
#define QM_REG_MAXPQSIZE_2_RT_OFFSET 29646
#define QM_REG_MAXPQSIZETXSEL_0_RT_OFFSET 29647
#define QM_REG_MAXPQSIZETXSEL_1_RT_OFFSET 29648
#define QM_REG_MAXPQSIZETXSEL_2_RT_OFFSET 29649
#define QM_REG_MAXPQSIZETXSEL_3_RT_OFFSET 29650
#define QM_REG_MAXPQSIZETXSEL_4_RT_OFFSET 29651
#define QM_REG_MAXPQSIZETXSEL_5_RT_OFFSET 29652
#define QM_REG_MAXPQSIZETXSEL_6_RT_OFFSET 29653
#define QM_REG_MAXPQSIZETXSEL_7_RT_OFFSET 29654
#define QM_REG_MAXPQSIZETXSEL_8_RT_OFFSET 29655
#define QM_REG_MAXPQSIZETXSEL_9_RT_OFFSET 29656
#define QM_REG_MAXPQSIZETXSEL_10_RT_OFFSET 29657
#define QM_REG_MAXPQSIZETXSEL_11_RT_OFFSET 29658
#define QM_REG_MAXPQSIZETXSEL_12_RT_OFFSET 29659
#define QM_REG_MAXPQSIZETXSEL_13_RT_OFFSET 29660
#define QM_REG_MAXPQSIZETXSEL_14_RT_OFFSET 29661
#define QM_REG_MAXPQSIZETXSEL_15_RT_OFFSET 29662
#define QM_REG_MAXPQSIZETXSEL_16_RT_OFFSET 29663
#define QM_REG_MAXPQSIZETXSEL_17_RT_OFFSET 29664
#define QM_REG_MAXPQSIZETXSEL_18_RT_OFFSET 29665
#define QM_REG_MAXPQSIZETXSEL_19_RT_OFFSET 29666
#define QM_REG_MAXPQSIZETXSEL_20_RT_OFFSET 29667
#define QM_REG_MAXPQSIZETXSEL_21_RT_OFFSET 29668
#define QM_REG_MAXPQSIZETXSEL_22_RT_OFFSET 29669
#define QM_REG_MAXPQSIZETXSEL_23_RT_OFFSET 29670
#define QM_REG_MAXPQSIZETXSEL_24_RT_OFFSET 29671
#define QM_REG_MAXPQSIZETXSEL_25_RT_OFFSET 29672
#define QM_REG_MAXPQSIZETXSEL_26_RT_OFFSET 29673
#define QM_REG_MAXPQSIZETXSEL_27_RT_OFFSET 29674
#define QM_REG_MAXPQSIZETXSEL_28_RT_OFFSET 29675
#define QM_REG_MAXPQSIZETXSEL_29_RT_OFFSET 29676
#define QM_REG_MAXPQSIZETXSEL_30_RT_OFFSET 29677
#define QM_REG_MAXPQSIZETXSEL_31_RT_OFFSET 29678
#define QM_REG_MAXPQSIZETXSEL_32_RT_OFFSET 29679
#define QM_REG_MAXPQSIZETXSEL_33_RT_OFFSET 29680
#define QM_REG_MAXPQSIZETXSEL_34_RT_OFFSET 29681
#define QM_REG_MAXPQSIZETXSEL_35_RT_OFFSET 29682
#define QM_REG_MAXPQSIZETXSEL_36_RT_OFFSET 29683
#define QM_REG_MAXPQSIZETXSEL_37_RT_OFFSET 29684
#define QM_REG_MAXPQSIZETXSEL_38_RT_OFFSET 29685
#define QM_REG_MAXPQSIZETXSEL_39_RT_OFFSET 29686
#define QM_REG_MAXPQSIZETXSEL_40_RT_OFFSET 29687
#define QM_REG_MAXPQSIZETXSEL_41_RT_OFFSET 29688
#define QM_REG_MAXPQSIZETXSEL_42_RT_OFFSET 29689
#define QM_REG_MAXPQSIZETXSEL_43_RT_OFFSET 29690
#define QM_REG_MAXPQSIZETXSEL_44_RT_OFFSET 29691
#define QM_REG_MAXPQSIZETXSEL_45_RT_OFFSET 29692
#define QM_REG_MAXPQSIZETXSEL_46_RT_OFFSET 29693
#define QM_REG_MAXPQSIZETXSEL_47_RT_OFFSET 29694
#define QM_REG_MAXPQSIZETXSEL_48_RT_OFFSET 29695
#define QM_REG_MAXPQSIZETXSEL_49_RT_OFFSET 29696
#define QM_REG_MAXPQSIZETXSEL_50_RT_OFFSET 29697
#define QM_REG_MAXPQSIZETXSEL_51_RT_OFFSET 29698
#define QM_REG_MAXPQSIZETXSEL_52_RT_OFFSET 29699
#define QM_REG_MAXPQSIZETXSEL_53_RT_OFFSET 29700
#define QM_REG_MAXPQSIZETXSEL_54_RT_OFFSET 29701
#define QM_REG_MAXPQSIZETXSEL_55_RT_OFFSET 29702
#define QM_REG_MAXPQSIZETXSEL_56_RT_OFFSET 29703
#define QM_REG_MAXPQSIZETXSEL_57_RT_OFFSET 29704
#define QM_REG_MAXPQSIZETXSEL_58_RT_OFFSET 29705
#define QM_REG_MAXPQSIZETXSEL_59_RT_OFFSET 29706
#define QM_REG_MAXPQSIZETXSEL_60_RT_OFFSET 29707
#define QM_REG_MAXPQSIZETXSEL_61_RT_OFFSET 29708
#define QM_REG_MAXPQSIZETXSEL_62_RT_OFFSET 29709
#define QM_REG_MAXPQSIZETXSEL_63_RT_OFFSET 29710
#define QM_REG_BASEADDROTHERPQ_RT_OFFSET 29711
#define QM_REG_BASEADDROTHERPQ_RT_SIZE 128
#define QM_REG_VOQCRDLINE_RT_OFFSET 29839
#define QM_REG_VOQCRDLINE_RT_SIZE 20
#define QM_REG_VOQINITCRDLINE_RT_OFFSET 29859
#define QM_REG_VOQINITCRDLINE_RT_SIZE 20
#define QM_REG_AFULLQMBYPTHRPFWFQ_RT_OFFSET 29879
#define QM_REG_AFULLQMBYPTHRVPWFQ_RT_OFFSET 29880
#define QM_REG_AFULLQMBYPTHRPFRL_RT_OFFSET 29881
#define QM_REG_AFULLQMBYPTHRGLBLRL_RT_OFFSET 29882
#define QM_REG_AFULLOPRTNSTCCRDMASK_RT_OFFSET 29883
#define QM_REG_WRROTHERPQGRP_0_RT_OFFSET 29884
#define QM_REG_WRROTHERPQGRP_1_RT_OFFSET 29885
#define QM_REG_WRROTHERPQGRP_2_RT_OFFSET 29886
#define QM_REG_WRROTHERPQGRP_3_RT_OFFSET 29887
#define QM_REG_WRROTHERPQGRP_4_RT_OFFSET 29888
#define QM_REG_WRROTHERPQGRP_5_RT_OFFSET 29889
#define QM_REG_WRROTHERPQGRP_6_RT_OFFSET 29890
#define QM_REG_WRROTHERPQGRP_7_RT_OFFSET 29891
#define QM_REG_WRROTHERPQGRP_8_RT_OFFSET 29892
#define QM_REG_WRROTHERPQGRP_9_RT_OFFSET 29893
#define QM_REG_WRROTHERPQGRP_10_RT_OFFSET 29894
#define QM_REG_WRROTHERPQGRP_11_RT_OFFSET 29895
#define QM_REG_WRROTHERPQGRP_12_RT_OFFSET 29896
#define QM_REG_WRROTHERPQGRP_13_RT_OFFSET 29897
#define QM_REG_WRROTHERPQGRP_14_RT_OFFSET 29898
#define QM_REG_WRROTHERPQGRP_15_RT_OFFSET 29899
#define QM_REG_WRROTHERGRPWEIGHT_0_RT_OFFSET 29900
#define QM_REG_WRROTHERGRPWEIGHT_1_RT_OFFSET 29901
#define QM_REG_WRROTHERGRPWEIGHT_2_RT_OFFSET 29902
#define QM_REG_WRROTHERGRPWEIGHT_3_RT_OFFSET 29903
#define QM_REG_WRRTXGRPWEIGHT_0_RT_OFFSET 29904
#define QM_REG_WRRTXGRPWEIGHT_1_RT_OFFSET 29905
#define QM_REG_PQTX2PF_0_RT_OFFSET 29906
#define QM_REG_PQTX2PF_1_RT_OFFSET 29907
#define QM_REG_PQTX2PF_2_RT_OFFSET 29908
#define QM_REG_PQTX2PF_3_RT_OFFSET 29909
#define QM_REG_PQTX2PF_4_RT_OFFSET 29910
#define QM_REG_PQTX2PF_5_RT_OFFSET 29911
#define QM_REG_PQTX2PF_6_RT_OFFSET 29912
#define QM_REG_PQTX2PF_7_RT_OFFSET 29913
#define QM_REG_PQTX2PF_8_RT_OFFSET 29914
#define QM_REG_PQTX2PF_9_RT_OFFSET 29915
#define QM_REG_PQTX2PF_10_RT_OFFSET 29916
#define QM_REG_PQTX2PF_11_RT_OFFSET 29917
#define QM_REG_PQTX2PF_12_RT_OFFSET 29918
#define QM_REG_PQTX2PF_13_RT_OFFSET 29919
#define QM_REG_PQTX2PF_14_RT_OFFSET 29920
#define QM_REG_PQTX2PF_15_RT_OFFSET 29921
#define QM_REG_PQTX2PF_16_RT_OFFSET 29922
#define QM_REG_PQTX2PF_17_RT_OFFSET 29923
#define QM_REG_PQTX2PF_18_RT_OFFSET 29924
#define QM_REG_PQTX2PF_19_RT_OFFSET 29925
#define QM_REG_PQTX2PF_20_RT_OFFSET 29926
#define QM_REG_PQTX2PF_21_RT_OFFSET 29927
#define QM_REG_PQTX2PF_22_RT_OFFSET 29928
#define QM_REG_PQTX2PF_23_RT_OFFSET 29929
#define QM_REG_PQTX2PF_24_RT_OFFSET 29930
#define QM_REG_PQTX2PF_25_RT_OFFSET 29931
#define QM_REG_PQTX2PF_26_RT_OFFSET 29932
#define QM_REG_PQTX2PF_27_RT_OFFSET 29933
#define QM_REG_PQTX2PF_28_RT_OFFSET 29934
#define QM_REG_PQTX2PF_29_RT_OFFSET 29935
#define QM_REG_PQTX2PF_30_RT_OFFSET 29936
#define QM_REG_PQTX2PF_31_RT_OFFSET 29937
#define QM_REG_PQTX2PF_32_RT_OFFSET 29938
#define QM_REG_PQTX2PF_33_RT_OFFSET 29939
#define QM_REG_PQTX2PF_34_RT_OFFSET 29940
#define QM_REG_PQTX2PF_35_RT_OFFSET 29941
#define QM_REG_PQTX2PF_36_RT_OFFSET 29942
#define QM_REG_PQTX2PF_37_RT_OFFSET 29943
#define QM_REG_PQTX2PF_38_RT_OFFSET 29944
#define QM_REG_PQTX2PF_39_RT_OFFSET 29945
#define QM_REG_PQTX2PF_40_RT_OFFSET 29946
#define QM_REG_PQTX2PF_41_RT_OFFSET 29947
#define QM_REG_PQTX2PF_42_RT_OFFSET 29948
#define QM_REG_PQTX2PF_43_RT_OFFSET 29949
#define QM_REG_PQTX2PF_44_RT_OFFSET 29950
#define QM_REG_PQTX2PF_45_RT_OFFSET 29951
#define QM_REG_PQTX2PF_46_RT_OFFSET 29952
#define QM_REG_PQTX2PF_47_RT_OFFSET 29953
#define QM_REG_PQTX2PF_48_RT_OFFSET 29954
#define QM_REG_PQTX2PF_49_RT_OFFSET 29955
#define QM_REG_PQTX2PF_50_RT_OFFSET 29956
#define QM_REG_PQTX2PF_51_RT_OFFSET 29957
#define QM_REG_PQTX2PF_52_RT_OFFSET 29958
#define QM_REG_PQTX2PF_53_RT_OFFSET 29959
#define QM_REG_PQTX2PF_54_RT_OFFSET 29960
#define QM_REG_PQTX2PF_55_RT_OFFSET 29961
#define QM_REG_PQTX2PF_56_RT_OFFSET 29962
#define QM_REG_PQTX2PF_57_RT_OFFSET 29963
#define QM_REG_PQTX2PF_58_RT_OFFSET 29964
#define QM_REG_PQTX2PF_59_RT_OFFSET 29965
#define QM_REG_PQTX2PF_60_RT_OFFSET 29966
#define QM_REG_PQTX2PF_61_RT_OFFSET 29967
#define QM_REG_PQTX2PF_62_RT_OFFSET 29968
#define QM_REG_PQTX2PF_63_RT_OFFSET 29969
#define QM_REG_PQOTHER2PF_0_RT_OFFSET 29970
#define QM_REG_PQOTHER2PF_1_RT_OFFSET 29971
#define QM_REG_PQOTHER2PF_2_RT_OFFSET 29972
#define QM_REG_PQOTHER2PF_3_RT_OFFSET 29973
#define QM_REG_PQOTHER2PF_4_RT_OFFSET 29974
#define QM_REG_PQOTHER2PF_5_RT_OFFSET 29975
#define QM_REG_PQOTHER2PF_6_RT_OFFSET 29976
#define QM_REG_PQOTHER2PF_7_RT_OFFSET 29977
#define QM_REG_PQOTHER2PF_8_RT_OFFSET 29978
#define QM_REG_PQOTHER2PF_9_RT_OFFSET 29979
#define QM_REG_PQOTHER2PF_10_RT_OFFSET 29980
#define QM_REG_PQOTHER2PF_11_RT_OFFSET 29981
#define QM_REG_PQOTHER2PF_12_RT_OFFSET 29982
#define QM_REG_PQOTHER2PF_13_RT_OFFSET 29983
#define QM_REG_PQOTHER2PF_14_RT_OFFSET 29984
#define QM_REG_PQOTHER2PF_15_RT_OFFSET 29985
#define QM_REG_RLGLBLPERIOD_0_RT_OFFSET 29986
#define QM_REG_RLGLBLPERIOD_1_RT_OFFSET 29987
#define QM_REG_RLGLBLPERIODTIMER_0_RT_OFFSET 29988
#define QM_REG_RLGLBLPERIODTIMER_1_RT_OFFSET 29989
#define QM_REG_RLGLBLPERIODSEL_0_RT_OFFSET 29990
#define QM_REG_RLGLBLPERIODSEL_1_RT_OFFSET 29991
#define QM_REG_RLGLBLPERIODSEL_2_RT_OFFSET 29992
#define QM_REG_RLGLBLPERIODSEL_3_RT_OFFSET 29993
#define QM_REG_RLGLBLPERIODSEL_4_RT_OFFSET 29994
#define QM_REG_RLGLBLPERIODSEL_5_RT_OFFSET 29995
#define QM_REG_RLGLBLPERIODSEL_6_RT_OFFSET 29996
#define QM_REG_RLGLBLPERIODSEL_7_RT_OFFSET 29997
#define QM_REG_RLGLBLINCVAL_RT_OFFSET 29998
#define QM_REG_RLGLBLINCVAL_RT_SIZE 256
#define QM_REG_RLGLBLUPPERBOUND_RT_OFFSET 30254
#define QM_REG_RLGLBLUPPERBOUND_RT_SIZE 256
#define QM_REG_RLGLBLCRD_RT_OFFSET 30510
#define QM_REG_RLGLBLCRD_RT_SIZE 256
#define QM_REG_RLGLBLENABLE_RT_OFFSET 30766
#define QM_REG_RLPFPERIOD_RT_OFFSET 30767
#define QM_REG_RLPFPERIODTIMER_RT_OFFSET 30768
#define QM_REG_RLPFINCVAL_RT_OFFSET 30769
#define QM_REG_RLPFINCVAL_RT_SIZE 16
#define QM_REG_RLPFUPPERBOUND_RT_OFFSET 30785
#define QM_REG_RLPFUPPERBOUND_RT_SIZE 16
#define QM_REG_RLPFCRD_RT_OFFSET 30801
#define QM_REG_RLPFCRD_RT_SIZE 16
#define QM_REG_RLPFENABLE_RT_OFFSET 30817
#define QM_REG_RLPFVOQENABLE_RT_OFFSET 30818
#define QM_REG_WFQPFWEIGHT_RT_OFFSET 30819
#define QM_REG_WFQPFWEIGHT_RT_SIZE 16
#define QM_REG_WFQPFUPPERBOUND_RT_OFFSET 30835
#define QM_REG_WFQPFUPPERBOUND_RT_SIZE 16
#define QM_REG_WFQPFCRD_RT_OFFSET 30851
#define QM_REG_WFQPFCRD_RT_SIZE 160
#define QM_REG_WFQPFENABLE_RT_OFFSET 31011
#define QM_REG_WFQVPENABLE_RT_OFFSET 31012
#define QM_REG_BASEADDRTXPQ_RT_OFFSET 31013
#define QM_REG_BASEADDRTXPQ_RT_SIZE 512
#define QM_REG_TXPQMAP_RT_OFFSET 31525
#define QM_REG_TXPQMAP_RT_SIZE 512
#define QM_REG_WFQVPWEIGHT_RT_OFFSET 32037
#define QM_REG_WFQVPWEIGHT_RT_SIZE 512
#define QM_REG_WFQVPCRD_RT_OFFSET 32549
#define QM_REG_WFQVPCRD_RT_SIZE 512
#define QM_REG_WFQVPMAP_RT_OFFSET 33061
#define QM_REG_WFQVPMAP_RT_SIZE 512
#define QM_REG_WFQPFCRD_MSB_RT_OFFSET 33573
#define QM_REG_WFQPFCRD_MSB_RT_SIZE 160
#define NIG_REG_TAG_ETHERTYPE_0_RT_OFFSET 33733
#define NIG_REG_OUTER_TAG_VALUE_LIST0_RT_OFFSET 33734
#define NIG_REG_OUTER_TAG_VALUE_LIST1_RT_OFFSET 33735
#define NIG_REG_OUTER_TAG_VALUE_LIST2_RT_OFFSET 33736
#define NIG_REG_OUTER_TAG_VALUE_LIST3_RT_OFFSET 33737
#define NIG_REG_OUTER_TAG_VALUE_MASK_RT_OFFSET 33738
#define NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE_RT_OFFSET 33739
#define NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET 33740
#define NIG_REG_LLH_FUNC_TAG_EN_RT_SIZE 4
#define NIG_REG_LLH_FUNC_TAG_HDR_SEL_RT_OFFSET 33744
#define NIG_REG_LLH_FUNC_TAG_HDR_SEL_RT_SIZE 4
#define NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET 33748
#define NIG_REG_LLH_FUNC_TAG_VALUE_RT_SIZE 4
#define NIG_REG_LLH_FUNC_NO_TAG_RT_OFFSET 33752
#define NIG_REG_LLH_FUNC_FILTER_VALUE_RT_OFFSET 33753
#define NIG_REG_LLH_FUNC_FILTER_VALUE_RT_SIZE 32
#define NIG_REG_LLH_FUNC_FILTER_EN_RT_OFFSET 33785
#define NIG_REG_LLH_FUNC_FILTER_EN_RT_SIZE 16
#define NIG_REG_LLH_FUNC_FILTER_MODE_RT_OFFSET 33801
#define NIG_REG_LLH_FUNC_FILTER_MODE_RT_SIZE 16
#define NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_RT_OFFSET 33817
#define NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_RT_SIZE 16
#define NIG_REG_LLH_FUNC_FILTER_HDR_SEL_RT_OFFSET 33833
#define NIG_REG_LLH_FUNC_FILTER_HDR_SEL_RT_SIZE 16
#define NIG_REG_TX_EDPM_CTRL_RT_OFFSET 33849
#define NIG_REG_ROCE_DUPLICATE_TO_HOST_RT_OFFSET 33850
#define CDU_REG_CID_ADDR_PARAMS_RT_OFFSET 33851
#define CDU_REG_SEGMENT0_PARAMS_RT_OFFSET 33852
#define CDU_REG_SEGMENT1_PARAMS_RT_OFFSET 33853
#define CDU_REG_PF_SEG0_TYPE_OFFSET_RT_OFFSET 33854
#define CDU_REG_PF_SEG1_TYPE_OFFSET_RT_OFFSET 33855
#define CDU_REG_PF_SEG2_TYPE_OFFSET_RT_OFFSET 33856
#define CDU_REG_PF_SEG3_TYPE_OFFSET_RT_OFFSET 33857
#define CDU_REG_PF_FL_SEG0_TYPE_OFFSET_RT_OFFSET 33858
#define CDU_REG_PF_FL_SEG1_TYPE_OFFSET_RT_OFFSET 33859
#define CDU_REG_PF_FL_SEG2_TYPE_OFFSET_RT_OFFSET 33860
#define CDU_REG_PF_FL_SEG3_TYPE_OFFSET_RT_OFFSET 33861
#define CDU_REG_VF_SEG_TYPE_OFFSET_RT_OFFSET 33862
#define CDU_REG_VF_FL_SEG_TYPE_OFFSET_RT_OFFSET 33863
#define PBF_REG_TAG_ETHERTYPE_0_RT_OFFSET 33864
#define PBF_REG_BTB_SHARED_AREA_SIZE_RT_OFFSET 33865
#define PBF_REG_YCMD_QS_NUM_LINES_VOQ0_RT_OFFSET 33866
#define PBF_REG_BTB_GUARANTEED_VOQ0_RT_OFFSET 33867
#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ0_RT_OFFSET 33868
#define PBF_REG_YCMD_QS_NUM_LINES_VOQ1_RT_OFFSET 33869
#define PBF_REG_BTB_GUARANTEED_VOQ1_RT_OFFSET 33870
#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ1_RT_OFFSET 33871
#define PBF_REG_YCMD_QS_NUM_LINES_VOQ2_RT_OFFSET 33872
#define PBF_REG_BTB_GUARANTEED_VOQ2_RT_OFFSET 33873
#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ2_RT_OFFSET 33874
#define PBF_REG_YCMD_QS_NUM_LINES_VOQ3_RT_OFFSET 33875
#define PBF_REG_BTB_GUARANTEED_VOQ3_RT_OFFSET 33876
#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ3_RT_OFFSET 33877
#define PBF_REG_YCMD_QS_NUM_LINES_VOQ4_RT_OFFSET 33878
#define PBF_REG_BTB_GUARANTEED_VOQ4_RT_OFFSET 33879
#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ4_RT_OFFSET 33880
#define PBF_REG_YCMD_QS_NUM_LINES_VOQ5_RT_OFFSET 33881
#define PBF_REG_BTB_GUARANTEED_VOQ5_RT_OFFSET 33882
#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ5_RT_OFFSET 33883
#define PBF_REG_YCMD_QS_NUM_LINES_VOQ6_RT_OFFSET 33884
#define PBF_REG_BTB_GUARANTEED_VOQ6_RT_OFFSET 33885
#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ6_RT_OFFSET 33886
#define PBF_REG_YCMD_QS_NUM_LINES_VOQ7_RT_OFFSET 33887
#define PBF_REG_BTB_GUARANTEED_VOQ7_RT_OFFSET 33888
#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ7_RT_OFFSET 33889
#define PBF_REG_YCMD_QS_NUM_LINES_VOQ8_RT_OFFSET 33890
#define PBF_REG_BTB_GUARANTEED_VOQ8_RT_OFFSET 33891
#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ8_RT_OFFSET 33892
#define PBF_REG_YCMD_QS_NUM_LINES_VOQ9_RT_OFFSET 33893
#define PBF_REG_BTB_GUARANTEED_VOQ9_RT_OFFSET 33894
#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ9_RT_OFFSET 33895
#define PBF_REG_YCMD_QS_NUM_LINES_VOQ10_RT_OFFSET 33896
#define PBF_REG_BTB_GUARANTEED_VOQ10_RT_OFFSET 33897
#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ10_RT_OFFSET 33898
#define PBF_REG_YCMD_QS_NUM_LINES_VOQ11_RT_OFFSET 33899
#define PBF_REG_BTB_GUARANTEED_VOQ11_RT_OFFSET 33900
#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ11_RT_OFFSET 33901
#define PBF_REG_YCMD_QS_NUM_LINES_VOQ12_RT_OFFSET 33902
#define PBF_REG_BTB_GUARANTEED_VOQ12_RT_OFFSET 33903
#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ12_RT_OFFSET 33904
#define PBF_REG_YCMD_QS_NUM_LINES_VOQ13_RT_OFFSET 33905
#define PBF_REG_BTB_GUARANTEED_VOQ13_RT_OFFSET 33906
#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ13_RT_OFFSET 33907
#define PBF_REG_YCMD_QS_NUM_LINES_VOQ14_RT_OFFSET 33908
#define PBF_REG_BTB_GUARANTEED_VOQ14_RT_OFFSET 33909
#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ14_RT_OFFSET 33910
#define PBF_REG_YCMD_QS_NUM_LINES_VOQ15_RT_OFFSET 33911
#define PBF_REG_BTB_GUARANTEED_VOQ15_RT_OFFSET 33912
#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ15_RT_OFFSET 33913
#define PBF_REG_YCMD_QS_NUM_LINES_VOQ16_RT_OFFSET 33914
#define PBF_REG_BTB_GUARANTEED_VOQ16_RT_OFFSET 33915
#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ16_RT_OFFSET 33916
#define PBF_REG_YCMD_QS_NUM_LINES_VOQ17_RT_OFFSET 33917
#define PBF_REG_BTB_GUARANTEED_VOQ17_RT_OFFSET 33918
#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ17_RT_OFFSET 33919
#define PBF_REG_YCMD_QS_NUM_LINES_VOQ18_RT_OFFSET 33920
#define PBF_REG_BTB_GUARANTEED_VOQ18_RT_OFFSET 33921
#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ18_RT_OFFSET 33922
#define PBF_REG_YCMD_QS_NUM_LINES_VOQ19_RT_OFFSET 33923
#define PBF_REG_BTB_GUARANTEED_VOQ19_RT_OFFSET 33924
#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ19_RT_OFFSET 33925
#define XCM_REG_CON_PHY_Q3_RT_OFFSET 33926
#define RUNTIME_ARRAY_SIZE 33927
/* The eth storm context for the Tstorm */
struct tstorm_eth_conn_st_ctx {
......@@ -3201,7 +3566,31 @@ struct eth_conn_context {
struct mstorm_eth_conn_st_ctx mstorm_st_context;
};
/* opcodes for the event ring */
enum eth_error_code {
ETH_OK = 0x00,
ETH_FILTERS_MAC_ADD_FAIL_FULL,
ETH_FILTERS_MAC_ADD_FAIL_FULL_MTT2,
ETH_FILTERS_MAC_ADD_FAIL_DUP_MTT2,
ETH_FILTERS_MAC_ADD_FAIL_DUP_STT2,
ETH_FILTERS_MAC_DEL_FAIL_NOF,
ETH_FILTERS_MAC_DEL_FAIL_NOF_MTT2,
ETH_FILTERS_MAC_DEL_FAIL_NOF_STT2,
ETH_FILTERS_MAC_ADD_FAIL_ZERO_MAC,
ETH_FILTERS_VLAN_ADD_FAIL_FULL,
ETH_FILTERS_VLAN_ADD_FAIL_DUP,
ETH_FILTERS_VLAN_DEL_FAIL_NOF,
ETH_FILTERS_VLAN_DEL_FAIL_NOF_TT1,
ETH_FILTERS_PAIR_ADD_FAIL_DUP,
ETH_FILTERS_PAIR_ADD_FAIL_FULL,
ETH_FILTERS_PAIR_ADD_FAIL_FULL_MAC,
ETH_FILTERS_PAIR_DEL_FAIL_NOF,
ETH_FILTERS_PAIR_DEL_FAIL_NOF_TT1,
ETH_FILTERS_PAIR_ADD_FAIL_ZERO_MAC,
ETH_FILTERS_VNI_ADD_FAIL_FULL,
ETH_FILTERS_VNI_ADD_FAIL_DUP,
MAX_ETH_ERROR_CODE
};
enum eth_event_opcode {
ETH_EVENT_UNUSED,
ETH_EVENT_VPORT_START,
......@@ -3269,7 +3658,13 @@ enum eth_filter_type {
MAX_ETH_FILTER_TYPE
};
/* Ethernet Ramrod Command IDs */
enum eth_ipv4_frag_type {
ETH_IPV4_NOT_FRAG,
ETH_IPV4_FIRST_FRAG,
ETH_IPV4_NON_FIRST_FRAG,
MAX_ETH_IPV4_FRAG_TYPE
};
enum eth_ramrod_cmd_id {
ETH_RAMROD_UNUSED,
ETH_RAMROD_VPORT_START,
......@@ -3451,8 +3846,8 @@ struct rx_queue_start_ramrod_data {
u8 toggle_val;
u8 vf_rx_prod_index;
u8 reserved[6];
u8 vf_rx_prod_use_zone_a;
u8 reserved[5];
__le16 reserved1;
struct regpair cqe_pbl_addr;
struct regpair bd_base;
......@@ -3526,10 +3921,11 @@ struct tx_queue_start_ramrod_data {
__le16 pxp_st_index;
__le16 comp_agg_size;
__le16 queue_zone_id;
__le16 test_dup_count;
__le16 reserved2;
__le16 pbl_size;
__le16 tx_queue_id;
__le16 same_as_last_id;
__le16 reserved[3];
struct regpair pbl_base_addr;
struct regpair bd_cons_address;
};
......@@ -4926,8 +5322,8 @@ struct roce_create_qp_resp_ramrod_data {
#define ROCE_CREATE_QP_RESP_RAMROD_DATA_SRQ_FLG_SHIFT 5
#define ROCE_CREATE_QP_RESP_RAMROD_DATA_E2E_FLOW_CONTROL_EN_MASK 0x1
#define ROCE_CREATE_QP_RESP_RAMROD_DATA_E2E_FLOW_CONTROL_EN_SHIFT 6
#define ROCE_CREATE_QP_RESP_RAMROD_DATA_RESERVED0_MASK 0x1
#define ROCE_CREATE_QP_RESP_RAMROD_DATA_RESERVED0_SHIFT 7
#define ROCE_CREATE_QP_RESP_RAMROD_DATA_RESERVED_KEY_EN_MASK 0x1
#define ROCE_CREATE_QP_RESP_RAMROD_DATA_RESERVED_KEY_EN_SHIFT 7
#define ROCE_CREATE_QP_RESP_RAMROD_DATA_PRI_MASK 0x7
#define ROCE_CREATE_QP_RESP_RAMROD_DATA_PRI_SHIFT 8
#define ROCE_CREATE_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_MASK 0x1F
......@@ -4988,6 +5384,10 @@ enum roce_event_opcode {
MAX_ROCE_EVENT_OPCODE
};
struct roce_init_func_ramrod_data {
struct rdma_init_func_ramrod_data rdma;
};
struct roce_modify_qp_req_ramrod_data {
__le16 flags;
#define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MOVE_TO_ERR_FLG_MASK 0x1
......
drivers/net/ethernet/qlogic/qed/qed_init_ops.c
View file @ 05fafbfb
......@@ -534,7 +534,7 @@ int qed_init_fw_data(struct qed_dev *cdev, const u8 *data)
/* First Dword contains metadata and should be skipped */
buf_hdr = (struct bin_buffer_hdr *)(data + sizeof(u32));
offset = buf_hdr[BIN_BUF_FW_VER_INFO].offset;
offset = buf_hdr[BIN_BUF_INIT_FW_VER_INFO].offset;
fw->fw_ver_info = (struct fw_ver_info *)(data + offset);
offset = buf_hdr[BIN_BUF_INIT_CMD].offset;
......
drivers/net/ethernet/qlogic/qed/qed_mcp.c
View file @ 05fafbfb
......@@ -802,34 +802,6 @@ static u32 qed_mcp_get_shmem_func(struct qed_hwfn *p_hwfn,
return size;
}
int qed_hw_init_first_eth(struct qed_hwfn *p_hwfn,
struct qed_ptt *p_ptt, u8 *p_pf)
{
struct public_func shmem_info;
int i;
/* Find first Ethernet interface in port */
for (i = 0; i < NUM_OF_ENG_PFS(p_hwfn->cdev);
i += p_hwfn->cdev->num_ports_in_engines) {
qed_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info,
MCP_PF_ID_BY_REL(p_hwfn, i));
if (shmem_info.config & FUNC_MF_CFG_FUNC_HIDE)
continue;
if ((shmem_info.config & FUNC_MF_CFG_PROTOCOL_MASK) ==
FUNC_MF_CFG_PROTOCOL_ETHERNET) {
*p_pf = (u8)i;
return 0;
}
}
DP_NOTICE(p_hwfn,
"Failed to find on port an ethernet interface in MF_SI mode\n");
return -EINVAL;
}
static void qed_mcp_update_bw(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
{
struct qed_mcp_function_info *p_info;
......
drivers/net/ethernet/qlogic/qed/qed_mcp.h
View file @ 05fafbfb
......@@ -500,6 +500,4 @@ int __qed_configure_pf_min_bandwidth(struct qed_hwfn *p_hwfn,
struct qed_mcp_link_state *p_link,
u8 min_bw);
int qed_hw_init_first_eth(struct qed_hwfn *p_hwfn,
struct qed_ptt *p_ptt, u8 *p_pf);
#endif
drivers/net/ethernet/qlogic/qed/qed_reg_addr.h
View file @ 05fafbfb
......@@ -116,8 +116,14 @@
0x1009c4UL
#define QM_REG_PF_EN \
0x2f2ea4UL
#define TCFC_REG_WEAK_ENABLE_VF \
0x2d0704UL
#define TCFC_REG_STRONG_ENABLE_PF \
0x2d0708UL
#define TCFC_REG_STRONG_ENABLE_VF \
0x2d070cUL
#define CCFC_REG_WEAK_ENABLE_VF \
0x2e0704UL
#define CCFC_REG_STRONG_ENABLE_PF \
0x2e0708UL
#define PGLUE_B_REG_PGL_ADDR_88_F0 \
......
drivers/net/ethernet/qlogic/qed/qed_sriov.c
View file @ 05fafbfb
......@@ -1280,6 +1280,13 @@ static void qed_iov_vf_mbx_acquire(struct qed_hwfn *p_hwfn,
memset(resp, 0, sizeof(*resp));
/* Write the PF version so that VF would know which version
* is supported - might be later overriden. This guarantees that
* VF could recognize legacy PF based on lack of versions in reply.
*/
pfdev_info->major_fp_hsi = ETH_HSI_VER_MAJOR;
pfdev_info->minor_fp_hsi = ETH_HSI_VER_MINOR;
/* Validate FW compatibility */
if (req->vfdev_info.eth_fp_hsi_major != ETH_HSI_VER_MAJOR) {
DP_INFO(p_hwfn,
......@@ -1289,12 +1296,6 @@ static void qed_iov_vf_mbx_acquire(struct qed_hwfn *p_hwfn,
req->vfdev_info.eth_fp_hsi_minor,
ETH_HSI_VER_MAJOR, ETH_HSI_VER_MINOR);
/* Write the PF version so that VF would know which version
* is supported.
*/
pfdev_info->major_fp_hsi = ETH_HSI_VER_MAJOR;
pfdev_info->minor_fp_hsi = ETH_HSI_VER_MINOR;
goto out;
}
......
drivers/net/ethernet/qlogic/qede/qede.h
View file @ 05fafbfb
......@@ -25,7 +25,7 @@
#define QEDE_MAJOR_VERSION 8
#define QEDE_MINOR_VERSION 10
#define QEDE_REVISION_VERSION 1
#define QEDE_REVISION_VERSION 9
#define QEDE_ENGINEERING_VERSION 20
#define DRV_MODULE_VERSION __stringify(QEDE_MAJOR_VERSION) "." \
__stringify(QEDE_MINOR_VERSION) "." \
......
include/linux/qed/common_hsi.h
View file @ 05fafbfb
......@@ -5,28 +5,83 @@
* (GPL) Version 2, available from the file COPYING in the main directory of
* this source tree.
*/
#ifndef _COMMON_HSI_H
#define _COMMON_HSI_H
#include <linux/types.h>
#include <asm/byteorder.h>
#include <linux/bitops.h>
#include <linux/slab.h>
/* dma_addr_t manip */
#define DMA_LO(x) ((u32)(((dma_addr_t)(x)) & 0xffffffff))
#define DMA_HI(x) ((u32)(((dma_addr_t)(x)) >> 32))
#define DMA_LO_LE(x) cpu_to_le32(DMA_LO(x))
#define DMA_HI_LE(x) cpu_to_le32(DMA_HI(x))
/* It's assumed that whoever includes this has previously included an hsi
* file defining the regpair.
*/
#define DMA_REGPAIR_LE(x, val) (x).hi = DMA_HI_LE((val)); \
(x).lo = DMA_LO_LE((val))
#define HILO_GEN(hi, lo, type) ((((type)(hi)) << 32) + (lo))
#define HILO_DMA(hi, lo) HILO_GEN(hi, lo, dma_addr_t)
#define HILO_64(hi, lo) HILO_GEN(hi, lo, u64)
#define HILO_DMA_REGPAIR(regpair) (HILO_DMA(regpair.hi, regpair.lo))
#define HILO_64_REGPAIR(regpair) (HILO_64(regpair.hi, regpair.lo))
#ifndef __COMMON_HSI__
#define __COMMON_HSI__
#define CORE_SPQE_PAGE_SIZE_BYTES 4096
#define X_FINAL_CLEANUP_AGG_INT 1
#define EVENT_RING_PAGE_SIZE_BYTES 4096
#define NUM_OF_GLOBAL_QUEUES 128
#define COMMON_QUEUE_ENTRY_MAX_BYTE_SIZE 64
#define ISCSI_CDU_TASK_SEG_TYPE 0
#define RDMA_CDU_TASK_SEG_TYPE 1
#define FW_ASSERT_GENERAL_ATTN_IDX 32
#define MAX_PINNED_CCFC 32
/* Queue Zone sizes in bytes */
#define TSTORM_QZONE_SIZE 8
#define MSTORM_QZONE_SIZE 0
#define MSTORM_QZONE_SIZE 16
#define USTORM_QZONE_SIZE 8
#define XSTORM_QZONE_SIZE 8
#define YSTORM_QZONE_SIZE 0
#define PSTORM_QZONE_SIZE 0
#define ETH_MAX_NUM_RX_QUEUES_PER_VF 16
#define MSTORM_VF_ZONE_DEFAULT_SIZE_LOG 7
#define ETH_MAX_NUM_RX_QUEUES_PER_VF_DEFAULT 16
#define ETH_MAX_NUM_RX_QUEUES_PER_VF_DOUBLE 48
#define ETH_MAX_NUM_RX_QUEUES_PER_VF_QUAD 112
/********************************/
/* CORE (LIGHT L2) FW CONSTANTS */
/********************************/
#define CORE_LL2_MAX_RAMROD_PER_CON 8
#define CORE_LL2_TX_BD_PAGE_SIZE_BYTES 4096
#define CORE_LL2_RX_BD_PAGE_SIZE_BYTES 4096
#define CORE_LL2_RX_CQE_PAGE_SIZE_BYTES 4096
#define CORE_LL2_RX_NUM_NEXT_PAGE_BDS 1
#define CORE_LL2_TX_MAX_BDS_PER_PACKET 12
#define CORE_SPQE_PAGE_SIZE_BYTES 4096
#define MAX_NUM_LL2_RX_QUEUES 32
#define MAX_NUM_LL2_TX_STATS_COUNTERS 32
#define FW_MAJOR_VERSION 8
#define FW_MINOR_VERSION 10
#define FW_REVISION_VERSION 5
#define FW_REVISION_VERSION 10
#define FW_ENGINEERING_VERSION 0
/***********************/
......@@ -83,6 +138,17 @@
#define NUM_OF_LCIDS (320)
#define NUM_OF_LTIDS (320)
/* Clock values */
#define MASTER_CLK_FREQ_E4 (375e6)
#define STORM_CLK_FREQ_E4 (1000e6)
#define CLK25M_CLK_FREQ_E4 (25e6)
/* Global PXP windows (GTT) */
#define NUM_OF_GTT 19
#define GTT_DWORD_SIZE_BITS 10
#define GTT_BYTE_SIZE_BITS (GTT_DWORD_SIZE_BITS + 2)
#define GTT_DWORD_SIZE BIT(GTT_DWORD_SIZE_BITS)
/*****************/
/* CDU CONSTANTS */
/*****************/
......@@ -90,6 +156,8 @@
#define CDU_SEG_TYPE_OFFSET_REG_TYPE_SHIFT (17)
#define CDU_SEG_TYPE_OFFSET_REG_OFFSET_MASK (0x1ffff)
#define CDU_VF_FL_SEG_TYPE_OFFSET_REG_TYPE_SHIFT (12)
#define CDU_VF_FL_SEG_TYPE_OFFSET_REG_OFFSET_MASK (0xfff)
/*****************/
/* DQ CONSTANTS */
/*****************/
......@@ -115,6 +183,11 @@
#define DQ_XCM_ETH_TX_BD_CONS_CMD DQ_XCM_AGG_VAL_SEL_WORD3
#define DQ_XCM_ETH_TX_BD_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4
#define DQ_XCM_ETH_GO_TO_BD_CONS_CMD DQ_XCM_AGG_VAL_SEL_WORD5
#define DQ_XCM_ISCSI_SQ_CONS_CMD DQ_XCM_AGG_VAL_SEL_WORD3
#define DQ_XCM_ISCSI_SQ_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4
#define DQ_XCM_ISCSI_MORE_TO_SEND_SEQ_CMD DQ_XCM_AGG_VAL_SEL_REG3
#define DQ_XCM_ISCSI_EXP_STAT_SN_CMD DQ_XCM_AGG_VAL_SEL_REG6
#define DQ_XCM_ROCE_SQ_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4
/* UCM agg val selection (HW) */
#define DQ_UCM_AGG_VAL_SEL_WORD0 0
......@@ -159,13 +232,16 @@
#define DQ_XCM_AGG_FLG_SHIFT_CF23 7
/* XCM agg counter flag selection */
#define DQ_XCM_CORE_DQ_CF_CMD (1 << DQ_XCM_AGG_FLG_SHIFT_CF18)
#define DQ_XCM_CORE_TERMINATE_CMD (1 << DQ_XCM_AGG_FLG_SHIFT_CF19)
#define DQ_XCM_CORE_SLOW_PATH_CMD (1 << DQ_XCM_AGG_FLG_SHIFT_CF22)
#define DQ_XCM_ETH_DQ_CF_CMD (1 << DQ_XCM_AGG_FLG_SHIFT_CF18)
#define DQ_XCM_ETH_TERMINATE_CMD (1 << DQ_XCM_AGG_FLG_SHIFT_CF19)
#define DQ_XCM_ETH_SLOW_PATH_CMD (1 << DQ_XCM_AGG_FLG_SHIFT_CF22)
#define DQ_XCM_ETH_TPH_EN_CMD (1 << DQ_XCM_AGG_FLG_SHIFT_CF23)
#define DQ_XCM_CORE_DQ_CF_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF18)
#define DQ_XCM_CORE_TERMINATE_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF19)
#define DQ_XCM_CORE_SLOW_PATH_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF22)
#define DQ_XCM_ETH_DQ_CF_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF18)
#define DQ_XCM_ETH_TERMINATE_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF19)
#define DQ_XCM_ETH_SLOW_PATH_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF22)
#define DQ_XCM_ETH_TPH_EN_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF23)
#define DQ_XCM_ISCSI_DQ_FLUSH_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF19)
#define DQ_XCM_ISCSI_SLOW_PATH_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF22)
#define DQ_XCM_ISCSI_PROC_ONLY_CLEANUP_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF23)
/* UCM agg counter flag selection (HW) */
#define DQ_UCM_AGG_FLG_SHIFT_CF0 0
......@@ -178,9 +254,45 @@
#define DQ_UCM_AGG_FLG_SHIFT_RULE1EN 7
/* UCM agg counter flag selection (FW) */
#define DQ_UCM_ETH_PMD_TX_ARM_CMD (1 << DQ_UCM_AGG_FLG_SHIFT_CF4)
#define DQ_UCM_ETH_PMD_RX_ARM_CMD (1 << DQ_UCM_AGG_FLG_SHIFT_CF5)
#define DQ_UCM_ETH_PMD_TX_ARM_CMD BIT(DQ_UCM_AGG_FLG_SHIFT_CF4)
#define DQ_UCM_ETH_PMD_RX_ARM_CMD BIT(DQ_UCM_AGG_FLG_SHIFT_CF5)
#define DQ_UCM_ROCE_CQ_ARM_SE_CF_CMD BIT(DQ_UCM_AGG_FLG_SHIFT_CF4)
#define DQ_UCM_ROCE_CQ_ARM_CF_CMD BIT(DQ_UCM_AGG_FLG_SHIFT_CF5)
/* TCM agg counter flag selection (HW) */
#define DQ_TCM_AGG_FLG_SHIFT_CF0 0
#define DQ_TCM_AGG_FLG_SHIFT_CF1 1
#define DQ_TCM_AGG_FLG_SHIFT_CF2 2
#define DQ_TCM_AGG_FLG_SHIFT_CF3 3
#define DQ_TCM_AGG_FLG_SHIFT_CF4 4
#define DQ_TCM_AGG_FLG_SHIFT_CF5 5
#define DQ_TCM_AGG_FLG_SHIFT_CF6 6
#define DQ_TCM_AGG_FLG_SHIFT_CF7 7
/* TCM agg counter flag selection (FW) */
#define DQ_TCM_ISCSI_FLUSH_Q0_CMD BIT(DQ_TCM_AGG_FLG_SHIFT_CF1)
#define DQ_TCM_ISCSI_TIMER_STOP_ALL_CMD BIT(DQ_TCM_AGG_FLG_SHIFT_CF3)
/* PWM address mapping */
#define DQ_PWM_OFFSET_DPM_BASE 0x0
#define DQ_PWM_OFFSET_DPM_END 0x27
#define DQ_PWM_OFFSET_XCM16_BASE 0x40
#define DQ_PWM_OFFSET_XCM32_BASE 0x44
#define DQ_PWM_OFFSET_UCM16_BASE 0x48
#define DQ_PWM_OFFSET_UCM32_BASE 0x4C
#define DQ_PWM_OFFSET_UCM16_4 0x50
#define DQ_PWM_OFFSET_TCM16_BASE 0x58
#define DQ_PWM_OFFSET_TCM32_BASE 0x5C
#define DQ_PWM_OFFSET_XCM_FLAGS 0x68
#define DQ_PWM_OFFSET_UCM_FLAGS 0x69
#define DQ_PWM_OFFSET_TCM_FLAGS 0x6B
#define DQ_PWM_OFFSET_XCM_RDMA_SQ_PROD (DQ_PWM_OFFSET_XCM16_BASE + 2)
#define DQ_PWM_OFFSET_UCM_RDMA_CQ_CONS_32BIT (DQ_PWM_OFFSET_UCM32_BASE)
#define DQ_PWM_OFFSET_UCM_RDMA_CQ_CONS_16BIT (DQ_PWM_OFFSET_UCM16_4)
#define DQ_PWM_OFFSET_UCM_RDMA_INT_TIMEOUT (DQ_PWM_OFFSET_UCM16_BASE + 2)
#define DQ_PWM_OFFSET_UCM_RDMA_ARM_FLAGS (DQ_PWM_OFFSET_UCM_FLAGS)
#define DQ_PWM_OFFSET_TCM_ROCE_RQ_PROD (DQ_PWM_OFFSET_TCM16_BASE + 1)
#define DQ_PWM_OFFSET_TCM_IWARP_RQ_PROD (DQ_PWM_OFFSET_TCM16_BASE + 3)
#define DQ_REGION_SHIFT (12)
/* DPM */
......@@ -214,15 +326,17 @@
*/
#define CM_TX_PQ_BASE 0x200
/* number of global Vport/QCN rate limiters */
#define MAX_QM_GLOBAL_RLS 256
/* QM registers data */
#define QM_LINE_CRD_REG_WIDTH 16
#define QM_LINE_CRD_REG_SIGN_BIT (1 << (QM_LINE_CRD_REG_WIDTH - 1))
#define QM_LINE_CRD_REG_SIGN_BIT BIT((QM_LINE_CRD_REG_WIDTH - 1))
#define QM_BYTE_CRD_REG_WIDTH 24
#define QM_BYTE_CRD_REG_SIGN_BIT (1 << (QM_BYTE_CRD_REG_WIDTH - 1))
#define QM_BYTE_CRD_REG_SIGN_BIT BIT((QM_BYTE_CRD_REG_WIDTH - 1))
#define QM_WFQ_CRD_REG_WIDTH 32
#define QM_WFQ_CRD_REG_SIGN_BIT (1 << (QM_WFQ_CRD_REG_WIDTH - 1))
#define QM_WFQ_CRD_REG_SIGN_BIT BIT((QM_WFQ_CRD_REG_WIDTH - 1))
#define QM_RL_CRD_REG_WIDTH 32
#define QM_RL_CRD_REG_SIGN_BIT (1 << (QM_RL_CRD_REG_WIDTH - 1))
#define QM_RL_CRD_REG_SIGN_BIT BIT((QM_RL_CRD_REG_WIDTH - 1))
/*****************/
/* CAU CONSTANTS */
......@@ -287,6 +401,17 @@
/* PXP CONSTANTS */
/*****************/
/* Bars for Blocks */
#define PXP_BAR_GRC 0
#define PXP_BAR_TSDM 0
#define PXP_BAR_USDM 0
#define PXP_BAR_XSDM 0
#define PXP_BAR_MSDM 0
#define PXP_BAR_YSDM 0
#define PXP_BAR_PSDM 0
#define PXP_BAR_IGU 0
#define PXP_BAR_DQ 1
/* PTT and GTT */
#define PXP_NUM_PF_WINDOWS 12
#define PXP_PER_PF_ENTRY_SIZE 8
......@@ -334,6 +459,52 @@
(PXP_EXTERNAL_BAR_GLOBAL_WINDOW_START + \
PXP_EXTERNAL_BAR_GLOBAL_WINDOW_LENGTH - 1)
/* PF BAR */
#define PXP_BAR0_START_GRC 0x0000
#define PXP_BAR0_GRC_LENGTH 0x1C00000
#define PXP_BAR0_END_GRC (PXP_BAR0_START_GRC + \
PXP_BAR0_GRC_LENGTH - 1)
#define PXP_BAR0_START_IGU 0x1C00000
#define PXP_BAR0_IGU_LENGTH 0x10000
#define PXP_BAR0_END_IGU (PXP_BAR0_START_IGU + \
PXP_BAR0_IGU_LENGTH - 1)
#define PXP_BAR0_START_TSDM 0x1C80000
#define PXP_BAR0_SDM_LENGTH 0x40000
#define PXP_BAR0_SDM_RESERVED_LENGTH 0x40000
#define PXP_BAR0_END_TSDM (PXP_BAR0_START_TSDM + \
PXP_BAR0_SDM_LENGTH - 1)
#define PXP_BAR0_START_MSDM 0x1D00000
#define PXP_BAR0_END_MSDM (PXP_BAR0_START_MSDM + \
PXP_BAR0_SDM_LENGTH - 1)
#define PXP_BAR0_START_USDM 0x1D80000
#define PXP_BAR0_END_USDM (PXP_BAR0_START_USDM + \
PXP_BAR0_SDM_LENGTH - 1)
#define PXP_BAR0_START_XSDM 0x1E00000
#define PXP_BAR0_END_XSDM (PXP_BAR0_START_XSDM + \
PXP_BAR0_SDM_LENGTH - 1)
#define PXP_BAR0_START_YSDM 0x1E80000
#define PXP_BAR0_END_YSDM (PXP_BAR0_START_YSDM + \
PXP_BAR0_SDM_LENGTH - 1)
#define PXP_BAR0_START_PSDM 0x1F00000
#define PXP_BAR0_END_PSDM (PXP_BAR0_START_PSDM + \
PXP_BAR0_SDM_LENGTH - 1)
#define PXP_BAR0_FIRST_INVALID_ADDRESS (PXP_BAR0_END_PSDM + 1)
/* VF BAR */
#define PXP_VF_BAR0 0
#define PXP_VF_BAR0_START_GRC 0x3E00
#define PXP_VF_BAR0_GRC_LENGTH 0x200
#define PXP_VF_BAR0_END_GRC (PXP_VF_BAR0_START_GRC + \
PXP_VF_BAR0_GRC_LENGTH - 1)
#define PXP_VF_BAR0_START_IGU 0
#define PXP_VF_BAR0_IGU_LENGTH 0x3000
......@@ -399,6 +570,20 @@
#define PXP_NUM_ILT_RECORDS_BB 7600
#define PXP_NUM_ILT_RECORDS_K2 11000
#define MAX_NUM_ILT_RECORDS MAX(PXP_NUM_ILT_RECORDS_BB, PXP_NUM_ILT_RECORDS_K2)
#define PXP_QUEUES_ZONE_MAX_NUM 320
/*****************/
/* PRM CONSTANTS */
/*****************/
#define PRM_DMA_PAD_BYTES_NUM 2
/******************/
/* SDMs CONSTANTS */
/******************/
#define SDM_OP_GEN_TRIG_NONE 0
#define SDM_OP_GEN_TRIG_WAKE_THREAD 1
#define SDM_OP_GEN_TRIG_AGG_INT 2
#define SDM_OP_GEN_TRIG_LOADER 4
#define SDM_OP_GEN_TRIG_INDICATE_ERROR 6
#define SDM_OP_GEN_TRIG_RELEASE_THREAD 7
#define SDM_COMP_TYPE_NONE 0
#define SDM_COMP_TYPE_WAKE_THREAD 1
......@@ -424,6 +609,8 @@
/* PRS CONSTANTS */
/*****************/
#define PRS_GFT_CAM_LINES_NO_MATCH 31
/* Async data KCQ CQE */
struct async_data {
__le32 cid;
......@@ -440,20 +627,6 @@ struct coalescing_timeset {
#define COALESCING_TIMESET_VALID_SHIFT 7
};
struct common_prs_pf_msg_info {
__le32 value;
#define COMMON_PRS_PF_MSG_INFO_NPAR_DEFAULT_PF_MASK 0x1
#define COMMON_PRS_PF_MSG_INFO_NPAR_DEFAULT_PF_SHIFT 0
#define COMMON_PRS_PF_MSG_INFO_FW_DEBUG_1_MASK 0x1
#define COMMON_PRS_PF_MSG_INFO_FW_DEBUG_1_SHIFT 1
#define COMMON_PRS_PF_MSG_INFO_FW_DEBUG_2_MASK 0x1
#define COMMON_PRS_PF_MSG_INFO_FW_DEBUG_2_SHIFT 2
#define COMMON_PRS_PF_MSG_INFO_FW_DEBUG_3_MASK 0x1
#define COMMON_PRS_PF_MSG_INFO_FW_DEBUG_3_SHIFT 3
#define COMMON_PRS_PF_MSG_INFO_RESERVED_MASK 0xFFFFFFF
#define COMMON_PRS_PF_MSG_INFO_RESERVED_SHIFT 4
};
struct common_queue_zone {
__le16 ring_drv_data_consumer;
__le16 reserved;
......@@ -473,6 +646,19 @@ struct vf_pf_channel_eqe_data {
struct regpair msg_addr;
};
struct iscsi_eqe_data {
__le32 cid;
__le16 conn_id;
u8 error_code;
u8 error_pdu_opcode_reserved;
#define ISCSI_EQE_DATA_ERROR_PDU_OPCODE_MASK 0x3F
#define ISCSI_EQE_DATA_ERROR_PDU_OPCODE_SHIFT 0
#define ISCSI_EQE_DATA_ERROR_PDU_OPCODE_VALID_MASK 0x1
#define ISCSI_EQE_DATA_ERROR_PDU_OPCODE_VALID_SHIFT 6
#define ISCSI_EQE_DATA_RESERVED0_MASK 0x1
#define ISCSI_EQE_DATA_RESERVED0_SHIFT 7
};
struct malicious_vf_eqe_data {
u8 vf_id;
u8 err_id;
......@@ -488,6 +674,7 @@ struct initial_cleanup_eqe_data {
union event_ring_data {
u8 bytes[8];
struct vf_pf_channel_eqe_data vf_pf_channel;
struct iscsi_eqe_data iscsi_info;
struct malicious_vf_eqe_data malicious_vf;
struct initial_cleanup_eqe_data vf_init_cleanup;
};
......@@ -616,6 +803,52 @@ enum db_dest {
MAX_DB_DEST
};
/* Enum of doorbell DPM types */
enum db_dpm_type {
DPM_LEGACY,
DPM_ROCE,
DPM_L2_INLINE,
DPM_L2_BD,
MAX_DB_DPM_TYPE
};
/* Structure for doorbell data, in L2 DPM mode, for 1st db in a DPM burst */
struct db_l2_dpm_data {
__le16 icid;
__le16 bd_prod;
__le32 params;
#define DB_L2_DPM_DATA_SIZE_MASK 0x3F
#define DB_L2_DPM_DATA_SIZE_SHIFT 0
#define DB_L2_DPM_DATA_DPM_TYPE_MASK 0x3
#define DB_L2_DPM_DATA_DPM_TYPE_SHIFT 6
#define DB_L2_DPM_DATA_NUM_BDS_MASK 0xFF
#define DB_L2_DPM_DATA_NUM_BDS_SHIFT 8
#define DB_L2_DPM_DATA_PKT_SIZE_MASK 0x7FF
#define DB_L2_DPM_DATA_PKT_SIZE_SHIFT 16
#define DB_L2_DPM_DATA_RESERVED0_MASK 0x1
#define DB_L2_DPM_DATA_RESERVED0_SHIFT 27
#define DB_L2_DPM_DATA_SGE_NUM_MASK 0x7
#define DB_L2_DPM_DATA_SGE_NUM_SHIFT 28
#define DB_L2_DPM_DATA_RESERVED1_MASK 0x1
#define DB_L2_DPM_DATA_RESERVED1_SHIFT 31
};
/* Structure for SGE in a DPM doorbell of type DPM_L2_BD */
struct db_l2_dpm_sge {
struct regpair addr;
__le16 nbytes;
__le16 bitfields;
#define DB_L2_DPM_SGE_TPH_ST_INDEX_MASK 0x1FF
#define DB_L2_DPM_SGE_TPH_ST_INDEX_SHIFT 0
#define DB_L2_DPM_SGE_RESERVED0_MASK 0x3
#define DB_L2_DPM_SGE_RESERVED0_SHIFT 9
#define DB_L2_DPM_SGE_ST_VALID_MASK 0x1
#define DB_L2_DPM_SGE_ST_VALID_SHIFT 11
#define DB_L2_DPM_SGE_RESERVED1_MASK 0xF
#define DB_L2_DPM_SGE_RESERVED1_SHIFT 12
__le32 reserved2;
};
/* Structure for doorbell address, in legacy mode */
struct db_legacy_addr {
__le32 addr;
......@@ -627,6 +860,49 @@ struct db_legacy_addr {
#define DB_LEGACY_ADDR_ICID_SHIFT 5
};
/* Structure for doorbell address, in PWM mode */
struct db_pwm_addr {
__le32 addr;
#define DB_PWM_ADDR_RESERVED0_MASK 0x7
#define DB_PWM_ADDR_RESERVED0_SHIFT 0
#define DB_PWM_ADDR_OFFSET_MASK 0x7F
#define DB_PWM_ADDR_OFFSET_SHIFT 3
#define DB_PWM_ADDR_WID_MASK 0x3
#define DB_PWM_ADDR_WID_SHIFT 10
#define DB_PWM_ADDR_DPI_MASK 0xFFFF
#define DB_PWM_ADDR_DPI_SHIFT 12
#define DB_PWM_ADDR_RESERVED1_MASK 0xF
#define DB_PWM_ADDR_RESERVED1_SHIFT 28
};
/* Parameters to RoCE firmware, passed in EDPM doorbell */
struct db_roce_dpm_params {
__le32 params;
#define DB_ROCE_DPM_PARAMS_SIZE_MASK 0x3F
#define DB_ROCE_DPM_PARAMS_SIZE_SHIFT 0
#define DB_ROCE_DPM_PARAMS_DPM_TYPE_MASK 0x3
#define DB_ROCE_DPM_PARAMS_DPM_TYPE_SHIFT 6
#define DB_ROCE_DPM_PARAMS_OPCODE_MASK 0xFF
#define DB_ROCE_DPM_PARAMS_OPCODE_SHIFT 8
#define DB_ROCE_DPM_PARAMS_WQE_SIZE_MASK 0x7FF
#define DB_ROCE_DPM_PARAMS_WQE_SIZE_SHIFT 16
#define DB_ROCE_DPM_PARAMS_RESERVED0_MASK 0x1
#define DB_ROCE_DPM_PARAMS_RESERVED0_SHIFT 27
#define DB_ROCE_DPM_PARAMS_COMPLETION_FLG_MASK 0x1
#define DB_ROCE_DPM_PARAMS_COMPLETION_FLG_SHIFT 28
#define DB_ROCE_DPM_PARAMS_S_FLG_MASK 0x1
#define DB_ROCE_DPM_PARAMS_S_FLG_SHIFT 29
#define DB_ROCE_DPM_PARAMS_RESERVED1_MASK 0x3
#define DB_ROCE_DPM_PARAMS_RESERVED1_SHIFT 30
};
/* Structure for doorbell data, in ROCE DPM mode, for 1st db in a DPM burst */
struct db_roce_dpm_data {
__le16 icid;
__le16 prod_val;
struct db_roce_dpm_params params;
};
/* Igu interrupt command */
enum igu_int_cmd {
IGU_INT_ENABLE = 0,
......@@ -764,6 +1040,19 @@ struct pxp_ptt_entry {
struct pxp_pretend_cmd pretend;
};
/* VF Zone A Permission Register. */
struct pxp_vf_zone_a_permission {
__le32 control;
#define PXP_VF_ZONE_A_PERMISSION_VFID_MASK 0xFF
#define PXP_VF_ZONE_A_PERMISSION_VFID_SHIFT 0
#define PXP_VF_ZONE_A_PERMISSION_VALID_MASK 0x1
#define PXP_VF_ZONE_A_PERMISSION_VALID_SHIFT 8
#define PXP_VF_ZONE_A_PERMISSION_RESERVED0_MASK 0x7F
#define PXP_VF_ZONE_A_PERMISSION_RESERVED0_SHIFT 9
#define PXP_VF_ZONE_A_PERMISSION_RESERVED1_MASK 0xFFFF
#define PXP_VF_ZONE_A_PERMISSION_RESERVED1_SHIFT 16
};
/* RSS hash type */
struct rdif_task_context {
__le32 initial_ref_tag;
......@@ -831,6 +1120,7 @@ struct rdif_task_context {
__le32 reserved2;
};
/* RSS hash type */
enum rss_hash_type {
RSS_HASH_TYPE_DEFAULT = 0,
RSS_HASH_TYPE_IPV4 = 1,
......@@ -942,7 +1232,7 @@ struct tdif_task_context {
};
struct timers_context {
__le32 logical_client0;
__le32 logical_client_0;
#define TIMERS_CONTEXT_EXPIRATIONTIMELC0_MASK 0xFFFFFFF
#define TIMERS_CONTEXT_EXPIRATIONTIMELC0_SHIFT 0
#define TIMERS_CONTEXT_VALIDLC0_MASK 0x1
......@@ -951,7 +1241,7 @@ struct timers_context {
#define TIMERS_CONTEXT_ACTIVELC0_SHIFT 29
#define TIMERS_CONTEXT_RESERVED0_MASK 0x3
#define TIMERS_CONTEXT_RESERVED0_SHIFT 30
__le32 logical_client1;
__le32 logical_client_1;
#define TIMERS_CONTEXT_EXPIRATIONTIMELC1_MASK 0xFFFFFFF
#define TIMERS_CONTEXT_EXPIRATIONTIMELC1_SHIFT 0
#define TIMERS_CONTEXT_VALIDLC1_MASK 0x1
......@@ -960,7 +1250,7 @@ struct timers_context {
#define TIMERS_CONTEXT_ACTIVELC1_SHIFT 29
#define TIMERS_CONTEXT_RESERVED1_MASK 0x3
#define TIMERS_CONTEXT_RESERVED1_SHIFT 30
__le32 logical_client2;
__le32 logical_client_2;
#define TIMERS_CONTEXT_EXPIRATIONTIMELC2_MASK 0xFFFFFFF
#define TIMERS_CONTEXT_EXPIRATIONTIMELC2_SHIFT 0
#define TIMERS_CONTEXT_VALIDLC2_MASK 0x1
......@@ -978,3 +1268,4 @@ struct timers_context {
#define TIMERS_CONTEXT_RESERVED3_SHIFT 29
};
#endif /* __COMMON_HSI__ */
#endif
include/linux/qed/eth_common.h
View file @ 05fafbfb
......@@ -13,9 +13,12 @@
/* ETH FW CONSTANTS */
/********************/
#define ETH_HSI_VER_MAJOR 3
#define ETH_HSI_VER_MINOR 0
#define ETH_CACHE_LINE_SIZE 64
#define ETH_HSI_VER_MINOR 10
#define ETH_HSI_VER_NO_PKT_LEN_TUNN 5
#define ETH_CACHE_LINE_SIZE 64
#define ETH_RX_CQE_GAP 32
#define ETH_MAX_RAMROD_PER_CON 8
#define ETH_TX_BD_PAGE_SIZE_BYTES 4096
#define ETH_RX_BD_PAGE_SIZE_BYTES 4096
......@@ -24,15 +27,25 @@
#define ETH_TX_MIN_BDS_PER_NON_LSO_PKT 1
#define ETH_TX_MAX_BDS_PER_NON_LSO_PACKET 18
#define ETH_TX_MAX_BDS_PER_LSO_PACKET 255
#define ETH_TX_MAX_LSO_HDR_NBD 4
#define ETH_TX_MIN_BDS_PER_LSO_PKT 3
#define ETH_TX_MIN_BDS_PER_TUNN_IPV6_WITH_EXT_PKT 3
#define ETH_TX_MIN_BDS_PER_IPV6_WITH_EXT_PKT 2
#define ETH_TX_MIN_BDS_PER_PKT_W_LOOPBACK_MODE 2
#define ETH_TX_MAX_NON_LSO_PKT_LEN (9700 - (4 + 12 + 8))
#define ETH_TX_MAX_NON_LSO_PKT_LEN (9700 - (4 + 4 + 12 + 8))
#define ETH_TX_MAX_LSO_HDR_BYTES 510
#define ETH_TX_LSO_WINDOW_BDS_NUM (18 - 1)
#define ETH_TX_LSO_WINDOW_MIN_LEN 9700
#define ETH_TX_MAX_LSO_PAYLOAD_LEN 0xFE000
#define ETH_TX_NUM_SAME_AS_LAST_ENTRIES 320
#define ETH_TX_INACTIVE_SAME_AS_LAST 0xFFFF
#define ETH_NUM_STATISTIC_COUNTERS MAX_NUM_VPORTS
#define ETH_NUM_STATISTIC_COUNTERS_DOUBLE_VF_ZONE \
(ETH_NUM_STATISTIC_COUNTERS - MAX_NUM_VFS / 2)
#define ETH_NUM_STATISTIC_COUNTERS_QUAD_VF_ZONE \
(ETH_NUM_STATISTIC_COUNTERS - 3 * MAX_NUM_VFS / 4)
/* Maximum number of buffers, used for RX packet placement */
#define ETH_RX_MAX_BUFF_PER_PKT 5
......@@ -59,6 +72,8 @@
#define ETH_TPA_CQE_CONT_LEN_LIST_SIZE 6
#define ETH_TPA_CQE_END_LEN_LIST_SIZE 4
/* Control frame check constants */
#define ETH_CTL_FRAME_ETH_TYPE_NUM 4
struct eth_tx_1st_bd_flags {
u8 bitfields;
......@@ -82,10 +97,10 @@ struct eth_tx_1st_bd_flags {
/* The parsing information data fo rthe first tx bd of a given packet. */
struct eth_tx_data_1st_bd {
__le16 vlan;
u8 nbds;
struct eth_tx_1st_bd_flags bd_flags;
__le16 bitfields;
__le16 vlan;
u8 nbds;
struct eth_tx_1st_bd_flags bd_flags;
__le16 bitfields;
#define ETH_TX_DATA_1ST_BD_TUNN_FLAG_MASK 0x1
#define ETH_TX_DATA_1ST_BD_TUNN_FLAG_SHIFT 0
#define ETH_TX_DATA_1ST_BD_RESERVED0_MASK 0x1
......@@ -96,7 +111,7 @@ struct eth_tx_data_1st_bd {
/* The parsing information data for the second tx bd of a given packet. */
struct eth_tx_data_2nd_bd {
__le16 tunn_ip_size;
__le16 tunn_ip_size;
__le16 bitfields1;
#define ETH_TX_DATA_2ND_BD_TUNN_INNER_L2_HDR_SIZE_W_MASK 0xF
#define ETH_TX_DATA_2ND_BD_TUNN_INNER_L2_HDR_SIZE_W_SHIFT 0
......@@ -125,9 +140,14 @@ struct eth_tx_data_2nd_bd {
#define ETH_TX_DATA_2ND_BD_RESERVED0_SHIFT 13
};
/* Firmware data for L2-EDPM packet. */
struct eth_edpm_fw_data {
struct eth_tx_data_1st_bd data_1st_bd;
struct eth_tx_data_2nd_bd data_2nd_bd;
__le32 reserved;
};
struct eth_fast_path_cqe_fw_debug {
u8 reserved0;
u8 reserved1;
__le16 reserved2;
};
......@@ -148,6 +168,17 @@ struct eth_tunnel_parsing_flags {
#define ETH_TUNNEL_PARSING_FLAGS_IPV4_OPTIONS_SHIFT 7
};
/* PMD flow control bits */
struct eth_pmd_flow_flags {
u8 flags;
#define ETH_PMD_FLOW_FLAGS_VALID_MASK 0x1
#define ETH_PMD_FLOW_FLAGS_VALID_SHIFT 0
#define ETH_PMD_FLOW_FLAGS_TOGGLE_MASK 0x1
#define ETH_PMD_FLOW_FLAGS_TOGGLE_SHIFT 1
#define ETH_PMD_FLOW_FLAGS_RESERVED_MASK 0x3F
#define ETH_PMD_FLOW_FLAGS_RESERVED_SHIFT 2
};
/* Regular ETH Rx FP CQE. */
struct eth_fast_path_rx_reg_cqe {
u8 type;
......@@ -166,64 +197,63 @@ struct eth_fast_path_rx_reg_cqe {
u8 placement_offset;
struct eth_tunnel_parsing_flags tunnel_pars_flags;
u8 bd_num;
u8 reserved[7];
u8 reserved[9];
struct eth_fast_path_cqe_fw_debug fw_debug;
u8 reserved1[3];
u8 flags;
#define ETH_FAST_PATH_RX_REG_CQE_VALID_MASK 0x1
#define ETH_FAST_PATH_RX_REG_CQE_VALID_SHIFT 0
#define ETH_FAST_PATH_RX_REG_CQE_VALID_TOGGLE_MASK 0x1
#define ETH_FAST_PATH_RX_REG_CQE_VALID_TOGGLE_SHIFT 1
#define ETH_FAST_PATH_RX_REG_CQE_RESERVED2_MASK 0x3F
#define ETH_FAST_PATH_RX_REG_CQE_RESERVED2_SHIFT 2
struct eth_pmd_flow_flags pmd_flags;
};
/* TPA-continue ETH Rx FP CQE. */
struct eth_fast_path_rx_tpa_cont_cqe {
u8 type;
u8 tpa_agg_index;
__le16 len_list[ETH_TPA_CQE_CONT_LEN_LIST_SIZE];
u8 reserved[5];
u8 reserved1;
__le16 reserved2[ETH_TPA_CQE_CONT_LEN_LIST_SIZE];
u8 type;
u8 tpa_agg_index;
__le16 len_list[ETH_TPA_CQE_CONT_LEN_LIST_SIZE];
u8 reserved;
u8 reserved1;
__le16 reserved2[ETH_TPA_CQE_CONT_LEN_LIST_SIZE];
u8 reserved3[3];
struct eth_pmd_flow_flags pmd_flags;
};
/* TPA-end ETH Rx FP CQE. */
struct eth_fast_path_rx_tpa_end_cqe {
u8 type;
u8 tpa_agg_index;
__le16 total_packet_len;
u8 num_of_bds;
u8 end_reason;
__le16 num_of_coalesced_segs;
__le32 ts_delta;
__le16 len_list[ETH_TPA_CQE_END_LEN_LIST_SIZE];
u8 reserved1[3];
u8 reserved2;
__le16 reserved3[ETH_TPA_CQE_END_LEN_LIST_SIZE];
u8 type;
u8 tpa_agg_index;
__le16 total_packet_len;
u8 num_of_bds;
u8 end_reason;
__le16 num_of_coalesced_segs;
__le32 ts_delta;
__le16 len_list[ETH_TPA_CQE_END_LEN_LIST_SIZE];
__le16 reserved3[ETH_TPA_CQE_END_LEN_LIST_SIZE];
__le16 reserved1;
u8 reserved2;
struct eth_pmd_flow_flags pmd_flags;
};
/* TPA-start ETH Rx FP CQE. */
struct eth_fast_path_rx_tpa_start_cqe {
u8 type;
u8 bitfields;
u8 type;
u8 bitfields;
#define ETH_FAST_PATH_RX_TPA_START_CQE_RSS_HASH_TYPE_MASK 0x7
#define ETH_FAST_PATH_RX_TPA_START_CQE_RSS_HASH_TYPE_SHIFT 0
#define ETH_FAST_PATH_RX_TPA_START_CQE_TC_MASK 0xF
#define ETH_FAST_PATH_RX_TPA_START_CQE_TC_SHIFT 3
#define ETH_FAST_PATH_RX_TPA_START_CQE_RESERVED0_MASK 0x1
#define ETH_FAST_PATH_RX_TPA_START_CQE_RESERVED0_SHIFT 7
__le16 seg_len;
__le16 seg_len;
struct parsing_and_err_flags pars_flags;
__le16 vlan_tag;
__le32 rss_hash;
__le16 len_on_first_bd;
u8 placement_offset;
__le16 vlan_tag;
__le32 rss_hash;
__le16 len_on_first_bd;
u8 placement_offset;
struct eth_tunnel_parsing_flags tunnel_pars_flags;
u8 tpa_agg_index;
u8 header_len;
__le16 ext_bd_len_list[ETH_TPA_CQE_START_LEN_LIST_SIZE];
u8 tpa_agg_index;
u8 header_len;
__le16 ext_bd_len_list[ETH_TPA_CQE_START_LEN_LIST_SIZE];
struct eth_fast_path_cqe_fw_debug fw_debug;
u8 reserved;
struct eth_pmd_flow_flags pmd_flags;
};
/* The L4 pseudo checksum mode for Ethernet */
......@@ -245,15 +275,7 @@ struct eth_slow_path_rx_cqe {
u8 reserved[25];
__le16 echo;
u8 reserved1;
u8 flags;
/* for PMD mode - valid indication */
#define ETH_SLOW_PATH_RX_CQE_VALID_MASK 0x1
#define ETH_SLOW_PATH_RX_CQE_VALID_SHIFT 0
/* for PMD mode - valid toggle indication */
#define ETH_SLOW_PATH_RX_CQE_VALID_TOGGLE_MASK 0x1
#define ETH_SLOW_PATH_RX_CQE_VALID_TOGGLE_SHIFT 1
#define ETH_SLOW_PATH_RX_CQE_RESERVED2_MASK 0x3F
#define ETH_SLOW_PATH_RX_CQE_RESERVED2_SHIFT 2
struct eth_pmd_flow_flags pmd_flags;
};
/* union for all ETH Rx CQE types */
......@@ -276,6 +298,11 @@ enum eth_rx_cqe_type {
MAX_ETH_RX_CQE_TYPE
};
struct eth_rx_pmd_cqe {
union eth_rx_cqe cqe;
u8 reserved[ETH_RX_CQE_GAP];
};
enum eth_rx_tunn_type {
ETH_RX_NO_TUNN,
ETH_RX_TUNN_GENEVE,
......@@ -313,8 +340,8 @@ struct eth_tx_2nd_bd {
/* The parsing information data for the third tx bd of a given packet. */
struct eth_tx_data_3rd_bd {
__le16 lso_mss;
__le16 bitfields;
__le16 lso_mss;
__le16 bitfields;
#define ETH_TX_DATA_3RD_BD_TCP_HDR_LEN_DW_MASK 0xF
#define ETH_TX_DATA_3RD_BD_TCP_HDR_LEN_DW_SHIFT 0
#define ETH_TX_DATA_3RD_BD_HDR_NBD_MASK 0xF
......@@ -323,8 +350,8 @@ struct eth_tx_data_3rd_bd {
#define ETH_TX_DATA_3RD_BD_START_BD_SHIFT 8
#define ETH_TX_DATA_3RD_BD_RESERVED0_MASK 0x7F
#define ETH_TX_DATA_3RD_BD_RESERVED0_SHIFT 9
u8 tunn_l4_hdr_start_offset_w;
u8 tunn_hdr_size_w;
u8 tunn_l4_hdr_start_offset_w;
u8 tunn_hdr_size_w;
};
/* The third tx bd of a given packet */
......@@ -355,10 +382,10 @@ struct eth_tx_bd {
};
union eth_tx_bd_types {
struct eth_tx_1st_bd first_bd;
struct eth_tx_2nd_bd second_bd;
struct eth_tx_3rd_bd third_bd;
struct eth_tx_bd reg_bd;
struct eth_tx_1st_bd first_bd;
struct eth_tx_2nd_bd second_bd;
struct eth_tx_3rd_bd third_bd;
struct eth_tx_bd reg_bd;
};
/* Mstorm Queue Zone */
......@@ -389,8 +416,8 @@ struct eth_db_data {
#define ETH_DB_DATA_RESERVED_SHIFT 5
#define ETH_DB_DATA_AGG_VAL_SEL_MASK 0x3
#define ETH_DB_DATA_AGG_VAL_SEL_SHIFT 6
u8 agg_flags;
__le16 bd_prod;
u8 agg_flags;
__le16 bd_prod;
};
#endif /* __ETH_COMMON__ */
include/linux/qed/iscsi_common.h
View file @ 05fafbfb
......@@ -311,7 +311,7 @@ struct iscsi_login_req_hdr {
#define ISCSI_LOGIN_REQ_HDR_DATA_SEG_LEN_SHIFT 0
#define ISCSI_LOGIN_REQ_HDR_TOTAL_AHS_LEN_MASK 0xFF
#define ISCSI_LOGIN_REQ_HDR_TOTAL_AHS_LEN_SHIFT 24
__le32 isid_TABC;
__le32 isid_tabc;
__le16 tsih;
__le16 isid_d;
__le32 itt;
......@@ -464,7 +464,7 @@ struct iscsi_login_response_hdr {
#define ISCSI_LOGIN_RESPONSE_HDR_DATA_SEG_LEN_SHIFT 0
#define ISCSI_LOGIN_RESPONSE_HDR_TOTAL_AHS_LEN_MASK 0xFF
#define ISCSI_LOGIN_RESPONSE_HDR_TOTAL_AHS_LEN_SHIFT 24
__le32 isid_TABC;
__le32 isid_tabc;
__le16 tsih;
__le16 isid_d;
__le32 itt;
......@@ -688,8 +688,7 @@ union iscsi_cqe {
enum iscsi_cqes_type {
ISCSI_CQE_TYPE_SOLICITED = 1,
ISCSI_CQE_TYPE_UNSOLICITED,
ISCSI_CQE_TYPE_SOLICITED_WITH_SENSE
,
ISCSI_CQE_TYPE_SOLICITED_WITH_SENSE,
ISCSI_CQE_TYPE_TASK_CLEANUP,
ISCSI_CQE_TYPE_DUMMY,
MAX_ISCSI_CQES_TYPE
......@@ -769,9 +768,9 @@ enum iscsi_eqe_opcode {
ISCSI_EVENT_TYPE_UPDATE_CONN,
ISCSI_EVENT_TYPE_CLEAR_SQ,
ISCSI_EVENT_TYPE_TERMINATE_CONN,
ISCSI_EVENT_TYPE_MAC_UPDATE_CONN,
ISCSI_EVENT_TYPE_ASYN_CONNECT_COMPLETE,
ISCSI_EVENT_TYPE_ASYN_TERMINATE_DONE,
RESERVED8,
RESERVED9,
ISCSI_EVENT_TYPE_START_OF_ERROR_TYPES = 10,
ISCSI_EVENT_TYPE_ASYN_ABORT_RCVD,
......@@ -867,6 +866,7 @@ enum iscsi_ramrod_cmd_id {
ISCSI_RAMROD_CMD_ID_UPDATE_CONN = 4,
ISCSI_RAMROD_CMD_ID_TERMINATION_CONN = 5,
ISCSI_RAMROD_CMD_ID_CLEAR_SQ = 6,
ISCSI_RAMROD_CMD_ID_MAC_UPDATE = 7,
MAX_ISCSI_RAMROD_CMD_ID
};
......@@ -883,6 +883,16 @@ union iscsi_seq_num {
__le16 r2t_sn;
};
struct iscsi_spe_conn_mac_update {
struct iscsi_slow_path_hdr hdr;
__le16 conn_id;
__le32 fw_cid;
__le16 remote_mac_addr_lo;
__le16 remote_mac_addr_mid;
__le16 remote_mac_addr_hi;
u8 reserved0[2];
};
struct iscsi_spe_conn_offload {
struct iscsi_slow_path_hdr hdr;
__le16 conn_id;
......@@ -1302,14 +1312,6 @@ struct mstorm_iscsi_stats_drv {
struct regpair iscsi_rx_dropped_pdus_task_not_valid;
};
struct ooo_opaque {
__le32 cid;
u8 drop_isle;
u8 drop_size;
u8 ooo_opcode;
u8 ooo_isle;
};
struct pstorm_iscsi_stats_drv {
struct regpair iscsi_tx_bytes_cnt;
struct regpair iscsi_tx_packet_cnt;
......
include/linux/qed/qed_chain.h
View file @ 05fafbfb
......@@ -16,19 +16,6 @@
#include <linux/slab.h>
#include <linux/qed/common_hsi.h>
/* dma_addr_t manip */
#define DMA_LO_LE(x) cpu_to_le32(lower_32_bits(x))
#define DMA_HI_LE(x) cpu_to_le32(upper_32_bits(x))
#define DMA_REGPAIR_LE(x, val) do { \
(x).hi = DMA_HI_LE((val)); \
(x).lo = DMA_LO_LE((val)); \
} while (0)
#define HILO_GEN(hi, lo, type) ((((type)(hi)) << 32) + (lo))
#define HILO_64(hi, lo) HILO_GEN((le32_to_cpu(hi)), (le32_to_cpu(lo)), u64)
#define HILO_64_REGPAIR(regpair) (HILO_64(regpair.hi, regpair.lo))
#define HILO_DMA_REGPAIR(regpair) ((dma_addr_t)HILO_64_REGPAIR(regpair))
enum qed_chain_mode {
/* Each Page contains a next pointer at its end */
QED_CHAIN_MODE_NEXT_PTR,
......
include/linux/qed/tcp_common.h
View file @ 05fafbfb
......@@ -11,6 +11,14 @@
#define TCP_INVALID_TIMEOUT_VAL -1
struct ooo_opaque {
__le32 cid;
u8 drop_isle;
u8 drop_size;
u8 ooo_opcode;
u8 ooo_isle;
};
enum tcp_connect_mode {
TCP_CONNECT_ACTIVE,
TCP_CONNECT_PASSIVE,
......@@ -18,14 +26,10 @@ enum tcp_connect_mode {
};
struct tcp_init_params {
__le32 max_cwnd;
__le16 dup_ack_threshold;
__le32 two_msl_timer;
__le16 tx_sws_timer;
__le16 min_rto;
__le16 min_rto_rt;
__le16 max_rto;
u8 maxfinrt;
u8 reserved[1];
u8 reserved[9];
};
enum tcp_ip_version {
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment
GitLab Nexedi Edition | About GitLab | About Nexedi | 沪ICP备2021021310号-2 | 沪ICP备2021021310号-7