Commit 0672d22a authored by Fabio Estevam's avatar Fabio Estevam Committed by Shawn Guo

ARM: dts: imx: Fix the AR803X phy-mode

Commit 6d4cd041 ("net: phy: at803x: disable delay only for RGMII mode")
exposed an issue on imx DTS files using AR8031/AR8035 PHYs.

The end result is that the boards can no longer obtain an IP address
via UDHCP, for example.

Quoting Andrew Lunn:

"The problem here is, all the DTs were broken since day 0. However,
because the PHY driver was also broken, nobody noticed and it
worked. Now that the PHY driver has been fixed, all the bugs in the
DTs now become an issue"

To fix this problem, the phy-mode property needs to be "rgmii-id",  which
has the following meaning as per
Documentation/devicetree/bindings/net/ethernet.txt:

"RGMII with internal RX and TX delays provided by the PHY, the MAC should
not add the RX or TX delays in this case)"

Tested on imx6-sabresd, imx6sx-sdb and imx7d-pico boards with
successfully restored networking.

Based on the initial submission from Steve Twiss for the
imx6qdl-sabresd.
Signed-off-by: default avatarFabio Estevam <festevam@gmail.com>
Tested-by: default avatarBaruch Siach <baruch@tkos.co.il>
Tested-by: default avatarSoeren Moch <smoch@web.de>
Tested-by: default avatarSteve Twiss <stwiss.opensource@diasemi.com>
Tested-by: default avatarAdam Thomson <Adam.Thomson@diasemi.com>
Signed-off-by: default avatarSteve Twiss <stwiss.opensource@diasemi.com>
Tested-by: default avatarMarc Kleine-Budde <mkl@pengutronix.de>
Signed-off-by: default avatarMarc Kleine-Budde <mkl@pengutronix.de>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent 507aaeee
...@@ -216,7 +216,7 @@ &ecspi1 { ...@@ -216,7 +216,7 @@ &ecspi1 {
&fec { &fec {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>; pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii"; phy-mode = "rgmii-id";
phy-reset-duration = <10>; phy-reset-duration = <10>;
phy-reset-gpios = <&gpio1 24 GPIO_ACTIVE_LOW>; phy-reset-gpios = <&gpio1 24 GPIO_ACTIVE_LOW>;
phy-supply = <&reg_enet>; phy-supply = <&reg_enet>;
......
...@@ -92,7 +92,7 @@ &clks { ...@@ -92,7 +92,7 @@ &clks {
&fec { &fec {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>; pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii"; phy-mode = "rgmii-id";
phy-reset-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>; phy-reset-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>;
interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>, interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>,
<&intc 0 119 IRQ_TYPE_LEVEL_HIGH>; <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
......
...@@ -171,7 +171,7 @@ partition@3f0000 { ...@@ -171,7 +171,7 @@ partition@3f0000 {
&fec { &fec {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>; pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii"; phy-mode = "rgmii-id";
status = "okay"; status = "okay";
}; };
......
...@@ -110,7 +110,7 @@ m25p80@0 { ...@@ -110,7 +110,7 @@ m25p80@0 {
&fec { &fec {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>; pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii"; phy-mode = "rgmii-id";
phy-reset-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>; phy-reset-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>;
status = "okay"; status = "okay";
}; };
......
...@@ -98,7 +98,7 @@ &audmux { ...@@ -98,7 +98,7 @@ &audmux {
&fec { &fec {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>; pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii"; phy-mode = "rgmii-id";
phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
status = "okay"; status = "okay";
}; };
......
...@@ -51,7 +51,7 @@ ...@@ -51,7 +51,7 @@
&fec { &fec {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>; pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii"; phy-mode = "rgmii-id";
phy-reset-duration = <10>; phy-reset-duration = <10>;
phy-reset-gpios = <&gpio1 24 GPIO_ACTIVE_LOW>; phy-reset-gpios = <&gpio1 24 GPIO_ACTIVE_LOW>;
status = "okay"; status = "okay";
......
...@@ -292,7 +292,7 @@ &esai { ...@@ -292,7 +292,7 @@ &esai {
&fec { &fec {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>; pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii"; phy-mode = "rgmii-id";
interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>, interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>,
<&intc 0 119 IRQ_TYPE_LEVEL_HIGH>; <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
fsl,err006687-workaround-present; fsl,err006687-workaround-present;
......
...@@ -202,7 +202,7 @@ flash: m25p80@0 { ...@@ -202,7 +202,7 @@ flash: m25p80@0 {
&fec { &fec {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>; pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii"; phy-mode = "rgmii-id";
phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
status = "okay"; status = "okay";
}; };
......
...@@ -53,7 +53,7 @@ vcc_3v3: regulator-vcc-3v3 { ...@@ -53,7 +53,7 @@ vcc_3v3: regulator-vcc-3v3 {
&fec { &fec {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_microsom_enet_ar8035>; pinctrl-0 = <&pinctrl_microsom_enet_ar8035>;
phy-mode = "rgmii"; phy-mode = "rgmii-id";
phy-reset-duration = <2>; phy-reset-duration = <2>;
phy-reset-gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; phy-reset-gpios = <&gpio4 15 GPIO_ACTIVE_LOW>;
status = "okay"; status = "okay";
......
...@@ -224,7 +224,7 @@ MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 ...@@ -224,7 +224,7 @@ MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
&fec { &fec {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>; pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii"; phy-mode = "rgmii-id";
phy-reset-gpios = <&gpio3 29 GPIO_ACTIVE_LOW>; phy-reset-gpios = <&gpio3 29 GPIO_ACTIVE_LOW>;
interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>, interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>,
<&intc 0 119 IRQ_TYPE_LEVEL_HIGH>; <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
......
...@@ -75,7 +75,7 @@ &anaclk2 { ...@@ -75,7 +75,7 @@ &anaclk2 {
&fec1 { &fec1 {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet1>; pinctrl-0 = <&pinctrl_enet1>;
phy-mode = "rgmii"; phy-mode = "rgmii-id";
phy-handle = <&ethphy1>; phy-handle = <&ethphy1>;
fsl,magic-packet; fsl,magic-packet;
status = "okay"; status = "okay";
......
...@@ -191,7 +191,7 @@ &fec1 { ...@@ -191,7 +191,7 @@ &fec1 {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet1>; pinctrl-0 = <&pinctrl_enet1>;
phy-supply = <&reg_enet_3v3>; phy-supply = <&reg_enet_3v3>;
phy-mode = "rgmii"; phy-mode = "rgmii-id";
phy-handle = <&ethphy1>; phy-handle = <&ethphy1>;
phy-reset-gpios = <&gpio2 7 GPIO_ACTIVE_LOW>; phy-reset-gpios = <&gpio2 7 GPIO_ACTIVE_LOW>;
status = "okay"; status = "okay";
......
...@@ -92,7 +92,7 @@ &fec1 { ...@@ -92,7 +92,7 @@ &fec1 {
<&clks IMX7D_ENET1_TIME_ROOT_CLK>; <&clks IMX7D_ENET1_TIME_ROOT_CLK>;
assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>; assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
assigned-clock-rates = <0>, <100000000>; assigned-clock-rates = <0>, <100000000>;
phy-mode = "rgmii"; phy-mode = "rgmii-id";
phy-handle = <&ethphy0>; phy-handle = <&ethphy0>;
fsl,magic-packet; fsl,magic-packet;
phy-reset-gpios = <&gpio6 11 GPIO_ACTIVE_LOW>; phy-reset-gpios = <&gpio6 11 GPIO_ACTIVE_LOW>;
......
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