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Commit 072ef40e authored by Paul Mackerras's avatar Paul Mackerras
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Merge branch 'for-2.6.24' of master.kernel.org:/pub/scm/linux/kernel/git/galak/powerpc into merge

parents 2b46b567 bebfa06c
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Showing with 254 additions and 60 deletions
Documentation/powerpc/booting-without-of.txt
View file @ 072ef40e
...@@ -1645,8 +1645,9 @@ platforms are moved over to use the flattened-device-tree model. ...@@ -1645,8 +1645,9 @@ platforms are moved over to use the flattened-device-tree model.
MAC addresses passed by the firmware when no information other MAC addresses passed by the firmware when no information other
than indices is available to associate an address with a device. than indices is available to associate an address with a device.
- phy-connection-type : a string naming the controller/PHY interface type, - phy-connection-type : a string naming the controller/PHY interface type,
i.e., "mii" (default), "rmii", "gmii", "rgmii", "rgmii-id", "tbi", i.e., "mii" (default), "rmii", "gmii", "rgmii", "rgmii-id" (Internal
or "rtbi". Delay), "rgmii-txid" (delay on TX only), "rgmii-rxid" (delay on RX only),
"tbi", or "rtbi".
Example: Example:
ucc@2000 { ucc@2000 {
......
arch/powerpc/boot/dts/mpc832x_mds.dts
View file @ 072ef40e
...@@ -117,7 +117,6 @@ pio3: ucc_pin@03 { ...@@ -117,7 +117,6 @@ pio3: ucc_pin@03 {
3 5 1 0 2 0 /* MDC */ 3 5 1 0 2 0 /* MDC */
0 d 2 0 1 0 /* RX_CLK (CLK9) */ 0 d 2 0 1 0 /* RX_CLK (CLK9) */
3 18 2 0 1 0 /* TX_CLK (CLK10) */ 3 18 2 0 1 0 /* TX_CLK (CLK10) */
1 1 1 0 1 0 /* TxD1 */
1 0 1 0 1 0 /* TxD0 */ 1 0 1 0 1 0 /* TxD0 */
1 1 1 0 1 0 /* TxD1 */ 1 1 1 0 1 0 /* TxD1 */
1 2 1 0 1 0 /* TxD2 */ 1 2 1 0 1 0 /* TxD2 */
...@@ -228,7 +227,7 @@ ucc@3200 { ...@@ -228,7 +227,7 @@ ucc@3200 {
compatible = "ucc_geth"; compatible = "ucc_geth";
model = "UCC"; model = "UCC";
device-id = <4>; device-id = <4>;
reg = <3000 200>; reg = <3200 200>;
interrupts = <23>; interrupts = <23>;
interrupt-parent = < &qeic >; interrupt-parent = < &qeic >;
/* /*
......
arch/powerpc/boot/dts/mpc8544ds.dts
View file @ 072ef40e
...@@ -272,24 +272,24 @@ pcie@e000b000 { ...@@ -272,24 +272,24 @@ pcie@e000b000 {
clock-frequency = <1fca055>; clock-frequency = <1fca055>;
interrupt-parent = <&mpic>; interrupt-parent = <&mpic>;
interrupts = <1b 2>; interrupts = <1b 2>;
interrupt-map-mask = <fb00 0 0 0>; interrupt-map-mask = <ff00 0 0 1>;
interrupt-map = < interrupt-map = <
// IDSEL 0x1c USB // IDSEL 0x1c USB
e000 0 0 0 &i8259 c 2 e000 0 0 1 &i8259 c 2
e100 0 0 0 &i8259 9 2 e100 0 0 1 &i8259 9 2
e200 0 0 0 &i8259 a 2 e200 0 0 1 &i8259 a 2
e300 0 0 0 &i8259 b 2 e300 0 0 1 &i8259 b 2
// IDSEL 0x1d Audio // IDSEL 0x1d Audio
e800 0 0 0 &i8259 6 2 e800 0 0 1 &i8259 6 2
// IDSEL 0x1e Legacy // IDSEL 0x1e Legacy
f000 0 0 0 &i8259 7 2 f000 0 0 1 &i8259 7 2
f100 0 0 0 &i8259 7 2 f100 0 0 1 &i8259 7 2
// IDSEL 0x1f IDE/SATA // IDSEL 0x1f IDE/SATA
f800 0 0 0 &i8259 e 2 f800 0 0 1 &i8259 e 2
f900 0 0 0 &i8259 5 2 f900 0 0 1 &i8259 5 2
>; >;
pcie@0 { pcie@0 {
......
arch/powerpc/boot/dts/mpc8572ds.dts
View file @ 072ef40e
...@@ -219,36 +219,120 @@ pcie@ffe08000 { ...@@ -219,36 +219,120 @@ pcie@ffe08000 {
clock-frequency = <1fca055>; clock-frequency = <1fca055>;
interrupt-parent = <&mpic>; interrupt-parent = <&mpic>;
interrupts = <18 2>; interrupts = <18 2>;
interrupt-map-mask = <fb00 0 0 0>; interrupt-map-mask = <ff00 0 0 7>;
interrupt-map = < interrupt-map = <
/* IDSEL 0x11 - PCI slot 1 */ /* IDSEL 0x11 func 0 - PCI slot 1 */
8800 0 0 1 &mpic 2 1 8800 0 0 1 &mpic 2 1
8800 0 0 2 &mpic 3 1 8800 0 0 2 &mpic 3 1
8800 0 0 3 &mpic 4 1 8800 0 0 3 &mpic 4 1
8800 0 0 4 &mpic 1 1 8800 0 0 4 &mpic 1 1
/* IDSEL 0x12 - PCI slot 2 */ /* IDSEL 0x11 func 1 - PCI slot 1 */
8900 0 0 1 &mpic 2 1
8900 0 0 2 &mpic 3 1
8900 0 0 3 &mpic 4 1
8900 0 0 4 &mpic 1 1
/* IDSEL 0x11 func 2 - PCI slot 1 */
8a00 0 0 1 &mpic 2 1
8a00 0 0 2 &mpic 3 1
8a00 0 0 3 &mpic 4 1
8a00 0 0 4 &mpic 1 1
/* IDSEL 0x11 func 3 - PCI slot 1 */
8b00 0 0 1 &mpic 2 1
8b00 0 0 2 &mpic 3 1
8b00 0 0 3 &mpic 4 1
8b00 0 0 4 &mpic 1 1
/* IDSEL 0x11 func 4 - PCI slot 1 */
8c00 0 0 1 &mpic 2 1
8c00 0 0 2 &mpic 3 1
8c00 0 0 3 &mpic 4 1
8c00 0 0 4 &mpic 1 1
/* IDSEL 0x11 func 5 - PCI slot 1 */
8d00 0 0 1 &mpic 2 1
8d00 0 0 2 &mpic 3 1
8d00 0 0 3 &mpic 4 1
8d00 0 0 4 &mpic 1 1
/* IDSEL 0x11 func 6 - PCI slot 1 */
8e00 0 0 1 &mpic 2 1
8e00 0 0 2 &mpic 3 1
8e00 0 0 3 &mpic 4 1
8e00 0 0 4 &mpic 1 1
/* IDSEL 0x11 func 7 - PCI slot 1 */
8f00 0 0 1 &mpic 2 1
8f00 0 0 2 &mpic 3 1
8f00 0 0 3 &mpic 4 1
8f00 0 0 4 &mpic 1 1
/* IDSEL 0x12 func 0 - PCI slot 2 */
9000 0 0 1 &mpic 3 1 9000 0 0 1 &mpic 3 1
9000 0 0 2 &mpic 4 1 9000 0 0 2 &mpic 4 1
9000 0 0 3 &mpic 1 1 9000 0 0 3 &mpic 1 1
9000 0 0 4 &mpic 2 1 9000 0 0 4 &mpic 2 1
/* IDSEL 0x12 func 1 - PCI slot 2 */
9100 0 0 1 &mpic 3 1
9100 0 0 2 &mpic 4 1
9100 0 0 3 &mpic 1 1
9100 0 0 4 &mpic 2 1
/* IDSEL 0x12 func 2 - PCI slot 2 */
9200 0 0 1 &mpic 3 1
9200 0 0 2 &mpic 4 1
9200 0 0 3 &mpic 1 1
9200 0 0 4 &mpic 2 1
/* IDSEL 0x12 func 3 - PCI slot 2 */
9300 0 0 1 &mpic 3 1
9300 0 0 2 &mpic 4 1
9300 0 0 3 &mpic 1 1
9300 0 0 4 &mpic 2 1
/* IDSEL 0x12 func 4 - PCI slot 2 */
9400 0 0 1 &mpic 3 1
9400 0 0 2 &mpic 4 1
9400 0 0 3 &mpic 1 1
9400 0 0 4 &mpic 2 1
/* IDSEL 0x12 func 5 - PCI slot 2 */
9500 0 0 1 &mpic 3 1
9500 0 0 2 &mpic 4 1
9500 0 0 3 &mpic 1 1
9500 0 0 4 &mpic 2 1
/* IDSEL 0x12 func 6 - PCI slot 2 */
9600 0 0 1 &mpic 3 1
9600 0 0 2 &mpic 4 1
9600 0 0 3 &mpic 1 1
9600 0 0 4 &mpic 2 1
/* IDSEL 0x12 func 7 - PCI slot 2 */
9700 0 0 1 &mpic 3 1
9700 0 0 2 &mpic 4 1
9700 0 0 3 &mpic 1 1
9700 0 0 4 &mpic 2 1
// IDSEL 0x1c USB // IDSEL 0x1c USB
e000 0 0 0 &i8259 c 2 e000 0 0 1 &i8259 c 2
e100 0 0 0 &i8259 9 2 e100 0 0 1 &i8259 9 2
e200 0 0 0 &i8259 a 2 e200 0 0 1 &i8259 a 2
e300 0 0 0 &i8259 b 2 e300 0 0 1 &i8259 b 2
// IDSEL 0x1d Audio // IDSEL 0x1d Audio
e800 0 0 0 &i8259 6 2 e800 0 0 1 &i8259 6 2
// IDSEL 0x1e Legacy // IDSEL 0x1e Legacy
f000 0 0 0 &i8259 7 2 f000 0 0 1 &i8259 7 2
f100 0 0 0 &i8259 7 2 f100 0 0 1 &i8259 7 2
// IDSEL 0x1f IDE/SATA // IDSEL 0x1f IDE/SATA
f800 0 0 0 &i8259 e 2 f800 0 0 1 &i8259 e 2
f900 0 0 0 &i8259 5 2 f900 0 0 1 &i8259 5 2
>; >;
......
arch/powerpc/boot/dts/mpc8641_hpcn.dts
View file @ 072ef40e
...@@ -235,36 +235,120 @@ pcie@f8008000 { ...@@ -235,36 +235,120 @@ pcie@f8008000 {
clock-frequency = <1fca055>; clock-frequency = <1fca055>;
interrupt-parent = <&mpic>; interrupt-parent = <&mpic>;
interrupts = <18 2>; interrupts = <18 2>;
interrupt-map-mask = <fb00 0 0 0>; interrupt-map-mask = <ff00 0 0 7>;
interrupt-map = < interrupt-map = <
/* IDSEL 0x11 */ /* IDSEL 0x11 func 0 - PCI slot 1 */
8800 0 0 1 &i8259 9 2 8800 0 0 1 &mpic 2 1
8800 0 0 2 &i8259 a 2 8800 0 0 2 &mpic 3 1
8800 0 0 3 &i8259 b 2 8800 0 0 3 &mpic 4 1
8800 0 0 4 &i8259 c 2 8800 0 0 4 &mpic 1 1
/* IDSEL 0x12 */ /* IDSEL 0x11 func 1 - PCI slot 1 */
9000 0 0 1 &i8259 a 2 8900 0 0 1 &mpic 2 1
9000 0 0 2 &i8259 b 2 8900 0 0 2 &mpic 3 1
9000 0 0 3 &i8259 c 2 8900 0 0 3 &mpic 4 1
9000 0 0 4 &i8259 9 2 8900 0 0 4 &mpic 1 1
/* IDSEL 0x11 func 2 - PCI slot 1 */
8a00 0 0 1 &mpic 2 1
8a00 0 0 2 &mpic 3 1
8a00 0 0 3 &mpic 4 1
8a00 0 0 4 &mpic 1 1
/* IDSEL 0x11 func 3 - PCI slot 1 */
8b00 0 0 1 &mpic 2 1
8b00 0 0 2 &mpic 3 1
8b00 0 0 3 &mpic 4 1
8b00 0 0 4 &mpic 1 1
/* IDSEL 0x11 func 4 - PCI slot 1 */
8c00 0 0 1 &mpic 2 1
8c00 0 0 2 &mpic 3 1
8c00 0 0 3 &mpic 4 1
8c00 0 0 4 &mpic 1 1
/* IDSEL 0x11 func 5 - PCI slot 1 */
8d00 0 0 1 &mpic 2 1
8d00 0 0 2 &mpic 3 1
8d00 0 0 3 &mpic 4 1
8d00 0 0 4 &mpic 1 1
/* IDSEL 0x11 func 6 - PCI slot 1 */
8e00 0 0 1 &mpic 2 1
8e00 0 0 2 &mpic 3 1
8e00 0 0 3 &mpic 4 1
8e00 0 0 4 &mpic 1 1
/* IDSEL 0x11 func 7 - PCI slot 1 */
8f00 0 0 1 &mpic 2 1
8f00 0 0 2 &mpic 3 1
8f00 0 0 3 &mpic 4 1
8f00 0 0 4 &mpic 1 1
/* IDSEL 0x12 func 0 - PCI slot 2 */
9000 0 0 1 &mpic 3 1
9000 0 0 2 &mpic 4 1
9000 0 0 3 &mpic 1 1
9000 0 0 4 &mpic 2 1
/* IDSEL 0x12 func 1 - PCI slot 2 */
9100 0 0 1 &mpic 3 1
9100 0 0 2 &mpic 4 1
9100 0 0 3 &mpic 1 1
9100 0 0 4 &mpic 2 1
/* IDSEL 0x12 func 2 - PCI slot 2 */
9200 0 0 1 &mpic 3 1
9200 0 0 2 &mpic 4 1
9200 0 0 3 &mpic 1 1
9200 0 0 4 &mpic 2 1
/* IDSEL 0x12 func 3 - PCI slot 2 */
9300 0 0 1 &mpic 3 1
9300 0 0 2 &mpic 4 1
9300 0 0 3 &mpic 1 1
9300 0 0 4 &mpic 2 1
/* IDSEL 0x12 func 4 - PCI slot 2 */
9400 0 0 1 &mpic 3 1
9400 0 0 2 &mpic 4 1
9400 0 0 3 &mpic 1 1
9400 0 0 4 &mpic 2 1
/* IDSEL 0x12 func 5 - PCI slot 2 */
9500 0 0 1 &mpic 3 1
9500 0 0 2 &mpic 4 1
9500 0 0 3 &mpic 1 1
9500 0 0 4 &mpic 2 1
/* IDSEL 0x12 func 6 - PCI slot 2 */
9600 0 0 1 &mpic 3 1
9600 0 0 2 &mpic 4 1
9600 0 0 3 &mpic 1 1
9600 0 0 4 &mpic 2 1
/* IDSEL 0x12 func 7 - PCI slot 2 */
9700 0 0 1 &mpic 3 1
9700 0 0 2 &mpic 4 1
9700 0 0 3 &mpic 1 1
9700 0 0 4 &mpic 2 1
// IDSEL 0x1c USB // IDSEL 0x1c USB
e000 0 0 0 &i8259 c 2 e000 0 0 1 &i8259 c 2
e100 0 0 0 &i8259 9 2 e100 0 0 1 &i8259 9 2
e200 0 0 0 &i8259 a 2 e200 0 0 1 &i8259 a 2
e300 0 0 0 &i8259 b 2 e300 0 0 1 &i8259 b 2
// IDSEL 0x1d Audio // IDSEL 0x1d Audio
e800 0 0 0 &i8259 6 2 e800 0 0 1 &i8259 6 2
// IDSEL 0x1e Legacy // IDSEL 0x1e Legacy
f000 0 0 0 &i8259 7 2 f000 0 0 1 &i8259 7 2
f100 0 0 0 &i8259 7 2 f100 0 0 1 &i8259 7 2
// IDSEL 0x1f IDE/SATA // IDSEL 0x1f IDE/SATA
f800 0 0 0 &i8259 e 2 f800 0 0 1 &i8259 e 2
f900 0 0 0 &i8259 5 2 f900 0 0 1 &i8259 5 2
>; >;
pcie@0 { pcie@0 {
......
arch/powerpc/platforms/83xx/mpc832x_mds.c
View file @ 072ef40e
...@@ -90,10 +90,11 @@ static void __init mpc832x_sys_setup_arch(void) ...@@ -90,10 +90,11 @@ static void __init mpc832x_sys_setup_arch(void)
if ((np = of_find_compatible_node(NULL, "network", "ucc_geth")) if ((np = of_find_compatible_node(NULL, "network", "ucc_geth"))
!= NULL){ != NULL){
/* Reset the Ethernet PHY */ /* Reset the Ethernet PHYs */
bcsr_regs[9] &= ~0x20; #define BCSR8_FETH_RST 0x50
bcsr_regs[8] &= ~BCSR8_FETH_RST;
udelay(1000); udelay(1000);
bcsr_regs[9] |= 0x20; bcsr_regs[8] |= BCSR8_FETH_RST;
iounmap(bcsr_regs); iounmap(bcsr_regs);
of_node_put(np); of_node_put(np);
} }
......
arch/powerpc/platforms/83xx/mpc836x_mds.c
View file @ 072ef40e
...@@ -96,14 +96,39 @@ static void __init mpc836x_mds_setup_arch(void) ...@@ -96,14 +96,39 @@ static void __init mpc836x_mds_setup_arch(void)
if ((np = of_find_compatible_node(NULL, "network", "ucc_geth")) if ((np = of_find_compatible_node(NULL, "network", "ucc_geth"))
!= NULL){ != NULL){
uint svid;
/* Reset the Ethernet PHY */ /* Reset the Ethernet PHY */
bcsr_regs[9] &= ~0x20; #define BCSR9_GETHRST 0x20
clrbits8(&bcsr_regs[9], BCSR9_GETHRST);
udelay(1000); udelay(1000);
bcsr_regs[9] |= 0x20; setbits8(&bcsr_regs[9], BCSR9_GETHRST);
/* handle mpc8360ea rev.2.1 erratum 2: RGMII Timing */
svid = mfspr(SPRN_SVR);
if (svid == 0x80480021) {
void __iomem *immap;
immap = ioremap(get_immrbase() + 0x14a8, 8);
/*
* IMMR + 0x14A8[4:5] = 11 (clk delay for UCC 2)
* IMMR + 0x14A8[18:19] = 11 (clk delay for UCC 1)
*/
setbits32(immap, 0x0c003000);
/*
* IMMR + 0x14AC[20:27] = 10101010
* (data delay for both UCC's)
*/
clrsetbits_be32(immap + 4, 0xff0, 0xaa0);
iounmap(immap);
}
iounmap(bcsr_regs); iounmap(bcsr_regs);
of_node_put(np); of_node_put(np);
} }
#endif /* CONFIG_QUICC_ENGINE */ #endif /* CONFIG_QUICC_ENGINE */
} }
......
arch/powerpc/platforms/83xx/usb.c
View file @ 072ef40e
...@@ -130,7 +130,7 @@ int mpc831x_usb_cfg(void) ...@@ -130,7 +130,7 @@ int mpc831x_usb_cfg(void)
out_be32(immap + MPC83XX_SCCR_OFFS, temp); out_be32(immap + MPC83XX_SCCR_OFFS, temp);
/* Configure pin mux for ULPI. There is no pin mux for UTMI */ /* Configure pin mux for ULPI. There is no pin mux for UTMI */
if (!strcmp(prop, "ulpi")) { if (prop && !strcmp(prop, "ulpi")) {
temp = in_be32(immap + MPC83XX_SICRL_OFFS); temp = in_be32(immap + MPC83XX_SICRL_OFFS);
temp &= ~MPC831X_SICRL_USB_MASK; temp &= ~MPC831X_SICRL_USB_MASK;
temp |= MPC831X_SICRL_USB_ULPI; temp |= MPC831X_SICRL_USB_ULPI;
...@@ -153,13 +153,13 @@ int mpc831x_usb_cfg(void) ...@@ -153,13 +153,13 @@ int mpc831x_usb_cfg(void)
usb_regs = ioremap(res.start, res.end - res.start + 1); usb_regs = ioremap(res.start, res.end - res.start + 1);
/* Using on-chip PHY */ /* Using on-chip PHY */
if (!strcmp(prop, "utmi_wide") || if (prop && (!strcmp(prop, "utmi_wide") ||
!strcmp(prop, "utmi")) { !strcmp(prop, "utmi"))) {
/* Set UTMI_PHY_EN, REFSEL to 48MHZ */ /* Set UTMI_PHY_EN, REFSEL to 48MHZ */
out_be32(usb_regs + FSL_USB2_CONTROL_OFFS, out_be32(usb_regs + FSL_USB2_CONTROL_OFFS,
CONTROL_UTMI_PHY_EN | CONTROL_REFSEL_48MHZ); CONTROL_UTMI_PHY_EN | CONTROL_REFSEL_48MHZ);
/* Using external UPLI PHY */ /* Using external UPLI PHY */
} else if (!strcmp(prop, "ulpi")) { } else if (prop && !strcmp(prop, "ulpi")) {
/* Set PHY_CLK_SEL to ULPI */ /* Set PHY_CLK_SEL to ULPI */
temp = CONTROL_PHY_CLK_SEL_ULPI; temp = CONTROL_PHY_CLK_SEL_ULPI;
#ifdef CONFIG_USB_OTG #ifdef CONFIG_USB_OTG
......
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