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Commit 07a356bb authored by Ben Skeggs's avatar Ben Skeggs
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drm/nouveau/msppp: switch to instanced constructor 

Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
Reviewed-by: default avatarLyude Paul <lyude@redhat.com>
parent 96321606
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Inline Side-by-side
Showing with 42 additions and 45 deletions
drivers/gpu/drm/nouveau/include/nvkm/core/device.h
View file @ 07a356bb
......@@ -60,7 +60,6 @@ struct nvkm_device {
struct notifier_block nb;
} acpi;
struct nvkm_engine *msppp;
struct nvkm_engine *msvld;
struct nvkm_nvenc *nvenc[3];
struct nvkm_nvdec *nvdec[3];
......@@ -110,7 +109,6 @@ struct nvkm_device_chip {
#undef NVKM_LAYOUT_INST
#undef NVKM_LAYOUT_ONCE
int (*msppp )(struct nvkm_device *, int idx, struct nvkm_engine **);
int (*msvld )(struct nvkm_device *, int idx, struct nvkm_engine **);
int (*nvenc[3])(struct nvkm_device *, int idx, struct nvkm_nvenc **);
int (*nvdec[3])(struct nvkm_device *, int idx, struct nvkm_nvdec **);
......
drivers/gpu/drm/nouveau/include/nvkm/core/layout.h
View file @ 07a356bb
......@@ -37,4 +37,5 @@ NVKM_LAYOUT_ONCE(NVKM_ENGINE_ME , struct nvkm_engine , me)
NVKM_LAYOUT_ONCE(NVKM_ENGINE_MPEG , struct nvkm_engine , mpeg)
NVKM_LAYOUT_ONCE(NVKM_ENGINE_MSENC , struct nvkm_engine , msenc)
NVKM_LAYOUT_ONCE(NVKM_ENGINE_MSPDEC , struct nvkm_engine , mspdec)
NVKM_LAYOUT_ONCE(NVKM_ENGINE_MSPPP , struct nvkm_engine , msppp)
NVKM_LAYOUT_ONCE(NVKM_ENGINE_VP , struct nvkm_engine , vp)
drivers/gpu/drm/nouveau/include/nvkm/engine/msppp.h
View file @ 07a356bb
......@@ -2,7 +2,7 @@
#ifndef __NVKM_MSPPP_H__
#define __NVKM_MSPPP_H__
#include <engine/falcon.h>
int g98_msppp_new(struct nvkm_device *, int, struct nvkm_engine **);
int gt215_msppp_new(struct nvkm_device *, int, struct nvkm_engine **);
int gf100_msppp_new(struct nvkm_device *, int, struct nvkm_engine **);
int g98_msppp_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_engine **);
int gt215_msppp_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_engine **);
int gf100_msppp_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_engine **);
#endif
drivers/gpu/drm/nouveau/nvkm/core/subdev.c
View file @ 07a356bb
......@@ -33,7 +33,6 @@ nvkm_subdev_type[NVKM_SUBDEV_NR] = {
#include <core/layout.h>
#undef NVKM_LAYOUT_ONCE
#undef NVKM_LAYOUT_INST
[NVKM_ENGINE_MSPPP ] = "msppp",
[NVKM_ENGINE_MSVLD ] = "msvld",
[NVKM_ENGINE_NVENC0 ] = "nvenc0",
[NVKM_ENGINE_NVENC1 ] = "nvenc1",
......
drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
View file @ 07a356bb
......@@ -1099,7 +1099,7 @@ nv98_chipset = {
.fifo = { 0x00000001, g84_fifo_new },
.gr = { 0x00000001, g84_gr_new },
.mspdec = { 0x00000001, g98_mspdec_new },
.msppp = g98_msppp_new,
.msppp = { 0x00000001, g98_msppp_new },
.msvld = g98_msvld_new,
.pm = g84_pm_new,
.sec = g98_sec_new,
......@@ -1166,7 +1166,7 @@ nva3_chipset = {
.gr = { 0x00000001, gt215_gr_new },
.mpeg = { 0x00000001, g84_mpeg_new },
.mspdec = { 0x00000001, gt215_mspdec_new },
.msppp = gt215_msppp_new,
.msppp = { 0x00000001, gt215_msppp_new },
.msvld = gt215_msvld_new,
.pm = gt215_pm_new,
.sw = nv50_sw_new,
......@@ -1199,7 +1199,7 @@ nva5_chipset = {
.fifo = { 0x00000001, g84_fifo_new },
.gr = { 0x00000001, gt215_gr_new },
.mspdec = { 0x00000001, gt215_mspdec_new },
.msppp = gt215_msppp_new,
.msppp = { 0x00000001, gt215_msppp_new },
.msvld = gt215_msvld_new,
.pm = gt215_pm_new,
.sw = nv50_sw_new,
......@@ -1232,7 +1232,7 @@ nva8_chipset = {
.fifo = { 0x00000001, g84_fifo_new },
.gr = { 0x00000001, gt215_gr_new },
.mspdec = { 0x00000001, gt215_mspdec_new },
.msppp = gt215_msppp_new,
.msppp = { 0x00000001, gt215_msppp_new },
.msvld = gt215_msvld_new,
.pm = gt215_pm_new,
.sw = nv50_sw_new,
......@@ -1263,7 +1263,7 @@ nvaa_chipset = {
.fifo = { 0x00000001, g84_fifo_new },
.gr = { 0x00000001, gt200_gr_new },
.mspdec = { 0x00000001, g98_mspdec_new },
.msppp = g98_msppp_new,
.msppp = { 0x00000001, g98_msppp_new },
.msvld = g98_msvld_new,
.pm = g84_pm_new,
.sec = g98_sec_new,
......@@ -1295,7 +1295,7 @@ nvac_chipset = {
.fifo = { 0x00000001, g84_fifo_new },
.gr = { 0x00000001, mcp79_gr_new },
.mspdec = { 0x00000001, g98_mspdec_new },
.msppp = g98_msppp_new,
.msppp = { 0x00000001, g98_msppp_new },
.msvld = g98_msvld_new,
.pm = g84_pm_new,
.sec = g98_sec_new,
......@@ -1329,7 +1329,7 @@ nvaf_chipset = {
.fifo = { 0x00000001, g84_fifo_new },
.gr = { 0x00000001, mcp89_gr_new },
.mspdec = { 0x00000001, gt215_mspdec_new },
.msppp = gt215_msppp_new,
.msppp = { 0x00000001, gt215_msppp_new },
.msvld = mcp89_msvld_new,
.pm = gt215_pm_new,
.sw = nv50_sw_new,
......@@ -1365,7 +1365,7 @@ nvc0_chipset = {
.fifo = { 0x00000001, gf100_fifo_new },
.gr = { 0x00000001, gf100_gr_new },
.mspdec = { 0x00000001, gf100_mspdec_new },
.msppp = gf100_msppp_new,
.msppp = { 0x00000001, gf100_msppp_new },
.msvld = gf100_msvld_new,
.pm = gf100_pm_new,
.sw = gf100_sw_new,
......@@ -1401,7 +1401,7 @@ nvc1_chipset = {
.fifo = { 0x00000001, gf100_fifo_new },
.gr = { 0x00000001, gf108_gr_new },
.mspdec = { 0x00000001, gf100_mspdec_new },
.msppp = gf100_msppp_new,
.msppp = { 0x00000001, gf100_msppp_new },
.msvld = gf100_msvld_new,
.pm = gf108_pm_new,
.sw = gf100_sw_new,
......@@ -1437,7 +1437,7 @@ nvc3_chipset = {
.fifo = { 0x00000001, gf100_fifo_new },
.gr = { 0x00000001, gf104_gr_new },
.mspdec = { 0x00000001, gf100_mspdec_new },
.msppp = gf100_msppp_new,
.msppp = { 0x00000001, gf100_msppp_new },
.msvld = gf100_msvld_new,
.pm = gf100_pm_new,
.sw = gf100_sw_new,
......@@ -1473,7 +1473,7 @@ nvc4_chipset = {
.fifo = { 0x00000001, gf100_fifo_new },
.gr = { 0x00000001, gf104_gr_new },
.mspdec = { 0x00000001, gf100_mspdec_new },
.msppp = gf100_msppp_new,
.msppp = { 0x00000001, gf100_msppp_new },
.msvld = gf100_msvld_new,
.pm = gf100_pm_new,
.sw = gf100_sw_new,
......@@ -1509,7 +1509,7 @@ nvc8_chipset = {
.fifo = { 0x00000001, gf100_fifo_new },
.gr = { 0x00000001, gf110_gr_new },
.mspdec = { 0x00000001, gf100_mspdec_new },
.msppp = gf100_msppp_new,
.msppp = { 0x00000001, gf100_msppp_new },
.msvld = gf100_msvld_new,
.pm = gf100_pm_new,
.sw = gf100_sw_new,
......@@ -1545,7 +1545,7 @@ nvce_chipset = {
.fifo = { 0x00000001, gf100_fifo_new },
.gr = { 0x00000001, gf104_gr_new },
.mspdec = { 0x00000001, gf100_mspdec_new },
.msppp = gf100_msppp_new,
.msppp = { 0x00000001, gf100_msppp_new },
.msvld = gf100_msvld_new,
.pm = gf100_pm_new,
.sw = gf100_sw_new,
......@@ -1581,7 +1581,7 @@ nvcf_chipset = {
.fifo = { 0x00000001, gf100_fifo_new },
.gr = { 0x00000001, gf104_gr_new },
.mspdec = { 0x00000001, gf100_mspdec_new },
.msppp = gf100_msppp_new,
.msppp = { 0x00000001, gf100_msppp_new },
.msvld = gf100_msvld_new,
.pm = gf100_pm_new,
.sw = gf100_sw_new,
......@@ -1616,7 +1616,7 @@ nvd7_chipset = {
.fifo = { 0x00000001, gf100_fifo_new },
.gr = { 0x00000001, gf117_gr_new },
.mspdec = { 0x00000001, gf100_mspdec_new },
.msppp = gf100_msppp_new,
.msppp = { 0x00000001, gf100_msppp_new },
.msvld = gf100_msvld_new,
.pm = gf117_pm_new,
.sw = gf100_sw_new,
......@@ -1652,7 +1652,7 @@ nvd9_chipset = {
.fifo = { 0x00000001, gf100_fifo_new },
.gr = { 0x00000001, gf119_gr_new },
.mspdec = { 0x00000001, gf100_mspdec_new },
.msppp = gf100_msppp_new,
.msppp = { 0x00000001, gf100_msppp_new },
.msvld = gf100_msvld_new,
.pm = gf117_pm_new,
.sw = gf100_sw_new,
......@@ -1689,7 +1689,7 @@ nve4_chipset = {
.fifo = { 0x00000001, gk104_fifo_new },
.gr = { 0x00000001, gk104_gr_new },
.mspdec = { 0x00000001, gk104_mspdec_new },
.msppp = gf100_msppp_new,
.msppp = { 0x00000001, gf100_msppp_new },
.msvld = gk104_msvld_new,
.pm = gk104_pm_new,
.sw = gf100_sw_new,
......@@ -1726,7 +1726,7 @@ nve6_chipset = {
.fifo = { 0x00000001, gk104_fifo_new },
.gr = { 0x00000001, gk104_gr_new },
.mspdec = { 0x00000001, gk104_mspdec_new },
.msppp = gf100_msppp_new,
.msppp = { 0x00000001, gf100_msppp_new },
.msvld = gk104_msvld_new,
.pm = gk104_pm_new,
.sw = gf100_sw_new,
......@@ -1763,7 +1763,7 @@ nve7_chipset = {
.fifo = { 0x00000001, gk104_fifo_new },
.gr = { 0x00000001, gk104_gr_new },
.mspdec = { 0x00000001, gk104_mspdec_new },
.msppp = gf100_msppp_new,
.msppp = { 0x00000001, gf100_msppp_new },
.msvld = gk104_msvld_new,
.pm = gk104_pm_new,
.sw = gf100_sw_new,
......@@ -1825,7 +1825,7 @@ nvf0_chipset = {
.fifo = { 0x00000001, gk110_fifo_new },
.gr = { 0x00000001, gk110_gr_new },
.mspdec = { 0x00000001, gk104_mspdec_new },
.msppp = gf100_msppp_new,
.msppp = { 0x00000001, gf100_msppp_new },
.msvld = gk104_msvld_new,
.sw = gf100_sw_new,
};
......@@ -1861,7 +1861,7 @@ nvf1_chipset = {
.fifo = { 0x00000001, gk110_fifo_new },
.gr = { 0x00000001, gk110b_gr_new },
.mspdec = { 0x00000001, gk104_mspdec_new },
.msppp = gf100_msppp_new,
.msppp = { 0x00000001, gf100_msppp_new },
.msvld = gk104_msvld_new,
.sw = gf100_sw_new,
};
......@@ -1897,7 +1897,7 @@ nv106_chipset = {
.fifo = { 0x00000001, gk208_fifo_new },
.gr = { 0x00000001, gk208_gr_new },
.mspdec = { 0x00000001, gk104_mspdec_new },
.msppp = gf100_msppp_new,
.msppp = { 0x00000001, gf100_msppp_new },
.msvld = gk104_msvld_new,
.sw = gf100_sw_new,
};
......@@ -1933,7 +1933,7 @@ nv108_chipset = {
.fifo = { 0x00000001, gk208_fifo_new },
.gr = { 0x00000001, gk208_gr_new },
.mspdec = { 0x00000001, gk104_mspdec_new },
.msppp = gf100_msppp_new,
.msppp = { 0x00000001, gf100_msppp_new },
.msvld = gk104_msvld_new,
.sw = gf100_sw_new,
};
......@@ -3174,7 +3174,6 @@ nvkm_device_ctor(const struct nvkm_device_func *func,
#include <core/layout.h>
#undef NVKM_LAYOUT_INST
#undef NVKM_LAYOUT_ONCE
_(NVKM_ENGINE_MSPPP , msppp);
_(NVKM_ENGINE_MSVLD , msvld);
_(NVKM_ENGINE_NVENC0 , nvenc[0]);
_(NVKM_ENGINE_NVENC1 , nvenc[1]);
......
drivers/gpu/drm/nouveau/nvkm/engine/msppp/base.c
View file @ 07a356bb
......@@ -25,7 +25,7 @@
int
nvkm_msppp_new_(const struct nvkm_falcon_func *func, struct nvkm_device *device,
int index, struct nvkm_engine **pengine)
enum nvkm_subdev_type type, int inst, struct nvkm_engine **pengine)
{
return nvkm_falcon_new_(func, device, index, true, 0x086000, pengine);
return nvkm_falcon_new_(func, device, type, inst, true, 0x086000, pengine);
}
drivers/gpu/drm/nouveau/nvkm/engine/msppp/g98.c
View file @ 07a356bb
......@@ -43,8 +43,8 @@ g98_msppp = {
};
int
g98_msppp_new(struct nvkm_device *device, int index,
g98_msppp_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
struct nvkm_engine **pengine)
{
return nvkm_msppp_new_(&g98_msppp, device, index, pengine);
return nvkm_msppp_new_(&g98_msppp, device, type, inst, pengine);
}
drivers/gpu/drm/nouveau/nvkm/engine/msppp/gf100.c
View file @ 07a356bb
......@@ -43,8 +43,8 @@ gf100_msppp = {
};
int
gf100_msppp_new(struct nvkm_device *device, int index,
gf100_msppp_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
struct nvkm_engine **pengine)
{
return nvkm_msppp_new_(&gf100_msppp, device, index, pengine);
return nvkm_msppp_new_(&gf100_msppp, device, type, inst, pengine);
}
drivers/gpu/drm/nouveau/nvkm/engine/msppp/gt215.c
View file @ 07a356bb
......@@ -35,8 +35,8 @@ gt215_msppp = {
};
int
gt215_msppp_new(struct nvkm_device *device, int index,
gt215_msppp_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
struct nvkm_engine **pengine)
{
return nvkm_msppp_new_(&gt215_msppp, device, index, pengine);
return nvkm_msppp_new_(&gt215_msppp, device, type, inst, pengine);
}
drivers/gpu/drm/nouveau/nvkm/engine/msppp/priv.h
View file @ 07a356bb
......@@ -3,8 +3,8 @@
#define __NVKM_MSPPP_PRIV_H__
#include <engine/msppp.h>
int nvkm_msppp_new_(const struct nvkm_falcon_func *, struct nvkm_device *,
int index, struct nvkm_engine **);
int nvkm_msppp_new_(const struct nvkm_falcon_func *, struct nvkm_device *, enum nvkm_subdev_type,
int, struct nvkm_engine **);
void g98_msppp_init(struct nvkm_falcon *);
#endif
drivers/gpu/drm/nouveau/nvkm/subdev/devinit/g98.c
View file @ 07a356bb
......@@ -37,7 +37,7 @@ g98_devinit_disable(struct nvkm_devinit *init)
if (!(r001540 & 0x40000000)) {
nvkm_subdev_disable(device, NVKM_ENGINE_MSPDEC, 0);
disable |= (1ULL << NVKM_ENGINE_MSVLD);
disable |= (1ULL << NVKM_ENGINE_MSPPP);
nvkm_subdev_disable(device, NVKM_ENGINE_MSPPP, 0);
}
if (!(r00154c & 0x00000004))
......
drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gf100.c
View file @ 07a356bb
......@@ -75,7 +75,7 @@ gf100_devinit_disable(struct nvkm_devinit *init)
if (r022500 & 0x00000002) {
nvkm_subdev_disable(device, NVKM_ENGINE_MSPDEC, 0);
disable |= (1ULL << NVKM_ENGINE_MSPPP);
nvkm_subdev_disable(device, NVKM_ENGINE_MSPPP, 0);
}
if (r022500 & 0x00000004)
......
drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gt215.c
View file @ 07a356bb
......@@ -72,7 +72,7 @@ gt215_devinit_disable(struct nvkm_devinit *init)
if (!(r001540 & 0x40000000)) {
nvkm_subdev_disable(device, NVKM_ENGINE_MSPDEC, 0);
disable |= (1ULL << NVKM_ENGINE_MSPPP);
nvkm_subdev_disable(device, NVKM_ENGINE_MSPPP, 0);
}
if (!(r00154c & 0x00000004))
......
drivers/gpu/drm/nouveau/nvkm/subdev/devinit/mcp89.c
View file @ 07a356bb
......@@ -36,7 +36,7 @@ mcp89_devinit_disable(struct nvkm_devinit *init)
if (!(r001540 & 0x40000000)) {
nvkm_subdev_disable(device, NVKM_ENGINE_MSPDEC, 0);
disable |= (1ULL << NVKM_ENGINE_MSPPP);
nvkm_subdev_disable(device, NVKM_ENGINE_MSPPP, 0);
}
if (!(r00154c & 0x00000004))
......
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