Skip to content

L
linux
Commit 09377d52 authored by Christopher Goldfarb's avatar Christopher Goldfarb Committed by Jeff Garzik
Browse files
Options

e1000 net drvr update 2/13: 

Update to low level hardware code.  Adds support for the new 
82540 device.  Replaces e1000_mac.c e1000_mac.h e1000_phy.c and 
e1000_phy.h with e1000_hw.c and e1000_hw.c.  Changes to the 
makefile, header includes, and some minor function syntax 
changes to get the driver working with the new code.
parent 6d87fb78
Hide whitespace changes
Inline Side-by-side
Showing with 3767 additions and 2084 deletions
drivers/net/e1000/Makefile
View file @ 09377d52
......@@ -9,8 +9,7 @@
O_TARGET := e1000.o
obj-y := e1000_main.o e1000_mac.o e1000_phy.o \
e1000_ethtool.o e1000_param.o e1000_proc.o
obj-y := e1000_main.o e1000_hw.o e1000_ethtool.o e1000_param.o e1000_proc.o
obj-m := $(O_TARGET)
include $(TOPDIR)/Rules.make
drivers/net/e1000/e1000.h
View file @ 09377d52
......@@ -111,8 +111,7 @@
struct e1000_adapter;
#include "e1000_mac.h"
#include "e1000_phy.h"
#include "e1000_hw.h"
#define BAR_0 0
......@@ -219,9 +218,9 @@ struct e1000_adapter {
struct pci_dev *pdev;
struct net_device_stats net_stats;
/* structs defined in e1000_mac.h or e1000_phy.h */
struct e1000_shared_adapter shared;
struct e1000_shared_stats stats;
/* structs defined in e1000_hw.h */
struct e1000_hw shared;
struct e1000_hw_stats stats;
struct e1000_phy_info phy_info;
struct e1000_phy_stats phy_stats;
};
......
drivers/net/e1000/e1000_ethtool.c
View file @ 09377d52
......@@ -88,7 +88,7 @@ extern void e1000_enable_WOL(struct e1000_adapter *adapter);
static void
e1000_ethtool_gset(struct e1000_adapter *adapter, struct ethtool_cmd *ecmd)
{
struct e1000_shared_adapter *shared = &adapter->shared;
struct e1000_hw *shared = &adapter->shared;
if(shared->media_type == e1000_media_type_copper) {
......@@ -158,7 +158,7 @@ e1000_ethtool_gset(struct e1000_adapter *adapter, struct ethtool_cmd *ecmd)
static int
e1000_ethtool_sset(struct e1000_adapter *adapter, struct ethtool_cmd *ecmd)
{
struct e1000_shared_adapter *shared = &adapter->shared;
struct e1000_hw *shared = &adapter->shared;
if(ecmd->autoneg == AUTONEG_ENABLE) {
shared->autoneg = 1;
......@@ -197,9 +197,13 @@ e1000_ethtool_sset(struct e1000_adapter *adapter, struct ethtool_cmd *ecmd)
}
static inline int
e1000_eeprom_size(struct e1000_shared_adapter *shared)
e1000_eeprom_size(struct e1000_hw *shared)
{
return 128;
if((shared->mac_type > e1000_82544) &&
(E1000_READ_REG(shared, EECD) & E1000_EECD_SIZE))
return 512;
else
return 128;
}
static void
......@@ -218,7 +222,7 @@ static void
e1000_ethtool_geeprom(struct e1000_adapter *adapter,
struct ethtool_eeprom *eeprom, uint16_t *eeprom_buff)
{
struct e1000_shared_adapter *shared = &adapter->shared;
struct e1000_hw *shared = &adapter->shared;
int i, max_len;
eeprom->magic = shared->vendor_id | (shared->device_id << 16);
......@@ -229,15 +233,13 @@ e1000_ethtool_geeprom(struct e1000_adapter *adapter,
eeprom->len = (max_len - eeprom->offset);
for(i = 0; i < max_len; i++)
eeprom_buff[i] = e1000_read_eeprom(&adapter->shared, i);
return;
e1000_read_eeprom(&adapter->shared, i, &eeprom_buff[i]);
}
static void
e1000_ethtool_gwol(struct e1000_adapter *adapter, struct ethtool_wolinfo *wol)
{
struct e1000_shared_adapter *shared = &adapter->shared;
struct e1000_hw *shared = &adapter->shared;
if(shared->mac_type < e1000_82544) {
wol->supported = 0;
......@@ -266,7 +268,7 @@ e1000_ethtool_gwol(struct e1000_adapter *adapter, struct ethtool_wolinfo *wol)
static int
e1000_ethtool_swol(struct e1000_adapter *adapter, struct ethtool_wolinfo *wol)
{
struct e1000_shared_adapter *shared = &adapter->shared;
struct e1000_hw *shared = &adapter->shared;
if(shared->mac_type < e1000_82544)
return wol->wolopts == 0 ? 0 : -EOPNOTSUPP;
......
drivers/net/e1000/e1000_mac.c → drivers/net/e1000/e1000_hw.c
View file @ 09377d52
This source diff could not be displayed because it is too large. You can view the blob instead.
drivers/net/e1000/e1000_mac.h → drivers/net/e1000/e1000_hw.h
View file @ 09377d52
......@@ -2,9 +2,8 @@
This software program is available to you under a choice of one of two
licenses. You may choose to be licensed under either the GNU General Public
License (GPL) Version 2, June 1991, available at
http://www.fsf.org/copyleft/gpl.html, or the Intel BSD + Patent License, the
text of which follows:
License 2.0, June 1991, available at http://www.fsf.org/copyleft/gpl.html,
or the Intel BSD + Patent License, the text of which follows:
Recipient has requested a license and Intel Corporation ("Intel") is willing
to grant a license for the software entitled Linux Base Driver for the
......@@ -18,7 +17,7 @@
"Recipient" means the party to whom Intel delivers this Software.
"Licensee" means Recipient and those third parties that receive a license to
any operating system available under the GNU Public License version 2.0 or
any operating system available under the GNU General Public License 2.0 or
later.
Copyright (c) 1999 - 2002 Intel Corporation.
......@@ -51,10 +50,10 @@
version of an operating system that has been distributed under the GNU
General Public License 2.0 or later. This patent license shall apply to the
combination of the Software and any operating system licensed under the GNU
Public License version 2.0 or later if, at the time Intel provides the
General Public License 2.0 or later if, at the time Intel provides the
Software to Recipient, such addition of the Software to the then publicly
available versions of such operating systems available under the GNU Public
License version 2.0 or later (whether in gold, beta or alpha form) causes
available versions of such operating systems available under the GNU General
Public License 2.0 or later (whether in gold, beta or alpha form) causes
such combination to be covered by the Licensed Patents. The patent license
shall not apply to any other combinations which include the Software. NO
hardware per se is licensed hereunder.
......@@ -72,18 +71,18 @@
*******************************************************************************/
/* e1000_mac.h
/* e1000_hw.h
* Structures, enums, and macros for the MAC
*/
#ifndef _E1000_MAC_H_
#define _E1000_MAC_H_
#ifndef _E1000_HW_H_
#define _E1000_HW_H_
#include "e1000_osdep.h"
/* Forward declarations of structures used by the shared code */
struct e1000_shared_adapter;
struct e1000_shared_stats;
struct e1000_hw;
struct e1000_hw_stats;
/* Enumerated types specific to the e1000 hardware */
/* Media Access Controlers */
......@@ -92,6 +91,7 @@ typedef enum {
e1000_82542_rev2_1,
e1000_82543,
e1000_82544,
e1000_82540,
e1000_num_macs
} e1000_mac_type;
......@@ -142,40 +142,125 @@ typedef enum {
e1000_bus_width_64
} e1000_bus_width;
/* PHY status info structure and supporting enums */
typedef enum {
e1000_cable_length_50 = 0,
e1000_cable_length_50_80,
e1000_cable_length_80_110,
e1000_cable_length_110_140,
e1000_cable_length_140,
e1000_cable_length_undefined = 0xFF
} e1000_cable_length;
typedef enum {
e1000_10bt_ext_dist_enable_normal = 0,
e1000_10bt_ext_dist_enable_lower,
e1000_10bt_ext_dist_enable_undefined = 0xFF
} e1000_10bt_ext_dist_enable;
/* Function prototypes */
/* Setup */
void e1000_adapter_stop(struct e1000_shared_adapter *shared);
boolean_t e1000_init_hw(struct e1000_shared_adapter *shared);
void e1000_init_rx_addrs(struct e1000_shared_adapter *shared);
typedef enum {
e1000_rev_polarity_normal = 0,
e1000_rev_polarity_reversed,
e1000_rev_polarity_undefined = 0xFF
} e1000_rev_polarity;
/* Filters (multicast, vlan, receive) */
void e1000_mc_addr_list_update(struct e1000_shared_adapter *shared, uint8_t * mc_addr_list, uint32_t mc_addr_count, uint32_t pad);
uint32_t e1000_hash_mc_addr(struct e1000_shared_adapter *shared, uint8_t * mc_addr);
void e1000_mta_set(struct e1000_shared_adapter *shared, uint32_t hash_value);
void e1000_rar_set(struct e1000_shared_adapter *shared, uint8_t * mc_addr, uint32_t rar_index);
void e1000_write_vfta(struct e1000_shared_adapter *shared, uint32_t offset, uint32_t value);
void e1000_clear_vfta(struct e1000_shared_adapter *shared);
/* Link layer setup functions */
boolean_t e1000_setup_fc_and_link(struct e1000_shared_adapter *shared);
boolean_t e1000_setup_pcs_link(struct e1000_shared_adapter *shared, uint32_t dev_ctrl_reg);
void e1000_config_fc_after_link_up(struct e1000_shared_adapter *shared);
void e1000_check_for_link(struct e1000_shared_adapter *shared);
void e1000_get_speed_and_duplex(struct e1000_shared_adapter *shared, uint16_t * speed, uint16_t * duplex);
typedef enum {
e1000_polarity_reversal_enabled = 0,
e1000_polarity_reversal_disabled,
e1000_polarity_reversal_undefined = 0xFF
} e1000_polarity_reversal;
typedef enum {
e1000_auto_x_mode_manual_mdi = 0,
e1000_auto_x_mode_manual_mdix,
e1000_auto_x_mode_auto1,
e1000_auto_x_mode_auto2,
e1000_auto_x_mode_undefined = 0xFF
} e1000_auto_x_mode;
typedef enum {
e1000_1000t_rx_status_not_ok = 0,
e1000_1000t_rx_status_ok,
e1000_1000t_rx_status_undefined = 0xFF
} e1000_1000t_rx_status;
struct e1000_phy_info {
e1000_cable_length cable_length;
e1000_10bt_ext_dist_enable extended_10bt_distance;
e1000_rev_polarity cable_polarity;
e1000_polarity_reversal polarity_correction;
e1000_auto_x_mode mdix_mode;
e1000_1000t_rx_status local_rx;
e1000_1000t_rx_status remote_rx;
};
struct e1000_phy_stats {
uint32_t idle_errors;
uint32_t receive_errors;
};
/* Error Codes */
#define E1000_SUCCESS 0
#define E1000_ERR_EEPROM 1
#define E1000_ERR_PHY 2
#define E1000_ERR_CONFIG 3
#define E1000_ERR_PARAM 4
/* Function prototypes */
/* Initialization */
void e1000_reset_hw(struct e1000_hw *hw);
int32_t e1000_init_hw(struct e1000_hw *hw);
/* Link Configuration */
int32_t e1000_setup_link(struct e1000_hw *hw);
int32_t e1000_phy_setup_autoneg(struct e1000_hw *hw);
void e1000_config_collision_dist(struct e1000_hw *hw);
int32_t e1000_config_fc_after_link_up(struct e1000_hw *hw);
int32_t e1000_check_for_link(struct e1000_hw *hw);
void e1000_get_speed_and_duplex(struct e1000_hw *hw, uint16_t * speed, uint16_t * duplex);
int32_t e1000_wait_autoneg(struct e1000_hw *hw);
/* PHY */
int32_t e1000_read_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t *phy_data);
int32_t e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t data);
void e1000_phy_hw_reset(struct e1000_hw *hw);
int32_t e1000_phy_reset(struct e1000_hw *hw);
int32_t e1000_detect_gig_phy(struct e1000_hw *hw);
int32_t e1000_phy_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info);
int32_t e1000_validate_mdi_setting(struct e1000_hw *hw);
/* EEPROM Functions */
uint16_t e1000_read_eeprom(struct e1000_shared_adapter *shared, uint16_t reg);
boolean_t e1000_validate_eeprom_checksum(struct e1000_shared_adapter *shared);
int32_t e1000_read_eeprom(struct e1000_hw *hw, uint16_t reg, uint16_t *data);
int32_t e1000_validate_eeprom_checksum(struct e1000_hw *hw);
int32_t e1000_read_part_num(struct e1000_hw *hw, uint32_t * part_num);
int32_t e1000_read_mac_addr(struct e1000_hw * hw);
/* Filters (multicast, vlan, receive) */
void e1000_init_rx_addrs(struct e1000_hw *hw);
void e1000_mc_addr_list_update(struct e1000_hw *hw, uint8_t * mc_addr_list, uint32_t mc_addr_count, uint32_t pad);
uint32_t e1000_hash_mc_addr(struct e1000_hw *hw, uint8_t * mc_addr);
void e1000_mta_set(struct e1000_hw *hw, uint32_t hash_value);
void e1000_rar_set(struct e1000_hw *hw, uint8_t * mc_addr, uint32_t rar_index);
void e1000_write_vfta(struct e1000_hw *hw, uint32_t offset, uint32_t value);
void e1000_clear_vfta(struct e1000_hw *hw);
/* LED functions */
int32_t e1000_setup_led(struct e1000_hw *hw);
int32_t e1000_cleanup_led(struct e1000_hw *hw);
int32_t e1000_led_on(struct e1000_hw *hw);
int32_t e1000_led_off(struct e1000_hw *hw);
/* Adaptive IFS Functions */
/* Everything else */
void e1000_clear_hw_cntrs(struct e1000_shared_adapter *shared);
boolean_t e1000_read_part_num(struct e1000_shared_adapter *shared, uint32_t * part_num);
void e1000_read_mac_addr(struct e1000_shared_adapter * shared);
void e1000_get_bus_info(struct e1000_shared_adapter *shared);
uint32_t e1000_tbi_adjust_stats(struct e1000_shared_adapter *shared, struct e1000_shared_stats *stats, uint32_t frame_len, uint8_t * mac_addr);
void e1000_write_pci_cfg(struct e1000_shared_adapter *shared, uint32_t reg, uint16_t * value);
void e1000_clear_hw_cntrs(struct e1000_hw *hw);
void e1000_reset_adaptive(struct e1000_hw *hw);
void e1000_update_adaptive(struct e1000_hw *hw);
void e1000_tbi_adjust_stats(struct e1000_hw *hw, struct e1000_hw_stats *stats, uint32_t frame_len, uint8_t * mac_addr);
void e1000_get_bus_info(struct e1000_hw *hw);
void e1000_write_pci_cfg(struct e1000_hw *hw, uint32_t reg, uint16_t * value);
/* PCI Device IDs */
#define E1000_DEV_ID_82542 0x1000
......@@ -185,7 +270,9 @@ void e1000_write_pci_cfg(struct e1000_shared_adapter *shared, uint32_t reg, uint
#define E1000_DEV_ID_82544EI_FIBER 0x1009
#define E1000_DEV_ID_82544GC_COPPER 0x100C
#define E1000_DEV_ID_82544GC_LOM 0x100D
#define NUM_DEV_IDS 7
#define E1000_DEV_ID_82540EM 0x100E
#define E1000_DEV_ID_82540EM_LOM 0x1015
#define NUM_DEV_IDS 9
#define NODE_ADDRESS_SIZE 6
#define ETH_LENGTH_OF_ADDRESS 6
......@@ -204,9 +291,14 @@ void e1000_write_pci_cfg(struct e1000_shared_adapter *shared, uint32_t reg, uint
/* The sizes (in bytes) of a ethernet packet */
#define ENET_HEADER_SIZE 14
#define MAXIMUM_ETHERNET_PACKET_SIZE 1514 /* Without FCS */
#define MINIMUM_ETHERNET_PACKET_SIZE 60 /* Without FCS */
#define CRC_LENGTH 4
#define MAXIMUM_ETHERNET_FRAME_SIZE 1518 /* With FCS */
#define MINIMUM_ETHERNET_FRAME_SIZE 64 /* With FCS */
#define ETHERNET_FCS_SIZE 4
#define MAXIMUM_ETHERNET_PACKET_SIZE \
(MAXIMUM_ETHERNET_FRAME_SIZE - ETHERNET_FCS_SIZE)
#define MINIMUM_ETHERNET_PACKET_SIZE \
(MINIMUM_ETHERNET_FRAME_SIZE - ETHERNET_FCS_SIZE)
#define CRC_LENGTH ETHERNET_FCS_SIZE
#define MAX_JUMBO_FRAME_SIZE 0x3F00
......@@ -481,6 +573,7 @@ struct e1000_ffvt_entry {
#define E1000_TCTL 0x00400 /* TX Control - RW */
#define E1000_TIPG 0x00410 /* TX Inter-packet gap -RW */
#define E1000_TBT 0x00448 /* TX Burst Timer - RW */
#define E1000_AIT 0x00458 /* Adaptive Interframe Spacing Throttle - RW */
#define E1000_LEDCTL 0x00E00 /* LED Control - RW */
#define E1000_PBA 0x01000 /* Packet Buffer Allocation - RW */
#define E1000_FCRTL 0x02160 /* Flow Control Receive Threshold Low - RW */
......@@ -623,6 +716,7 @@ struct e1000_ffvt_entry {
#define E1000_82542_TDT 0x00438
#define E1000_82542_TIDV 0x00440
#define E1000_82542_TBT E1000_TBT
#define E1000_82542_AIT E1000_AIT
#define E1000_82542_VFTA 0x00600
#define E1000_82542_LEDCTL E1000_LEDCTL
#define E1000_82542_PBA E1000_PBA
......@@ -706,7 +800,7 @@ struct e1000_ffvt_entry {
#define E1000_82542_FFVT E1000_FFVT
/* Statistics counters collected by the MAC */
struct e1000_shared_stats {
struct e1000_hw_stats {
uint64_t crcerrs;
uint64_t algnerrc;
uint64_t symerrs;
......@@ -767,10 +861,8 @@ struct e1000_shared_stats {
uint64_t tsctfc;
};
/* Structure containing variables used by the shared code (e1000_mac.c and
* e1000_phy.c)
*/
struct e1000_shared_adapter {
/* Structure containing variables used by the shared code (e1000_hw.c) */
struct e1000_hw {
uint8_t *hw_addr;
e1000_mac_type mac_type;
e1000_media_type media_type;
......@@ -782,29 +874,30 @@ struct e1000_shared_adapter {
uint32_t phy_id;
uint32_t phy_addr;
uint32_t original_fc;
uint32_t txcw_reg;
uint32_t txcw;
uint32_t autoneg_failed;
uint32_t max_frame_size;
uint32_t min_frame_size;
uint32_t mc_filter_type;
uint32_t num_mc_addrs;
uint32_t collision_delta;
uint32_t tx_packet_delta;
uint32_t ledctl;
uint16_t autoneg_advertised;
uint16_t pci_cmd_word;
uint16_t fc_high_water;
uint16_t fc_low_water;
uint16_t fc_pause_time;
uint16_t current_ifs_val;
uint16_t ifs_min_val;
uint16_t ifs_max_val;
uint16_t ifs_step_size;
uint16_t ifs_ratio;
uint16_t device_id;
uint16_t vendor_id;
uint16_t subsystem_id;
uint16_t subsystem_vendor_id;
uint8_t revision_id;
boolean_t disable_polarity_correction;
boolean_t get_link_status;
boolean_t tbi_compatibility_en;
boolean_t tbi_compatibility_on;
boolean_t adapter_stopped;
boolean_t fc_send_xon;
boolean_t report_tx_early;
uint8_t autoneg;
uint8_t mdix;
uint8_t forced_speed_duplex;
......@@ -812,6 +905,15 @@ struct e1000_shared_adapter {
uint8_t dma_fairness;
uint8_t mac_addr[NODE_ADDRESS_SIZE];
uint8_t perm_mac_addr[NODE_ADDRESS_SIZE];
boolean_t disable_polarity_correction;
boolean_t get_link_status;
boolean_t tbi_compatibility_en;
boolean_t tbi_compatibility_on;
boolean_t fc_send_xon;
boolean_t report_tx_early;
boolean_t adaptive_ifs;
boolean_t ifs_params_forced;
boolean_t in_ifs_mode;
};
......@@ -1254,8 +1356,9 @@ struct e1000_shared_adapter {
/* Collision related configuration parameters */
#define E1000_COLLISION_THRESHOLD 16
#define E1000_CT_SHIFT 4
#define E1000_FDX_COLLISION_DISTANCE 64
#define E1000_HDX_COLLISION_DISTANCE 64
#define E1000_COLLISION_DISTANCE 64
#define E1000_FDX_COLLISION_DISTANCE E1000_COLLISION_DISTANCE
#define E1000_HDX_COLLISION_DISTANCE E1000_COLLISION_DISTANCE
#define E1000_GB_HDX_COLLISION_DISTANCE 512
#define E1000_COLD_SHIFT 12
......@@ -1282,6 +1385,19 @@ struct e1000_shared_adapter {
#define E1000_TXDMAC_DPP 0x00000001
/* Adaptive IFS defines */
#define TX_THRESHOLD_START 8
#define TX_THRESHOLD_INCREMENT 10
#define TX_THRESHOLD_DECREMENT 1
#define TX_THRESHOLD_STOP 190
#define TX_THRESHOLD_DISABLE 0
#define TX_THRESHOLD_TIMER_MS 10000
#define MIN_NUM_XMITS 1000
#define IFS_MAX 80
#define IFS_STEP 10
#define IFS_MIN 40
#define IFS_RATIO 4
/* PBA constants */
#define E1000_PBA_16K 0x0010 /* 16KB, default TX allocation */
#define E1000_PBA_24K 0x0018
......@@ -1336,18 +1452,10 @@ struct e1000_shared_adapter {
#define CARRIER_EXTENSION 0x0F
/* TBI_ACCEPT macro definition:
*
* If Tbi Compatibility mode is turned-on, then we should accept frames with
* receive errors if and only if:
* 1) errors is equal to the CRC error bit.
* 2) The last byte is a Carrier extension (0x0F).
* 3) The frame length (as reported by Hardware) is greater than 64 (60
* if a VLAN tag was stripped from the frame.
* 4) " " " " " " " <= max_frame_size+1.
*
* This macro requires:
* adapter = a pointer to struct e1000_shared_adapter
* special = the 16 bit special field of the RX descriptor with EOP set
* adapter = a pointer to struct e1000_hw
* status = the 8 bit status field of the RX descriptor with EOP set
* error = the 8 bit error field of the RX descriptor with EOP set
* length = the sum of all the length fields of the RX descriptors that
* make up the current frame
......@@ -1370,14 +1478,290 @@ struct e1000_shared_adapter {
* ...
*/
#define TBI_ACCEPT(adapter, special, errors, length, last_byte) \
#define TBI_ACCEPT(adapter, status, errors, length, last_byte) \
((adapter)->tbi_compatibility_on && \
(((errors) & E1000_RXD_ERR_FRAME_ERR_MASK) == E1000_RXD_ERR_CE) && \
((last_byte) == CARRIER_EXTENSION) && \
((length) <= ((adapter)->max_frame_size + 1)) && \
((length) > ((special == 0x0000) ? \
((adapter)->min_frame_size) : \
((adapter)->min_frame_size - VLAN_TAG_SIZE))))
(((status) & E1000_RXD_STAT_VP) ? \
(((length) > ((adapter)->min_frame_size - VLAN_TAG_SIZE)) && \
((length) <= ((adapter)->max_frame_size + 1))) : \
(((length) > (adapter)->min_frame_size) && \
((length) <= ((adapter)->max_frame_size + VLAN_TAG_SIZE + 1)))))
#endif /* _E1000_MAC_H_ */
/* Structures, enums, and macros for the PHY */
/* Bit definitions for the Management Data IO (MDIO) and Management Data
* Clock (MDC) pins in the Device Control Register.
*/
#define E1000_CTRL_PHY_RESET_DIR E1000_CTRL_SWDPIO0
#define E1000_CTRL_PHY_RESET E1000_CTRL_SWDPIN0
#define E1000_CTRL_MDIO_DIR E1000_CTRL_SWDPIO2
#define E1000_CTRL_MDIO E1000_CTRL_SWDPIN2
#define E1000_CTRL_MDC_DIR E1000_CTRL_SWDPIO3
#define E1000_CTRL_MDC E1000_CTRL_SWDPIN3
#define E1000_CTRL_PHY_RESET_DIR4 E1000_CTRL_EXT_SDP4_DIR
#define E1000_CTRL_PHY_RESET4 E1000_CTRL_EXT_SDP4_DATA
/* PHY 1000 MII Register/Bit Definitions */
/* PHY Registers defined by IEEE */
#define PHY_CTRL 0x00 /* Control Register */
#define PHY_STATUS 0x01 /* Status Regiser */
#define PHY_ID1 0x02 /* Phy Id Reg (word 1) */
#define PHY_ID2 0x03 /* Phy Id Reg (word 2) */
#define PHY_AUTONEG_ADV 0x04 /* Autoneg Advertisement */
#define PHY_LP_ABILITY 0x05 /* Link Partner Ability (Base Page) */
#define PHY_AUTONEG_EXP 0x06 /* Autoneg Expansion Reg */
#define PHY_NEXT_PAGE_TX 0x07 /* Next Page TX */
#define PHY_LP_NEXT_PAGE 0x08 /* Link Partner Next Page */
#define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Reg */
#define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */
#define PHY_EXT_STATUS 0x0F /* Extended Status Reg */
/* M88E1000 Specific Registers */
#define M88E1000_PHY_SPEC_CTRL 0x10 /* PHY Specific Control Register */
#define M88E1000_PHY_SPEC_STATUS 0x11 /* PHY Specific Status Register */
#define M88E1000_INT_ENABLE 0x12 /* Interrupt Enable Register */
#define M88E1000_INT_STATUS 0x13 /* Interrupt Status Register */
#define M88E1000_EXT_PHY_SPEC_CTRL 0x14 /* Extended PHY Specific Control */
#define M88E1000_RX_ERR_CNTR 0x15 /* Receive Error Counter */
#define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */
/* PHY Control Register */
#define MII_CR_SPEED_SELECT_MSB 0x0040 /* bits 6,13: 10=1000, 01=100, 00=10 */
#define MII_CR_COLL_TEST_ENABLE 0x0080 /* Collision test enable */
#define MII_CR_FULL_DUPLEX 0x0100 /* FDX =1, half duplex =0 */
#define MII_CR_RESTART_AUTO_NEG 0x0200 /* Restart auto negotiation */
#define MII_CR_ISOLATE 0x0400 /* Isolate PHY from MII */
#define MII_CR_POWER_DOWN 0x0800 /* Power down */
#define MII_CR_AUTO_NEG_EN 0x1000 /* Auto Neg Enable */
#define MII_CR_SPEED_SELECT_LSB 0x2000 /* bits 6,13: 10=1000, 01=100, 00=10 */
#define MII_CR_LOOPBACK 0x4000 /* 0 = normal, 1 = loopback */
#define MII_CR_RESET 0x8000 /* 0 = normal, 1 = PHY reset */
/* PHY Status Register */
#define MII_SR_EXTENDED_CAPS 0x0001 /* Extended register capabilities */
#define MII_SR_JABBER_DETECT 0x0002 /* Jabber Detected */
#define MII_SR_LINK_STATUS 0x0004 /* Link Status 1 = link */
#define MII_SR_AUTONEG_CAPS 0x0008 /* Auto Neg Capable */
#define MII_SR_REMOTE_FAULT 0x0010 /* Remote Fault Detect */
#define MII_SR_AUTONEG_COMPLETE 0x0020 /* Auto Neg Complete */
#define MII_SR_PREAMBLE_SUPPRESS 0x0040 /* Preamble may be suppressed */
#define MII_SR_EXTENDED_STATUS 0x0100 /* Ext. status info in Reg 0x0F */
#define MII_SR_100T2_HD_CAPS 0x0200 /* 100T2 Half Duplex Capable */
#define MII_SR_100T2_FD_CAPS 0x0400 /* 100T2 Full Duplex Capable */
#define MII_SR_10T_HD_CAPS 0x0800 /* 10T Half Duplex Capable */
#define MII_SR_10T_FD_CAPS 0x1000 /* 10T Full Duplex Capable */
#define MII_SR_100X_HD_CAPS 0x2000 /* 100X Half Duplex Capable */
#define MII_SR_100X_FD_CAPS 0x4000 /* 100X Full Duplex Capable */
#define MII_SR_100T4_CAPS 0x8000 /* 100T4 Capable */
/* Autoneg Advertisement Register */
#define NWAY_AR_SELECTOR_FIELD 0x0001 /* indicates IEEE 802.3 CSMA/CD */
#define NWAY_AR_10T_HD_CAPS 0x0020 /* 10T Half Duplex Capable */
#define NWAY_AR_10T_FD_CAPS 0x0040 /* 10T Full Duplex Capable */
#define NWAY_AR_100TX_HD_CAPS 0x0080 /* 100TX Half Duplex Capable */
#define NWAY_AR_100TX_FD_CAPS 0x0100 /* 100TX Full Duplex Capable */
#define NWAY_AR_100T4_CAPS 0x0200 /* 100T4 Capable */
#define NWAY_AR_PAUSE 0x0400 /* Pause operation desired */
#define NWAY_AR_ASM_DIR 0x0800 /* Asymmetric Pause Direction bit */
#define NWAY_AR_REMOTE_FAULT 0x2000 /* Remote Fault detected */
#define NWAY_AR_NEXT_PAGE 0x8000 /* Next Page ability supported */
/* Link Partner Ability Register (Base Page) */
#define NWAY_LPAR_SELECTOR_FIELD 0x0000 /* LP protocol selector field */
#define NWAY_LPAR_10T_HD_CAPS 0x0020 /* LP is 10T Half Duplex Capable */
#define NWAY_LPAR_10T_FD_CAPS 0x0040 /* LP is 10T Full Duplex Capable */
#define NWAY_LPAR_100TX_HD_CAPS 0x0080 /* LP is 100TX Half Duplex Capable */
#define NWAY_LPAR_100TX_FD_CAPS 0x0100 /* LP is 100TX Full Duplex Capable */
#define NWAY_LPAR_100T4_CAPS 0x0200 /* LP is 100T4 Capable */
#define NWAY_LPAR_PAUSE 0x0400 /* LP Pause operation desired */
#define NWAY_LPAR_ASM_DIR 0x0800 /* LP Asymmetric Pause Direction bit */
#define NWAY_LPAR_REMOTE_FAULT 0x2000 /* LP has detected Remote Fault */
#define NWAY_LPAR_ACKNOWLEDGE 0x4000 /* LP has rx'd link code word */
#define NWAY_LPAR_NEXT_PAGE 0x8000 /* Next Page ability supported */
/* Autoneg Expansion Register */
#define NWAY_ER_LP_NWAY_CAPS 0x0001 /* LP has Auto Neg Capability */
#define NWAY_ER_PAGE_RXD 0x0002 /* LP is 10T Half Duplex Capable */
#define NWAY_ER_NEXT_PAGE_CAPS 0x0004 /* LP is 10T Full Duplex Capable */
#define NWAY_ER_LP_NEXT_PAGE_CAPS 0x0008 /* LP is 100TX Half Duplex Capable */
#define NWAY_ER_PAR_DETECT_FAULT 0x0100 /* LP is 100TX Full Duplex Capable */
/* Next Page TX Register */
#define NPTX_MSG_CODE_FIELD 0x0001 /* NP msg code or unformatted data */
#define NPTX_TOGGLE 0x0800 /* Toggles between exchanges
* of different NP
*/
#define NPTX_ACKNOWLDGE2 0x1000 /* 1 = will comply with msg
* 0 = cannot comply with msg
*/
#define NPTX_MSG_PAGE 0x2000 /* formatted(1)/unformatted(0) pg */
#define NPTX_NEXT_PAGE 0x8000 /* 1 = addition NP will follow
* 0 = sending last NP
*/
/* Link Partner Next Page Register */
#define LP_RNPR_MSG_CODE_FIELD 0x0001 /* NP msg code or unformatted data */
#define LP_RNPR_TOGGLE 0x0800 /* Toggles between exchanges
* of different NP
*/
#define LP_RNPR_ACKNOWLDGE2 0x1000 /* 1 = will comply with msg
* 0 = cannot comply with msg
*/
#define LP_RNPR_MSG_PAGE 0x2000 /* formatted(1)/unformatted(0) pg */
#define LP_RNPR_ACKNOWLDGE 0x4000 /* 1 = ACK / 0 = NO ACK */
#define LP_RNPR_NEXT_PAGE 0x8000 /* 1 = addition NP will follow
* 0 = sending last NP
*/
/* 1000BASE-T Control Register */
#define CR_1000T_ASYM_PAUSE 0x0080 /* Advertise asymmetric pause bit */
#define CR_1000T_HD_CAPS 0x0100 /* Advertise 1000T HD capability */
#define CR_1000T_FD_CAPS 0x0200 /* Advertise 1000T FD capability */
#define CR_1000T_REPEATER_DTE 0x0400 /* 1=Repeater/switch device port */
/* 0=DTE device */
#define CR_1000T_MS_VALUE 0x0800 /* 1=Configure PHY as Master */
/* 0=Configure PHY as Slave */
#define CR_1000T_MS_ENABLE 0x1000 /* 1=Master/Slave manual config value */
/* 0=Automatic Master/Slave config */
#define CR_1000T_TEST_MODE_NORMAL 0x0000 /* Normal Operation */
#define CR_1000T_TEST_MODE_1 0x2000 /* Transmit Waveform test */
#define CR_1000T_TEST_MODE_2 0x4000 /* Master Transmit Jitter test */
#define CR_1000T_TEST_MODE_3 0x6000 /* Slave Transmit Jitter test */
#define CR_1000T_TEST_MODE_4 0x8000 /* Transmitter Distortion test */
/* 1000BASE-T Status Register */
#define SR_1000T_IDLE_ERROR_CNT 0x00FF /* Num idle errors since last read */
#define SR_1000T_ASYM_PAUSE_DIR 0x0100 /* LP asymmetric pause direction bit */
#define SR_1000T_LP_HD_CAPS 0x0400 /* LP is 1000T HD capable */
#define SR_1000T_LP_FD_CAPS 0x0800 /* LP is 1000T FD capable */
#define SR_1000T_REMOTE_RX_STATUS 0x1000 /* Remote receiver OK */
#define SR_1000T_LOCAL_RX_STATUS 0x2000 /* Local receiver OK */
#define SR_1000T_MS_CONFIG_RES 0x4000 /* 1=Local TX is Master, 0=Slave */
#define SR_1000T_MS_CONFIG_FAULT 0x8000 /* Master/Slave config fault */
#define SR_1000T_REMOTE_RX_STATUS_SHIFT 12
#define SR_1000T_LOCAL_RX_STATUS_SHIFT 13
/* Extended Status Register */
#define IEEE_ESR_1000T_HD_CAPS 0x1000 /* 1000T HD capable */
#define IEEE_ESR_1000T_FD_CAPS 0x2000 /* 1000T FD capable */
#define IEEE_ESR_1000X_HD_CAPS 0x4000 /* 1000X HD capable */
#define IEEE_ESR_1000X_FD_CAPS 0x8000 /* 1000X FD capable */
#define PHY_TX_POLARITY_MASK 0x0100 /* register 10h bit 8 (polarity bit) */
#define PHY_TX_NORMAL_POLARITY 0 /* register 10h bit 8 (normal polarity) */
#define AUTO_POLARITY_DISABLE 0x0010 /* register 11h bit 4 */
/* (0=enable, 1=disable) */
/* M88E1000 PHY Specific Control Register */
#define M88E1000_PSCR_JABBER_DISABLE 0x0001 /* 1=Jabber Function disabled */
#define M88E1000_PSCR_POLARITY_REVERSAL 0x0002 /* 1=Polarity Reversal enabled */
#define M88E1000_PSCR_SQE_TEST 0x0004 /* 1=SQE Test enabled */
#define M88E1000_PSCR_CLK125_DISABLE 0x0010 /* 1=CLK125 low,
* 0=CLK125 toggling
*/
#define M88E1000_PSCR_MDI_MANUAL_MODE 0x0000 /* MDI Crossover Mode bits 6:5 */
/* Manual MDI configuration */
#define M88E1000_PSCR_MDIX_MANUAL_MODE 0x0020 /* Manual MDIX configuration */
#define M88E1000_PSCR_AUTO_X_1000T 0x0040 /* 1000BASE-T: Auto crossover,
* 100BASE-TX/10BASE-T:
* MDI Mode
*/
#define M88E1000_PSCR_AUTO_X_MODE 0x0060 /* Auto crossover enabled
* all speeds.
*/
#define M88E1000_PSCR_10BT_EXT_DIST_ENABLE 0x0080
/* 1=Enable Extended 10BASE-T distance
* (Lower 10BASE-T RX Threshold)
* 0=Normal 10BASE-T RX Threshold */
#define M88E1000_PSCR_MII_5BIT_ENABLE 0x0100
/* 1=5-Bit interface in 100BASE-TX
* 0=MII interface in 100BASE-TX */
#define M88E1000_PSCR_SCRAMBLER_DISABLE 0x0200 /* 1=Scrambler disable */
#define M88E1000_PSCR_FORCE_LINK_GOOD 0x0400 /* 1=Force link good */
#define M88E1000_PSCR_ASSERT_CRS_ON_TX 0x0800 /* 1=Assert CRS on Transmit */
#define M88E1000_PSCR_POLARITY_REVERSAL_SHIFT 1
#define M88E1000_PSCR_AUTO_X_MODE_SHIFT 5
#define M88E1000_PSCR_10BT_EXT_DIST_ENABLE_SHIFT 7
/* M88E1000 PHY Specific Status Register */
#define M88E1000_PSSR_JABBER 0x0001 /* 1=Jabber */
#define M88E1000_PSSR_REV_POLARITY 0x0002 /* 1=Polarity reversed */
#define M88E1000_PSSR_MDIX 0x0040 /* 1=MDIX; 0=MDI */
#define M88E1000_PSSR_CABLE_LENGTH 0x0380 /* 0=<50M;1=50-80M;2=80-110M;
* 3=110-140M;4=>140M */
#define M88E1000_PSSR_LINK 0x0400 /* 1=Link up, 0=Link down */
#define M88E1000_PSSR_SPD_DPLX_RESOLVED 0x0800 /* 1=Speed & Duplex resolved */
#define M88E1000_PSSR_PAGE_RCVD 0x1000 /* 1=Page received */
#define M88E1000_PSSR_DPLX 0x2000 /* 1=Duplex 0=Half Duplex */
#define M88E1000_PSSR_SPEED 0xC000 /* Speed, bits 14:15 */
#define M88E1000_PSSR_10MBS 0x0000 /* 00=10Mbs */
#define M88E1000_PSSR_100MBS 0x4000 /* 01=100Mbs */
#define M88E1000_PSSR_1000MBS 0x8000 /* 10=1000Mbs */
#define M88E1000_PSSR_REV_POLARITY_SHIFT 1
#define M88E1000_PSSR_MDIX_SHIFT 6
#define M88E1000_PSSR_CABLE_LENGTH_SHIFT 7
/* M88E1000 Extended PHY Specific Control Register */
#define M88E1000_EPSCR_FIBER_LOOPBACK 0x4000 /* 1=Fiber loopback */
#define M88E1000_EPSCR_DOWN_NO_IDLE 0x8000 /* 1=Lost lock detect enabled.
* Will assert lost lock and bring
* link down if idle not seen
* within 1ms in 1000BASE-T
*/
/* Number of times we will attempt to autonegotiate before downshifting if we
* are the master */
#define M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK 0x0C00
#define M88E1000_EPSCR_MASTER_DOWNSHIFT_1X 0x0000
#define M88E1000_EPSCR_MASTER_DOWNSHIFT_2X 0x0400
#define M88E1000_EPSCR_MASTER_DOWNSHIFT_3X 0x0800
#define M88E1000_EPSCR_MASTER_DOWNSHIFT_4X 0x0C00
/* Number of times we will attempt to autonegotiate before downshifting if we
* are the slave */
#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK 0x0300
#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_DIS 0x0000
#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X 0x0100
#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_2X 0x0200
#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_3X 0x0300
#define M88E1000_EPSCR_TX_CLK_2_5 0x0060 /* 2.5 MHz TX_CLK */
#define M88E1000_EPSCR_TX_CLK_25 0x0070 /* 25 MHz TX_CLK */
#define M88E1000_EPSCR_TX_CLK_0 0x0000 /* NO TX_CLK */
/* Bit definitions for valid PHY IDs. */
#define M88E1000_E_PHY_ID 0x01410C50
#define M88E1000_I_PHY_ID 0x01410C30
#define M88E1011_I_PHY_ID 0x01410C20
#define M88E1000_12_PHY_ID M88E1000_E_PHY_ID
#define M88E1000_14_PHY_ID M88E1000_E_PHY_ID
/* Miscellaneous PHY bit definitions. */
#define PHY_PREAMBLE 0xFFFFFFFF
#define PHY_SOF 0x01
#define PHY_OP_READ 0x02
#define PHY_OP_WRITE 0x01
#define PHY_TURNAROUND 0x02
#define PHY_PREAMBLE_SIZE 32
#define MII_CR_SPEED_1000 0x0040
#define MII_CR_SPEED_100 0x2000
#define MII_CR_SPEED_10 0x0000
#define E1000_PHY_ADDRESS 0x01
#define PHY_AUTO_NEG_TIME 45 /* 4.5 Seconds */
#define PHY_FORCE_TIME 20 /* 2.0 Seconds */
#define PHY_REVISION_MASK 0xFFFFFFF0
#define DEVICE_SPEED_MASK 0x00000300 /* Device Ctrl Reg Speed Mask */
#define REG4_SPEED_MASK 0x01E0
#define REG9_SPEED_MASK 0x0300
#define ADVERTISE_10_HALF 0x0001
#define ADVERTISE_10_FULL 0x0002
#define ADVERTISE_100_HALF 0x0004
#define ADVERTISE_100_FULL 0x0008
#define ADVERTISE_1000_HALF 0x0010
#define ADVERTISE_1000_FULL 0x0020
#define AUTONEG_ADVERTISE_SPEED_DEFAULT 0x002F /* Everything but 1000-Half */
#endif /* _E1000_HW_H_ */
drivers/net/e1000/e1000_main.c
View file @ 09377d52
......@@ -99,6 +99,7 @@ static struct pci_device_id e1000_pci_tbl[] __devinitdata = {
{0x8086, 0x1008, 0x8086, 0x1107, 0, 0, 0},
{0x8086, 0x1009, 0x8086, 0x1109, 0, 0, 0},
{0x8086, 0x100C, 0x8086, 0x1112, 0, 0, 0},
{0x8086, 0x100E, 0x8086, 0x001E, 0, 0, 0},
/* Compaq Gigabit Ethernet Server Adapter */
{0x8086, 0x1000, 0x0E11, PCI_ANY_ID, 0, 0, 1},
{0x8086, 0x1001, 0x0E11, PCI_ANY_ID, 0, 0, 1},
......@@ -115,6 +116,7 @@ static struct pci_device_id e1000_pci_tbl[] __devinitdata = {
{0x8086, 0x1009, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
{0x8086, 0x100C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
{0x8086, 0x100D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
{0x8086, 0x100E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
/* required last entry */
{0,}
};
......@@ -131,6 +133,8 @@ static char *e1000_strings[] = {
int e1000_up(struct e1000_adapter *adapter);
void e1000_down(struct e1000_adapter *adapter);
void e1000_reset(struct e1000_adapter *adapter);
static int e1000_init_module(void);
static void e1000_exit_module(void);
static int e1000_probe(struct pci_dev *pdev, const struct pci_device_id *ent);
......@@ -163,7 +167,6 @@ static void e1000_clean_tx_irq(struct e1000_adapter *adapter);
static void e1000_clean_rx_irq(struct e1000_adapter *adapter);
static void e1000_alloc_rx_buffers(struct e1000_adapter *adapter);
static int e1000_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd);
static void e1000_reset(struct e1000_adapter *adapter);
static void e1000_enter_82542_rst(struct e1000_adapter *adapter);
static void e1000_leave_82542_rst(struct e1000_adapter *adapter);
static inline void e1000_rx_checksum(struct e1000_adapter *adapter,
......@@ -248,8 +251,6 @@ e1000_up(struct e1000_adapter *adapter)
e1000_configure_rx(adapter);
e1000_alloc_rx_buffers(adapter);
e1000_clear_hw_cntrs(&adapter->shared);
mod_timer(&adapter->watchdog_timer, jiffies);
e1000_irq_enable(adapter);
......@@ -259,7 +260,6 @@ e1000_up(struct e1000_adapter *adapter)
void
e1000_down(struct e1000_adapter *adapter)
{
struct e1000_shared_adapter *shared = &adapter->shared;
struct net_device *netdev = adapter->netdev;
e1000_irq_disable(adapter);
......@@ -269,64 +269,30 @@ e1000_down(struct e1000_adapter *adapter)
netif_carrier_off(netdev);
netif_stop_queue(netdev);
/* disable the transmit and receive units */
E1000_WRITE_REG(shared, RCTL, 0);
E1000_WRITE_REG(shared, TCTL, E1000_TCTL_PSP);
/* delay to allow PCI transactions to complete */
msec_delay(10);
e1000_reset(adapter);
e1000_clean_tx_ring(adapter);
e1000_clean_rx_ring(adapter);
e1000_reset(adapter);
}
static void
void
e1000_reset(struct e1000_adapter *adapter)
{
struct e1000_shared_adapter *shared = &adapter->shared;
uint32_t ctrl_ext;
/* Repartition Pba for greater than 9k mtu
* To take effect CTRL.RST is required.
*/
if(adapter->rx_buffer_len > E1000_RXBUFFER_8192)
E1000_WRITE_REG(shared, PBA, E1000_JUMBO_PBA);
E1000_WRITE_REG(&adapter->shared, PBA, E1000_JUMBO_PBA);
else
E1000_WRITE_REG(shared, PBA, E1000_DEFAULT_PBA);
/* 82542 2.0 needs MWI disabled while issuing a reset */
if(shared->mac_type == e1000_82542_rev2_0)
e1000_enter_82542_rst(adapter);
/* global reset */
E1000_WRITE_REG(shared, CTRL, E1000_CTRL_RST);
msec_delay(10);
/* EEPROM reload */
E1000_WRITE_REG(&adapter->shared, PBA, E1000_DEFAULT_PBA);
ctrl_ext = E1000_READ_REG(shared, CTRL_EXT);
ctrl_ext |= E1000_CTRL_EXT_EE_RST;
E1000_WRITE_REG(shared, CTRL_EXT, ctrl_ext);
msec_delay(5);
if(shared->mac_type == e1000_82542_rev2_0)
e1000_leave_82542_rst(adapter);
shared->tbi_compatibility_on = FALSE;
shared->fc = shared->original_fc;
e1000_init_hw(shared);
adapter->shared.fc = adapter->shared.original_fc;
e1000_reset_hw(&adapter->shared);
e1000_init_hw(&adapter->shared);
e1000_reset_adaptive(&adapter->shared);
e1000_phy_get_info(&adapter->shared, &adapter->phy_info);
e1000_enable_WOL(adapter);
return;
}
/**
......@@ -422,7 +388,7 @@ e1000_probe(struct pci_dev *pdev,
/* make sure the EEPROM is good */
if(!e1000_validate_eeprom_checksum(&adapter->shared))
if(e1000_validate_eeprom_checksum(&adapter->shared) < 0)
goto err_eeprom;
/* copy the MAC address out of the EEPROM */
......@@ -516,7 +482,7 @@ e1000_remove(struct pci_dev *pdev)
static void __devinit
e1000_sw_init(struct e1000_adapter *adapter)
{
struct e1000_shared_adapter *shared = &adapter->shared;
struct e1000_hw *shared = &adapter->shared;
struct net_device *netdev = adapter->netdev;
struct pci_dev *pdev = adapter->pdev;
......@@ -566,6 +532,9 @@ e1000_sw_init(struct e1000_adapter *adapter)
case E1000_DEV_ID_82544GC_LOM:
shared->mac_type = e1000_82544;
break;
case E1000_DEV_ID_82540EM:
shared->mac_type = e1000_82540;
break;
default:
/* should never have loaded on this device */
BUG();
......@@ -890,8 +859,19 @@ e1000_configure_rx(struct e1000_adapter *adapter)
/* set the Receive Delay Timer Register */
E1000_WRITE_REG(&adapter->shared, RDTR,
adapter->rx_int_delay | E1000_RDT_FPDB);
if(adapter->shared.mac_type == e1000_82540) {
E1000_WRITE_REG(&adapter->shared, RADV, adapter->rx_int_delay);
E1000_WRITE_REG(&adapter->shared, RDTR, 64);
/* Set the interrupt throttling rate. Value is calculated
* as DEFAULT_ITR = 1/(MAX_INTS_PER_SEC * 256ns) */
#define MAX_INTS_PER_SEC 8000
#define DEFAULT_ITR 1000000000/(MAX_INTS_PER_SEC * 256)
E1000_WRITE_REG(&adapter->shared, ITR, DEFAULT_ITR);
} else {
E1000_WRITE_REG(&adapter->shared, RDTR, adapter->rx_int_delay);
}
/* Setup the Base and Length of the Rx Descriptor Ring */
......@@ -1152,7 +1132,7 @@ static void
e1000_set_multi(struct net_device *netdev)
{
struct e1000_adapter *adapter = netdev->priv;
struct e1000_shared_adapter *shared = &adapter->shared;
struct e1000_hw *shared = &adapter->shared;
struct dev_mc_list *mc_ptr;
uint32_t rctl;
uint32_t hash_value;
......@@ -1519,8 +1499,9 @@ e1000_change_mtu(struct net_device *netdev, int new_mtu)
static void
e1000_update_stats(struct e1000_adapter *adapter)
{
struct e1000_shared_adapter *shared = &adapter->shared;
struct e1000_hw *shared = &adapter->shared;
unsigned long flags;
uint16_t phy_tmp;
#define PHY_IDLE_ERROR_COUNT_MASK 0x00FF
......@@ -1626,14 +1607,18 @@ e1000_update_stats(struct e1000_adapter *adapter)
/* Tx Dropped needs to be maintained elsewhere */
if(adapter->shared.media_type == e1000_media_type_copper) {
adapter->phy_stats.idle_errors +=
(e1000_read_phy_reg(shared, PHY_1000T_STATUS)
& PHY_IDLE_ERROR_COUNT_MASK);
adapter->phy_stats.receive_errors +=
e1000_read_phy_reg(shared, M88E1000_RX_ERR_CNTR);
/* Phy Stats */
if(shared->media_type == e1000_media_type_copper) {
if((adapter->link_speed == SPEED_1000) &&
(!e1000_read_phy_reg(shared, PHY_1000T_STATUS, &phy_tmp))) {
phy_tmp &= PHY_IDLE_ERROR_COUNT_MASK;
adapter->phy_stats.idle_errors += phy_tmp;
}
if(!e1000_read_phy_reg(shared, M88E1000_RX_ERR_CNTR, &phy_tmp))
adapter->phy_stats.receive_errors += phy_tmp;
}
return;
}
/**
......@@ -1804,7 +1789,7 @@ e1000_clean_rx_irq(struct e1000_adapter *adapter)
last_byte = *(skb->data + length - 1);
if(TBI_ACCEPT(&adapter->shared, rx_desc->special,
if(TBI_ACCEPT(&adapter->shared, rx_desc->status,
rx_desc->errors, length, last_byte)) {
spin_lock_irqsave(&adapter->stats_lock, flags);
......@@ -2003,7 +1988,7 @@ e1000_enable_WOL(struct e1000_adapter *adapter)
}
void
e1000_write_pci_cfg(struct e1000_shared_adapter *shared,
e1000_write_pci_cfg(struct e1000_hw *shared,
uint32_t reg, uint16_t *value)
{
struct e1000_adapter *adapter = shared->back;
......
drivers/net/e1000/e1000_param.c
View file @ 09377d52
......@@ -205,7 +205,7 @@ E1000_PARAM(TxIntDelay, "Transmit Interrupt Delay");
*
* Valid Range: 0-65535
*
* Default Value: 64
* Default Value: 64/128
*/
E1000_PARAM(RxIntDelay, "Receive Interrupt Delay");
......@@ -255,9 +255,10 @@ E1000_PARAM(DisablePolarityCorrection,
#define MAX_TIDV 0xFFFF
#define MIN_TIDV 0
#define DEFAULT_RIDV 64
#define MAX_RIDV 0xFFFF
#define MIN_RIDV 0
#define DEFAULT_RDTR 64
#define DEFAULT_RADV 128
#define MAX_RXDELAY 0xFFFF
#define MIN_RXDELAY 0
#define DEFAULT_MDIX 0
#define MAX_MDIX 3
......@@ -435,13 +436,16 @@ e1000_check_options(struct e1000_adapter *adapter)
e1000_validate_option(&adapter->tx_int_delay, &opt);
}
{ /* Receive Interrupt Delay */
char *rdtr = "using default of " __MODULE_STRING(DEFAULT_RDTR);
char *radv = "using default of " __MODULE_STRING(DEFAULT_RADV);
struct e1000_option opt = {
type: range_option,
name: "Receive Interrupt Delay",
err: "using default of " __MODULE_STRING(DEFAULT_RIDV),
def: DEFAULT_RIDV,
arg: { r: { min: MIN_RIDV, max: MAX_RIDV }}
arg: { r: { min: MIN_RXDELAY, max: MAX_RXDELAY }}
};
e1000_mac_type mac_type = adapter->shared.mac_type;
opt.def = mac_type < e1000_82540 ? DEFAULT_RDTR : DEFAULT_RADV;
opt.err = mac_type < e1000_82540 ? rdtr : radv;
adapter->rx_int_delay = RxIntDelay[bd];
e1000_validate_option(&adapter->rx_int_delay, &opt);
......@@ -700,7 +704,7 @@ e1000_check_copper_options(struct e1000_adapter *adapter)
}
/* Speed, AutoNeg and MDI/MDI-X must all play nice */
if (!e1000_validate_mdi_setting(&(adapter->shared))) {
if (e1000_validate_mdi_setting(&(adapter->shared)) < 0) {
printk(KERN_INFO "Speed, AutoNeg and MDI-X specifications are "
"incompatible. Setting MDI-X to a compatible value.\n");
}
......
drivers/net/e1000/e1000_phy.c deleted 100644 → 0
View file @ 6d87fb78
/*******************************************************************************
This software program is available to you under a choice of one of two
licenses. You may choose to be licensed under either the GNU General Public
License (GPL) Version 2, June 1991, available at
http://www.fsf.org/copyleft/gpl.html, or the Intel BSD + Patent License, the
text of which follows:
Recipient has requested a license and Intel Corporation ("Intel") is willing
to grant a license for the software entitled Linux Base Driver for the
Intel(R) PRO/1000 Family of Adapters (e1000) (the "Software") being provided
by Intel Corporation. The following definitions apply to this license:
"Licensed Patents" means patent claims licensable by Intel Corporation which
are necessarily infringed by the use of sale of the Software alone or when
combined with the operating system referred to below.
"Recipient" means the party to whom Intel delivers this Software.
"Licensee" means Recipient and those third parties that receive a license to
any operating system available under the GNU Public License version 2.0 or
later.
Copyright (c) 1999 - 2002 Intel Corporation.
All rights reserved.
The license is provided to Recipient and Recipient's Licensees under the
following terms.
Redistribution and use in source and binary forms of the Software, with or
without modification, are permitted provided that the following conditions
are met:
Redistributions of source code of the Software may retain the above
copyright notice, this list of conditions and the following disclaimer.
Redistributions in binary form of the Software may reproduce the above
copyright notice, this list of conditions and the following disclaimer in
the documentation and/or materials provided with the distribution.
Neither the name of Intel Corporation nor the names of its contributors
shall be used to endorse or promote products derived from this Software
without specific prior written permission.
Intel hereby grants Recipient and Licensees a non-exclusive, worldwide,
royalty-free patent license under Licensed Patents to make, use, sell, offer
to sell, import and otherwise transfer the Software, if any, in source code
and object code form. This license shall include changes to the Software
that are error corrections or other minor changes to the Software that do
not add functionality or features when the Software is incorporated in any
version of an operating system that has been distributed under the GNU
General Public License 2.0 or later. This patent license shall apply to the
combination of the Software and any operating system licensed under the GNU
Public License version 2.0 or later if, at the time Intel provides the
Software to Recipient, such addition of the Software to the then publicly
available versions of such operating systems available under the GNU Public
License version 2.0 or later (whether in gold, beta or alpha form) causes
such combination to be covered by the Licensed Patents. The patent license
shall not apply to any other combinations which include the Software. NO
hardware per se is licensed hereunder.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MECHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL INTEL OR IT CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
ANY LOSS OF USE; DATA, OR PROFITS; OR BUSINESS INTERUPTION) HOWEVER CAUSED
AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY OR
TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************/
/* e1000_phy.c
* Shared functions for accessing and configuring the PHY
*/
#include "e1000_mac.h"
#include "e1000_phy.h"
/******************************************************************************
* Raises the Management Data Clock
*
* shared - Struct containing variables accessed by shared code
* ctrl_reg - Device control register's current value
******************************************************************************/
static void
e1000_raise_mdc(struct e1000_shared_adapter *shared,
uint32_t *ctrl_reg)
{
/* Raise the clock input to the Management Data Clock (by setting
* the MDC bit), and then delay 2 microseconds.
*/
E1000_WRITE_REG(shared, CTRL, (*ctrl_reg | E1000_CTRL_MDC));
usec_delay(2);
return;
}
/******************************************************************************
* Lowers the Management Data Clock
*
* shared - Struct containing variables accessed by shared code
* ctrl_reg - Device control register's current value
******************************************************************************/
static void
e1000_lower_mdc(struct e1000_shared_adapter *shared,
uint32_t *ctrl_reg)
{
/* Lower the clock input to the Management Data Clock (by clearing
* the MDC bit), and then delay 2 microseconds.
*/
E1000_WRITE_REG(shared, CTRL, (*ctrl_reg & ~E1000_CTRL_MDC));
usec_delay(2);
return;
}
/******************************************************************************
* Shifts data bits out to the PHY
*
* shared - Struct containing variables accessed by shared code
* data - Data to send out to the PHY
* count - Number of bits to shift out
*
* Bits are shifted out in MSB to LSB order.
******************************************************************************/
static void
e1000_phy_shift_out(struct e1000_shared_adapter *shared,
uint32_t data,
uint16_t count)
{
uint32_t ctrl_reg;
uint32_t mask;
ASSERT(count <= 32);
/* We need to shift "count" number of bits out to the PHY. So, the
* value in the "Data" parameter will be shifted out to the PHY
* one bit at a time. In order to do this, "Data" must be broken
* down into bits, which is what the "while" logic does below.
*/
mask = 0x01;
mask <<= (count - 1);
ctrl_reg = E1000_READ_REG(shared, CTRL);
/* Set MDIO_DIR (SWDPIO1) and MDC_DIR (SWDPIO2) direction bits to
* be used as output pins.
*/
ctrl_reg |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR);
while(mask) {
/* A "1" is shifted out to the PHY by setting the MDIO bit to
* "1" and then raising and lowering the Management Data Clock
* (MDC). A "0" is shifted out to the PHY by setting the MDIO
* bit to "0" and then raising and lowering the clock.
*/
if(data & mask)
ctrl_reg |= E1000_CTRL_MDIO;
else
ctrl_reg &= ~E1000_CTRL_MDIO;
E1000_WRITE_REG(shared, CTRL, ctrl_reg);
usec_delay(2);
e1000_raise_mdc(shared, &ctrl_reg);
e1000_lower_mdc(shared, &ctrl_reg);
mask = mask >> 1;
}
/* Clear the data bit just before leaving this routine. */
ctrl_reg &= ~E1000_CTRL_MDIO;
return;
}
/******************************************************************************
* Shifts data bits in from the PHY
*
* shared - Struct containing variables accessed by shared code
*
* Bits are shifted in in MSB to LSB order.
******************************************************************************/
static uint16_t
e1000_phy_shift_in(struct e1000_shared_adapter *shared)
{
uint32_t ctrl_reg;
uint16_t data = 0;
uint8_t i;
/* In order to read a register from the PHY, we need to shift in a
* total of 18 bits from the PHY. The first two bit (TurnAround)
* times are used to avoid contention on the MDIO pin when a read
* operation is performed. These two bits are ignored by us and
* thrown away. Bits are "shifted in" by raising the clock input
* to the Management Data Clock (setting the MDC bit), and then
* reading the value of the MDIO bit.
*/
ctrl_reg = E1000_READ_REG(shared, CTRL);
/* Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as
* input.
*/
ctrl_reg &= ~E1000_CTRL_MDIO_DIR;
ctrl_reg &= ~E1000_CTRL_MDIO;
E1000_WRITE_REG(shared, CTRL, ctrl_reg);
/* Raise and Lower the clock before reading in the data. This
* accounts for the TurnAround bits. The first clock occurred
* when we clocked out the last bit of the Register Address.
*/
e1000_raise_mdc(shared, &ctrl_reg);
e1000_lower_mdc(shared, &ctrl_reg);
for(data = 0, i = 0; i < 16; i++) {
data = data << 1;
e1000_raise_mdc(shared, &ctrl_reg);
ctrl_reg = E1000_READ_REG(shared, CTRL);
/* Check to see if we shifted in a "1". */
if(ctrl_reg & E1000_CTRL_MDIO)
data |= 1;
e1000_lower_mdc(shared, &ctrl_reg);
}
e1000_raise_mdc(shared, &ctrl_reg);
e1000_lower_mdc(shared, &ctrl_reg);
/* Clear the MDIO bit just before leaving this routine. */
ctrl_reg &= ~E1000_CTRL_MDIO;
return (data);
}
/******************************************************************************
* Force PHY speed and duplex settings to shared->forced_speed_duplex
*
* shared - Struct containing variables accessed by shared code
******************************************************************************/
static void
e1000_phy_force_speed_duplex(struct e1000_shared_adapter *shared)
{
uint32_t tctl_reg;
uint32_t ctrl_reg;
uint32_t shift;
uint16_t mii_ctrl_reg;
uint16_t mii_status_reg;
uint16_t phy_data;
uint16_t i;
DEBUGFUNC("e1000_phy_force_speed_duplex");
/* Turn off Flow control if we are forcing speed and duplex. */
shared->fc = e1000_fc_none;
DEBUGOUT1("shared->fc = %d\n", shared->fc);
/* Read the Device Control Register. */
ctrl_reg = E1000_READ_REG(shared, CTRL);
/* Set the bits to Force Speed and Duplex in the Device Ctrl Reg. */
ctrl_reg |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
ctrl_reg &= ~(DEVICE_SPEED_MASK);
/* Clear the Auto Speed Detect Enable bit. */
ctrl_reg &= ~E1000_CTRL_ASDE;
/* Read the MII Control Register. */
mii_ctrl_reg = e1000_read_phy_reg(shared, PHY_CTRL);
/* We need to disable autoneg in order to force link and duplex. */
mii_ctrl_reg &= ~MII_CR_AUTO_NEG_EN;
/* Are we forcing Full or Half Duplex? */
if(shared->forced_speed_duplex == e1000_100_full ||
shared->forced_speed_duplex == e1000_10_full) {
/* We want to force full duplex so we SET the full duplex bits
* in the Device and MII Control Registers.
*/
ctrl_reg |= E1000_CTRL_FD;
mii_ctrl_reg |= MII_CR_FULL_DUPLEX;
DEBUGOUT("Full Duplex\n");
} else {
/* We want to force half duplex so we CLEAR the full duplex
* bits in the Device and MII Control Registers.
*/
ctrl_reg &= ~E1000_CTRL_FD;
mii_ctrl_reg &= ~MII_CR_FULL_DUPLEX; /* Do this implies HALF */
DEBUGOUT("Half Duplex\n");
}
/* Are we forcing 100Mbps??? */
if(shared->forced_speed_duplex == e1000_100_full ||
shared->forced_speed_duplex == e1000_100_half) {
/* Set the 100Mb bit and turn off the 1000Mb and 10Mb bits. */
ctrl_reg |= E1000_CTRL_SPD_100;
mii_ctrl_reg |= MII_CR_SPEED_100;
mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10);
DEBUGOUT("Forcing 100mb ");
} else { /* Force 10MB Full or Half */
/* Set the 10Mb bit and turn off the 1000Mb and 100Mb bits. */
ctrl_reg &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
mii_ctrl_reg |= MII_CR_SPEED_10;
mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100);
DEBUGOUT("Forcing 10mb ");
}
/* Now we need to configure the Collision Distance. We need to read
* the Transmit Control Register to do this.
* Note: This must be done for both Half or Full Duplex.
*/
tctl_reg = E1000_READ_REG(shared, TCTL);
DEBUGOUT1("tctl_reg = %x\n", tctl_reg);
if(!(mii_ctrl_reg & MII_CR_FULL_DUPLEX)) {
/* We are in Half Duplex mode so we need to set up our collision
* distance for 10/100.
*/
tctl_reg &= ~E1000_TCTL_COLD;
shift = E1000_HDX_COLLISION_DISTANCE;
shift <<= E1000_COLD_SHIFT;
tctl_reg |= shift;
} else {
/* We are in Full Duplex mode. We have the same collision
* distance regardless of speed.
*/
tctl_reg &= ~E1000_TCTL_COLD;
shift = E1000_FDX_COLLISION_DISTANCE;
shift <<= E1000_COLD_SHIFT;
tctl_reg |= shift;
}
/* Write the configured values back to the Transmit Control Reg. */
E1000_WRITE_REG(shared, TCTL, tctl_reg);
/* Write the configured values back to the Device Control Reg. */
E1000_WRITE_REG(shared, CTRL, ctrl_reg);
/* Write the MII Control Register with the new PHY configuration. */
phy_data = e1000_read_phy_reg(shared, M88E1000_PHY_SPEC_CTRL);
/* Clear Auto-Crossover to force MDI manually.
* M88E1000 requires MDI forced whenever speed/duplex is forced
*/
phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
e1000_write_phy_reg(shared, M88E1000_PHY_SPEC_CTRL, phy_data);
DEBUGOUT1("M88E1000 PSCR: %x \n", phy_data);
/* Need to reset the PHY or these bits will get ignored. */
mii_ctrl_reg |= MII_CR_RESET;
e1000_write_phy_reg(shared, PHY_CTRL, mii_ctrl_reg);
/* The wait_autoneg_complete flag may be a little misleading here.
* Since we are forcing speed and duplex, Auto-Neg is not enabled.
* But we do want to delay for a period while forcing only so we
* don't generate false No Link messages. So we will wait here
* only if the user has set wait_autoneg_complete to 1, which is
* the default.
*/
if(shared->wait_autoneg_complete) {
/* We will wait for autoneg to complete. */
DEBUGOUT("Waiting for forced speed/duplex link.\n");
mii_status_reg = 0;
/* We will wait for autoneg to complete or 4.5 seconds to expire. */
for(i = PHY_FORCE_TIME; i > 0; i--) {
/* Read the MII Status Register and wait for Auto-Neg
* Complete bit to be set.
*/
mii_status_reg = e1000_read_phy_reg(shared, PHY_STATUS);
mii_status_reg = e1000_read_phy_reg(shared, PHY_STATUS);
if(mii_status_reg & MII_SR_LINK_STATUS)
break;
msec_delay(100);
} /* end for loop */
if(i == 0) { /* We didn't get link */
/* Reset the DSP and wait again for link. */
e1000_phy_reset_dsp(shared);
}
/* This loop will early-out if the link condition has been met. */
for(i = PHY_FORCE_TIME; i > 0; i--) {
if(mii_status_reg & MII_SR_LINK_STATUS)
break;
msec_delay(100);
/* Read the MII Status Register and wait for Auto-Neg
* Complete bit to be set.
*/
mii_status_reg = e1000_read_phy_reg(shared, PHY_STATUS);
mii_status_reg = e1000_read_phy_reg(shared, PHY_STATUS);
} /* end for loop */
} /* end if wait_autoneg_complete */
/*
* Because we reset the PHY above, we need to re-force TX_CLK in the
* Extended PHY Specific Control Register to 25MHz clock. This
* value defaults back to a 2.5MHz clock when the PHY is reset.
*/
phy_data = e1000_read_phy_reg(shared, M88E1000_EXT_PHY_SPEC_CTRL);
phy_data |= M88E1000_EPSCR_TX_CLK_25;
e1000_write_phy_reg(shared, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
/* In addition, because of the s/w reset above, we need to enable
* CRS on TX. This must be set for both full and half duplex
* operation.
*/
phy_data = e1000_read_phy_reg(shared, M88E1000_PHY_SPEC_CTRL);
phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
e1000_write_phy_reg(shared, M88E1000_PHY_SPEC_CTRL, phy_data);
DEBUGOUT1("M88E1000 Phy Specific Ctrl Reg = %4x\r\n", phy_data);
return;
}
/*****************************************************************************
* Reads the value from a PHY register
*
* shared - Struct containing variables accessed by shared code
* reg_addr - address of the PHY register to read
******************************************************************************/
uint16_t
e1000_read_phy_reg(struct e1000_shared_adapter *shared,
uint32_t reg_addr)
{
uint32_t i;
uint32_t data = 0;
uint32_t command = 0;
ASSERT(reg_addr <= MAX_PHY_REG_ADDRESS);
if(shared->mac_type > e1000_82543) {
/* Set up Op-code, Phy Address, and
* register address in the MDI Control register. The MAC will
* take care of interfacing with the PHY to retrieve the
* desired data.
*/
command = ((reg_addr << E1000_MDIC_REG_SHIFT) |
(shared->phy_addr << E1000_MDIC_PHY_SHIFT) |
(E1000_MDIC_OP_READ));
E1000_WRITE_REG(shared, MDIC, command);
/* Check every 10 usec to see if the read completed. The read
* may take as long as 64 usecs (we'll wait 100 usecs max)
* from the CPU Write to the Ready bit assertion.
*/
for(i = 0; i < 64; i++) {
usec_delay(10);
data = E1000_READ_REG(shared, MDIC);
if(data & E1000_MDIC_READY)
break;
}
} else {
/* We must first send a preamble through the MDIO pin to signal the
* beginning of an MII instruction. This is done by sending 32
* consecutive "1" bits.
*/
e1000_phy_shift_out(shared, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
/* Now combine the next few fields that are required for a read
* operation. We use this method instead of calling the
* e1000_phy_shift_out routine five different times. The format of
* a MII read instruction consists of a shift out of 14 bits and is
* defined as follows:
* <Preamble><SOF><Op Code><Phy Addr><Reg Addr>
* followed by a shift in of 18 bits. This first two bits shifted
* in are TurnAround bits used to avoid contention on the MDIO pin
* when a READ operation is performed. These two bits are thrown
* away followed by a shift in of 16 bits which contains the
* desired data.
*/
command = ((reg_addr) |
(shared->phy_addr << 5) |
(PHY_OP_READ << 10) | (PHY_SOF << 12));
e1000_phy_shift_out(shared, command, 14);
/* Now that we've shifted out the read command to the MII, we need
* to "shift in" the 16-bit value (18 total bits) of the requested
* PHY register address.
*/
data = (uint32_t) e1000_phy_shift_in(shared);
}
ASSERT(!(data & E1000_MDIC_ERROR));
return ((uint16_t) data);
}
/******************************************************************************
* Writes a value to a PHY register
*
* shared - Struct containing variables accessed by shared code
* reg_addr - address of the PHY register to write
* data - data to write to the PHY
******************************************************************************/
void
e1000_write_phy_reg(struct e1000_shared_adapter *shared,
uint32_t reg_addr,
uint16_t data)
{
uint32_t i;
uint32_t command = 0;
uint32_t mdic_reg;
ASSERT(reg_addr <= MAX_PHY_REG_ADDRESS);
if(shared->mac_type > e1000_82543) {
/* Set up Op-code, Phy Address, register
* address, and data intended for the PHY register in the MDI
* Control register. The MAC will take care of interfacing
* with the PHY to send the desired data.
*/
command = (((uint32_t) data) |
(reg_addr << E1000_MDIC_REG_SHIFT) |
(shared->phy_addr << E1000_MDIC_PHY_SHIFT) |
(E1000_MDIC_OP_WRITE));
E1000_WRITE_REG(shared, MDIC, command);
/* Check every 10 usec to see if the read completed. The read
* may take as long as 64 usecs (we'll wait 100 usecs max)
* from the CPU Write to the Ready bit assertion.
*/
for(i = 0; i < 10; i++) {
usec_delay(10);
mdic_reg = E1000_READ_REG(shared, MDIC);
if(mdic_reg & E1000_MDIC_READY)
break;
}
} else {
/* We'll need to use the SW defined pins to shift the write command
* out to the PHY. We first send a preamble to the PHY to signal the
* beginning of the MII instruction. This is done by sending 32
* consecutive "1" bits.
*/
e1000_phy_shift_out(shared, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
/* Now combine the remaining required fields that will indicate
* a write operation. We use this method instead of calling the
* e1000_phy_shift_out routine for each field in the command. The
* format of a MII write instruction is as follows:
* <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>.
*/
command = ((PHY_TURNAROUND) |
(reg_addr << 2) |
(shared->phy_addr << 7) |
(PHY_OP_WRITE << 12) | (PHY_SOF << 14));
command <<= 16;
command |= ((uint32_t) data);
e1000_phy_shift_out(shared, command, 32);
}
return;
}
/******************************************************************************
* Returns the PHY to the power-on reset state
*
* shared - Struct containing variables accessed by shared code
******************************************************************************/
void
e1000_phy_hw_reset(struct e1000_shared_adapter *shared)
{
uint32_t ctrl_reg;
uint32_t ctrl_ext_reg;
DEBUGFUNC("e1000_phy_hw_reset");
DEBUGOUT("Resetting Phy...\n");
if(shared->mac_type > e1000_82543) {
/* Read the device control register and assert the
* E1000_CTRL_PHY_RST bit. Hold for 20ms and then take it out
* of reset.
*/
ctrl_reg = E1000_READ_REG(shared, CTRL);
ctrl_reg |= E1000_CTRL_PHY_RST;
E1000_WRITE_REG(shared, CTRL, ctrl_reg);
msec_delay(20);
ctrl_reg &= ~E1000_CTRL_PHY_RST;
E1000_WRITE_REG(shared, CTRL, ctrl_reg);
msec_delay(20);
} else {
/* Read the Extended Device Control Register, assert the
* PHY_RESET_DIR bit. Then clock it out to the PHY.
*/
ctrl_ext_reg = E1000_READ_REG(shared, CTRL_EXT);
ctrl_ext_reg |= E1000_CTRL_PHY_RESET_DIR4;
E1000_WRITE_REG(shared, CTRL_EXT, ctrl_ext_reg);
msec_delay(20);
/* Set the reset bit in the device control register and clock
* it out to the PHY.
*/
ctrl_ext_reg = E1000_READ_REG(shared, CTRL_EXT);
ctrl_ext_reg &= ~E1000_CTRL_PHY_RESET4;
E1000_WRITE_REG(shared, CTRL_EXT, ctrl_ext_reg);
msec_delay(20);
ctrl_ext_reg = E1000_READ_REG(shared, CTRL_EXT);
ctrl_ext_reg |= E1000_CTRL_PHY_RESET4;
E1000_WRITE_REG(shared, CTRL_EXT, ctrl_ext_reg);
msec_delay(20);
}
return;
}
/******************************************************************************
* Resets the PHY
*
* shared - Struct containing variables accessed by shared code
*
* Sets bit 15 of the MII Control regiser
******************************************************************************/
boolean_t
e1000_phy_reset(struct e1000_shared_adapter *shared)
{
uint16_t reg_data;
uint16_t i;
DEBUGFUNC("e1000_phy_reset");
/* Read the MII control register, set the reset bit and write the
* value back by clocking it out to the PHY.
*/
reg_data = e1000_read_phy_reg(shared, PHY_CTRL);
reg_data |= MII_CR_RESET;
e1000_write_phy_reg(shared, PHY_CTRL, reg_data);
/* Wait for bit 15 of the MII Control Register to be cleared
* indicating the PHY has been reset.
*/
i = 0;
while((reg_data & MII_CR_RESET) && i++ < 500) {
reg_data = e1000_read_phy_reg(shared, PHY_CTRL);
usec_delay(1);
}
if(i >= 500) {
DEBUGOUT("Timeout waiting for PHY to reset.\n");
return FALSE;
}
return TRUE;
}
/******************************************************************************
* Detects which PHY is present and the speed and duplex
*
* shared - Struct containing variables accessed by shared code
* ctrl_reg - current value of the device control register
******************************************************************************/
boolean_t
e1000_phy_setup(struct e1000_shared_adapter *shared,
uint32_t ctrl_reg)
{
uint16_t mii_ctrl_reg;
uint16_t mii_status_reg;
uint16_t phy_specific_ctrl_reg;
uint16_t mii_autoneg_adv_reg;
uint16_t mii_1000t_ctrl_reg;
uint16_t i;
uint16_t data;
uint16_t autoneg_hw_setting;
uint16_t autoneg_fc_setting;
boolean_t restart_autoneg = FALSE;
boolean_t force_autoneg_restart = FALSE;
DEBUGFUNC("e1000_phy_setup");
/* We want to enable the Auto-Speed Detection bit in the Device
* Control Register. When set to 1, the MAC automatically detects
* the resolved speed of the link and self-configures appropriately.
* The Set Link Up bit must also be set for this behavior work
* properly.
*/
/* Nothing but 82543 and newer */
ASSERT(shared->mac_type >= e1000_82543);
/* With 82543, we need to force speed/duplex
* on the MAC equal to what the PHY speed/duplex configuration is.
* In addition, on 82543, we need to perform a hardware reset
* on the PHY to take it out of reset.
*/
if(shared->mac_type >= e1000_82544) {
ctrl_reg |= E1000_CTRL_SLU;
E1000_WRITE_REG(shared, CTRL, ctrl_reg);
} else {
ctrl_reg |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX | E1000_CTRL_SLU);
E1000_WRITE_REG(shared, CTRL, ctrl_reg);
if(shared->mac_type == e1000_82543)
e1000_phy_hw_reset(shared);
}
if(!e1000_detect_gig_phy(shared)) {
/* No PHY detected, return FALSE */
DEBUGOUT("PhySetup failure, did not detect valid phy.\n");
return (FALSE);
}
DEBUGOUT1("Phy ID = %x \n", shared->phy_id);
/* Read the MII Control Register. */
mii_ctrl_reg = e1000_read_phy_reg(shared, PHY_CTRL);
DEBUGOUT1("MII Ctrl Reg contents = %x\n", mii_ctrl_reg);
/* Check to see if the Auto Neg Enable bit is set in the MII Control
* Register. If not, we could be in a situation where a driver was
* loaded previously and was forcing speed and duplex. Then the
* driver was unloaded but a e1000_phy_hw_reset was not performed, so
* link was still being forced and link was still achieved. Then
* the driver was reloaded with the intention to auto-negotiate, but
* since link is already established we end up not restarting
* auto-neg. So if the auto-neg bit is not enabled and the driver
* is being loaded with the desire to auto-neg, we set this flag to
* to ensure the restart of the auto-neg engine later in the logic.
*/
if(!(mii_ctrl_reg & MII_CR_AUTO_NEG_EN))
force_autoneg_restart = TRUE;
/* Clear the isolate bit for normal operation and write it back to
* the MII Control Reg. Although the spec says this doesn't need
* to be done when the PHY address is not equal to zero, we do it
* anyway just to be safe.
*/
mii_ctrl_reg &= ~(MII_CR_ISOLATE);
e1000_write_phy_reg(shared, PHY_CTRL, mii_ctrl_reg);
data = e1000_read_phy_reg(shared, M88E1000_PHY_SPEC_CTRL);
/* Enable CRS on TX. This must be set for half-duplex operation. */
data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
DEBUGOUT1("M88E1000 PSCR: %x \n", data);
e1000_write_phy_reg(shared, M88E1000_PHY_SPEC_CTRL, data);
data = e1000_read_phy_reg(shared, M88E1000_EXT_PHY_SPEC_CTRL);
/* Force TX_CLK in the Extended PHY Specific Control Register
* to 25MHz clock.
*/
data |= M88E1000_EPSCR_TX_CLK_25;
e1000_write_phy_reg(shared, M88E1000_EXT_PHY_SPEC_CTRL, data);
/* Certain PHYs will set the default of MII register 4 differently.
* We need to check this against our fc value. If it is
* different, we need to setup up register 4 correctly and restart
* autonegotiation.
*/
/* Read the MII Auto-Neg Advertisement Register (Address 4). */
mii_autoneg_adv_reg = e1000_read_phy_reg(shared, PHY_AUTONEG_ADV);
/* Shift right to put 10T-Half bit in bit 0
* Isolate the four bits for 100/10 Full/Half.
*/
autoneg_hw_setting = (mii_autoneg_adv_reg >> 5) & 0xF;
/* Get the 1000T settings. */
mii_1000t_ctrl_reg = e1000_read_phy_reg(shared, PHY_1000T_CTRL);
/* Isolate and OR in the 1000T settings. */
autoneg_hw_setting |= ((mii_1000t_ctrl_reg & 0x0300) >> 4);
/* mask all bits in the MII Auto-Neg Advertisement Register
* except for ASM_DIR and PAUSE and shift. This value
* will be used later to see if we need to restart Auto-Negotiation.
*/
autoneg_fc_setting = ((mii_autoneg_adv_reg & 0x0C00) >> 10);
/* Perform some bounds checking on the shared->autoneg_advertised
* parameter. If this variable is zero, then set it to the default.
*/
shared->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT;
/* If autoneg_advertised is zero, we assume it was not defaulted
* by the calling code so we set to advertise full capability.
*/
if(shared->autoneg_advertised == 0)
shared->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT;
/* We could be in the situation where Auto-Neg has already completed
* and the user has not indicated any overrides. In this case we
* simply need to call e1000_get_speed_and_duplex to obtain the Auto-
* Negotiated speed and duplex, then return.
*/
if(!force_autoneg_restart && shared->autoneg &&
(shared->autoneg_advertised == autoneg_hw_setting) &&
(shared->fc == autoneg_fc_setting)) {
DEBUGOUT("No overrides - Reading MII Status Reg..\n");
/* Read the MII Status Register. We read this twice because
* certain bits are "sticky" and need to be read twice.
*/
mii_status_reg = e1000_read_phy_reg(shared, PHY_STATUS);
mii_status_reg = e1000_read_phy_reg(shared, PHY_STATUS);
DEBUGOUT1("MII Status Reg contents = %x\n", mii_status_reg);
/* Do we have link now? (if so, auto-neg has completed) */
if(mii_status_reg & MII_SR_LINK_STATUS) {
data = e1000_read_phy_reg(shared, M88E1000_PHY_SPEC_STATUS);
DEBUGOUT1("M88E1000 Phy Specific Status Reg contents = %x\n", data);
/* We have link, so we need to finish the config process:
* 1) Set up the MAC to the current PHY speed/duplex
* if we are on 82543. If we
* are on newer silicon, we only need to configure
* collision distance in the Transmit Control Register.
* 2) Set up flow control on the MAC to that established
* with the link partner.
*/
if(shared->mac_type >= e1000_82544)
e1000_config_collision_dist(shared);
else
e1000_config_mac_to_phy(shared, data);
e1000_config_fc_after_link_up(shared);
return (TRUE);
}
}
/* Options:
* MDI/MDI-X = 0 (default)
* 0 - Auto for all speeds
* 1 - MDI mode
* 2 - MDI-X mode
* 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
*/
phy_specific_ctrl_reg = e1000_read_phy_reg(shared, M88E1000_PHY_SPEC_CTRL);
phy_specific_ctrl_reg &= ~M88E1000_PSCR_AUTO_X_MODE;
switch (shared->mdix) {
case 1:
phy_specific_ctrl_reg |= M88E1000_PSCR_MDI_MANUAL_MODE;
break;
case 2:
phy_specific_ctrl_reg |= M88E1000_PSCR_MDIX_MANUAL_MODE;
break;
case 3:
phy_specific_ctrl_reg |= M88E1000_PSCR_AUTO_X_1000T;
break;
case 0:
default:
phy_specific_ctrl_reg |= M88E1000_PSCR_AUTO_X_MODE;
break;
}
e1000_write_phy_reg(shared, M88E1000_PHY_SPEC_CTRL, phy_specific_ctrl_reg);
/* Options:
* disable_polarity_correction = 0 (default)
* Automatic Correction for Reversed Cable Polarity
* 0 - Disabled
* 1 - Enabled
*/
phy_specific_ctrl_reg = e1000_read_phy_reg(shared, M88E1000_PHY_SPEC_CTRL);
phy_specific_ctrl_reg &= ~M88E1000_PSCR_POLARITY_REVERSAL;
if(shared->disable_polarity_correction == 1)
phy_specific_ctrl_reg |= M88E1000_PSCR_POLARITY_REVERSAL;
e1000_write_phy_reg(shared, M88E1000_PHY_SPEC_CTRL, phy_specific_ctrl_reg);
/* Options:
* autoneg = 1 (default)
* PHY will advertise value(s) parsed from
* autoneg_advertised and fc
* autoneg = 0
* PHY will be set to 10H, 10F, 100H, or 100F
* depending on value parsed from forced_speed_duplex.
*/
/* Is autoneg enabled? This is enabled by default or by software override.
* If so, call e1000_phy_setup_autoneg routine to parse the
* autoneg_advertised and fc options. If autoneg is NOT enabled, then the
* user should have provided a speed/duplex override. If so, then call
* e1000_phy_force_speed_duplex to parse and set this up. Otherwise,
* we are in an error situation and need to bail.
*/
if(shared->autoneg) {
DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
restart_autoneg = e1000_phy_setup_autoneg(shared);
} else {
DEBUGOUT("Forcing speed and duplex\n");
e1000_phy_force_speed_duplex(shared);
}
/* Based on information parsed above, check the flag to indicate
* whether we need to restart Auto-Neg.
*/
if(restart_autoneg) {
DEBUGOUT("Restarting Auto-Neg\n");
/* Read the MII Control Register. */
mii_ctrl_reg = e1000_read_phy_reg(shared, PHY_CTRL);
/* Restart auto-negotiation by setting the Auto Neg Enable bit and
* the Auto Neg Restart bit.
*/
mii_ctrl_reg |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
e1000_write_phy_reg(shared, PHY_CTRL, mii_ctrl_reg);
/* Does the user want to wait for Auto-Neg to complete here, or
* check at a later time (for example, callback routine).
*/
if(shared->wait_autoneg_complete)
e1000_wait_autoneg(shared);
} /* end if restart_autoneg */
/* Read the MII Status Register. */
mii_status_reg = e1000_read_phy_reg(shared, PHY_STATUS);
mii_status_reg = e1000_read_phy_reg(shared, PHY_STATUS);
DEBUGOUT1("Checking for link status - MII Status Reg contents = %x\n",
mii_status_reg);
/* Check link status. Wait up to 100 microseconds for link to
* become valid.
*/
for(i = 0; i < 10; i++) {
if(mii_status_reg & MII_SR_LINK_STATUS)
break;
usec_delay(10);
DEBUGOUT(". ");
mii_status_reg = e1000_read_phy_reg(shared, PHY_STATUS);
mii_status_reg = e1000_read_phy_reg(shared, PHY_STATUS);
}
if(mii_status_reg & MII_SR_LINK_STATUS) {
/* Yes, so configure MAC to PHY settings as well as flow control
* registers.
*/
data = e1000_read_phy_reg(shared, M88E1000_PHY_SPEC_STATUS);
DEBUGOUT1("M88E1000 Phy Specific Status Reg contents = %x\n", data);
/* We have link, so we need to finish the config process:
* 1) Set up the MAC to the current PHY speed/duplex
* if we are on 82543. If we
* are on newer silicon, we only need to configure
* collision distance in the Transmit Control Register.
* 2) Set up flow control on the MAC to that established with
* the link partner.
*/
if(shared->mac_type >= e1000_82544)
e1000_config_collision_dist(shared);
else
e1000_config_mac_to_phy(shared, data);
e1000_config_fc_after_link_up(shared);
DEBUGOUT("Valid link established!!!\n");
} else {
DEBUGOUT("Unable to establish link!!!\n");
}
return (TRUE);
}
/******************************************************************************
* Configures PHY autoneg and flow control advertisement settings
*
* shared - Struct containing variables accessed by shared code
******************************************************************************/
boolean_t
e1000_phy_setup_autoneg(struct e1000_shared_adapter *shared)
{
uint16_t mii_autoneg_adv_reg;
uint16_t mii_1000t_ctrl_reg;
DEBUGFUNC("e1000_phy_setup_autoneg");
/* Read the MII Auto-Neg Advertisement Register (Address 4). */
mii_autoneg_adv_reg = e1000_read_phy_reg(shared, PHY_AUTONEG_ADV);
/* Read the MII 1000Base-T Control Register (Address 9). */
mii_1000t_ctrl_reg = e1000_read_phy_reg(shared, PHY_1000T_CTRL);
/* Need to parse both autoneg_advertised and fc and set up
* the appropriate PHY registers. First we will parse for
* autoneg_advertised software override. Since we can advertise
* a plethora of combinations, we need to check each bit
* individually.
*/
/* First we clear all the 10/100 mb speed bits in the Auto-Neg
* Advertisement Register (Address 4) and the 1000 mb speed bits in
* the 1000Base-T Control Register (Address 9).
*/
mii_autoneg_adv_reg &= ~REG4_SPEED_MASK;
mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK;
DEBUGOUT1("autoneg_advertised %x\n", shared->autoneg_advertised);
/* Do we want to advertise 10 Mb Half Duplex? */
if(shared->autoneg_advertised & ADVERTISE_10_HALF) {
DEBUGOUT("Advertise 10mb Half duplex\n");
mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
}
/* Do we want to advertise 10 Mb Full Duplex? */
if(shared->autoneg_advertised & ADVERTISE_10_FULL) {
DEBUGOUT("Advertise 10mb Full duplex\n");
mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
}
/* Do we want to advertise 100 Mb Half Duplex? */
if(shared->autoneg_advertised & ADVERTISE_100_HALF) {
DEBUGOUT("Advertise 100mb Half duplex\n");
mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
}
/* Do we want to advertise 100 Mb Full Duplex? */
if(shared->autoneg_advertised & ADVERTISE_100_FULL) {
DEBUGOUT("Advertise 100mb Full duplex\n");
mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
}
/* We do not allow the Phy to advertise 1000 Mb Half Duplex */
if(shared->autoneg_advertised & ADVERTISE_1000_HALF) {
DEBUGOUT("Advertise 1000mb Half duplex requested, request denied!\n");
}
/* Do we want to advertise 1000 Mb Full Duplex? */
if(shared->autoneg_advertised & ADVERTISE_1000_FULL) {
DEBUGOUT("Advertise 1000mb Full duplex\n");
mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
}
/* Check for a software override of the flow control settings, and
* setup the PHY advertisement registers accordingly. If
* auto-negotiation is enabled, then software will have to set the
* "PAUSE" bits to the correct value in the Auto-Negotiation
* Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-negotiation.
*
* The possible values of the "fc" parameter are:
* 0: Flow control is completely disabled
* 1: Rx flow control is enabled (we can receive pause frames
* but not send pause frames).
* 2: Tx flow control is enabled (we can send pause frames
* but we do not support receiving pause frames).
* 3: Both Rx and TX flow control (symmetric) are enabled.
* other: No software override. The flow control configuration
* in the EEPROM is used.
*/
switch (shared->fc) {
case e1000_fc_none: /* 0 */
/* Flow control (RX & TX) is completely disabled by a
* software over-ride.
*/
mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
break;
case e1000_fc_rx_pause: /* 1 */
/* RX Flow control is enabled, and TX Flow control is
* disabled, by a software over-ride.
*/
/* Since there really isn't a way to advertise that we are
* capable of RX Pause ONLY, we will advertise that we
* support both symmetric and asymmetric RX PAUSE. Later
* (in e1000_config_fc_after_link_up) we will disable the
*shared's ability to send PAUSE frames.
*/
mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
break;
case e1000_fc_tx_pause: /* 2 */
/* TX Flow control is enabled, and RX Flow control is
* disabled, by a software over-ride.
*/
mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
break;
case e1000_fc_full: /* 3 */
/* Flow control (both RX and TX) is enabled by a software
* over-ride.
*/
mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
break;
default:
/* We should never get here. The value should be 0-3. */
DEBUGOUT("Flow control param set incorrectly\n");
ASSERT(0);
break;
}
/* Write the MII Auto-Neg Advertisement Register (Address 4). */
e1000_write_phy_reg(shared, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
/* Write the MII 1000Base-T Control Register (Address 9). */
e1000_write_phy_reg(shared, PHY_1000T_CTRL, mii_1000t_ctrl_reg);
return (TRUE);
}
/******************************************************************************
* Sets MAC speed and duplex settings to reflect the those in the PHY
*
* shared - Struct containing variables accessed by shared code
* mii_reg - data to write to the MII control register
*
* The contents of the PHY register containing the needed information need to
* be passed in.
******************************************************************************/
void
e1000_config_mac_to_phy(struct e1000_shared_adapter *shared,
uint16_t mii_reg)
{
uint32_t ctrl_reg;
uint32_t tctl_reg;
uint32_t shift;
DEBUGFUNC("e1000_config_mac_to_phy");
/* We need to read the Transmit Control register to configure the
* collision distance.
* Note: This must be done for both Half or Full Duplex.
*/
tctl_reg = E1000_READ_REG(shared, TCTL);
DEBUGOUT1("tctl_reg = %x\n", tctl_reg);
/* Read the Device Control Register and set the bits to Force Speed
* and Duplex.
*/
ctrl_reg = E1000_READ_REG(shared, CTRL);
ctrl_reg |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
ctrl_reg &= ~(DEVICE_SPEED_MASK);
DEBUGOUT1("MII Register Data = %x\r\n", mii_reg);
/* Clear the ILOS bit. */
ctrl_reg &= ~E1000_CTRL_ILOS;
/* Set up duplex in the Device Control and Transmit Control
* registers depending on negotiated values.
*/
if(mii_reg & M88E1000_PSSR_DPLX) {
ctrl_reg |= E1000_CTRL_FD;
/* We are in Full Duplex mode. We have the same collision
* distance regardless of speed.
*/
tctl_reg &= ~E1000_TCTL_COLD;
shift = E1000_FDX_COLLISION_DISTANCE;
shift <<= E1000_COLD_SHIFT;
tctl_reg |= shift;
} else {
ctrl_reg &= ~E1000_CTRL_FD;
/* We are in Half Duplex mode. Our Half Duplex collision
* distance is different for Gigabit than for 10/100 so we will
* set accordingly.
*/
if((mii_reg & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) {
/* 1000Mbs HDX */
tctl_reg &= ~E1000_TCTL_COLD;
shift = E1000_GB_HDX_COLLISION_DISTANCE;
shift <<= E1000_COLD_SHIFT;
tctl_reg |= shift;
tctl_reg |= E1000_TCTL_PBE; /* Enable Packet Bursting */
} else {
/* 10/100Mbs HDX */
tctl_reg &= ~E1000_TCTL_COLD;
shift = E1000_HDX_COLLISION_DISTANCE;
shift <<= E1000_COLD_SHIFT;
tctl_reg |= shift;
}
}
/* Set up speed in the Device Control register depending on
* negotiated values.
*/
if((mii_reg & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS)
ctrl_reg |= E1000_CTRL_SPD_1000;
else if((mii_reg & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS)
ctrl_reg |= E1000_CTRL_SPD_100;
else
ctrl_reg &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
/* Write the configured values back to the Transmit Control Reg. */
E1000_WRITE_REG(shared, TCTL, tctl_reg);
/* Write the configured values back to the Device Control Reg. */
E1000_WRITE_REG(shared, CTRL, ctrl_reg);
return;
}
/******************************************************************************
* Sets the collision distance in the Transmit Control register
*
* shared - Struct containing variables accessed by shared code
*
* Link should have been established previously. Reads the speed and duplex
* information from the Device Status register.
******************************************************************************/
void
e1000_config_collision_dist(struct e1000_shared_adapter *shared)
{
uint32_t tctl_reg;
uint16_t speed;
uint16_t duplex;
uint32_t shift;
DEBUGFUNC("e1000_config_collision_dist");
/* Get our current speed and duplex from the Device Status Register. */
e1000_get_speed_and_duplex(shared, &speed, &duplex);
/* We need to configure the Collision Distance for both Full or
* Half Duplex.
*/
tctl_reg = E1000_READ_REG(shared, TCTL);
DEBUGOUT1("tctl_reg = %x\n", tctl_reg);
/* mask the Collision Distance bits in the Transmit Control Reg. */
tctl_reg &= ~E1000_TCTL_COLD;
if(duplex == FULL_DUPLEX) {
/* We are in Full Duplex mode. Therefore, the collision distance
* is the same regardless of speed.
*/
shift = E1000_FDX_COLLISION_DISTANCE;
shift <<= E1000_COLD_SHIFT;
tctl_reg |= shift;
} else {
/* We are in Half Duplex mode. Half Duplex collision distance is
* different for Gigabit vs. 10/100, so we will set accordingly.
*/
if(speed == SPEED_1000) { /* 1000Mbs HDX */
shift = E1000_GB_HDX_COLLISION_DISTANCE;
shift <<= E1000_COLD_SHIFT;
tctl_reg |= shift;
tctl_reg |= E1000_TCTL_PBE; /* Enable Packet Bursting */
} else { /* 10/100Mbs HDX */
shift = E1000_HDX_COLLISION_DISTANCE;
shift <<= E1000_COLD_SHIFT;
tctl_reg |= shift;
}
}
/* Write the configured values back to the Transmit Control Reg. */
E1000_WRITE_REG(shared, TCTL, tctl_reg);
return;
}
/******************************************************************************
* Probes the expected PHY address for known PHY IDs
*
* shared - Struct containing variables accessed by shared code
******************************************************************************/
boolean_t
e1000_detect_gig_phy(struct e1000_shared_adapter *shared)
{
uint32_t phy_id_high;
uint16_t phy_id_low;
DEBUGFUNC("e1000_detect_gig_phy");
/* Read the PHY ID Registers to identify which PHY is onboard. */
shared->phy_addr = 1;
phy_id_high = e1000_read_phy_reg(shared, PHY_ID1);
usec_delay(2);
phy_id_low = e1000_read_phy_reg(shared, PHY_ID2);
shared->phy_id = (phy_id_low | (phy_id_high << 16)) & PHY_REVISION_MASK;
if(shared->phy_id == M88E1000_12_PHY_ID ||
shared->phy_id == M88E1000_14_PHY_ID ||
shared->phy_id == M88E1000_I_PHY_ID) {
DEBUGOUT2("phy_id 0x%x detected at address 0x%x\n",
shared->phy_id, shared->phy_addr);
return (TRUE);
} else {
DEBUGOUT("Could not auto-detect Phy!\n");
return (FALSE);
}
}
/******************************************************************************
* Resets the PHY's DSP
*
* shared - Struct containing variables accessed by shared code
******************************************************************************/
void
e1000_phy_reset_dsp(struct e1000_shared_adapter *shared)
{
e1000_write_phy_reg(shared, 29, 0x1d);
e1000_write_phy_reg(shared, 30, 0xc1);
e1000_write_phy_reg(shared, 30, 0x00);
return;
}
/******************************************************************************
* Blocks until autoneg completes or times out (~4.5 seconds)
*
* shared - Struct containing variables accessed by shared code
******************************************************************************/
boolean_t
e1000_wait_autoneg(struct e1000_shared_adapter *shared)
{
uint16_t i;
uint16_t mii_status_reg;
boolean_t autoneg_complete = FALSE;
DEBUGFUNC("e1000_wait_autoneg");
/* We will wait for autoneg to complete. */
DEBUGOUT("Waiting for Auto-Neg to complete.\n");
mii_status_reg = 0;
/* We will wait for autoneg to complete or 4.5 seconds to expire. */
for(i = PHY_AUTO_NEG_TIME; i > 0; i--) {
/* Read the MII Status Register and wait for Auto-Neg
* Complete bit to be set.
*/
mii_status_reg = e1000_read_phy_reg(shared, PHY_STATUS);
mii_status_reg = e1000_read_phy_reg(shared, PHY_STATUS);
if(mii_status_reg & MII_SR_AUTONEG_COMPLETE) {
autoneg_complete = TRUE;
break;
}
msec_delay(100);
}
return (autoneg_complete);
}
/******************************************************************************
* Get PHY information from various PHY registers
*
* shared - Struct containing variables accessed by shared code
* phy_status_info - PHY information structure
******************************************************************************/
boolean_t
e1000_phy_get_info(struct e1000_shared_adapter *shared,
struct e1000_phy_info *phy_status_info)
{
uint16_t phy_mii_status_reg;
uint16_t phy_specific_ctrl_reg;
uint16_t phy_specific_status_reg;
uint16_t phy_specific_ext_ctrl_reg;
uint16_t phy_1000t_stat_reg;
phy_status_info->cable_length = e1000_cable_length_undefined;
phy_status_info->extended_10bt_distance =
e1000_10bt_ext_dist_enable_undefined;
phy_status_info->cable_polarity = e1000_rev_polarity_undefined;
phy_status_info->polarity_correction = e1000_polarity_reversal_undefined;
phy_status_info->link_reset = e1000_down_no_idle_undefined;
phy_status_info->mdix_mode = e1000_auto_x_mode_undefined;
phy_status_info->local_rx = e1000_1000t_rx_status_undefined;
phy_status_info->remote_rx = e1000_1000t_rx_status_undefined;
/* PHY info only valid for copper media. */
if(shared == NULL || shared->media_type != e1000_media_type_copper)
return FALSE;
/* PHY info only valid for LINK UP. Read MII status reg
* back-to-back to get link status.
*/
phy_mii_status_reg = e1000_read_phy_reg(shared, PHY_STATUS);
phy_mii_status_reg = e1000_read_phy_reg(shared, PHY_STATUS);
if((phy_mii_status_reg & MII_SR_LINK_STATUS) != MII_SR_LINK_STATUS)
return FALSE;
/* Read various PHY registers to get the PHY info. */
phy_specific_ctrl_reg = e1000_read_phy_reg(shared, M88E1000_PHY_SPEC_CTRL);
phy_specific_status_reg =
e1000_read_phy_reg(shared, M88E1000_PHY_SPEC_STATUS);
phy_specific_ext_ctrl_reg =
e1000_read_phy_reg(shared, M88E1000_EXT_PHY_SPEC_CTRL);
phy_1000t_stat_reg = e1000_read_phy_reg(shared, PHY_1000T_STATUS);
phy_status_info->cable_length =
((phy_specific_status_reg & M88E1000_PSSR_CABLE_LENGTH) >>
M88E1000_PSSR_CABLE_LENGTH_SHIFT);
phy_status_info->extended_10bt_distance =
(phy_specific_ctrl_reg & M88E1000_PSCR_10BT_EXT_DIST_ENABLE) >>
M88E1000_PSCR_10BT_EXT_DIST_ENABLE_SHIFT;
phy_status_info->cable_polarity =
(phy_specific_status_reg & M88E1000_PSSR_REV_POLARITY) >>
M88E1000_PSSR_REV_POLARITY_SHIFT;
phy_status_info->polarity_correction =
(phy_specific_ctrl_reg & M88E1000_PSCR_POLARITY_REVERSAL) >>
M88E1000_PSCR_POLARITY_REVERSAL_SHIFT;
phy_status_info->link_reset =
(phy_specific_ext_ctrl_reg & M88E1000_EPSCR_DOWN_NO_IDLE) >>
M88E1000_EPSCR_DOWN_NO_IDLE_SHIFT;
phy_status_info->mdix_mode =
(phy_specific_status_reg & M88E1000_PSSR_MDIX) >>
M88E1000_PSSR_MDIX_SHIFT;
phy_status_info->local_rx =
(phy_1000t_stat_reg & SR_1000T_LOCAL_RX_STATUS) >>
SR_1000T_LOCAL_RX_STATUS_SHIFT;
phy_status_info->remote_rx =
(phy_1000t_stat_reg & SR_1000T_REMOTE_RX_STATUS) >>
SR_1000T_REMOTE_RX_STATUS_SHIFT;
return TRUE;
}
boolean_t
e1000_validate_mdi_setting(struct e1000_shared_adapter *shared)
{
if(!shared->autoneg && (shared->mdix == 0 || shared->mdix == 3)) {
shared->mdix = 1;
return FALSE;
}
return TRUE;
}
drivers/net/e1000/e1000_phy.h deleted 100644 → 0
View file @ 6d87fb78
/*******************************************************************************
This software program is available to you under a choice of one of two
licenses. You may choose to be licensed under either the GNU General Public
License (GPL) Version 2, June 1991, available at
http://www.fsf.org/copyleft/gpl.html, or the Intel BSD + Patent License, the
text of which follows:
Recipient has requested a license and Intel Corporation ("Intel") is willing
to grant a license for the software entitled Linux Base Driver for the
Intel(R) PRO/1000 Family of Adapters (e1000) (the "Software") being provided
by Intel Corporation. The following definitions apply to this license:
"Licensed Patents" means patent claims licensable by Intel Corporation which
are necessarily infringed by the use of sale of the Software alone or when
combined with the operating system referred to below.
"Recipient" means the party to whom Intel delivers this Software.
"Licensee" means Recipient and those third parties that receive a license to
any operating system available under the GNU Public License version 2.0 or
later.
Copyright (c) 1999 - 2002 Intel Corporation.
All rights reserved.
The license is provided to Recipient and Recipient's Licensees under the
following terms.
Redistribution and use in source and binary forms of the Software, with or
without modification, are permitted provided that the following conditions
are met:
Redistributions of source code of the Software may retain the above
copyright notice, this list of conditions and the following disclaimer.
Redistributions in binary form of the Software may reproduce the above
copyright notice, this list of conditions and the following disclaimer in
the documentation and/or materials provided with the distribution.
Neither the name of Intel Corporation nor the names of its contributors
shall be used to endorse or promote products derived from this Software
without specific prior written permission.
Intel hereby grants Recipient and Licensees a non-exclusive, worldwide,
royalty-free patent license under Licensed Patents to make, use, sell, offer
to sell, import and otherwise transfer the Software, if any, in source code
and object code form. This license shall include changes to the Software
that are error corrections or other minor changes to the Software that do
not add functionality or features when the Software is incorporated in any
version of an operating system that has been distributed under the GNU
General Public License 2.0 or later. This patent license shall apply to the
combination of the Software and any operating system licensed under the GNU
Public License version 2.0 or later if, at the time Intel provides the
Software to Recipient, such addition of the Software to the then publicly
available versions of such operating systems available under the GNU Public
License version 2.0 or later (whether in gold, beta or alpha form) causes
such combination to be covered by the Licensed Patents. The patent license
shall not apply to any other combinations which include the Software. NO
hardware per se is licensed hereunder.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MECHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL INTEL OR IT CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
ANY LOSS OF USE; DATA, OR PROFITS; OR BUSINESS INTERUPTION) HOWEVER CAUSED
AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY OR
TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************/
/* e1000_phy.h
* Structures, enums, and macros for the PHY
*/
#ifndef _E1000_PHY_H_
#define _E1000_PHY_H_
#include "e1000_osdep.h"
/* PHY status info structure and supporting enums */
typedef enum {
e1000_cable_length_50 = 0,
e1000_cable_length_50_80,
e1000_cable_length_80_110,
e1000_cable_length_110_140,
e1000_cable_length_140,
e1000_cable_length_undefined = 0xFF
} e1000_cable_length;
typedef enum {
e1000_10bt_ext_dist_enable_normal = 0,
e1000_10bt_ext_dist_enable_lower,
e1000_10bt_ext_dist_enable_undefined = 0xFF
} e1000_10bt_ext_dist_enable;
typedef enum {
e1000_rev_polarity_normal = 0,
e1000_rev_polarity_reversed,
e1000_rev_polarity_undefined = 0xFF
} e1000_rev_polarity;
typedef enum {
e1000_polarity_reversal_enabled = 0,
e1000_polarity_reversal_disabled,
e1000_polarity_reversal_undefined = 0xFF
} e1000_polarity_reversal;
typedef enum {
e1000_down_no_idle_no_detect = 0,
e1000_down_no_idle_detect,
e1000_down_no_idle_undefined = 0xFF
} e1000_down_no_idle;
typedef enum {
e1000_auto_x_mode_manual_mdi = 0,
e1000_auto_x_mode_manual_mdix,
e1000_auto_x_mode_auto1,
e1000_auto_x_mode_auto2,
e1000_auto_x_mode_undefined = 0xFF
} e1000_auto_x_mode;
typedef enum {
e1000_1000t_rx_status_not_ok = 0,
e1000_1000t_rx_status_ok,
e1000_1000t_rx_status_undefined = 0xFF
} e1000_1000t_rx_status;
struct e1000_phy_info {
e1000_cable_length cable_length;
e1000_10bt_ext_dist_enable extended_10bt_distance;
e1000_rev_polarity cable_polarity;
e1000_polarity_reversal polarity_correction;
e1000_down_no_idle link_reset;
e1000_auto_x_mode mdix_mode;
e1000_1000t_rx_status local_rx;
e1000_1000t_rx_status remote_rx;
};
struct e1000_phy_stats {
uint32_t idle_errors;
uint32_t receive_errors;
};
/* Function Prototypes */
uint16_t e1000_read_phy_reg(struct e1000_shared_adapter *shared, uint32_t reg_addr);
void e1000_write_phy_reg(struct e1000_shared_adapter *shared, uint32_t reg_addr, uint16_t data);
void e1000_phy_hw_reset(struct e1000_shared_adapter *shared);
boolean_t e1000_phy_reset(struct e1000_shared_adapter *shared);
boolean_t e1000_phy_setup(struct e1000_shared_adapter *shared, uint32_t ctrl_reg);
boolean_t e1000_phy_setup_autoneg(struct e1000_shared_adapter *shared);
void e1000_config_mac_to_phy(struct e1000_shared_adapter *shared, uint16_t mii_reg);
void e1000_config_collision_dist(struct e1000_shared_adapter *shared);
boolean_t e1000_detect_gig_phy(struct e1000_shared_adapter *shared);
void e1000_phy_reset_dsp(struct e1000_shared_adapter *shared);
boolean_t e1000_wait_autoneg(struct e1000_shared_adapter *shared);
boolean_t e1000_phy_get_info(struct e1000_shared_adapter *shared, struct e1000_phy_info *phy_status_info);
boolean_t e1000_validate_mdi_setting(struct e1000_shared_adapter *shared);
/* Bit definitions for the Management Data IO (MDIO) and Management Data
* Clock (MDC) pins in the Device Control Register.
*/
#define E1000_CTRL_PHY_RESET_DIR E1000_CTRL_SWDPIO0
#define E1000_CTRL_PHY_RESET E1000_CTRL_SWDPIN0
#define E1000_CTRL_MDIO_DIR E1000_CTRL_SWDPIO2
#define E1000_CTRL_MDIO E1000_CTRL_SWDPIN2
#define E1000_CTRL_MDC_DIR E1000_CTRL_SWDPIO3
#define E1000_CTRL_MDC E1000_CTRL_SWDPIN3
#define E1000_CTRL_PHY_RESET_DIR4 E1000_CTRL_EXT_SDP4_DIR
#define E1000_CTRL_PHY_RESET4 E1000_CTRL_EXT_SDP4_DATA
/* PHY 1000 MII Register/Bit Definitions */
/* PHY Registers defined by IEEE */
#define PHY_CTRL 0x00 /* Control Register */
#define PHY_STATUS 0x01 /* Status Regiser */
#define PHY_ID1 0x02 /* Phy Id Reg (word 1) */
#define PHY_ID2 0x03 /* Phy Id Reg (word 2) */
#define PHY_AUTONEG_ADV 0x04 /* Autoneg Advertisement */
#define PHY_LP_ABILITY 0x05 /* Link Partner Ability (Base Page) */
#define PHY_AUTONEG_EXP 0x06 /* Autoneg Expansion Reg */
#define PHY_NEXT_PAGE_TX 0x07 /* Next Page TX */
#define PHY_LP_NEXT_PAGE 0x08 /* Link Partner Next Page */
#define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Reg */
#define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */
#define PHY_EXT_STATUS 0x0F /* Extended Status Reg */
/* M88E1000 Specific Registers */
#define M88E1000_PHY_SPEC_CTRL 0x10 /* PHY Specific Control Register */
#define M88E1000_PHY_SPEC_STATUS 0x11 /* PHY Specific Status Register */
#define M88E1000_INT_ENABLE 0x12 /* Interrupt Enable Register */
#define M88E1000_INT_STATUS 0x13 /* Interrupt Status Register */
#define M88E1000_EXT_PHY_SPEC_CTRL 0x14 /* Extended PHY Specific Control */
#define M88E1000_RX_ERR_CNTR 0x15 /* Receive Error Counter */
#define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */
/* PHY Control Register */
#define MII_CR_SPEED_SELECT_MSB 0x0040 /* bits 6,13: 10=1000, 01=100, 00=10 */
#define MII_CR_COLL_TEST_ENABLE 0x0080 /* Collision test enable */
#define MII_CR_FULL_DUPLEX 0x0100 /* FDX =1, half duplex =0 */
#define MII_CR_RESTART_AUTO_NEG 0x0200 /* Restart auto negotiation */
#define MII_CR_ISOLATE 0x0400 /* Isolate PHY from MII */
#define MII_CR_POWER_DOWN 0x0800 /* Power down */
#define MII_CR_AUTO_NEG_EN 0x1000 /* Auto Neg Enable */
#define MII_CR_SPEED_SELECT_LSB 0x2000 /* bits 6,13: 10=1000, 01=100, 00=10 */
#define MII_CR_LOOPBACK 0x4000 /* 0 = normal, 1 = loopback */
#define MII_CR_RESET 0x8000 /* 0 = normal, 1 = PHY reset */
/* PHY Status Register */
#define MII_SR_EXTENDED_CAPS 0x0001 /* Extended register capabilities */
#define MII_SR_JABBER_DETECT 0x0002 /* Jabber Detected */
#define MII_SR_LINK_STATUS 0x0004 /* Link Status 1 = link */
#define MII_SR_AUTONEG_CAPS 0x0008 /* Auto Neg Capable */
#define MII_SR_REMOTE_FAULT 0x0010 /* Remote Fault Detect */
#define MII_SR_AUTONEG_COMPLETE 0x0020 /* Auto Neg Complete */
#define MII_SR_PREAMBLE_SUPPRESS 0x0040 /* Preamble may be suppressed */
#define MII_SR_EXTENDED_STATUS 0x0100 /* Ext. status info in Reg 0x0F */
#define MII_SR_100T2_HD_CAPS 0x0200 /* 100T2 Half Duplex Capable */
#define MII_SR_100T2_FD_CAPS 0x0400 /* 100T2 Full Duplex Capable */
#define MII_SR_10T_HD_CAPS 0x0800 /* 10T Half Duplex Capable */
#define MII_SR_10T_FD_CAPS 0x1000 /* 10T Full Duplex Capable */
#define MII_SR_100X_HD_CAPS 0x2000 /* 100X Half Duplex Capable */
#define MII_SR_100X_FD_CAPS 0x4000 /* 100X Full Duplex Capable */
#define MII_SR_100T4_CAPS 0x8000 /* 100T4 Capable */
/* Autoneg Advertisement Register */
#define NWAY_AR_SELECTOR_FIELD 0x0001 /* indicates IEEE 802.3 CSMA/CD */
#define NWAY_AR_10T_HD_CAPS 0x0020 /* 10T Half Duplex Capable */
#define NWAY_AR_10T_FD_CAPS 0x0040 /* 10T Full Duplex Capable */
#define NWAY_AR_100TX_HD_CAPS 0x0080 /* 100TX Half Duplex Capable */
#define NWAY_AR_100TX_FD_CAPS 0x0100 /* 100TX Full Duplex Capable */
#define NWAY_AR_100T4_CAPS 0x0200 /* 100T4 Capable */
#define NWAY_AR_PAUSE 0x0400 /* Pause operation desired */
#define NWAY_AR_ASM_DIR 0x0800 /* Asymmetric Pause Direction bit */
#define NWAY_AR_REMOTE_FAULT 0x2000 /* Remote Fault detected */
#define NWAY_AR_NEXT_PAGE 0x8000 /* Next Page ability supported */
/* Link Partner Ability Register (Base Page) */
#define NWAY_LPAR_SELECTOR_FIELD 0x0000 /* LP protocol selector field */
#define NWAY_LPAR_10T_HD_CAPS 0x0020 /* LP is 10T Half Duplex Capable */
#define NWAY_LPAR_10T_FD_CAPS 0x0040 /* LP is 10T Full Duplex Capable */
#define NWAY_LPAR_100TX_HD_CAPS 0x0080 /* LP is 100TX Half Duplex Capable */
#define NWAY_LPAR_100TX_FD_CAPS 0x0100 /* LP is 100TX Full Duplex Capable */
#define NWAY_LPAR_100T4_CAPS 0x0200 /* LP is 100T4 Capable */
#define NWAY_LPAR_PAUSE 0x0400 /* LP Pause operation desired */
#define NWAY_LPAR_ASM_DIR 0x0800 /* LP Asymmetric Pause Direction bit */
#define NWAY_LPAR_REMOTE_FAULT 0x2000 /* LP has detected Remote Fault */
#define NWAY_LPAR_ACKNOWLEDGE 0x4000 /* LP has rx'd link code word */
#define NWAY_LPAR_NEXT_PAGE 0x8000 /* Next Page ability supported */
/* Autoneg Expansion Register */
#define NWAY_ER_LP_NWAY_CAPS 0x0001 /* LP has Auto Neg Capability */
#define NWAY_ER_PAGE_RXD 0x0002 /* LP is 10T Half Duplex Capable */
#define NWAY_ER_NEXT_PAGE_CAPS 0x0004 /* LP is 10T Full Duplex Capable */
#define NWAY_ER_LP_NEXT_PAGE_CAPS 0x0008 /* LP is 100TX Half Duplex Capable */
#define NWAY_ER_PAR_DETECT_FAULT 0x0100 /* LP is 100TX Full Duplex Capable */
/* Next Page TX Register */
#define NPTX_MSG_CODE_FIELD 0x0001 /* NP msg code or unformatted data */
#define NPTX_TOGGLE 0x0800 /* Toggles between exchanges
* of different NP
*/
#define NPTX_ACKNOWLDGE2 0x1000 /* 1 = will comply with msg
* 0 = cannot comply with msg
*/
#define NPTX_MSG_PAGE 0x2000 /* formatted(1)/unformatted(0) pg */
#define NPTX_NEXT_PAGE 0x8000 /* 1 = addition NP will follow
* 0 = sending last NP
*/
/* Link Partner Next Page Register */
#define LP_RNPR_MSG_CODE_FIELD 0x0001 /* NP msg code or unformatted data */
#define LP_RNPR_TOGGLE 0x0800 /* Toggles between exchanges
* of different NP
*/
#define LP_RNPR_ACKNOWLDGE2 0x1000 /* 1 = will comply with msg
* 0 = cannot comply with msg
*/
#define LP_RNPR_MSG_PAGE 0x2000 /* formatted(1)/unformatted(0) pg */
#define LP_RNPR_ACKNOWLDGE 0x4000 /* 1 = ACK / 0 = NO ACK */
#define LP_RNPR_NEXT_PAGE 0x8000 /* 1 = addition NP will follow
* 0 = sending last NP
*/
/* 1000BASE-T Control Register */
#define CR_1000T_ASYM_PAUSE 0x0080 /* Advertise asymmetric pause bit */
#define CR_1000T_HD_CAPS 0x0100 /* Advertise 1000T HD capability */
#define CR_1000T_FD_CAPS 0x0200 /* Advertise 1000T FD capability */
#define CR_1000T_REPEATER_DTE 0x0400 /* 1=Repeater/switch device port */
/* 0=DTE device */
#define CR_1000T_MS_VALUE 0x0800 /* 1=Configure PHY as Master */
/* 0=Configure PHY as Slave */
#define CR_1000T_MS_ENABLE 0x1000 /* 1=Master/Slave manual config value */
/* 0=Automatic Master/Slave config */
#define CR_1000T_TEST_MODE_NORMAL 0x0000 /* Normal Operation */
#define CR_1000T_TEST_MODE_1 0x2000 /* Transmit Waveform test */
#define CR_1000T_TEST_MODE_2 0x4000 /* Master Transmit Jitter test */
#define CR_1000T_TEST_MODE_3 0x6000 /* Slave Transmit Jitter test */
#define CR_1000T_TEST_MODE_4 0x8000 /* Transmitter Distortion test */
/* 1000BASE-T Status Register */
#define SR_1000T_IDLE_ERROR_CNT 0x00FF /* Num idle errors since last read */
#define SR_1000T_ASYM_PAUSE_DIR 0x0100 /* LP asymmetric pause direction bit */
#define SR_1000T_LP_HD_CAPS 0x0400 /* LP is 1000T HD capable */
#define SR_1000T_LP_FD_CAPS 0x0800 /* LP is 1000T FD capable */
#define SR_1000T_REMOTE_RX_STATUS 0x1000 /* Remote receiver OK */
#define SR_1000T_LOCAL_RX_STATUS 0x2000 /* Local receiver OK */
#define SR_1000T_MS_CONFIG_RES 0x4000 /* 1=Local TX is Master, 0=Slave */
#define SR_1000T_MS_CONFIG_FAULT 0x8000 /* Master/Slave config fault */
#define SR_1000T_REMOTE_RX_STATUS_SHIFT 12
#define SR_1000T_LOCAL_RX_STATUS_SHIFT 13
/* Extended Status Register */
#define IEEE_ESR_1000T_HD_CAPS 0x1000 /* 1000T HD capable */
#define IEEE_ESR_1000T_FD_CAPS 0x2000 /* 1000T FD capable */
#define IEEE_ESR_1000X_HD_CAPS 0x4000 /* 1000X HD capable */
#define IEEE_ESR_1000X_FD_CAPS 0x8000 /* 1000X FD capable */
#define PHY_TX_POLARITY_MASK 0x0100 /* register 10h bit 8 (polarity bit) */
#define PHY_TX_NORMAL_POLARITY 0 /* register 10h bit 8 (normal polarity) */
#define AUTO_POLARITY_DISABLE 0x0010 /* register 11h bit 4 */
/* (0=enable, 1=disable) */
/* M88E1000 PHY Specific Control Register */
#define M88E1000_PSCR_JABBER_DISABLE 0x0001 /* 1=Jabber Function disabled */
#define M88E1000_PSCR_POLARITY_REVERSAL 0x0002 /* 1=Polarity Reversal enabled */
#define M88E1000_PSCR_SQE_TEST 0x0004 /* 1=SQE Test enabled */
#define M88E1000_PSCR_CLK125_DISABLE 0x0010 /* 1=CLK125 low,
* 0=CLK125 toggling
*/
#define M88E1000_PSCR_MDI_MANUAL_MODE 0x0000 /* MDI Crossover Mode bits 6:5 */
/* Manual MDI configuration */
#define M88E1000_PSCR_MDIX_MANUAL_MODE 0x0020 /* Manual MDIX configuration */
#define M88E1000_PSCR_AUTO_X_1000T 0x0040 /* 1000BASE-T: Auto crossover,
* 100BASE-TX/10BASE-T:
* MDI Mode
*/
#define M88E1000_PSCR_AUTO_X_MODE 0x0060 /* Auto crossover enabled
* all speeds.
*/
#define M88E1000_PSCR_10BT_EXT_DIST_ENABLE 0x0080
/* 1=Enable Extended 10BASE-T distance
* (Lower 10BASE-T RX Threshold)
* 0=Normal 10BASE-T RX Threshold */
#define M88E1000_PSCR_MII_5BIT_ENABLE 0x0100
/* 1=5-Bit interface in 100BASE-TX
* 0=MII interface in 100BASE-TX */
#define M88E1000_PSCR_SCRAMBLER_DISABLE 0x0200 /* 1=Scrambler disable */
#define M88E1000_PSCR_FORCE_LINK_GOOD 0x0400 /* 1=Force link good */
#define M88E1000_PSCR_ASSERT_CRS_ON_TX 0x0800 /* 1=Assert CRS on Transmit */
#define M88E1000_PSCR_POLARITY_REVERSAL_SHIFT 1
#define M88E1000_PSCR_AUTO_X_MODE_SHIFT 5
#define M88E1000_PSCR_10BT_EXT_DIST_ENABLE_SHIFT 7
/* M88E1000 PHY Specific Status Register */
#define M88E1000_PSSR_JABBER 0x0001 /* 1=Jabber */
#define M88E1000_PSSR_REV_POLARITY 0x0002 /* 1=Polarity reversed */
#define M88E1000_PSSR_MDIX 0x0040 /* 1=MDIX; 0=MDI */
#define M88E1000_PSSR_CABLE_LENGTH 0x0380 /* 0=<50M;1=50-80M;2=80-110M;
* 3=110-140M;4=>140M */
#define M88E1000_PSSR_LINK 0x0400 /* 1=Link up, 0=Link down */
#define M88E1000_PSSR_SPD_DPLX_RESOLVED 0x0800 /* 1=Speed & Duplex resolved */
#define M88E1000_PSSR_PAGE_RCVD 0x1000 /* 1=Page received */
#define M88E1000_PSSR_DPLX 0x2000 /* 1=Duplex 0=Half Duplex */
#define M88E1000_PSSR_SPEED 0xC000 /* Speed, bits 14:15 */
#define M88E1000_PSSR_10MBS 0x0000 /* 00=10Mbs */
#define M88E1000_PSSR_100MBS 0x4000 /* 01=100Mbs */
#define M88E1000_PSSR_1000MBS 0x8000 /* 10=1000Mbs */
#define M88E1000_PSSR_REV_POLARITY_SHIFT 1
#define M88E1000_PSSR_MDIX_SHIFT 6
#define M88E1000_PSSR_CABLE_LENGTH_SHIFT 7
/* M88E1000 Extended PHY Specific Control Register */
#define M88E1000_EPSCR_FIBER_LOOPBACK 0x4000 /* 1=Fiber loopback */
#define M88E1000_EPSCR_DOWN_NO_IDLE 0x8000 /* 1=Lost lock detect enabled.
* Will assert lost lock and bring
* link down if idle not seen
* within 1ms in 1000BASE-T
*/
#define M88E1000_EPSCR_TX_CLK_2_5 0x0060 /* 2.5 MHz TX_CLK */
#define M88E1000_EPSCR_TX_CLK_25 0x0070 /* 25 MHz TX_CLK */
#define M88E1000_EPSCR_TX_CLK_0 0x0000 /* NO TX_CLK */
#define M88E1000_EPSCR_DOWN_NO_IDLE_SHIFT 15
/* Bit definitions for valid PHY IDs. */
#define M88E1000_12_PHY_ID 0x01410C50
#define M88E1000_14_PHY_ID 0x01410C40
#define M88E1000_I_PHY_ID 0x01410C30
/* Miscellaneous PHY bit definitions. */
#define PHY_PREAMBLE 0xFFFFFFFF
#define PHY_SOF 0x01
#define PHY_OP_READ 0x02
#define PHY_OP_WRITE 0x01
#define PHY_TURNAROUND 0x02
#define PHY_PREAMBLE_SIZE 32
#define MII_CR_SPEED_1000 0x0040
#define MII_CR_SPEED_100 0x2000
#define MII_CR_SPEED_10 0x0000
#define E1000_PHY_ADDRESS 0x01
#define PHY_AUTO_NEG_TIME 45 /* 4.5 Seconds */
#define PHY_FORCE_TIME 20 /* 2.0 Seconds */
#define PHY_REVISION_MASK 0xFFFFFFF0
#define DEVICE_SPEED_MASK 0x00000300 /* Device Ctrl Reg Speed Mask */
#define REG4_SPEED_MASK 0x01E0
#define REG9_SPEED_MASK 0x0300
#define ADVERTISE_10_HALF 0x0001
#define ADVERTISE_10_FULL 0x0002
#define ADVERTISE_100_HALF 0x0004
#define ADVERTISE_100_FULL 0x0008
#define ADVERTISE_1000_HALF 0x0010
#define ADVERTISE_1000_FULL 0x0020
#define AUTONEG_ADVERTISE_SPEED_DEFAULT 0x002F /* Everything but 1000-Half */
#endif /* _E1000_PHY_H_ */
drivers/net/e1000/e1000_proc.c
View file @ 09377d52
......@@ -546,18 +546,6 @@ e1000_proc_polarity_correction(void *data, size_t len, char *buf)
sprintf(buf,
correction == e1000_polarity_reversal_enabled ? "Disabled" :
correction == e1000_polarity_reversal_disabled ? "Enabled" :
"Undefined");
return buf;
}
static char *
e1000_proc_link_reset_enabled(void *data, size_t len, char *buf)
{
struct e1000_adapter *adapter = data;
e1000_down_no_idle link_reset = adapter->phy_info.link_reset;
sprintf(buf,
link_reset == e1000_down_no_idle_no_detect ? "Disabled" :
link_reset == e1000_down_no_idle_detect ? "Enabled" :
"Unknown");
return buf;
}
......@@ -567,7 +555,10 @@ e1000_proc_mdi_x_enabled(void *data, size_t len, char *buf)
{
struct e1000_adapter *adapter = data;
e1000_auto_x_mode mdix_mode = adapter->phy_info.mdix_mode;
sprintf(buf, mdix_mode == 0 ? "MDI" : "MDI-X");
sprintf(buf,
mdix_mode == e1000_auto_x_mode_manual_mdi ? "MDI" :
mdix_mode == e1000_auto_x_mode_manual_mdix ? "MDI-X" :
"Unknown");
return buf;
}
......@@ -600,7 +591,7 @@ e1000_proc_rx_status(void *data, size_t len, char *buf)
static void __devinit
e1000_proc_list_setup(struct e1000_adapter *adapter)
{
struct e1000_shared_adapter *shared = &adapter->shared;
struct e1000_hw *shared = &adapter->shared;
struct list_head *proc_list_head = &adapter->proc_list_head;
INIT_LIST_HEAD(proc_list_head);
......@@ -703,8 +694,6 @@ e1000_proc_list_setup(struct e1000_adapter *adapter)
adapter, e1000_proc_polarity_correction);
LIST_ADD_U("PHY_Idle_Errors",
&adapter->phy_stats.idle_errors);
LIST_ADD_F("PHY_Link_Reset_Enabled",
adapter, e1000_proc_link_reset_enabled);
LIST_ADD_U("PHY_Receive_Errors",
&adapter->phy_stats.receive_errors);
LIST_ADD_F("PHY_MDI_X_Enabled",
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment
GitLab Nexedi Edition | About GitLab | About Nexedi | 沪ICP备2021021310号-2 | 沪ICP备2021021310号-7