Commit 0afa0724 authored by Mark Brown's avatar Mark Brown

Merge remote-tracking branches 'spi/topic/armada', 'spi/topic/ath79',...

Merge remote-tracking branches 'spi/topic/armada', 'spi/topic/ath79', 'spi/topic/atmel' and 'spi/topic/axi' into spi-next
* Marvell Armada 3700 SPI Controller
Required Properties:
- compatible: should be "marvell,armada-3700-spi"
- reg: physical base address of the controller and length of memory mapped
region.
- interrupts: The interrupt number. The interrupt specifier format depends on
the interrupt controller and of its driver.
- clocks: Must contain the clock source, usually from the North Bridge clocks.
- num-cs: The number of chip selects that is supported by this SPI Controller
- #address-cells: should be 1.
- #size-cells: should be 0.
Example:
spi0: spi@10600 {
compatible = "marvell,armada-3700-spi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x10600 0x5d>;
clocks = <&nb_perih_clk 7>;
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
num-cs = <4>;
};
...@@ -67,6 +67,13 @@ config SPI_ATH79 ...@@ -67,6 +67,13 @@ config SPI_ATH79
This enables support for the SPI controller present on the This enables support for the SPI controller present on the
Atheros AR71XX/AR724X/AR913X SoCs. Atheros AR71XX/AR724X/AR913X SoCs.
config SPI_ARMADA_3700
tristate "Marvell Armada 3700 SPI Controller"
depends on (ARCH_MVEBU && OF) || COMPILE_TEST
help
This enables support for the SPI controller present on the
Marvell Armada 3700 SoCs.
config SPI_ATMEL config SPI_ATMEL
tristate "Atmel SPI Controller" tristate "Atmel SPI Controller"
depends on HAS_DMA depends on HAS_DMA
......
...@@ -12,6 +12,7 @@ obj-$(CONFIG_SPI_LOOPBACK_TEST) += spi-loopback-test.o ...@@ -12,6 +12,7 @@ obj-$(CONFIG_SPI_LOOPBACK_TEST) += spi-loopback-test.o
# SPI master controller drivers (bus) # SPI master controller drivers (bus)
obj-$(CONFIG_SPI_ALTERA) += spi-altera.o obj-$(CONFIG_SPI_ALTERA) += spi-altera.o
obj-$(CONFIG_SPI_ARMADA_3700) += spi-armada-3700.o
obj-$(CONFIG_SPI_ATMEL) += spi-atmel.o obj-$(CONFIG_SPI_ATMEL) += spi-atmel.o
obj-$(CONFIG_SPI_ATH79) += spi-ath79.o obj-$(CONFIG_SPI_ATH79) += spi-ath79.o
obj-$(CONFIG_SPI_AU1550) += spi-au1550.o obj-$(CONFIG_SPI_AU1550) += spi-au1550.o
......
/*
* Marvell Armada-3700 SPI controller driver
*
* Copyright (C) 2016 Marvell Ltd.
*
* Author: Wilson Ding <dingwei@marvell.com>
* Author: Romain Perier <romain.perier@free-electrons.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/clk.h>
#include <linux/completion.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_irq.h>
#include <linux/of_device.h>
#include <linux/pinctrl/consumer.h>
#include <linux/spi/spi.h>
#define DRIVER_NAME "armada_3700_spi"
#define A3700_SPI_TIMEOUT 10
/* SPI Register Offest */
#define A3700_SPI_IF_CTRL_REG 0x00
#define A3700_SPI_IF_CFG_REG 0x04
#define A3700_SPI_DATA_OUT_REG 0x08
#define A3700_SPI_DATA_IN_REG 0x0C
#define A3700_SPI_IF_INST_REG 0x10
#define A3700_SPI_IF_ADDR_REG 0x14
#define A3700_SPI_IF_RMODE_REG 0x18
#define A3700_SPI_IF_HDR_CNT_REG 0x1C
#define A3700_SPI_IF_DIN_CNT_REG 0x20
#define A3700_SPI_IF_TIME_REG 0x24
#define A3700_SPI_INT_STAT_REG 0x28
#define A3700_SPI_INT_MASK_REG 0x2C
/* A3700_SPI_IF_CTRL_REG */
#define A3700_SPI_EN BIT(16)
#define A3700_SPI_ADDR_NOT_CONFIG BIT(12)
#define A3700_SPI_WFIFO_OVERFLOW BIT(11)
#define A3700_SPI_WFIFO_UNDERFLOW BIT(10)
#define A3700_SPI_RFIFO_OVERFLOW BIT(9)
#define A3700_SPI_RFIFO_UNDERFLOW BIT(8)
#define A3700_SPI_WFIFO_FULL BIT(7)
#define A3700_SPI_WFIFO_EMPTY BIT(6)
#define A3700_SPI_RFIFO_FULL BIT(5)
#define A3700_SPI_RFIFO_EMPTY BIT(4)
#define A3700_SPI_WFIFO_RDY BIT(3)
#define A3700_SPI_RFIFO_RDY BIT(2)
#define A3700_SPI_XFER_RDY BIT(1)
#define A3700_SPI_XFER_DONE BIT(0)
/* A3700_SPI_IF_CFG_REG */
#define A3700_SPI_WFIFO_THRS BIT(28)
#define A3700_SPI_RFIFO_THRS BIT(24)
#define A3700_SPI_AUTO_CS BIT(20)
#define A3700_SPI_DMA_RD_EN BIT(18)
#define A3700_SPI_FIFO_MODE BIT(17)
#define A3700_SPI_SRST BIT(16)
#define A3700_SPI_XFER_START BIT(15)
#define A3700_SPI_XFER_STOP BIT(14)
#define A3700_SPI_INST_PIN BIT(13)
#define A3700_SPI_ADDR_PIN BIT(12)
#define A3700_SPI_DATA_PIN1 BIT(11)
#define A3700_SPI_DATA_PIN0 BIT(10)
#define A3700_SPI_FIFO_FLUSH BIT(9)
#define A3700_SPI_RW_EN BIT(8)
#define A3700_SPI_CLK_POL BIT(7)
#define A3700_SPI_CLK_PHA BIT(6)
#define A3700_SPI_BYTE_LEN BIT(5)
#define A3700_SPI_CLK_PRESCALE BIT(0)
#define A3700_SPI_CLK_PRESCALE_MASK (0x1f)
#define A3700_SPI_WFIFO_THRS_BIT 28
#define A3700_SPI_RFIFO_THRS_BIT 24
#define A3700_SPI_FIFO_THRS_MASK 0x7
#define A3700_SPI_DATA_PIN_MASK 0x3
/* A3700_SPI_IF_HDR_CNT_REG */
#define A3700_SPI_DUMMY_CNT_BIT 12
#define A3700_SPI_DUMMY_CNT_MASK 0x7
#define A3700_SPI_RMODE_CNT_BIT 8
#define A3700_SPI_RMODE_CNT_MASK 0x3
#define A3700_SPI_ADDR_CNT_BIT 4
#define A3700_SPI_ADDR_CNT_MASK 0x7
#define A3700_SPI_INSTR_CNT_BIT 0
#define A3700_SPI_INSTR_CNT_MASK 0x3
/* A3700_SPI_IF_TIME_REG */
#define A3700_SPI_CLK_CAPT_EDGE BIT(7)
/* Flags and macros for struct a3700_spi */
#define A3700_INSTR_CNT 1
#define A3700_ADDR_CNT 3
#define A3700_DUMMY_CNT 1
struct a3700_spi {
struct spi_master *master;
void __iomem *base;
struct clk *clk;
unsigned int irq;
unsigned int flags;
bool xmit_data;
const u8 *tx_buf;
u8 *rx_buf;
size_t buf_len;
u8 byte_len;
u32 wait_mask;
struct completion done;
u32 addr_cnt;
u32 instr_cnt;
size_t hdr_cnt;
};
static u32 spireg_read(struct a3700_spi *a3700_spi, u32 offset)
{
return readl(a3700_spi->base + offset);
}
static void spireg_write(struct a3700_spi *a3700_spi, u32 offset, u32 data)
{
writel(data, a3700_spi->base + offset);
}
static void a3700_spi_auto_cs_unset(struct a3700_spi *a3700_spi)
{
u32 val;
val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
val &= ~A3700_SPI_AUTO_CS;
spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
}
static void a3700_spi_activate_cs(struct a3700_spi *a3700_spi, unsigned int cs)
{
u32 val;
val = spireg_read(a3700_spi, A3700_SPI_IF_CTRL_REG);
val |= (A3700_SPI_EN << cs);
spireg_write(a3700_spi, A3700_SPI_IF_CTRL_REG, val);
}
static void a3700_spi_deactivate_cs(struct a3700_spi *a3700_spi,
unsigned int cs)
{
u32 val;
val = spireg_read(a3700_spi, A3700_SPI_IF_CTRL_REG);
val &= ~(A3700_SPI_EN << cs);
spireg_write(a3700_spi, A3700_SPI_IF_CTRL_REG, val);
}
static int a3700_spi_pin_mode_set(struct a3700_spi *a3700_spi,
unsigned int pin_mode)
{
u32 val;
val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
val &= ~(A3700_SPI_INST_PIN | A3700_SPI_ADDR_PIN);
val &= ~(A3700_SPI_DATA_PIN0 | A3700_SPI_DATA_PIN1);
switch (pin_mode) {
case 1:
break;
case 2:
val |= A3700_SPI_DATA_PIN0;
break;
case 4:
val |= A3700_SPI_DATA_PIN1;
break;
default:
dev_err(&a3700_spi->master->dev, "wrong pin mode %u", pin_mode);
return -EINVAL;
}
spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
return 0;
}
static void a3700_spi_fifo_mode_set(struct a3700_spi *a3700_spi)
{
u32 val;
val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
val |= A3700_SPI_FIFO_MODE;
spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
}
static void a3700_spi_mode_set(struct a3700_spi *a3700_spi,
unsigned int mode_bits)
{
u32 val;
val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
if (mode_bits & SPI_CPOL)
val |= A3700_SPI_CLK_POL;
else
val &= ~A3700_SPI_CLK_POL;
if (mode_bits & SPI_CPHA)
val |= A3700_SPI_CLK_PHA;
else
val &= ~A3700_SPI_CLK_PHA;
spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
}
static void a3700_spi_clock_set(struct a3700_spi *a3700_spi,
unsigned int speed_hz, u16 mode)
{
u32 val;
u32 prescale;
prescale = DIV_ROUND_UP(clk_get_rate(a3700_spi->clk), speed_hz);
val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
val = val & ~A3700_SPI_CLK_PRESCALE_MASK;
val = val | (prescale & A3700_SPI_CLK_PRESCALE_MASK);
spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
if (prescale <= 2) {
val = spireg_read(a3700_spi, A3700_SPI_IF_TIME_REG);
val |= A3700_SPI_CLK_CAPT_EDGE;
spireg_write(a3700_spi, A3700_SPI_IF_TIME_REG, val);
}
val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
val &= ~(A3700_SPI_CLK_POL | A3700_SPI_CLK_PHA);
if (mode & SPI_CPOL)
val |= A3700_SPI_CLK_POL;
if (mode & SPI_CPHA)
val |= A3700_SPI_CLK_PHA;
spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
}
static void a3700_spi_bytelen_set(struct a3700_spi *a3700_spi, unsigned int len)
{
u32 val;
val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
if (len == 4)
val |= A3700_SPI_BYTE_LEN;
else
val &= ~A3700_SPI_BYTE_LEN;
spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
a3700_spi->byte_len = len;
}
static int a3700_spi_fifo_flush(struct a3700_spi *a3700_spi)
{
int timeout = A3700_SPI_TIMEOUT;
u32 val;
val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
val |= A3700_SPI_FIFO_FLUSH;
spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
while (--timeout) {
val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
if (!(val & A3700_SPI_FIFO_FLUSH))
return 0;
udelay(1);
}
return -ETIMEDOUT;
}
static int a3700_spi_init(struct a3700_spi *a3700_spi)
{
struct spi_master *master = a3700_spi->master;
u32 val;
int i, ret = 0;
/* Reset SPI unit */
val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
val |= A3700_SPI_SRST;
spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
udelay(A3700_SPI_TIMEOUT);
val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
val &= ~A3700_SPI_SRST;
spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
/* Disable AUTO_CS and deactivate all chip-selects */
a3700_spi_auto_cs_unset(a3700_spi);
for (i = 0; i < master->num_chipselect; i++)
a3700_spi_deactivate_cs(a3700_spi, i);
/* Enable FIFO mode */
a3700_spi_fifo_mode_set(a3700_spi);
/* Set SPI mode */
a3700_spi_mode_set(a3700_spi, master->mode_bits);
/* Reset counters */
spireg_write(a3700_spi, A3700_SPI_IF_HDR_CNT_REG, 0);
spireg_write(a3700_spi, A3700_SPI_IF_DIN_CNT_REG, 0);
/* Mask the interrupts and clear cause bits */
spireg_write(a3700_spi, A3700_SPI_INT_MASK_REG, 0);
spireg_write(a3700_spi, A3700_SPI_INT_STAT_REG, ~0U);
return ret;
}
static irqreturn_t a3700_spi_interrupt(int irq, void *dev_id)
{
struct spi_master *master = dev_id;
struct a3700_spi *a3700_spi;
u32 cause;
a3700_spi = spi_master_get_devdata(master);
/* Get interrupt causes */
cause = spireg_read(a3700_spi, A3700_SPI_INT_STAT_REG);
if (!cause || !(a3700_spi->wait_mask & cause))
return IRQ_NONE;
/* mask and acknowledge the SPI interrupts */
spireg_write(a3700_spi, A3700_SPI_INT_MASK_REG, 0);
spireg_write(a3700_spi, A3700_SPI_INT_STAT_REG, cause);
/* Wake up the transfer */
if (a3700_spi->wait_mask & cause)
complete(&a3700_spi->done);
return IRQ_HANDLED;
}
static bool a3700_spi_wait_completion(struct spi_device *spi)
{
struct a3700_spi *a3700_spi;
unsigned int timeout;
unsigned int ctrl_reg;
unsigned long timeout_jiffies;
a3700_spi = spi_master_get_devdata(spi->master);
/* SPI interrupt is edge-triggered, which means an interrupt will
* be generated only when detecting a specific status bit changed
* from '0' to '1'. So when we start waiting for a interrupt, we
* need to check status bit in control reg first, if it is already 1,
* then we do not need to wait for interrupt
*/
ctrl_reg = spireg_read(a3700_spi, A3700_SPI_IF_CTRL_REG);
if (a3700_spi->wait_mask & ctrl_reg)
return true;
reinit_completion(&a3700_spi->done);
spireg_write(a3700_spi, A3700_SPI_INT_MASK_REG,
a3700_spi->wait_mask);
timeout_jiffies = msecs_to_jiffies(A3700_SPI_TIMEOUT);
timeout = wait_for_completion_timeout(&a3700_spi->done,
timeout_jiffies);
a3700_spi->wait_mask = 0;
if (timeout)
return true;
/* there might be the case that right after we checked the
* status bits in this routine and before start to wait for
* interrupt by wait_for_completion_timeout, the interrupt
* happens, to avoid missing it we need to double check
* status bits in control reg, if it is already 1, then
* consider that we have the interrupt successfully and
* return true.
*/
ctrl_reg = spireg_read(a3700_spi, A3700_SPI_IF_CTRL_REG);
if (a3700_spi->wait_mask & ctrl_reg)
return true;
spireg_write(a3700_spi, A3700_SPI_INT_MASK_REG, 0);
return true;
}
static bool a3700_spi_transfer_wait(struct spi_device *spi,
unsigned int bit_mask)
{
struct a3700_spi *a3700_spi;
a3700_spi = spi_master_get_devdata(spi->master);
a3700_spi->wait_mask = bit_mask;
return a3700_spi_wait_completion(spi);
}
static void a3700_spi_fifo_thres_set(struct a3700_spi *a3700_spi,
unsigned int bytes)
{
u32 val;
val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
val &= ~(A3700_SPI_FIFO_THRS_MASK << A3700_SPI_RFIFO_THRS_BIT);
val |= (bytes - 1) << A3700_SPI_RFIFO_THRS_BIT;
val &= ~(A3700_SPI_FIFO_THRS_MASK << A3700_SPI_WFIFO_THRS_BIT);
val |= (7 - bytes) << A3700_SPI_WFIFO_THRS_BIT;
spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
}
static void a3700_spi_transfer_setup(struct spi_device *spi,
struct spi_transfer *xfer)
{
struct a3700_spi *a3700_spi;
unsigned int byte_len;
a3700_spi = spi_master_get_devdata(spi->master);
a3700_spi_clock_set(a3700_spi, xfer->speed_hz, spi->mode);
byte_len = xfer->bits_per_word >> 3;
a3700_spi_fifo_thres_set(a3700_spi, byte_len);
}
static void a3700_spi_set_cs(struct spi_device *spi, bool enable)
{
struct a3700_spi *a3700_spi = spi_master_get_devdata(spi->master);
if (!enable)
a3700_spi_activate_cs(a3700_spi, spi->chip_select);
else
a3700_spi_deactivate_cs(a3700_spi, spi->chip_select);
}
static void a3700_spi_header_set(struct a3700_spi *a3700_spi)
{
u32 instr_cnt = 0, addr_cnt = 0, dummy_cnt = 0;
u32 val = 0;
/* Clear the header registers */
spireg_write(a3700_spi, A3700_SPI_IF_INST_REG, 0);
spireg_write(a3700_spi, A3700_SPI_IF_ADDR_REG, 0);
spireg_write(a3700_spi, A3700_SPI_IF_RMODE_REG, 0);
/* Set header counters */
if (a3700_spi->tx_buf) {
if (a3700_spi->buf_len <= a3700_spi->instr_cnt) {
instr_cnt = a3700_spi->buf_len;
} else if (a3700_spi->buf_len <= (a3700_spi->instr_cnt +
a3700_spi->addr_cnt)) {
instr_cnt = a3700_spi->instr_cnt;
addr_cnt = a3700_spi->buf_len - instr_cnt;
} else if (a3700_spi->buf_len <= a3700_spi->hdr_cnt) {
instr_cnt = a3700_spi->instr_cnt;
addr_cnt = a3700_spi->addr_cnt;
/* Need to handle the normal write case with 1 byte
* data
*/
if (!a3700_spi->tx_buf[instr_cnt + addr_cnt])
dummy_cnt = a3700_spi->buf_len - instr_cnt -
addr_cnt;
}
val |= ((instr_cnt & A3700_SPI_INSTR_CNT_MASK)
<< A3700_SPI_INSTR_CNT_BIT);
val |= ((addr_cnt & A3700_SPI_ADDR_CNT_MASK)
<< A3700_SPI_ADDR_CNT_BIT);
val |= ((dummy_cnt & A3700_SPI_DUMMY_CNT_MASK)
<< A3700_SPI_DUMMY_CNT_BIT);
}
spireg_write(a3700_spi, A3700_SPI_IF_HDR_CNT_REG, val);
/* Update the buffer length to be transferred */
a3700_spi->buf_len -= (instr_cnt + addr_cnt + dummy_cnt);
/* Set Instruction */
val = 0;
while (instr_cnt--) {
val = (val << 8) | a3700_spi->tx_buf[0];
a3700_spi->tx_buf++;
}
spireg_write(a3700_spi, A3700_SPI_IF_INST_REG, val);
/* Set Address */
val = 0;
while (addr_cnt--) {
val = (val << 8) | a3700_spi->tx_buf[0];
a3700_spi->tx_buf++;
}
spireg_write(a3700_spi, A3700_SPI_IF_ADDR_REG, val);
}
static int a3700_is_wfifo_full(struct a3700_spi *a3700_spi)
{
u32 val;
val = spireg_read(a3700_spi, A3700_SPI_IF_CTRL_REG);
return (val & A3700_SPI_WFIFO_FULL);
}
static int a3700_spi_fifo_write(struct a3700_spi *a3700_spi)
{
u32 val;
int i = 0;
while (!a3700_is_wfifo_full(a3700_spi) && a3700_spi->buf_len) {
val = 0;
if (a3700_spi->buf_len >= 4) {
val = cpu_to_le32(*(u32 *)a3700_spi->tx_buf);
spireg_write(a3700_spi, A3700_SPI_DATA_OUT_REG, val);
a3700_spi->buf_len -= 4;
a3700_spi->tx_buf += 4;
} else {
/*
* If the remained buffer length is less than 4-bytes,
* we should pad the write buffer with all ones. So that
* it avoids overwrite the unexpected bytes following
* the last one.
*/
val = GENMASK(31, 0);
while (a3700_spi->buf_len) {
val &= ~(0xff << (8 * i));
val |= *a3700_spi->tx_buf++ << (8 * i);
i++;
a3700_spi->buf_len--;
spireg_write(a3700_spi, A3700_SPI_DATA_OUT_REG,
val);
}
break;
}
}
return 0;
}
static int a3700_is_rfifo_empty(struct a3700_spi *a3700_spi)
{
u32 val = spireg_read(a3700_spi, A3700_SPI_IF_CTRL_REG);
return (val & A3700_SPI_RFIFO_EMPTY);
}
static int a3700_spi_fifo_read(struct a3700_spi *a3700_spi)
{
u32 val;
while (!a3700_is_rfifo_empty(a3700_spi) && a3700_spi->buf_len) {
val = spireg_read(a3700_spi, A3700_SPI_DATA_IN_REG);
if (a3700_spi->buf_len >= 4) {
u32 data = le32_to_cpu(val);
memcpy(a3700_spi->rx_buf, &data, 4);
a3700_spi->buf_len -= 4;
a3700_spi->rx_buf += 4;
} else {
/*
* When remain bytes is not larger than 4, we should
* avoid memory overwriting and just write the left rx
* buffer bytes.
*/
while (a3700_spi->buf_len) {
*a3700_spi->rx_buf = val & 0xff;
val >>= 8;
a3700_spi->buf_len--;
a3700_spi->rx_buf++;
}
}
}
return 0;
}
static void a3700_spi_transfer_abort_fifo(struct a3700_spi *a3700_spi)
{
int timeout = A3700_SPI_TIMEOUT;
u32 val;
val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
val |= A3700_SPI_XFER_STOP;
spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
while (--timeout) {
val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
if (!(val & A3700_SPI_XFER_START))
break;
udelay(1);
}
a3700_spi_fifo_flush(a3700_spi);
val &= ~A3700_SPI_XFER_STOP;
spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
}
static int a3700_spi_prepare_message(struct spi_master *master,
struct spi_message *message)
{
struct a3700_spi *a3700_spi = spi_master_get_devdata(master);
struct spi_device *spi = message->spi;
int ret;
ret = clk_enable(a3700_spi->clk);
if (ret) {
dev_err(&spi->dev, "failed to enable clk with error %d\n", ret);
return ret;
}
/* Flush the FIFOs */
ret = a3700_spi_fifo_flush(a3700_spi);
if (ret)
return ret;
a3700_spi_bytelen_set(a3700_spi, 4);
return 0;
}
static int a3700_spi_transfer_one(struct spi_master *master,
struct spi_device *spi,
struct spi_transfer *xfer)
{
struct a3700_spi *a3700_spi = spi_master_get_devdata(master);
int ret = 0, timeout = A3700_SPI_TIMEOUT;
unsigned int nbits = 0;
u32 val;
a3700_spi_transfer_setup(spi, xfer);
a3700_spi->tx_buf = xfer->tx_buf;
a3700_spi->rx_buf = xfer->rx_buf;
a3700_spi->buf_len = xfer->len;
/* SPI transfer headers */
a3700_spi_header_set(a3700_spi);
if (xfer->tx_buf)
nbits = xfer->tx_nbits;
else if (xfer->rx_buf)
nbits = xfer->rx_nbits;
a3700_spi_pin_mode_set(a3700_spi, nbits);
if (xfer->rx_buf) {
/* Set read data length */
spireg_write(a3700_spi, A3700_SPI_IF_DIN_CNT_REG,
a3700_spi->buf_len);
/* Start READ transfer */
val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
val &= ~A3700_SPI_RW_EN;
val |= A3700_SPI_XFER_START;
spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
} else if (xfer->tx_buf) {
/* Start Write transfer */
val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
val |= (A3700_SPI_XFER_START | A3700_SPI_RW_EN);
spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
/*
* If there are data to be written to the SPI device, xmit_data
* flag is set true; otherwise the instruction in SPI_INSTR does
* not require data to be written to the SPI device, then
* xmit_data flag is set false.
*/
a3700_spi->xmit_data = (a3700_spi->buf_len != 0);
}
while (a3700_spi->buf_len) {
if (a3700_spi->tx_buf) {
/* Wait wfifo ready */
if (!a3700_spi_transfer_wait(spi,
A3700_SPI_WFIFO_RDY)) {
dev_err(&spi->dev,
"wait wfifo ready timed out\n");
ret = -ETIMEDOUT;
goto error;
}
/* Fill up the wfifo */
ret = a3700_spi_fifo_write(a3700_spi);
if (ret)
goto error;
} else if (a3700_spi->rx_buf) {
/* Wait rfifo ready */
if (!a3700_spi_transfer_wait(spi,
A3700_SPI_RFIFO_RDY)) {
dev_err(&spi->dev,
"wait rfifo ready timed out\n");
ret = -ETIMEDOUT;
goto error;
}
/* Drain out the rfifo */
ret = a3700_spi_fifo_read(a3700_spi);
if (ret)
goto error;
}
}
/*
* Stop a write transfer in fifo mode:
* - wait all the bytes in wfifo to be shifted out
* - set XFER_STOP bit
* - wait XFER_START bit clear
* - clear XFER_STOP bit
* Stop a read transfer in fifo mode:
* - the hardware is to reset the XFER_START bit
* after the number of bytes indicated in DIN_CNT
* register
* - just wait XFER_START bit clear
*/
if (a3700_spi->tx_buf) {
if (a3700_spi->xmit_data) {
/*
* If there are data written to the SPI device, wait
* until SPI_WFIFO_EMPTY is 1 to wait for all data to
* transfer out of write FIFO.
*/
if (!a3700_spi_transfer_wait(spi,
A3700_SPI_WFIFO_EMPTY)) {
dev_err(&spi->dev, "wait wfifo empty timed out\n");
return -ETIMEDOUT;
}
} else {
/*
* If the instruction in SPI_INSTR does not require data
* to be written to the SPI device, wait until SPI_RDY
* is 1 for the SPI interface to be in idle.
*/
if (!a3700_spi_transfer_wait(spi, A3700_SPI_XFER_RDY)) {
dev_err(&spi->dev, "wait xfer ready timed out\n");
return -ETIMEDOUT;
}
}
val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
val |= A3700_SPI_XFER_STOP;
spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
}
while (--timeout) {
val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
if (!(val & A3700_SPI_XFER_START))
break;
udelay(1);
}
if (timeout == 0) {
dev_err(&spi->dev, "wait transfer start clear timed out\n");
ret = -ETIMEDOUT;
goto error;
}
val &= ~A3700_SPI_XFER_STOP;
spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
goto out;
error:
a3700_spi_transfer_abort_fifo(a3700_spi);
out:
spi_finalize_current_transfer(master);
return ret;
}
static int a3700_spi_unprepare_message(struct spi_master *master,
struct spi_message *message)
{
struct a3700_spi *a3700_spi = spi_master_get_devdata(master);
clk_disable(a3700_spi->clk);
return 0;
}
static const struct of_device_id a3700_spi_dt_ids[] = {
{ .compatible = "marvell,armada-3700-spi", .data = NULL },
{},
};
MODULE_DEVICE_TABLE(of, a3700_spi_dt_ids);
static int a3700_spi_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct device_node *of_node = dev->of_node;
struct resource *res;
struct spi_master *master;
struct a3700_spi *spi;
u32 num_cs = 0;
int ret = 0;
master = spi_alloc_master(dev, sizeof(*spi));
if (!master) {
dev_err(dev, "master allocation failed\n");
ret = -ENOMEM;
goto out;
}
if (of_property_read_u32(of_node, "num-cs", &num_cs)) {
dev_err(dev, "could not find num-cs\n");
ret = -ENXIO;
goto error;
}
master->bus_num = pdev->id;
master->dev.of_node = of_node;
master->mode_bits = SPI_MODE_3;
master->num_chipselect = num_cs;
master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(32);
master->prepare_message = a3700_spi_prepare_message;
master->transfer_one = a3700_spi_transfer_one;
master->unprepare_message = a3700_spi_unprepare_message;
master->set_cs = a3700_spi_set_cs;
master->flags = SPI_MASTER_HALF_DUPLEX;
master->mode_bits |= (SPI_RX_DUAL | SPI_RX_DUAL |
SPI_RX_QUAD | SPI_TX_QUAD);
platform_set_drvdata(pdev, master);
spi = spi_master_get_devdata(master);
memset(spi, 0, sizeof(struct a3700_spi));
spi->master = master;
spi->instr_cnt = A3700_INSTR_CNT;
spi->addr_cnt = A3700_ADDR_CNT;
spi->hdr_cnt = A3700_INSTR_CNT + A3700_ADDR_CNT +
A3700_DUMMY_CNT;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
spi->base = devm_ioremap_resource(dev, res);
if (IS_ERR(spi->base)) {
ret = PTR_ERR(spi->base);
goto error;
}
spi->irq = platform_get_irq(pdev, 0);
if (spi->irq < 0) {
dev_err(dev, "could not get irq: %d\n", spi->irq);
ret = -ENXIO;
goto error;
}
init_completion(&spi->done);
spi->clk = devm_clk_get(dev, NULL);
if (IS_ERR(spi->clk)) {
dev_err(dev, "could not find clk: %ld\n", PTR_ERR(spi->clk));
goto error;
}
ret = clk_prepare(spi->clk);
if (ret) {
dev_err(dev, "could not prepare clk: %d\n", ret);
goto error;
}
ret = a3700_spi_init(spi);
if (ret)
goto error_clk;
ret = devm_request_irq(dev, spi->irq, a3700_spi_interrupt, 0,
dev_name(dev), master);
if (ret) {
dev_err(dev, "could not request IRQ: %d\n", ret);
goto error_clk;
}
ret = devm_spi_register_master(dev, master);
if (ret) {
dev_err(dev, "Failed to register master\n");
goto error_clk;
}
return 0;
error_clk:
clk_disable_unprepare(spi->clk);
error:
spi_master_put(master);
out:
return ret;
}
static int a3700_spi_remove(struct platform_device *pdev)
{
struct spi_master *master = platform_get_drvdata(pdev);
struct a3700_spi *spi = spi_master_get_devdata(master);
clk_unprepare(spi->clk);
spi_master_put(master);
return 0;
}
static struct platform_driver a3700_spi_driver = {
.driver = {
.name = DRIVER_NAME,
.owner = THIS_MODULE,
.of_match_table = of_match_ptr(a3700_spi_dt_ids),
},
.probe = a3700_spi_probe,
.remove = a3700_spi_remove,
};
module_platform_driver(a3700_spi_driver);
MODULE_DESCRIPTION("Armada-3700 SPI driver");
MODULE_AUTHOR("Wilson Ding <dingwei@marvell.com>");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:" DRIVER_NAME);
...@@ -304,6 +304,7 @@ static const struct of_device_id ath79_spi_of_match[] = { ...@@ -304,6 +304,7 @@ static const struct of_device_id ath79_spi_of_match[] = {
{ .compatible = "qca,ar7100-spi", }, { .compatible = "qca,ar7100-spi", },
{ }, { },
}; };
MODULE_DEVICE_TABLE(of, ath79_spi_of_match);
static struct platform_driver ath79_spi_driver = { static struct platform_driver ath79_spi_driver = {
.probe = ath79_spi_probe, .probe = ath79_spi_probe,
......
...@@ -265,17 +265,6 @@ ...@@ -265,17 +265,6 @@
#define AUTOSUSPEND_TIMEOUT 2000 #define AUTOSUSPEND_TIMEOUT 2000
struct atmel_spi_dma {
struct dma_chan *chan_rx;
struct dma_chan *chan_tx;
struct scatterlist sgrx;
struct scatterlist sgtx;
struct dma_async_tx_descriptor *data_desc_rx;
struct dma_async_tx_descriptor *data_desc_tx;
struct at_dma_slave dma_slave;
};
struct atmel_spi_caps { struct atmel_spi_caps {
bool is_spi2; bool is_spi2;
bool has_wdrbt; bool has_wdrbt;
...@@ -304,17 +293,11 @@ struct atmel_spi { ...@@ -304,17 +293,11 @@ struct atmel_spi {
struct completion xfer_completion; struct completion xfer_completion;
/* scratch buffer */
void *buffer;
dma_addr_t buffer_dma;
struct atmel_spi_caps caps; struct atmel_spi_caps caps;
bool use_dma; bool use_dma;
bool use_pdc; bool use_pdc;
bool use_cs_gpios; bool use_cs_gpios;
/* dmaengine data */
struct atmel_spi_dma dma;
bool keep_cs; bool keep_cs;
bool cs_active; bool cs_active;
...@@ -328,7 +311,7 @@ struct atmel_spi_device { ...@@ -328,7 +311,7 @@ struct atmel_spi_device {
u32 csr; u32 csr;
}; };
#define BUFFER_SIZE PAGE_SIZE #define SPI_MAX_DMA_XFER 65535 /* true for both PDC and DMA */
#define INVALID_DMA_ADDRESS 0xffffffff #define INVALID_DMA_ADDRESS 0xffffffff
/* /*
...@@ -458,10 +441,20 @@ static inline bool atmel_spi_use_dma(struct atmel_spi *as, ...@@ -458,10 +441,20 @@ static inline bool atmel_spi_use_dma(struct atmel_spi *as,
return as->use_dma && xfer->len >= DMA_MIN_BYTES; return as->use_dma && xfer->len >= DMA_MIN_BYTES;
} }
static bool atmel_spi_can_dma(struct spi_master *master,
struct spi_device *spi,
struct spi_transfer *xfer)
{
struct atmel_spi *as = spi_master_get_devdata(master);
return atmel_spi_use_dma(as, xfer);
}
static int atmel_spi_dma_slave_config(struct atmel_spi *as, static int atmel_spi_dma_slave_config(struct atmel_spi *as,
struct dma_slave_config *slave_config, struct dma_slave_config *slave_config,
u8 bits_per_word) u8 bits_per_word)
{ {
struct spi_master *master = platform_get_drvdata(as->pdev);
int err = 0; int err = 0;
if (bits_per_word > 8) { if (bits_per_word > 8) {
...@@ -493,7 +486,7 @@ static int atmel_spi_dma_slave_config(struct atmel_spi *as, ...@@ -493,7 +486,7 @@ static int atmel_spi_dma_slave_config(struct atmel_spi *as,
* path works the same whether FIFOs are available (and enabled) or not. * path works the same whether FIFOs are available (and enabled) or not.
*/ */
slave_config->direction = DMA_MEM_TO_DEV; slave_config->direction = DMA_MEM_TO_DEV;
if (dmaengine_slave_config(as->dma.chan_tx, slave_config)) { if (dmaengine_slave_config(master->dma_tx, slave_config)) {
dev_err(&as->pdev->dev, dev_err(&as->pdev->dev,
"failed to configure tx dma channel\n"); "failed to configure tx dma channel\n");
err = -EINVAL; err = -EINVAL;
...@@ -508,7 +501,7 @@ static int atmel_spi_dma_slave_config(struct atmel_spi *as, ...@@ -508,7 +501,7 @@ static int atmel_spi_dma_slave_config(struct atmel_spi *as,
* enabled) or not. * enabled) or not.
*/ */
slave_config->direction = DMA_DEV_TO_MEM; slave_config->direction = DMA_DEV_TO_MEM;
if (dmaengine_slave_config(as->dma.chan_rx, slave_config)) { if (dmaengine_slave_config(master->dma_rx, slave_config)) {
dev_err(&as->pdev->dev, dev_err(&as->pdev->dev,
"failed to configure rx dma channel\n"); "failed to configure rx dma channel\n");
err = -EINVAL; err = -EINVAL;
...@@ -517,7 +510,8 @@ static int atmel_spi_dma_slave_config(struct atmel_spi *as, ...@@ -517,7 +510,8 @@ static int atmel_spi_dma_slave_config(struct atmel_spi *as,
return err; return err;
} }
static int atmel_spi_configure_dma(struct atmel_spi *as) static int atmel_spi_configure_dma(struct spi_master *master,
struct atmel_spi *as)
{ {
struct dma_slave_config slave_config; struct dma_slave_config slave_config;
struct device *dev = &as->pdev->dev; struct device *dev = &as->pdev->dev;
...@@ -527,26 +521,26 @@ static int atmel_spi_configure_dma(struct atmel_spi *as) ...@@ -527,26 +521,26 @@ static int atmel_spi_configure_dma(struct atmel_spi *as)
dma_cap_zero(mask); dma_cap_zero(mask);
dma_cap_set(DMA_SLAVE, mask); dma_cap_set(DMA_SLAVE, mask);
as->dma.chan_tx = dma_request_slave_channel_reason(dev, "tx"); master->dma_tx = dma_request_slave_channel_reason(dev, "tx");
if (IS_ERR(as->dma.chan_tx)) { if (IS_ERR(master->dma_tx)) {
err = PTR_ERR(as->dma.chan_tx); err = PTR_ERR(master->dma_tx);
if (err == -EPROBE_DEFER) { if (err == -EPROBE_DEFER) {
dev_warn(dev, "no DMA channel available at the moment\n"); dev_warn(dev, "no DMA channel available at the moment\n");
return err; goto error_clear;
} }
dev_err(dev, dev_err(dev,
"DMA TX channel not available, SPI unable to use DMA\n"); "DMA TX channel not available, SPI unable to use DMA\n");
err = -EBUSY; err = -EBUSY;
goto error; goto error_clear;
} }
/* /*
* No reason to check EPROBE_DEFER here since we have already requested * No reason to check EPROBE_DEFER here since we have already requested
* tx channel. If it fails here, it's for another reason. * tx channel. If it fails here, it's for another reason.
*/ */
as->dma.chan_rx = dma_request_slave_channel(dev, "rx"); master->dma_rx = dma_request_slave_channel(dev, "rx");
if (!as->dma.chan_rx) { if (!master->dma_rx) {
dev_err(dev, dev_err(dev,
"DMA RX channel not available, SPI unable to use DMA\n"); "DMA RX channel not available, SPI unable to use DMA\n");
err = -EBUSY; err = -EBUSY;
...@@ -559,31 +553,38 @@ static int atmel_spi_configure_dma(struct atmel_spi *as) ...@@ -559,31 +553,38 @@ static int atmel_spi_configure_dma(struct atmel_spi *as)
dev_info(&as->pdev->dev, dev_info(&as->pdev->dev,
"Using %s (tx) and %s (rx) for DMA transfers\n", "Using %s (tx) and %s (rx) for DMA transfers\n",
dma_chan_name(as->dma.chan_tx), dma_chan_name(master->dma_tx),
dma_chan_name(as->dma.chan_rx)); dma_chan_name(master->dma_rx));
return 0; return 0;
error: error:
if (as->dma.chan_rx) if (master->dma_rx)
dma_release_channel(as->dma.chan_rx); dma_release_channel(master->dma_rx);
if (!IS_ERR(as->dma.chan_tx)) if (!IS_ERR(master->dma_tx))
dma_release_channel(as->dma.chan_tx); dma_release_channel(master->dma_tx);
error_clear:
master->dma_tx = master->dma_rx = NULL;
return err; return err;
} }
static void atmel_spi_stop_dma(struct atmel_spi *as) static void atmel_spi_stop_dma(struct spi_master *master)
{ {
if (as->dma.chan_rx) if (master->dma_rx)
dmaengine_terminate_all(as->dma.chan_rx); dmaengine_terminate_all(master->dma_rx);
if (as->dma.chan_tx) if (master->dma_tx)
dmaengine_terminate_all(as->dma.chan_tx); dmaengine_terminate_all(master->dma_tx);
} }
static void atmel_spi_release_dma(struct atmel_spi *as) static void atmel_spi_release_dma(struct spi_master *master)
{ {
if (as->dma.chan_rx) if (master->dma_rx) {
dma_release_channel(as->dma.chan_rx); dma_release_channel(master->dma_rx);
if (as->dma.chan_tx) master->dma_rx = NULL;
dma_release_channel(as->dma.chan_tx); }
if (master->dma_tx) {
dma_release_channel(master->dma_tx);
master->dma_tx = NULL;
}
} }
/* This function is called by the DMA driver from tasklet context */ /* This function is called by the DMA driver from tasklet context */
...@@ -613,14 +614,10 @@ static void atmel_spi_next_xfer_single(struct spi_master *master, ...@@ -613,14 +614,10 @@ static void atmel_spi_next_xfer_single(struct spi_master *master,
cpu_relax(); cpu_relax();
} }
if (xfer->tx_buf) { if (xfer->bits_per_word > 8)
if (xfer->bits_per_word > 8) spi_writel(as, TDR, *(u16 *)(xfer->tx_buf + xfer_pos));
spi_writel(as, TDR, *(u16 *)(xfer->tx_buf + xfer_pos)); else
else spi_writel(as, TDR, *(u8 *)(xfer->tx_buf + xfer_pos));
spi_writel(as, TDR, *(u8 *)(xfer->tx_buf + xfer_pos));
} else {
spi_writel(as, TDR, 0);
}
dev_dbg(master->dev.parent, dev_dbg(master->dev.parent,
" start pio xfer %p: len %u tx %p rx %p bitpw %d\n", " start pio xfer %p: len %u tx %p rx %p bitpw %d\n",
...@@ -667,17 +664,12 @@ static void atmel_spi_next_xfer_fifo(struct spi_master *master, ...@@ -667,17 +664,12 @@ static void atmel_spi_next_xfer_fifo(struct spi_master *master,
/* Fill TX FIFO */ /* Fill TX FIFO */
while (num_data >= 2) { while (num_data >= 2) {
if (xfer->tx_buf) { if (xfer->bits_per_word > 8) {
if (xfer->bits_per_word > 8) { td0 = *words++;
td0 = *words++; td1 = *words++;
td1 = *words++;
} else {
td0 = *bytes++;
td1 = *bytes++;
}
} else { } else {
td0 = 0; td0 = *bytes++;
td1 = 0; td1 = *bytes++;
} }
spi_writel(as, TDR, (td1 << 16) | td0); spi_writel(as, TDR, (td1 << 16) | td0);
...@@ -685,14 +677,10 @@ static void atmel_spi_next_xfer_fifo(struct spi_master *master, ...@@ -685,14 +677,10 @@ static void atmel_spi_next_xfer_fifo(struct spi_master *master,
} }
if (num_data) { if (num_data) {
if (xfer->tx_buf) { if (xfer->bits_per_word > 8)
if (xfer->bits_per_word > 8) td0 = *words++;
td0 = *words++; else
else td0 = *bytes++;
td0 = *bytes++;
} else {
td0 = 0;
}
spi_writew(as, TDR, td0); spi_writew(as, TDR, td0);
num_data--; num_data--;
...@@ -732,13 +720,12 @@ static int atmel_spi_next_xfer_dma_submit(struct spi_master *master, ...@@ -732,13 +720,12 @@ static int atmel_spi_next_xfer_dma_submit(struct spi_master *master,
u32 *plen) u32 *plen)
{ {
struct atmel_spi *as = spi_master_get_devdata(master); struct atmel_spi *as = spi_master_get_devdata(master);
struct dma_chan *rxchan = as->dma.chan_rx; struct dma_chan *rxchan = master->dma_rx;
struct dma_chan *txchan = as->dma.chan_tx; struct dma_chan *txchan = master->dma_tx;
struct dma_async_tx_descriptor *rxdesc; struct dma_async_tx_descriptor *rxdesc;
struct dma_async_tx_descriptor *txdesc; struct dma_async_tx_descriptor *txdesc;
struct dma_slave_config slave_config; struct dma_slave_config slave_config;
dma_cookie_t cookie; dma_cookie_t cookie;
u32 len = *plen;
dev_vdbg(master->dev.parent, "atmel_spi_next_xfer_dma_submit\n"); dev_vdbg(master->dev.parent, "atmel_spi_next_xfer_dma_submit\n");
...@@ -749,44 +736,22 @@ static int atmel_spi_next_xfer_dma_submit(struct spi_master *master, ...@@ -749,44 +736,22 @@ static int atmel_spi_next_xfer_dma_submit(struct spi_master *master,
/* release lock for DMA operations */ /* release lock for DMA operations */
atmel_spi_unlock(as); atmel_spi_unlock(as);
/* prepare the RX dma transfer */ *plen = xfer->len;
sg_init_table(&as->dma.sgrx, 1);
if (xfer->rx_buf) {
as->dma.sgrx.dma_address = xfer->rx_dma + xfer->len - *plen;
} else {
as->dma.sgrx.dma_address = as->buffer_dma;
if (len > BUFFER_SIZE)
len = BUFFER_SIZE;
}
/* prepare the TX dma transfer */
sg_init_table(&as->dma.sgtx, 1);
if (xfer->tx_buf) {
as->dma.sgtx.dma_address = xfer->tx_dma + xfer->len - *plen;
} else {
as->dma.sgtx.dma_address = as->buffer_dma;
if (len > BUFFER_SIZE)
len = BUFFER_SIZE;
memset(as->buffer, 0, len);
}
sg_dma_len(&as->dma.sgtx) = len;
sg_dma_len(&as->dma.sgrx) = len;
*plen = len;
if (atmel_spi_dma_slave_config(as, &slave_config, if (atmel_spi_dma_slave_config(as, &slave_config,
xfer->bits_per_word)) xfer->bits_per_word))
goto err_exit; goto err_exit;
/* Send both scatterlists */ /* Send both scatterlists */
rxdesc = dmaengine_prep_slave_sg(rxchan, &as->dma.sgrx, 1, rxdesc = dmaengine_prep_slave_sg(rxchan,
xfer->rx_sg.sgl, xfer->rx_sg.nents,
DMA_FROM_DEVICE, DMA_FROM_DEVICE,
DMA_PREP_INTERRUPT | DMA_CTRL_ACK); DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
if (!rxdesc) if (!rxdesc)
goto err_dma; goto err_dma;
txdesc = dmaengine_prep_slave_sg(txchan, &as->dma.sgtx, 1, txdesc = dmaengine_prep_slave_sg(txchan,
xfer->tx_sg.sgl, xfer->tx_sg.nents,
DMA_TO_DEVICE, DMA_TO_DEVICE,
DMA_PREP_INTERRUPT | DMA_CTRL_ACK); DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
if (!txdesc) if (!txdesc)
...@@ -820,7 +785,7 @@ static int atmel_spi_next_xfer_dma_submit(struct spi_master *master, ...@@ -820,7 +785,7 @@ static int atmel_spi_next_xfer_dma_submit(struct spi_master *master,
err_dma: err_dma:
spi_writel(as, IDR, SPI_BIT(OVRES)); spi_writel(as, IDR, SPI_BIT(OVRES));
atmel_spi_stop_dma(as); atmel_spi_stop_dma(master);
err_exit: err_exit:
atmel_spi_lock(as); atmel_spi_lock(as);
return -ENOMEM; return -ENOMEM;
...@@ -832,30 +797,10 @@ static void atmel_spi_next_xfer_data(struct spi_master *master, ...@@ -832,30 +797,10 @@ static void atmel_spi_next_xfer_data(struct spi_master *master,
dma_addr_t *rx_dma, dma_addr_t *rx_dma,
u32 *plen) u32 *plen)
{ {
struct atmel_spi *as = spi_master_get_devdata(master); *rx_dma = xfer->rx_dma + xfer->len - *plen;
u32 len = *plen; *tx_dma = xfer->tx_dma + xfer->len - *plen;
if (*plen > master->max_dma_len)
/* use scratch buffer only when rx or tx data is unspecified */ *plen = master->max_dma_len;
if (xfer->rx_buf)
*rx_dma = xfer->rx_dma + xfer->len - *plen;
else {
*rx_dma = as->buffer_dma;
if (len > BUFFER_SIZE)
len = BUFFER_SIZE;
}
if (xfer->tx_buf)
*tx_dma = xfer->tx_dma + xfer->len - *plen;
else {
*tx_dma = as->buffer_dma;
if (len > BUFFER_SIZE)
len = BUFFER_SIZE;
memset(as->buffer, 0, len);
dma_sync_single_for_device(&as->pdev->dev,
as->buffer_dma, len, DMA_TO_DEVICE);
}
*plen = len;
} }
static int atmel_spi_set_xfer_speed(struct atmel_spi *as, static int atmel_spi_set_xfer_speed(struct atmel_spi *as,
...@@ -1027,16 +972,12 @@ atmel_spi_pump_single_data(struct atmel_spi *as, struct spi_transfer *xfer) ...@@ -1027,16 +972,12 @@ atmel_spi_pump_single_data(struct atmel_spi *as, struct spi_transfer *xfer)
u16 *rxp16; u16 *rxp16;
unsigned long xfer_pos = xfer->len - as->current_remaining_bytes; unsigned long xfer_pos = xfer->len - as->current_remaining_bytes;
if (xfer->rx_buf) { if (xfer->bits_per_word > 8) {
if (xfer->bits_per_word > 8) { rxp16 = (u16 *)(((u8 *)xfer->rx_buf) + xfer_pos);
rxp16 = (u16 *)(((u8 *)xfer->rx_buf) + xfer_pos); *rxp16 = spi_readl(as, RDR);
*rxp16 = spi_readl(as, RDR);
} else {
rxp = ((u8 *)xfer->rx_buf) + xfer_pos;
*rxp = spi_readl(as, RDR);
}
} else { } else {
spi_readl(as, RDR); rxp = ((u8 *)xfer->rx_buf) + xfer_pos;
*rxp = spi_readl(as, RDR);
} }
if (xfer->bits_per_word > 8) { if (xfer->bits_per_word > 8) {
if (as->current_remaining_bytes > 2) if (as->current_remaining_bytes > 2)
...@@ -1075,12 +1016,10 @@ atmel_spi_pump_fifo_data(struct atmel_spi *as, struct spi_transfer *xfer) ...@@ -1075,12 +1016,10 @@ atmel_spi_pump_fifo_data(struct atmel_spi *as, struct spi_transfer *xfer)
/* Read data */ /* Read data */
while (num_data) { while (num_data) {
rd = spi_readl(as, RDR); rd = spi_readl(as, RDR);
if (xfer->rx_buf) { if (xfer->bits_per_word > 8)
if (xfer->bits_per_word > 8) *words++ = rd;
*words++ = rd; else
else *bytes++ = rd;
*bytes++ = rd;
}
num_data--; num_data--;
} }
} }
...@@ -1301,7 +1240,7 @@ static int atmel_spi_one_transfer(struct spi_master *master, ...@@ -1301,7 +1240,7 @@ static int atmel_spi_one_transfer(struct spi_master *master,
* better fault reporting. * better fault reporting.
*/ */
if ((!msg->is_dma_mapped) if ((!msg->is_dma_mapped)
&& (atmel_spi_use_dma(as, xfer) || as->use_pdc)) { && as->use_pdc) {
if (atmel_spi_dma_map_xfer(as, xfer) < 0) if (atmel_spi_dma_map_xfer(as, xfer) < 0)
return -ENOMEM; return -ENOMEM;
} }
...@@ -1374,11 +1313,11 @@ static int atmel_spi_one_transfer(struct spi_master *master, ...@@ -1374,11 +1313,11 @@ static int atmel_spi_one_transfer(struct spi_master *master,
spi_readl(as, SR); spi_readl(as, SR);
} else if (atmel_spi_use_dma(as, xfer)) { } else if (atmel_spi_use_dma(as, xfer)) {
atmel_spi_stop_dma(as); atmel_spi_stop_dma(master);
} }
if (!msg->is_dma_mapped if (!msg->is_dma_mapped
&& (atmel_spi_use_dma(as, xfer) || as->use_pdc)) && as->use_pdc)
atmel_spi_dma_unmap_xfer(master, xfer); atmel_spi_dma_unmap_xfer(master, xfer);
return 0; return 0;
...@@ -1389,7 +1328,7 @@ static int atmel_spi_one_transfer(struct spi_master *master, ...@@ -1389,7 +1328,7 @@ static int atmel_spi_one_transfer(struct spi_master *master,
} }
if (!msg->is_dma_mapped if (!msg->is_dma_mapped
&& (atmel_spi_use_dma(as, xfer) || as->use_pdc)) && as->use_pdc)
atmel_spi_dma_unmap_xfer(master, xfer); atmel_spi_dma_unmap_xfer(master, xfer);
if (xfer->delay_usecs) if (xfer->delay_usecs)
...@@ -1511,15 +1450,15 @@ static int atmel_spi_gpio_cs(struct platform_device *pdev) ...@@ -1511,15 +1450,15 @@ static int atmel_spi_gpio_cs(struct platform_device *pdev)
int cs_gpio = of_get_named_gpio(pdev->dev.of_node, int cs_gpio = of_get_named_gpio(pdev->dev.of_node,
"cs-gpios", i); "cs-gpios", i);
if (cs_gpio == -EPROBE_DEFER) if (cs_gpio == -EPROBE_DEFER)
return cs_gpio; return cs_gpio;
if (gpio_is_valid(cs_gpio)) { if (gpio_is_valid(cs_gpio)) {
ret = devm_gpio_request(&pdev->dev, cs_gpio, ret = devm_gpio_request(&pdev->dev, cs_gpio,
dev_name(&pdev->dev)); dev_name(&pdev->dev));
if (ret) if (ret)
return ret; return ret;
} }
} }
return 0; return 0;
...@@ -1562,29 +1501,23 @@ static int atmel_spi_probe(struct platform_device *pdev) ...@@ -1562,29 +1501,23 @@ static int atmel_spi_probe(struct platform_device *pdev)
master->bus_num = pdev->id; master->bus_num = pdev->id;
master->num_chipselect = master->dev.of_node ? 0 : 4; master->num_chipselect = master->dev.of_node ? 0 : 4;
master->setup = atmel_spi_setup; master->setup = atmel_spi_setup;
master->flags = (SPI_MASTER_MUST_RX | SPI_MASTER_MUST_TX);
master->transfer_one_message = atmel_spi_transfer_one_message; master->transfer_one_message = atmel_spi_transfer_one_message;
master->cleanup = atmel_spi_cleanup; master->cleanup = atmel_spi_cleanup;
master->auto_runtime_pm = true; master->auto_runtime_pm = true;
master->max_dma_len = SPI_MAX_DMA_XFER;
master->can_dma = atmel_spi_can_dma;
platform_set_drvdata(pdev, master); platform_set_drvdata(pdev, master);
as = spi_master_get_devdata(master); as = spi_master_get_devdata(master);
/*
* Scratch buffer is used for throwaway rx and tx data.
* It's coherent to minimize dcache pollution.
*/
as->buffer = dma_alloc_coherent(&pdev->dev, BUFFER_SIZE,
&as->buffer_dma, GFP_KERNEL);
if (!as->buffer)
goto out_free;
spin_lock_init(&as->lock); spin_lock_init(&as->lock);
as->pdev = pdev; as->pdev = pdev;
as->regs = devm_ioremap_resource(&pdev->dev, regs); as->regs = devm_ioremap_resource(&pdev->dev, regs);
if (IS_ERR(as->regs)) { if (IS_ERR(as->regs)) {
ret = PTR_ERR(as->regs); ret = PTR_ERR(as->regs);
goto out_free_buffer; goto out_unmap_regs;
} }
as->phybase = regs->start; as->phybase = regs->start;
as->irq = irq; as->irq = irq;
...@@ -1609,11 +1542,12 @@ static int atmel_spi_probe(struct platform_device *pdev) ...@@ -1609,11 +1542,12 @@ static int atmel_spi_probe(struct platform_device *pdev)
as->use_dma = false; as->use_dma = false;
as->use_pdc = false; as->use_pdc = false;
if (as->caps.has_dma_support) { if (as->caps.has_dma_support) {
ret = atmel_spi_configure_dma(as); ret = atmel_spi_configure_dma(master, as);
if (ret == 0) if (ret == 0) {
as->use_dma = true; as->use_dma = true;
else if (ret == -EPROBE_DEFER) } else if (ret == -EPROBE_DEFER) {
return ret; return ret;
}
} else { } else {
as->use_pdc = true; as->use_pdc = true;
} }
...@@ -1658,10 +1592,6 @@ static int atmel_spi_probe(struct platform_device *pdev) ...@@ -1658,10 +1592,6 @@ static int atmel_spi_probe(struct platform_device *pdev)
spi_writel(as, CR, SPI_BIT(FIFOEN)); spi_writel(as, CR, SPI_BIT(FIFOEN));
} }
/* go! */
dev_info(&pdev->dev, "Atmel SPI Controller at 0x%08lx (irq %d)\n",
(unsigned long)regs->start, irq);
pm_runtime_set_autosuspend_delay(&pdev->dev, AUTOSUSPEND_TIMEOUT); pm_runtime_set_autosuspend_delay(&pdev->dev, AUTOSUSPEND_TIMEOUT);
pm_runtime_use_autosuspend(&pdev->dev); pm_runtime_use_autosuspend(&pdev->dev);
pm_runtime_set_active(&pdev->dev); pm_runtime_set_active(&pdev->dev);
...@@ -1671,6 +1601,10 @@ static int atmel_spi_probe(struct platform_device *pdev) ...@@ -1671,6 +1601,10 @@ static int atmel_spi_probe(struct platform_device *pdev)
if (ret) if (ret)
goto out_free_dma; goto out_free_dma;
/* go! */
dev_info(&pdev->dev, "Atmel SPI Controller at 0x%08lx (irq %d)\n",
(unsigned long)regs->start, irq);
return 0; return 0;
out_free_dma: out_free_dma:
...@@ -1678,16 +1612,13 @@ static int atmel_spi_probe(struct platform_device *pdev) ...@@ -1678,16 +1612,13 @@ static int atmel_spi_probe(struct platform_device *pdev)
pm_runtime_set_suspended(&pdev->dev); pm_runtime_set_suspended(&pdev->dev);
if (as->use_dma) if (as->use_dma)
atmel_spi_release_dma(as); atmel_spi_release_dma(master);
spi_writel(as, CR, SPI_BIT(SWRST)); spi_writel(as, CR, SPI_BIT(SWRST));
spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */ spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */
clk_disable_unprepare(clk); clk_disable_unprepare(clk);
out_free_irq: out_free_irq:
out_unmap_regs: out_unmap_regs:
out_free_buffer:
dma_free_coherent(&pdev->dev, BUFFER_SIZE, as->buffer,
as->buffer_dma);
out_free: out_free:
spi_master_put(master); spi_master_put(master);
return ret; return ret;
...@@ -1703,8 +1634,8 @@ static int atmel_spi_remove(struct platform_device *pdev) ...@@ -1703,8 +1634,8 @@ static int atmel_spi_remove(struct platform_device *pdev)
/* reset the hardware and block queue progress */ /* reset the hardware and block queue progress */
spin_lock_irq(&as->lock); spin_lock_irq(&as->lock);
if (as->use_dma) { if (as->use_dma) {
atmel_spi_stop_dma(as); atmel_spi_stop_dma(master);
atmel_spi_release_dma(as); atmel_spi_release_dma(master);
} }
spi_writel(as, CR, SPI_BIT(SWRST)); spi_writel(as, CR, SPI_BIT(SWRST));
...@@ -1712,9 +1643,6 @@ static int atmel_spi_remove(struct platform_device *pdev) ...@@ -1712,9 +1643,6 @@ static int atmel_spi_remove(struct platform_device *pdev)
spi_readl(as, SR); spi_readl(as, SR);
spin_unlock_irq(&as->lock); spin_unlock_irq(&as->lock);
dma_free_coherent(&pdev->dev, BUFFER_SIZE, as->buffer,
as->buffer_dma);
clk_disable_unprepare(as->clk); clk_disable_unprepare(as->clk);
pm_runtime_put_noidle(&pdev->dev); pm_runtime_put_noidle(&pdev->dev);
......
...@@ -574,6 +574,7 @@ static const struct of_device_id spi_engine_match_table[] = { ...@@ -574,6 +574,7 @@ static const struct of_device_id spi_engine_match_table[] = {
{ .compatible = "adi,axi-spi-engine-1.00.a" }, { .compatible = "adi,axi-spi-engine-1.00.a" },
{ }, { },
}; };
MODULE_DEVICE_TABLE(of, spi_engine_match_table);
static struct platform_driver spi_engine_driver = { static struct platform_driver spi_engine_driver = {
.probe = spi_engine_probe, .probe = spi_engine_probe,
......
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