Merge tag 'sunxi-dt64-for-5.1' of...

Merge tag 'sunxi-dt64-for-5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into arm/dt

Allwinner DT64 changes for 5.1

A few small improvements for the A64 this cycle:

  - ARM PMU added
  - Allwinner ARM architected timer workaround enabled
    This works around timer value wrapping found in the Allwinner
    implementation of the ARM architected timer.

* tag 'sunxi-dt64-for-5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
  arm64: dts: allwinner: a64: Enable A64 timer workaround
  arm64: dts: allwinner: a64: Fix a typo
  arm64: dts: allwinner: a64: Add PMU node
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

arch/arm64/boot/dts/allwinner/sun50i-a64-teres-i.dts

@@ -239,7 +239,7 @@ &reg_fldo1 {
 };
 
 /*
- * The A64 chip cannot work without this regulator off, although
+ * The A64 chip cannot work with this regulator off, although
  * it seems to be only driving the AR100 core.
  * Maybe we don't still know well about CPUs domain.
  */

arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi

@@ -142,6 +142,15 @@ osc32k: osc32k_clk {
 		clock-output-names = "ext-osc32k";
 	};
 
+	pmu {
+		compatible = "arm,cortex-a53-pmu";
+		interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
+	};
+
 	psci {
 		compatible = "arm,psci-0.2";
 		method = "smc";
@@ -191,6 +200,7 @@ spdif_out: spdif-out {
 
 	timer {
 		compatible = "arm,armv8-timer";
+		allwinner,erratum-unknown1;
 		interrupts = <GIC_PPI 13
 			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 			     <GIC_PPI 14