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Commit 0b1f3ea0 authored by Jeff Garzik's avatar Jeff Garzik
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Hand-merge module_param() conflicts in s2io net driver.

parents 34fe9c27 cec9f92e
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drivers/net/Kconfig
View file @ 0b1f3ea0
......@@ -2191,6 +2191,17 @@ config S2IO_NAPI
If in doubt, say N.
config 2BUFF_MODE
bool "Use 2 Buffer Mode on Rx side."
depends on S2IO
---help---
On enabling the 2 buffer mode, the received frame will be
split into 2 parts before being DMA'ed to the hosts memory.
The parts are the ethernet header and ethernet payload.
This is useful on systems where DMA'ing to to unaligned
physical memory loactions comes with a heavy price.
If not sure please say N.
endmenu
source "drivers/net/tokenring/Kconfig"
......
drivers/net/s2io-regs.h
View file @ 0b1f3ea0
......@@ -289,6 +289,8 @@ typedef struct _XENA_dev_config {
u64 tda_err_alarm;
u64 pcc_err_reg;
#define PCC_FB_ECC_DB_ERR vBIT(0xFF, 16, 8)
u64 pcc_err_mask;
u64 pcc_err_alarm;
......@@ -512,6 +514,7 @@ typedef struct _XENA_dev_config {
#define RX_PA_CFG_IGNORE_FRM_ERR BIT(1)
#define RX_PA_CFG_IGNORE_SNAP_OUI BIT(2)
#define RX_PA_CFG_IGNORE_LLC_CTRL BIT(3)
#define RX_PA_CFG_IGNORE_L2_ERR BIT(6)
u8 unused12[0x700 - 0x1D8];
......
drivers/net/s2io.c
View file @ 0b1f3ea0
This source diff could not be displayed because it is too large. You can view the blob instead.
drivers/net/s2io.h
View file @ 0b1f3ea0
......@@ -16,6 +16,7 @@
#define TBD 0
#define BIT(loc) (0x8000000000000000ULL >> (loc))
#define vBIT(val, loc, sz) (((u64)val) << (64-loc-sz))
#define INV(d) ((d&0xff)<<24) | (((d>>8)&0xff)<<16) | (((d>>16)&0xff)<<8)| ((d>>24)&0xff)
#ifndef BOOL
#define BOOL int
......@@ -52,8 +53,6 @@ typedef enum xena_max_outstanding_splits {
/*
* Debug related variables.
*/
#define DEBUG_ON TRUE
/* different debug levels. */
#define ERR_DBG 0
#define INIT_DBG 1
......@@ -312,7 +311,7 @@ typedef struct stat_block {
/* Maintains Per FIFO related information. */
typedef struct tx_fifo_config {
#define MAX_AVAILABLE_TXDS 8192
u32 FifoLen; /* specifies len of FIFO upto 8192, ie no of TxDLs */
u32 fifo_len; /* specifies len of FIFO upto 8192, ie no of TxDLs */
/* Priority definition */
#define TX_FIFO_PRI_0 0 /*Highest */
#define TX_FIFO_PRI_1 1
......@@ -322,9 +321,9 @@ typedef struct tx_fifo_config {
#define TX_FIFO_PRI_5 5
#define TX_FIFO_PRI_6 6
#define TX_FIFO_PRI_7 7 /*lowest */
u8 FifoPriority; /* specifies pointer level for FIFO */
u8 fifo_priority; /* specifies pointer level for FIFO */
/* user should not set twos fifos with same pri */
u8 fNoSnoop;
u8 f_no_snoop;
#define NO_SNOOP_TXD 0x01
#define NO_SNOOP_TXD_BUFFER 0x02
} tx_fifo_config_t;
......@@ -332,7 +331,7 @@ typedef struct tx_fifo_config {
/* Maintains per Ring related information */
typedef struct rx_ring_config {
u32 NumRxd; /*No of RxDs per Rx Ring */
u32 num_rxd; /*No of RxDs per Rx Ring */
#define RX_RING_PRI_0 0 /* highest */
#define RX_RING_PRI_1 1
#define RX_RING_PRI_2 2
......@@ -342,70 +341,37 @@ typedef struct rx_ring_config {
#define RX_RING_PRI_6 6
#define RX_RING_PRI_7 7 /* lowest */
u8 RingPriority; /*Specifies service priority of ring */
u8 ring_priority; /*Specifies service priority of ring */
/* OSM should not set any two rings with same priority */
u8 RingOrg; /*Organization of ring */
u8 ring_org; /*Organization of ring */
#define RING_ORG_BUFF1 0x01
#define RX_RING_ORG_BUFF3 0x03
#define RX_RING_ORG_BUFF5 0x05
/* In case of 3 buffer recv. mode, size of three buffers is expected as.. */
#define BUFF_SZ_1 22 /* ethernet header */
#define BUFF_SZ_2 (64+64) /* max. IP+TCP header size */
#define BUFF_SZ_3 (1500-20-20) /* TCP payload */
#define BUFF_SZ_3_JUMBO (9600-20-20) /* Jumbo TCP payload */
u32 RxdThresh; /*No of used Rxds NIC can store before transfer to host */
#define DEFAULT_RXD_THRESHOLD 0x1 /* TODO */
u8 fNoSnoop;
u8 f_no_snoop;
#define NO_SNOOP_RXD 0x01
#define NO_SNOOP_RXD_BUFFER 0x02
u32 RxD_BackOff_Interval;
#define RXD_BACKOFF_INTERVAL_DEF 0x0
#define RXD_BACKOFF_INTERVAL_MIN 0x0
#define RXD_BACKOFF_INTERVAL_MAX 0x0
} rx_ring_config_t;
/* This structure provides contains values of the tunable parameters
* of the H/W
*/
struct config_param {
/* Tx Side */
u32 TxFIFONum; /*Number of Tx FIFOs */
u32 tx_fifo_num; /*Number of Tx FIFOs */
#define MAX_TX_FIFOS 8
tx_fifo_config_t TxCfg[MAX_TX_FIFOS]; /*Per-Tx FIFO config */
u32 MaxTxDs; /*Max no. of Tx buffer descriptor per TxDL */
BOOL TxVLANEnable; /*TRUE: Insert VLAN ID, FALSE: Don't insert */
#define TX_REQ_TIMEOUT_DEFAULT 0x0
#define TX_REQ_TIMEOUT_MIN 0x0
#define TX_REQ_TIMEOUT_MAX 0x0
u32 TxReqTimeOut;
BOOL TxFlow; /*Tx flow control enable */
BOOL RxFlow;
BOOL OverrideTxServiceState; /* TRUE: Overide, FALSE: Do not override
Use the new priority information
of service state. It is not recommended
to change but OSM can opt to do so */
#define MAX_SERVICE_STATES 36
u8 TxServiceState[MAX_SERVICE_STATES];
/* Array element represent 'priority'
* and array index represents
* 'Service state' e.g.
* TxServiceState[3]=7; it means
* Service state 3 is associated
* with priority 7 of a Tx FIFO */
u64 TxIntrType; /* Specifies if Tx Intr is UTILZ or PER_LIST type. */
tx_fifo_config_t tx_cfg[MAX_TX_FIFOS]; /*Per-Tx FIFO config */
u32 max_txds; /*Max no. of Tx buffer descriptor per TxDL */
u64 tx_intr_type;
/* Specifies if Tx Intr is UTILZ or PER_LIST type. */
/* Rx Side */
u32 RxRingNum; /*Number of receive rings */
u32 rx_ring_num; /*Number of receive rings */
#define MAX_RX_RINGS 8
#define MAX_RX_BLOCKS_PER_RING 150
rx_ring_config_t RxCfg[MAX_RX_RINGS]; /*Per-Rx Ring config */
BOOL RxVLANEnable; /*TRUE: Strip off VLAN tag from the frame,
FALSE: Don't strip off VLAN tag */
rx_ring_config_t rx_cfg[MAX_RX_RINGS]; /*Per-Rx Ring config */
#define HEADER_ETHERNET_II_802_3_SIZE 14
#define HEADER_802_2_SIZE 3
......@@ -419,23 +385,6 @@ struct config_param {
#define MAX_PYLD_JUMBO 9600
#define MAX_MTU_JUMBO (MAX_PYLD_JUMBO+18)
#define MAX_MTU_JUMBO_VLAN (MAX_PYLD_JUMBO+22)
u32 MTU; /*Maximum Payload */
BOOL JumboEnable; /*Enable Jumbo frames recv/send */
BOOL OverrideRxServiceState; /* TRUE: Overide, FALSE: Do not override
Use the new priority information
of service state. It is not recommended
to change but OSM can opt to do so */
#define MAX_SERVICE_STATES 36
u8 RxServiceState[MAX_SERVICE_STATES];
/* Array element represent 'priority'
* and array index represents
* 'Service state'e.g.
* RxServiceState[3]=7; it means
* Service state 3 is associated
* with priority 7 of a Rx FIFO */
BOOL StatAutoRefresh; /* When true, StatRefreshTime have valid value */
u32 StatRefreshTime; /*Time for refreshing statistics */
#define STAT_TRSF_PER_1_SECOND 0x208D5
};
/* Structure representing MAC Addrs */
......@@ -491,6 +440,12 @@ typedef struct _TxD {
u64 Host_Control; /* reserved for host */
} TxD_t;
/* Structure to hold the phy and virt addr of every TxDL. */
typedef struct list_info_hold {
dma_addr_t list_phy_addr;
void *list_virt_addr;
} list_info_hold_t;
/* Rx descriptor structure */
typedef struct _RxD_t {
u64 Host_Control; /* reserved for host */
......@@ -507,36 +462,80 @@ typedef struct _RxD_t {
#define RXD_GET_L4_CKSUM(val) ((u16)(val) & 0xFFFF)
u64 Control_2;
#ifndef CONFIG_2BUFF_MODE
#define MASK_BUFFER0_SIZE vBIT(0xFFFF,0,16)
#define SET_BUFFER0_SIZE(val) vBIT(val,0,16)
#else
#define MASK_BUFFER0_SIZE vBIT(0xFF,0,16)
#define MASK_BUFFER1_SIZE vBIT(0xFFFF,16,16)
#define MASK_BUFFER2_SIZE vBIT(0xFFFF,32,16)
#define SET_BUFFER0_SIZE(val) vBIT(val,8,8)
#define SET_BUFFER1_SIZE(val) vBIT(val,16,16)
#define SET_BUFFER2_SIZE(val) vBIT(val,32,16)
#endif
#define MASK_VLAN_TAG vBIT(0xFFFF,48,16)
#define SET_VLAN_TAG(val) vBIT(val,48,16)
#define SET_NUM_TAG(val) vBIT(val,16,32)
#ifndef CONFIG_2BUFF_MODE
#define RXD_GET_BUFFER0_SIZE(Control_2) (u64)((Control_2 & vBIT(0xFFFF,0,16)))
/*
#define TXD_GET_BUFFER1_SIZE(Control_2) (u16)((Control_2 & MASK_BUFFER1_SIZE) >> (63-31))
#define TXD_GET_BUFFER2_SIZE(Control_2) (u16)((Control_2 & MASK_BUFFER2_SIZE) >> (63-47))
*/
#else
#define RXD_GET_BUFFER0_SIZE(Control_2) (u8)((Control_2 & MASK_BUFFER0_SIZE) \
>> 48)
#define RXD_GET_BUFFER1_SIZE(Control_2) (u16)((Control_2 & MASK_BUFFER1_SIZE) \
>> 32)
#define RXD_GET_BUFFER2_SIZE(Control_2) (u16)((Control_2 & MASK_BUFFER2_SIZE) \
>> 16)
#define BUF0_LEN 40
#define BUF1_LEN 1
#endif
u64 Buffer0_ptr;
#ifdef CONFIG_2BUFF_MODE
u64 Buffer1_ptr;
u64 Buffer2_ptr;
#endif
} RxD_t;
/* Structure that represents the Rx descriptor block which contains
* 128 Rx descriptors.
*/
#ifndef CONFIG_2BUFF_MODE
typedef struct _RxD_block {
#define MAX_RXDS_PER_BLOCK 127
RxD_t rxd[MAX_RXDS_PER_BLOCK];
u64 reserved_0;
#define END_OF_BLOCK 0xFEFFFFFFFFFFFFFFULL
u64 reserved_1; /* 0xFEFFFFFFFFFFFFFF to mark last Rxd in this blk */
u64 reserved_2_pNext_RxD_block; /*@ Logical ptr to next */
u64 pNext_RxD_Blk_physical; /* Buff0_ptr.
In a 32 bit arch the upper 32 bits
should be 0 */
u64 reserved_1; /* 0xFEFFFFFFFFFFFFFF to mark last
* Rxd in this blk */
u64 reserved_2_pNext_RxD_block; /* Logical ptr to next */
u64 pNext_RxD_Blk_physical; /* Buff0_ptr.In a 32 bit arch
* the upper 32 bits should
* be 0 */
} RxD_block_t;
#else
typedef struct _RxD_block {
#define MAX_RXDS_PER_BLOCK 85
RxD_t rxd[MAX_RXDS_PER_BLOCK];
#define END_OF_BLOCK 0xFEFFFFFFFFFFFFFFULL
u64 reserved_1; /* 0xFEFFFFFFFFFFFFFF to mark last Rxd
* in this blk */
u64 pNext_RxD_Blk_physical; /* Phy ponter to next blk. */
} RxD_block_t;
#define SIZE_OF_BLOCK 4096
/* Structure to hold virtual addresses of Buf0 and Buf1 in
* 2buf mode. */
typedef struct bufAdd {
void *ba_0_org;
void *ba_1_org;
void *ba_0;
void *ba_1;
} buffAdd_t;
#endif
/* Structure which stores all the MAC control parameters */
......@@ -568,10 +567,6 @@ typedef tx_curr_get_info_t tx_curr_put_info_t;
*/
typedef struct mac_info {
/* rx side stuff */
u32 rxd_ring_mem_sz;
RxD_t *RxRing[MAX_RX_RINGS]; /* Logical Rx ring pointers */
dma_addr_t RxRing_Phy[MAX_RX_RINGS];
/* Put pointer info which indictes which RxD has to be replenished
* with a new buffer.
*/
......@@ -583,41 +578,21 @@ typedef struct mac_info {
rx_curr_get_info_t rx_curr_get_info[MAX_RX_RINGS];
u16 rmac_pause_time;
/* this will be used in receive function, this decides which ring would
be processed first. eg: ring with priority value 0 (highest) should
be processed first.
first 3 LSB bits represent ring number which should be processed
first, similarly next 3 bits represent next ring to be processed.
eg: value of _rx_ring_pri_map = 0x0000 003A means
ring #2 would be processed first and #7 would be processed next
*/
u32 _rx_ring_pri_map;
u16 mc_pause_threshold_q0q3;
u16 mc_pause_threshold_q4q7;
/* tx side stuff */
void *txd_list_mem; /* orignal pointer to allocated mem */
dma_addr_t txd_list_mem_phy;
u32 txd_list_mem_sz;
/* logical pointer of start of each Tx FIFO */
TxFIFO_element_t *tx_FIFO_start[MAX_TX_FIFOS];
/* logical pointer of start of TxDL which corresponds to each Tx FIFO */
TxD_t *txdl_start[MAX_TX_FIFOS];
/* Same as txdl_start but phy addr */
dma_addr_t txdl_start_phy[MAX_TX_FIFOS];
/* Current offset within tx_FIFO_start, where driver would write new Tx frame*/
tx_curr_put_info_t tx_curr_put_info[MAX_TX_FIFOS];
tx_curr_get_info_t tx_curr_get_info[MAX_TX_FIFOS];
u16 txdl_len; /* length of a TxDL, same for all */
void *stats_mem; /* orignal pointer to allocated mem */
dma_addr_t stats_mem_phy; /* Physical address of the stat block */
u32 stats_mem_sz;
StatInfo_t *StatsInfo; /* Logical address of the stat block */
StatInfo_t *stats_info; /* Logical address of the stat block */
} mac_info_t;
/* structure representing the user defined MAC addresses */
......@@ -632,13 +607,20 @@ typedef struct rx_block_info {
dma_addr_t block_dma_addr;
} rx_block_info_t;
/* Default Tunable parameters of the NIC. */
#define DEFAULT_FIFO_LEN 4096
#define SMALL_RXD_CNT 30 * (MAX_RXDS_PER_BLOCK+1)
#define LARGE_RXD_CNT 100 * (MAX_RXDS_PER_BLOCK+1)
#define SMALL_BLK_CNT 30
#define LARGE_BLK_CNT 100
/* Structure representing one instance of the NIC */
typedef struct s2io_nic {
#define MAX_MAC_SUPPORTED 16
#define MAX_SUPPORTED_MULTICASTS MAX_MAC_SUPPORTED
macaddr_t defMacAddr[MAX_MAC_SUPPORTED];
macaddr_t preMacAddr[MAX_MAC_SUPPORTED];
macaddr_t def_mac_addr[MAX_MAC_SUPPORTED];
macaddr_t pre_mac_addr[MAX_MAC_SUPPORTED];
struct net_device_stats stats;
caddr_t bar0;
......@@ -651,7 +633,7 @@ typedef struct s2io_nic {
char name[32];
struct tasklet_struct task;
atomic_t tasklet_status;
volatile unsigned long tasklet_status;
struct timer_list timer;
struct net_device *dev;
struct pci_dev *pdev;
......@@ -670,8 +652,10 @@ typedef struct s2io_nic {
u32 irq;
atomic_t rx_bufs_left[MAX_RX_RINGS];
spinlock_t isr_lock;
spinlock_t tx_lock;
#ifndef CONFIG_S2IO_NAPI
spinlock_t put_lock;
#endif
#define PROMISC 1
#define ALL_MULTI 2
......@@ -690,23 +674,22 @@ typedef struct s2io_nic {
u16 tx_err_count;
u16 rx_err_count;
#if DEBUG_ON
u64 rxpkt_bytes;
u64 txpkt_bytes;
int int_cnt;
int rxint_cnt;
int txint_cnt;
u64 rxpkt_cnt;
#ifndef CONFIG_S2IO_NAPI
/* Index to the absolute position of the put pointer of Rx ring. */
int put_pos[MAX_RX_RINGS];
#endif
/* Place holders for the virtual and physical addresses of
/*
* Place holders for the virtual and physical addresses of
* all the Rx Blocks
*/
struct rx_block_info
rx_blocks[MAX_RX_RINGS][MAX_RX_BLOCKS_PER_RING];
rx_block_info_t rx_blocks[MAX_RX_RINGS][MAX_RX_BLOCKS_PER_RING];
int block_count[MAX_RX_RINGS];
int pkt_cnt[MAX_RX_RINGS];
/* Place holder of all the TX List's Phy and Virt addresses. */
list_info_hold_t *list_info[MAX_TX_FIFOS];
/* Id timer, used to blink NIC to physically identify NIC. */
struct timer_list id_timer;
......@@ -736,24 +719,29 @@ typedef struct s2io_nic {
u16 last_link_state;
#define LINK_DOWN 1
#define LINK_UP 2
#ifdef CONFIG_2BUFF_MODE
/* Buffer Address store. */
buffAdd_t **ba[MAX_RX_RINGS];
#endif
int task_flag;
#define CARD_DOWN 1
#define CARD_UP 2
atomic_t card_state;
volatile unsigned long link_state;
} nic_t;
#define RESET_ERROR 1;
#define CMD_ERROR 2;
/* Default Tunable parameters of the NIC. */
#define DEFAULT_FIFO_LEN 4096
#define SMALL_RXD_CNT 40 * (MAX_RXDS_PER_BLOCK+1)
#define LARGE_RXD_CNT 100 * (MAX_RXDS_PER_BLOCK+1)
/* OS related system calls */
#ifndef readq
static inline u64 readq(void *addr)
{
u64 ret = 0;
ret = readl(addr + 4);
ret <<= 32;
ret |= readl(addr);
(u64) ret <<= 32;
(u64) ret |= readl(addr);
return ret;
}
......@@ -765,6 +753,27 @@ static inline void writeq(u64 val, void *addr)
writel((u32) (val), addr);
writel((u32) (val >> 32), (addr + 4));
}
/* In 32 bit modes, some registers have to be written in a
* particular order to expect correct hardware operation. The
* macro SPECIAL_REG_WRITE is used to perform such ordered
* writes. Defines UF (Upper First) and LF (Lower First) will
* be used to specify the required write order.
*/
#define UF 1
#define LF 2
static inline void SPECIAL_REG_WRITE(u64 val, void *addr, int order)
{
if (order == LF) {
writel((u32) (val), addr);
writel((u32) (val >> 32), (addr + 4));
} else {
writel((u32) (val >> 32), (addr + 4));
writel((u32) (val), addr);
}
}
#else
#define SPECIAL_REG_WRITE(val, addr, dummy) writeq(val, addr)
#endif
/* Interrupt related values of Xena */
......@@ -815,30 +824,41 @@ static inline void writeq(u64 val, void *addr)
/* DMA level Inressupts */
#define TXDMA_PFC_INT_M BIT(0)
/* PFC block interrupts */
#define TXDMA_PCC_INT_M BIT(2)
/* PFC block interrupts */
#define PFC_MISC_ERR_1 BIT(0) /* Interrupt to indicate FIFO full */
/* PCC block interrupts. */
#define PCC_FB_ECC_ERR vBIT(0xff, 16, 8) /* Interrupt to indicate
PCC_FB_ECC Error. */
/*
* Prototype declaration.
*/
static int __devinit s2io_init_nic(struct pci_dev *pdev,
const struct pci_device_id *pre);
static void __devexit s2io_rem_nic(struct pci_dev *pdev);
static int initSharedMem(struct s2io_nic *sp);
static void freeSharedMem(struct s2io_nic *sp);
static int initNic(struct s2io_nic *nic);
static int init_shared_mem(struct s2io_nic *sp);
static void free_shared_mem(struct s2io_nic *sp);
static int init_nic(struct s2io_nic *nic);
#ifndef CONFIG_S2IO_NAPI
static void rxIntrHandler(struct s2io_nic *sp);
static void rx_intr_handler(struct s2io_nic *sp);
#endif
static void txIntrHandler(struct s2io_nic *sp);
static void alarmIntrHandler(struct s2io_nic *sp);
static void tx_intr_handler(struct s2io_nic *sp);
static void alarm_intr_handler(struct s2io_nic *sp);
static int s2io_starter(void);
void s2io_closer(void);
static void s2io_tx_watchdog(struct net_device *dev);
static void s2io_tasklet(unsigned long dev_addr);
static void s2io_set_multicast(struct net_device *dev);
static int rxOsmHandler(nic_t * sp, u16 len, RxD_t * rxdp, int ring_no);
#ifndef CONFIG_2BUFF_MODE
static int rx_osm_handler(nic_t * sp, u16 len, RxD_t * rxdp, int ring_no);
#else
static int rx_osm_handler(nic_t * sp, RxD_t * rxdp, int ring_no,
buffAdd_t * ba);
#endif
void s2io_link(nic_t * sp, int link);
void s2io_reset(nic_t * sp);
#ifdef CONFIG_S2IO_NAPI
......@@ -849,5 +869,8 @@ int s2io_set_mac_addr(struct net_device *dev, u8 * addr);
static irqreturn_t s2io_isr(int irq, void *dev_id, struct pt_regs *regs);
static int verify_xena_quiescence(u64 val64, int flag);
static struct ethtool_ops netdev_ethtool_ops;
static void s2io_set_link(unsigned long data);
static void s2io_card_down(nic_t * nic);
static int s2io_card_up(nic_t * nic);
#endif /* _S2IO_H */
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