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Commit 0b788f20 authored by James Bottomley's avatar James Bottomley
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[SCSI] Remove 53c7,8xx since we have plenty of alternatives. 

We have 53c700.c and 53c7xx for the 7xx series and
ncr53c8xx for the 720.  The sym53c8xx_2 covers all the 8xx chips.
parent 53e20c84
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/*
* NCR 53c{7,8}0x0 driver, header file
*
* Sponsored by
* iX Multiuser Multitasking Magazine
* Hannover, Germany
* hm@ix.de
*
* Copyright 1993, 1994, 1995 Drew Eckhardt
* Visionary Computing
* (Unix and Linux consulting and custom programming)
* drew@PoohSticks.ORG
* +1 (303) 786-7975
*
* TolerANT and SCSI SCRIPTS are registered trademarks of NCR Corporation.
*
* PRE-ALPHA
*
* For more information, please consult
*
* NCR 53C700/53C700-66
* SCSI I/O Processor
* Data Manual
*
* NCR 53C810
* PCI-SCSI I/O Processor
* Data Manual
*
* NCR Microelectronics
* 1635 Aeroplaza Drive
* Colorado Springs, CO 80916
* +1 (719) 578-3400
*
* Toll free literature number
* +1 (800) 334-5454
*
*/
#ifndef NCR53c7x0_H
#define NCR53c7x0_H
#include <linux/version.h>
/*
* Prevent name space pollution in hosts.c, and only provide the
* define we need to get the NCR53c7x0 driver into the host template
* array.
*/
#include <scsi/scsicam.h>
extern int NCR53c7xx_abort(Scsi_Cmnd *);
extern int NCR53c7xx_detect(Scsi_Host_Template *tpnt);
extern int NCR53c7xx_queue_command(Scsi_Cmnd *, void (*done)(Scsi_Cmnd *));
extern int NCR53c7xx_reset(Scsi_Cmnd *, unsigned int);
#ifdef MODULE
extern int NCR53c7xx_release(struct Scsi_Host *);
#else
#define NCR53c7xx_release NULL
#endif
#define NCR53c7xx { \
.name = "NCR53c{7,8}xx (rel 17)", \
.detect = NCR53c7xx_detect, \
.queuecommand = NCR53c7xx_queue_command, \
.abort = NCR53c7xx_abort, \
.reset = NCR53c7xx_reset, \
.can_queue = 24, \
.this_id = 7, \
.sg_tablesize = 127, \
.cmd_per_lun = 3, \
.use_clustering = DISABLE_CLUSTERING}
#ifndef HOSTS_C
/* Register addresses, ordered numerically */
/* SCSI control 0 rw, default = 0xc0 */
#define SCNTL0_REG 0x00
#define SCNTL0_ARB1 0x80 /* 0 0 = simple arbitration */
#define SCNTL0_ARB2 0x40 /* 1 1 = full arbitration */
#define SCNTL0_STRT 0x20 /* Start Sequence */
#define SCNTL0_WATN 0x10 /* Select with ATN */
#define SCNTL0_EPC 0x08 /* Enable parity checking */
/* Bit 2 is reserved on 800 series chips */
#define SCNTL0_EPG_700 0x04 /* Enable parity generation */
#define SCNTL0_AAP 0x02 /* ATN/ on parity error */
#define SCNTL0_TRG 0x01 /* Target mode */
/* SCSI control 1 rw, default = 0x00 */
#define SCNTL1_REG 0x01
#define SCNTL1_EXC 0x80 /* Extra Clock Cycle of Data setup */
#define SCNTL1_ADB 0x40 /* contents of SODL on bus */
#define SCNTL1_ESR_700 0x20 /* Enable SIOP response to selection
and reselection */
#define SCNTL1_DHP_800 0x20 /* Disable halt on parity error or ATN
target mode only */
#define SCNTL1_CON 0x10 /* Connected */
#define SCNTL1_RST 0x08 /* SCSI RST/ */
#define SCNTL1_AESP 0x04 /* Force bad parity */
#define SCNTL1_SND_700 0x02 /* Start SCSI send */
#define SCNTL1_IARB_800 0x02 /* Immediate Arbitration, start
arbitration immediately after
busfree is detected */
#define SCNTL1_RCV_700 0x01 /* Start SCSI receive */
#define SCNTL1_SST_800 0x01 /* Start SCSI transfer */
/* SCSI control 2 rw, */
#define SCNTL2_REG_800 0x02
#define SCNTL2_800_SDU 0x80 /* SCSI disconnect unexpected */
/* SCSI control 3 rw */
#define SCNTL3_REG_800 0x03
#define SCNTL3_800_SCF_SHIFT 4
#define SCNTL3_800_SCF_MASK 0x70
#define SCNTL3_800_SCF2 0x40 /* Synchronous divisor */
#define SCNTL3_800_SCF1 0x20 /* 0x00 = SCLK/3 */
#define SCNTL3_800_SCF0 0x10 /* 0x10 = SCLK/1 */
/* 0x20 = SCLK/1.5
0x30 = SCLK/2
0x40 = SCLK/3 */
#define SCNTL3_800_CCF_SHIFT 0
#define SCNTL3_800_CCF_MASK 0x07
#define SCNTL3_800_CCF2 0x04 /* 0x00 50.01 to 66 */
#define SCNTL3_800_CCF1 0x02 /* 0x01 16.67 to 25 */
#define SCNTL3_800_CCF0 0x01 /* 0x02 25.01 - 37.5
0x03 37.51 - 50
0x04 50.01 - 66 */
/*
* SCSI destination ID rw - the appropriate bit is set for the selected
* target ID. This is written by the SCSI SCRIPTS processor.
* default = 0x00
*/
#define SDID_REG_700 0x02
#define SDID_REG_800 0x06
#define GP_REG_800 0x07 /* General purpose IO */
#define GP_800_IO1 0x02
#define GP_800_IO2 0x01
/* SCSI interrupt enable rw, default = 0x00 */
#define SIEN_REG_700 0x03
#define SIEN0_REG_800 0x40
#define SIEN_MA 0x80 /* Phase mismatch (ini) or ATN (tgt) */
#define SIEN_FC 0x40 /* Function complete */
#define SIEN_700_STO 0x20 /* Selection or reselection timeout */
#define SIEN_800_SEL 0x20 /* Selected */
#define SIEN_700_SEL 0x10 /* Selected or reselected */
#define SIEN_800_RESEL 0x10 /* Reselected */
#define SIEN_SGE 0x08 /* SCSI gross error */
#define SIEN_UDC 0x04 /* Unexpected disconnect */
#define SIEN_RST 0x02 /* SCSI RST/ received */
#define SIEN_PAR 0x01 /* Parity error */
/*
* SCSI chip ID rw
* NCR53c700 :
* When arbitrating, the highest bit is used, when reselection or selection
* occurs, the chip responds to all IDs for which a bit is set.
* default = 0x00
* NCR53c810 :
* Uses bit mapping
*/
#define SCID_REG 0x04
/* Bit 7 is reserved on 800 series chips */
#define SCID_800_RRE 0x40 /* Enable response to reselection */
#define SCID_800_SRE 0x20 /* Enable response to selection */
/* Bits four and three are reserved on 800 series chips */
#define SCID_800_ENC_MASK 0x07 /* Encoded SCSI ID */
/* SCSI transfer rw, default = 0x00 */
#define SXFER_REG 0x05
#define SXFER_DHP 0x80 /* Disable halt on parity */
#define SXFER_TP2 0x40 /* Transfer period msb */
#define SXFER_TP1 0x20
#define SXFER_TP0 0x10 /* lsb */
#define SXFER_TP_MASK 0x70
/* FIXME : SXFER_TP_SHIFT == 5 is right for '8xx chips */
#define SXFER_TP_SHIFT 5
#define SXFER_TP_4 0x00 /* Divisors */
#define SXFER_TP_5 0x10<<1
#define SXFER_TP_6 0x20<<1
#define SXFER_TP_7 0x30<<1
#define SXFER_TP_8 0x40<<1
#define SXFER_TP_9 0x50<<1
#define SXFER_TP_10 0x60<<1
#define SXFER_TP_11 0x70<<1
#define SXFER_MO3 0x08 /* Max offset msb */
#define SXFER_MO2 0x04
#define SXFER_MO1 0x02
#define SXFER_MO0 0x01 /* lsb */
#define SXFER_MO_MASK 0x0f
#define SXFER_MO_SHIFT 0
/*
* SCSI output data latch rw
* The contents of this register are driven onto the SCSI bus when
* the Assert Data Bus bit of the SCNTL1 register is set and
* the CD, IO, and MSG bits of the SOCL register match the SCSI phase
*/
#define SODL_REG_700 0x06
#define SODL_REG_800 0x54
/*
* SCSI output control latch rw, default = 0
* Note that when the chip is being manually programmed as an initiator,
* the MSG, CD, and IO bits must be set correctly for the phase the target
* is driving the bus in. Otherwise no data transfer will occur due to
* phase mismatch.
*/
#define SBCL_REG 0x0b
#define SBCL_REQ 0x80 /* REQ */
#define SBCL_ACK 0x40 /* ACK */
#define SBCL_BSY 0x20 /* BSY */
#define SBCL_SEL 0x10 /* SEL */
#define SBCL_ATN 0x08 /* ATN */
#define SBCL_MSG 0x04 /* MSG */
#define SBCL_CD 0x02 /* C/D */
#define SBCL_IO 0x01 /* I/O */
#define SBCL_PHASE_CMDOUT SBCL_CD
#define SBCL_PHASE_DATAIN SBCL_IO
#define SBCL_PHASE_DATAOUT 0
#define SBCL_PHASE_MSGIN (SBCL_CD|SBCL_IO|SBCL_MSG)
#define SBCL_PHASE_MSGOUT (SBCL_CD|SBCL_MSG)
#define SBCL_PHASE_STATIN (SBCL_CD|SBCL_IO)
#define SBCL_PHASE_MASK (SBCL_CD|SBCL_IO|SBCL_MSG)
/*
* SCSI first byte received latch ro
* This register contains the first byte received during a block MOVE
* SCSI SCRIPTS instruction, including
*
* Initiator mode Target mode
* Message in Command
* Status Message out
* Data in Data out
*
* It also contains the selecting or reselecting device's ID and our
* ID.
*
* Note that this is the register the various IF conditionals can
* operate on.
*/
#define SFBR_REG 0x08
/*
* SCSI input data latch ro
* In initiator mode, data is latched into this register on the rising
* edge of REQ/. In target mode, data is latched on the rising edge of
* ACK/
*/
#define SIDL_REG_700 0x09
#define SIDL_REG_800 0x50
/*
* SCSI bus data lines ro
* This register reflects the instantaneous status of the SCSI data
* lines. Note that SCNTL0 must be set to disable parity checking,
* otherwise reading this register will latch new parity.
*/
#define SBDL_REG_700 0x0a
#define SBDL_REG_800 0x58
#define SSID_REG_800 0x0a
#define SSID_800_VAL 0x80 /* Exactly two bits asserted at sel */
#define SSID_800_ENCID_MASK 0x07 /* Device which performed operation */
/*
* SCSI bus control lines rw,
* instantaneous readout of control lines
*/
#define SOCL_REG 0x0b
#define SOCL_REQ 0x80 /* REQ ro */
#define SOCL_ACK 0x40 /* ACK ro */
#define SOCL_BSY 0x20 /* BSY ro */
#define SOCL_SEL 0x10 /* SEL ro */
#define SOCL_ATN 0x08 /* ATN ro */
#define SOCL_MSG 0x04 /* MSG ro */
#define SOCL_CD 0x02 /* C/D ro */
#define SOCL_IO 0x01 /* I/O ro */
/*
* Synchronous SCSI Clock Control bits
* 0 - set by DCNTL
* 1 - SCLK / 1.0
* 2 - SCLK / 1.5
* 3 - SCLK / 2.0
*/
#define SBCL_SSCF1 0x02 /* wo, -66 only */
#define SBCL_SSCF0 0x01 /* wo, -66 only */
#define SBCL_SSCF_MASK 0x03
/*
* XXX note : when reading the DSTAT and STAT registers to clear interrupts,
* insure that 10 clocks elapse between the two
*/
/* DMA status ro */
#define DSTAT_REG 0x0c
#define DSTAT_DFE 0x80 /* DMA FIFO empty */
#define DSTAT_800_MDPE 0x40 /* Master Data Parity Error */
#define DSTAT_800_BF 0x20 /* Bus Fault */
#define DSTAT_ABRT 0x10 /* Aborted - set on error */
#define DSTAT_SSI 0x08 /* SCRIPTS single step interrupt */
#define DSTAT_SIR 0x04 /* SCRIPTS interrupt received -
set when INT instruction is
executed */
#define DSTAT_WTD 0x02 /* Watchdog timeout detected */
#define DSTAT_OPC 0x01 /* Illegal instruction */
#define DSTAT_800_IID 0x01 /* Same thing, different name */
/* NCR53c800 moves this stuff into SIST0 */
#define SSTAT0_REG 0x0d /* SCSI status 0 ro */
#define SIST0_REG_800 0x42
#define SSTAT0_MA 0x80 /* ini : phase mismatch,
* tgt : ATN/ asserted
*/
#define SSTAT0_CMP 0x40 /* function complete */
#define SSTAT0_700_STO 0x20 /* Selection or reselection timeout */
#define SIST0_800_SEL 0x20 /* Selected */
#define SSTAT0_700_SEL 0x10 /* Selected or reselected */
#define SIST0_800_RSL 0x10 /* Reselected */
#define SSTAT0_SGE 0x08 /* SCSI gross error */
#define SSTAT0_UDC 0x04 /* Unexpected disconnect */
#define SSTAT0_RST 0x02 /* SCSI RST/ received */
#define SSTAT0_PAR 0x01 /* Parity error */
/* And uses SSTAT0 for what was SSTAT1 */
#define SSTAT1_REG 0x0e /* SCSI status 1 ro */
#define SSTAT1_ILF 0x80 /* SIDL full */
#define SSTAT1_ORF 0x40 /* SODR full */
#define SSTAT1_OLF 0x20 /* SODL full */
#define SSTAT1_AIP 0x10 /* Arbitration in progress */
#define SSTAT1_LOA 0x08 /* Lost arbitration */
#define SSTAT1_WOA 0x04 /* Won arbitration */
#define SSTAT1_RST 0x02 /* Instant readout of RST/ */
#define SSTAT1_SDP 0x01 /* Instant readout of SDP/ */
#define SSTAT2_REG 0x0f /* SCSI status 2 ro */
#define SSTAT2_FF3 0x80 /* number of bytes in synchronous */
#define SSTAT2_FF2 0x40 /* data FIFO */
#define SSTAT2_FF1 0x20
#define SSTAT2_FF0 0x10
#define SSTAT2_FF_MASK 0xf0
#define SSTAT2_FF_SHIFT 4
/*
* Latched signals, latched on the leading edge of REQ/ for initiators,
* ACK/ for targets.
*/
#define SSTAT2_SDP 0x08 /* SDP */
#define SSTAT2_MSG 0x04 /* MSG */
#define SSTAT2_CD 0x02 /* C/D */
#define SSTAT2_IO 0x01 /* I/O */
#define SSTAT2_PHASE_CMDOUT SSTAT2_CD
#define SSTAT2_PHASE_DATAIN SSTAT2_IO
#define SSTAT2_PHASE_DATAOUT 0
#define SSTAT2_PHASE_MSGIN (SSTAT2_CD|SSTAT2_IO|SSTAT2_MSG)
#define SSTAT2_PHASE_MSGOUT (SSTAT2_CD|SSTAT2_MSG)
#define SSTAT2_PHASE_STATIN (SSTAT2_CD|SSTAT2_IO)
#define SSTAT2_PHASE_MASK (SSTAT2_CD|SSTAT2_IO|SSTAT2_MSG)
/* NCR53c700-66 only */
#define SCRATCHA_REG_00 0x10 /* through 0x13 Scratch A rw */
/* NCR53c710 and higher */
#define DSA_REG 0x10 /* DATA structure address */
#define CTEST0_REG_700 0x14 /* Chip test 0 ro */
#define CTEST0_REG_800 0x18 /* Chip test 0 rw, general purpose */
/* 0x80 - 0x04 are reserved */
#define CTEST0_700_RTRG 0x02 /* Real target mode */
#define CTEST0_700_DDIR 0x01 /* Data direction, 1 =
* SCSI bus to host, 0 =
* host to SCSI.
*/
#define CTEST1_REG_700 0x15 /* Chip test 1 ro */
#define CTEST1_REG_800 0x19 /* Chip test 1 ro */
#define CTEST1_FMT3 0x80 /* Identify which byte lanes are empty */
#define CTEST1_FMT2 0x40 /* in the DMA FIFO */
#define CTEST1_FMT1 0x20
#define CTEST1_FMT0 0x10
#define CTEST1_FFL3 0x08 /* Identify which bytes lanes are full */
#define CTEST1_FFL2 0x04 /* in the DMA FIFO */
#define CTEST1_FFL1 0x02
#define CTEST1_FFL0 0x01
#define CTEST2_REG_700 0x16 /* Chip test 2 ro */
#define CTEST2_REG_800 0x1a /* Chip test 2 ro */
#define CTEST2_800_DDIR 0x80 /* 1 = SCSI->host */
#define CTEST2_800_SIGP 0x40 /* A copy of SIGP in ISTAT.
Reading this register clears */
#define CTEST2_800_CIO 0x20 /* Configured as IO */.
#define CTEST2_800_CM 0x10 /* Configured as memory */
/* 0x80 - 0x40 are reserved on 700 series chips */
#define CTEST2_700_SOFF 0x20 /* SCSI Offset Compare,
* As an initiator, this bit is
* one when the synchronous offset
* is zero, as a target this bit
* is one when the synchronous
* offset is at the maximum
* defined in SXFER
*/
#define CTEST2_700_SFP 0x10 /* SCSI FIFO parity bit,
* reading CTEST3 unloads a byte
* from the FIFO and sets this
*/
#define CTEST2_700_DFP 0x08 /* DMA FIFO parity bit,
* reading CTEST6 unloads a byte
* from the FIFO and sets this
*/
#define CTEST2_TEOP 0x04 /* SCSI true end of process,
* indicates a totally finished
* transfer
*/
#define CTEST2_DREQ 0x02 /* Data request signal */
/* 0x01 is reserved on 700 series chips */
#define CTEST2_800_DACK 0x01
/*
* Chip test 3 ro
* Unloads the bottom byte of the eight deep SCSI synchronous FIFO,
* check SSTAT2 FIFO full bits to determine size. Note that a GROSS
* error results if a read is attempted on this register. Also note
* that 16 and 32 bit reads of this register will cause corruption.
*/
#define CTEST3_REG_700 0x17
/* Chip test 3 rw */
#define CTEST3_REG_800 0x1b
#define CTEST3_800_V3 0x80 /* Chip revision */
#define CTEST3_800_V2 0x40
#define CTEST3_800_V1 0x20
#define CTEST3_800_V0 0x10
#define CTEST3_800_FLF 0x08 /* Flush DMA FIFO */
#define CTEST3_800_CLF 0x04 /* Clear DMA FIFO */
#define CTEST3_800_FM 0x02 /* Fetch mode pin */
/* bit 0 is reserved on 800 series chips */
#define CTEST4_REG_700 0x18 /* Chip test 4 rw */
#define CTEST4_REG_800 0x21 /* Chip test 4 rw */
/* 0x80 is reserved on 700 series chips */
#define CTEST4_800_BDIS 0x80 /* Burst mode disable */
#define CTEST4_ZMOD 0x40 /* High impedance mode */
#define CTEST4_SZM 0x20 /* SCSI bus high impedance */
#define CTEST4_700_SLBE 0x10 /* SCSI loopback enabled */
#define CTEST4_800_SRTM 0x10 /* Shadow Register Test Mode */
#define CTEST4_700_SFWR 0x08 /* SCSI FIFO write enable,
* redirects writes from SODL
* to the SCSI FIFO.
*/
#define CTEST4_800_MPEE 0x08 /* Enable parity checking
during master cycles on PCI
bus */
/*
* These bits send the contents of the CTEST6 register to the appropriate
* byte lane of the 32 bit DMA FIFO. Normal operation is zero, otherwise
* the high bit means the low two bits select the byte lane.
*/
#define CTEST4_FBL2 0x04
#define CTEST4_FBL1 0x02
#define CTEST4_FBL0 0x01
#define CTEST4_FBL_MASK 0x07
#define CTEST4_FBL_0 0x04 /* Select DMA FIFO byte lane 0 */
#define CTEST4_FBL_1 0x05 /* Select DMA FIFO byte lane 1 */
#define CTEST4_FBL_2 0x06 /* Select DMA FIFO byte lane 2 */
#define CTEST4_FBL_3 0x07 /* Select DMA FIFO byte lane 3 */
#define CTEST4_800_SAVE (CTEST4_800_BDIS)
#define CTEST5_REG_700 0x19 /* Chip test 5 rw */
#define CTEST5_REG_800 0x22 /* Chip test 5 rw */
/*
* Clock Address Incrementor. When set, it increments the
* DNAD register to the next bus size boundary. It automatically
* resets itself when the operation is complete.
*/
#define CTEST5_ADCK 0x80
/*
* Clock Byte Counter. When set, it decrements the DBC register to
* the next bus size boundary.
*/
#define CTEST5_BBCK 0x40
/*
* Reset SCSI Offset. Setting this bit to 1 clears the current offset
* pointer in the SCSI synchronous offset counter (SSTAT). This bit
* is set to 1 if a SCSI Gross Error Condition occurs. The offset should
* be cleared when a synchronous transfer fails. When written, it is
* automatically cleared after the SCSI synchronous offset counter is
* reset.
*/
/* Bit 5 is reserved on 800 series chips */
#define CTEST5_700_ROFF 0x20
/*
* Master Control for Set or Reset pulses. When 1, causes the low
* four bits of register to set when set, 0 causes the low bits to
* clear when set.
*/
#define CTEST5_MASR 0x10
#define CTEST5_DDIR 0x08 /* DMA direction */
/*
* Bits 2-0 are reserved on 800 series chips
*/
#define CTEST5_700_EOP 0x04 /* End of process */
#define CTEST5_700_DREQ 0x02 /* Data request */
#define CTEST5_700_DACK 0x01 /* Data acknowledge */
/*
* Chip test 6 rw - writing to this register writes to the byte
* lane in the DMA FIFO as determined by the FBL bits in the CTEST4
* register.
*/
#define CTEST6_REG_700 0x1a
#define CTEST6_REG_800 0x23
#define CTEST7_REG 0x1b /* Chip test 7 rw */
/* 0x80 - 0x40 are reserved on NCR53c700 and NCR53c700-66 chips */
#define CTEST7_10_CDIS 0x80 /* Cache burst disable */
#define CTEST7_10_SC1 0x40 /* Snoop control bits */
#define CTEST7_10_SC0 0x20
#define CTEST7_10_SC_MASK 0x60
/* 0x20 is reserved on the NCR53c700 */
#define CTEST7_0060_FM 0x20 /* Fetch mode */
#define CTEST7_STD 0x10 /* Selection timeout disable */
#define CTEST7_DFP 0x08 /* DMA FIFO parity bit for CTEST6 */
#define CTEST7_EVP 0x04 /* 1 = host bus even parity, 0 = odd */
#define CTEST7_10_TT1 0x02 /* Transfer type */
#define CTEST7_00_DC 0x02 /* Set to drive DC low during instruction
fetch */
#define CTEST7_DIFF 0x01 /* Differential mode */
#define CTEST7_SAVE ( CTEST7_EVP | CTEST7_DIFF )
#define TEMP_REG 0x1c /* through 0x1f Temporary stack rw */
#define DFIFO_REG 0x20 /* DMA FIFO rw */
/*
* 0x80 is reserved on the NCR53c710, the CLF and FLF bits have been
* moved into the CTEST8 register.
*/
#define DFIFO_00_FLF 0x80 /* Flush DMA FIFO to memory */
#define DFIFO_00_CLF 0x40 /* Clear DMA and SCSI FIFOs */
#define DFIFO_BO6 0x40
#define DFIFO_BO5 0x20
#define DFIFO_BO4 0x10
#define DFIFO_BO3 0x08
#define DFIFO_BO2 0x04
#define DFIFO_BO1 0x02
#define DFIFO_BO0 0x01
#define DFIFO_10_BO_MASK 0x7f /* 7 bit counter */
#define DFIFO_00_BO_MASK 0x3f /* 6 bit counter */
/*
* Interrupt status rw
* Note that this is the only register which can be read while SCSI
* SCRIPTS are being executed.
*/
#define ISTAT_REG_700 0x21
#define ISTAT_REG_800 0x14
#define ISTAT_ABRT 0x80 /* Software abort, write
*1 to abort, wait for interrupt. */
/* 0x40 and 0x20 are reserved on NCR53c700 and NCR53c700-66 chips */
#define ISTAT_10_SRST 0x40 /* software reset */
#define ISTAT_10_SIGP 0x20 /* signal script */
/* 0x10 is reserved on NCR53c700 series chips */
#define ISTAT_800_SEM 0x10 /* semaphore */
#define ISTAT_CON 0x08 /* 1 when connected */
#define ISTAT_800_INTF 0x04 /* Interrupt on the fly */
#define ISTAT_700_PRE 0x04 /* Pointer register empty.
* Set to 1 when DSPS and DSP
* registers are empty in pipeline
* mode, always set otherwise.
*/
#define ISTAT_SIP 0x02 /* SCSI interrupt pending from
* SCSI portion of SIOP see
* SSTAT0
*/
#define ISTAT_DIP 0x01 /* DMA interrupt pending
* see DSTAT
*/
/* NCR53c700-66 and NCR53c710 only */
#define CTEST8_REG 0x22 /* Chip test 8 rw */
#define CTEST8_0066_EAS 0x80 /* Enable alternate SCSI clock,
* ie read from SCLK/ rather than CLK/
*/
#define CTEST8_0066_EFM 0x40 /* Enable fetch and master outputs */
#define CTEST8_0066_GRP 0x20 /* Generate Receive Parity for
* pass through. This insures that
* bad parity won't reach the host
* bus.
*/
#define CTEST8_0066_TE 0x10 /* TolerANT enable. Enable
* active negation, should only
* be used for slow SCSI
* non-differential.
*/
#define CTEST8_0066_HSC 0x08 /* Halt SCSI clock */
#define CTEST8_0066_SRA 0x04 /* Shorten REQ/ACK filtering,
* must be set for fast SCSI-II
* speeds.
*/
#define CTEST8_0066_DAS 0x02 /* Disable automatic target/initiator
* switching.
*/
#define CTEST8_0066_LDE 0x01 /* Last disconnect enable.
* The status of pending
* disconnect is maintained by
* the core, eliminating
* the possibility of missing a
* selection or reselection
* while waiting to fetch a
* WAIT DISCONNECT opcode.
*/
#define CTEST8_10_V3 0x80 /* Chip revision */
#define CTEST8_10_V2 0x40
#define CTEST8_10_V1 0x20
#define CTEST8_10_V0 0x10
#define CTEST8_10_V_MASK 0xf0
#define CTEST8_10_FLF 0x08 /* Flush FIFOs */
#define CTEST8_10_CLF 0x04 /* Clear FIFOs */
#define CTEST8_10_FM 0x02 /* Fetch pin mode */
#define CTEST8_10_SM 0x01 /* Snoop pin mode */
/*
* The CTEST9 register may be used to differentiate between a
* NCR53c700 and a NCR53c710.
*
* Write 0xff to this register.
* Read it.
* If the contents are 0xff, it is a NCR53c700
* If the contents are 0x00, it is a NCR53c700-66 first revision
* If the contents are some other value, it is some other NCR53c700-66
*/
#define CTEST9_REG_00 0x23 /* Chip test 9 ro */
#define LCRC_REG_10 0x23
/*
* 0x24 through 0x27 are the DMA byte counter register. Instructions
* write their high 8 bits into the DCMD register, the low 24 bits into
* the DBC register.
*
* Function is dependent on the command type being executed.
*/
#define DBC_REG 0x24
/*
* For Block Move Instructions, DBC is a 24 bit quantity representing
* the number of bytes to transfer.
* For Transfer Control Instructions, DBC is bit fielded as follows :
*/
/* Bits 20 - 23 should be clear */
#define DBC_TCI_TRUE (1 << 19) /* Jump when true */
#define DBC_TCI_COMPARE_DATA (1 << 18) /* Compare data */
#define DBC_TCI_COMPARE_PHASE (1 << 17) /* Compare phase with DCMD field */
#define DBC_TCI_WAIT_FOR_VALID (1 << 16) /* Wait for REQ */
/* Bits 8 - 15 are reserved on some implementations ? */
#define DBC_TCI_MASK_MASK 0xff00 /* Mask for data compare */
#define DBC_TCI_MASK_SHIFT 8
#define DBC_TCI_DATA_MASK 0xff /* Data to be compared */
#define DBC_TCI_DATA_SHIFT 0
#define DBC_RWRI_IMMEDIATE_MASK 0xff00 /* Immediate data */
#define DBC_RWRI_IMMEDIATE_SHIFT 8 /* Amount to shift */
#define DBC_RWRI_ADDRESS_MASK 0x3f0000 /* Register address */
#define DBC_RWRI_ADDRESS_SHIFT 16
/*
* DMA command r/w
*/
#define DCMD_REG 0x27
#define DCMD_TYPE_MASK 0xc0 /* Masks off type */
#define DCMD_TYPE_BMI 0x00 /* Indicates a Block Move instruction */
#define DCMD_BMI_IO 0x01 /* I/O, CD, and MSG bits selecting */
#define DCMD_BMI_CD 0x02 /* the phase for the block MOVE */
#define DCMD_BMI_MSG 0x04 /* instruction */
#define DCMD_BMI_OP_MASK 0x18 /* mask for opcode */
#define DCMD_BMI_OP_MOVE_T 0x00 /* MOVE */
#define DCMD_BMI_OP_MOVE_I 0x08 /* MOVE Initiator */
#define DCMD_BMI_INDIRECT 0x20 /* Indirect addressing */
#define DCMD_TYPE_TCI 0x80 /* Indicates a Transfer Control
instruction */
#define DCMD_TCI_IO 0x01 /* I/O, CD, and MSG bits selecting */
#define DCMD_TCI_CD 0x02 /* the phase for the block MOVE */
#define DCMD_TCI_MSG 0x04 /* instruction */
#define DCMD_TCI_OP_MASK 0x38 /* mask for opcode */
#define DCMD_TCI_OP_JUMP 0x00 /* JUMP */
#define DCMD_TCI_OP_CALL 0x08 /* CALL */
#define DCMD_TCI_OP_RETURN 0x10 /* RETURN */
#define DCMD_TCI_OP_INT 0x18 /* INT */
#define DCMD_TYPE_RWRI 0x40 /* Indicates I/O or register Read/Write
instruction */
#define DCMD_RWRI_OPC_MASK 0x38 /* Opcode mask */
#define DCMD_RWRI_OPC_WRITE 0x28 /* Write SFBR to register */
#define DCMD_RWRI_OPC_READ 0x30 /* Read register to SFBR */
#define DCMD_RWRI_OPC_MODIFY 0x38 /* Modify in place */
#define DCMD_RWRI_OP_MASK 0x07
#define DCMD_RWRI_OP_MOVE 0x00
#define DCMD_RWRI_OP_SHL 0x01
#define DCMD_RWRI_OP_OR 0x02
#define DCMD_RWRI_OP_XOR 0x03
#define DCMD_RWRI_OP_AND 0x04
#define DCMD_RWRI_OP_SHR 0x05
#define DCMD_RWRI_OP_ADD 0x06
#define DCMD_RWRI_OP_ADDC 0x07
#define DCMD_TYPE_MMI 0xc0 /* Indicates a Memory Move instruction
(three words) */
#define DNAD_REG 0x28 /* through 0x2b DMA next address for
data */
#define DSP_REG 0x2c /* through 0x2f DMA SCRIPTS pointer rw */
#define DSPS_REG 0x30 /* through 0x33 DMA SCRIPTS pointer
save rw */
#define DMODE_REG_00 0x34 /* DMA mode rw */
#define DMODE_00_BL1 0x80 /* Burst length bits */
#define DMODE_00_BL0 0x40
#define DMODE_BL_MASK 0xc0
/* Burst lengths (800) */
#define DMODE_BL_2 0x00 /* 2 transfer */
#define DMODE_BL_4 0x40 /* 4 transfers */
#define DMODE_BL_8 0x80 /* 8 transfers */
#define DMODE_BL_16 0xc0 /* 16 transfers */
#define DMODE_700_BW16 0x20 /* Host buswidth = 16 */
#define DMODE_700_286 0x10 /* 286 mode */
#define DMODE_700_IOM 0x08 /* Transfer to IO port */
#define DMODE_700_FAM 0x04 /* Fixed address mode */
#define DMODE_700_PIPE 0x02 /* Pipeline mode disables
* automatic fetch / exec
*/
#define DMODE_MAN 0x01 /* Manual start mode,
* requires a 1 to be written
* to the start DMA bit in the DCNTL
* register to run scripts
*/
#define DMODE_700_SAVE ( DMODE_00_BL_MASK | DMODE_00_BW16 | DMODE_00_286 )
/* NCR53c800 series only */
#define SCRATCHA_REG_800 0x34 /* through 0x37 Scratch A rw */
/* NCR53c710 only */
#define SCRATCB_REG_10 0x34 /* through 0x37 scratch B rw */
#define DMODE_REG_10 0x38 /* DMA mode rw, NCR53c710 and newer */
#define DMODE_800_SIOM 0x20 /* Source IO = 1 */
#define DMODE_800_DIOM 0x10 /* Destination IO = 1 */
#define DMODE_800_ERL 0x08 /* Enable Read Line */
/* 35-38 are reserved on 700 and 700-66 series chips */
#define DIEN_REG 0x39 /* DMA interrupt enable rw */
/* 0x80, 0x40, and 0x20 are reserved on 700-series chips */
#define DIEN_800_MDPE 0x40 /* Master data parity error */
#define DIEN_800_BF 0x20 /* BUS fault */
#define DIEN_ABRT 0x10 /* Enable aborted interrupt */
#define DIEN_SSI 0x08 /* Enable single step interrupt */
#define DIEN_SIR 0x04 /* Enable SCRIPTS INT command
* interrupt
*/
/* 0x02 is reserved on 800 series chips */
#define DIEN_700_WTD 0x02 /* Enable watchdog timeout interrupt */
#define DIEN_700_OPC 0x01 /* Enable illegal instruction
* interrupt
*/
#define DIEN_800_IID 0x01 /* Same meaning, different name */
/*
* DMA watchdog timer rw
* set in 16 CLK input periods.
*/
#define DWT_REG 0x3a
/* DMA control rw */
#define DCNTL_REG 0x3b
#define DCNTL_700_CF1 0x80 /* Clock divisor bits */
#define DCNTL_700_CF0 0x40
#define DCNTL_700_CF_MASK 0xc0
/* Clock divisors Divisor SCLK range (MHZ) */
#define DCNTL_700_CF_2 0x00 /* 2.0 37.51-50.00 */
#define DCNTL_700_CF_1_5 0x40 /* 1.5 25.01-37.50 */
#define DCNTL_700_CF_1 0x80 /* 1.0 16.67-25.00 */
#define DCNTL_700_CF_3 0xc0 /* 3.0 50.01-66.67 (53c700-66) */
#define DCNTL_700_S16 0x20 /* Load scripts 16 bits at a time */
#define DCNTL_SSM 0x10 /* Single step mode */
#define DCNTL_700_LLM 0x08 /* Low level mode, can only be set
* after selection */
#define DCNTL_800_IRQM 0x08 /* Totem pole IRQ pin */
#define DCNTL_STD 0x04 /* Start DMA / SCRIPTS */
/* 0x02 is reserved */
#define DCNTL_00_RST 0x01 /* Software reset, resets everything
* but 286 mode bit in DMODE. On the
* NCR53c710, this bit moved to CTEST8
*/
#define DCNTL_10_COM 0x01 /* 700 software compatibility mode */
#define DCNTL_700_SAVE ( DCNTL_CF_MASK | DCNTL_S16)
/* NCR53c700-66 only */
#define SCRATCHB_REG_00 0x3c /* through 0x3f scratch b rw */
#define SCRATCHB_REG_800 0x5c /* through 0x5f scratch b rw */
/* NCR53c710 only */
#define ADDER_REG_10 0x3c /* Adder, NCR53c710 only */
#define SIEN1_REG_800 0x41
#define SIEN1_800_STO 0x04 /* selection/reselection timeout */
#define SIEN1_800_GEN 0x02 /* general purpose timer */
#define SIEN1_800_HTH 0x01 /* handshake to handshake */
#define SIST1_REG_800 0x43
#define SIST1_800_STO 0x04 /* selection/reselection timeout */
#define SIST1_800_GEN 0x02 /* general purpose timer */
#define SIST1_800_HTH 0x01 /* handshake to handshake */
#define SLPAR_REG_800 0x44 /* Parity */
#define MACNTL_REG_800 0x46 /* Memory access control */
#define MACNTL_800_TYP3 0x80
#define MACNTL_800_TYP2 0x40
#define MACNTL_800_TYP1 0x20
#define MACNTL_800_TYP0 0x10
#define MACNTL_800_DWR 0x08
#define MACNTL_800_DRD 0x04
#define MACNTL_800_PSCPT 0x02
#define MACNTL_800_SCPTS 0x01
#define GPCNTL_REG_800 0x47 /* General Purpose Pin Control */
/* Timeouts are expressed such that 0=off, 1=100us, doubling after that */
#define STIME0_REG_800 0x48 /* SCSI Timer Register 0 */
#define STIME0_800_HTH_MASK 0xf0 /* Handshake to Handshake timeout */
#define STIME0_800_HTH_SHIFT 4
#define STIME0_800_SEL_MASK 0x0f /* Selection timeout */
#define STIME0_800_SEL_SHIFT 0
#define STIME1_REG_800 0x49
#define STIME1_800_GEN_MASK 0x0f /* General purpose timer */
#define RESPID_REG_800 0x4a /* Response ID, bit fielded. 8
bits on narrow chips, 16 on WIDE */
#define STEST0_REG_800 0x4c
#define STEST0_800_SLT 0x08 /* Selection response logic test */
#define STEST0_800_ART 0x04 /* Arbitration priority encoder test */
#define STEST0_800_SOZ 0x02 /* Synchronous offset zero */
#define STEST0_800_SOM 0x01 /* Synchronous offset maximum */
#define STEST1_REG_800 0x4d
#define STEST1_800_SCLK 0x80 /* Disable SCSI clock */
#define STEST2_REG_800 0x4e
#define STEST2_800_SCE 0x80 /* Enable SOCL/SODL */
#define STEST2_800_ROF 0x40 /* Reset SCSI sync offset */
#define STEST2_800_SLB 0x10 /* Enable SCSI loopback mode */
#define STEST2_800_SZM 0x08 /* SCSI high impedance mode */
#define STEST2_800_EXT 0x02 /* Extend REQ/ACK filter 30 to 60ns */
#define STEST2_800_LOW 0x01 /* SCSI low level mode */
#define STEST3_REG_800 0x4f
#define STEST3_800_TE 0x80 /* Enable active negation */
#define STEST3_800_STR 0x40 /* SCSI FIFO test read */
#define STEST3_800_HSC 0x20 /* Halt SCSI clock */
#define STEST3_800_DSI 0x10 /* Disable single initiator response */
#define STEST3_800_TTM 0x04 /* Time test mode */
#define STEST3_800_CSF 0x02 /* Clear SCSI FIFO */
#define STEST3_800_STW 0x01 /* SCSI FIFO test write */
#define OPTION_PARITY 0x1 /* Enable parity checking */
#define OPTION_TAGGED_QUEUE 0x2 /* Enable SCSI-II tagged queuing */
#define OPTION_700 0x8 /* Always run NCR53c700 scripts */
#define OPTION_INTFLY 0x10 /* Use INTFLY interrupts */
#define OPTION_DEBUG_INTR 0x20 /* Debug interrupts */
#define OPTION_DEBUG_INIT_ONLY 0x40 /* Run initialization code and
simple test code, return
DID_NO_CONNECT if any SCSI
commands are attempted. */
#define OPTION_DEBUG_READ_ONLY 0x80 /* Return DID_ERROR if any
SCSI write is attempted */
#define OPTION_DEBUG_TRACE 0x100 /* Animated trace mode, print
each address and instruction
executed to debug buffer. */
#define OPTION_DEBUG_SINGLE 0x200 /* stop after executing one
instruction */
#define OPTION_SYNCHRONOUS 0x400 /* Enable sync SCSI. */
#define OPTION_MEMORY_MAPPED 0x800 /* NCR registers have valid
memory mapping */
#define OPTION_IO_MAPPED 0x1000 /* NCR registers have valid
I/O mapping */
#define OPTION_DEBUG_PROBE_ONLY 0x2000 /* Probe only, don't even init */
#define OPTION_DEBUG_TESTS_ONLY 0x4000 /* Probe, init, run selected tests */
#define OPTION_DEBUG_TEST0 0x08000 /* Run test 0 */
#define OPTION_DEBUG_TEST1 0x10000 /* Run test 1 */
#define OPTION_DEBUG_TEST2 0x20000 /* Run test 2 */
#define OPTION_DEBUG_DUMP 0x40000 /* Dump commands */
#define OPTION_DEBUG_TARGET_LIMIT 0x80000 /* Only talk to target+luns specified */
#define OPTION_DEBUG_NCOMMANDS_LIMIT 0x100000 /* Limit the number of commands */
#define OPTION_DEBUG_SCRIPT 0x200000 /* Print when checkpoints are passed */
#define OPTION_DEBUG_FIXUP 0x400000 /* print fixup values */
#define OPTION_DEBUG_DSA 0x800000
#define OPTION_DEBUG_CORRUPTION 0x1000000 /* Detect script corruption */
#define OPTION_DEBUG_SDTR 0x2000000 /* Debug SDTR problem */
#define OPTION_DEBUG_MISMATCH 0x4000000 /* Debug phase mismatches */
#define OPTION_DISCONNECT 0x8000000 /* Allow disconnect */
#define OPTION_DEBUG_DISCONNECT 0x10000000
#define OPTION_ALWAYS_SYNCHRONOUS 0x20000000 /* Negotiate sync. transfers
on power up */
#define OPTION_DEBUG_QUEUES 0x80000000
#define OPTION_DEBUG_ALLOCATION 0x100000000LL
#define OPTION_DEBUG_SYNCHRONOUS 0x200000000LL /* Sanity check SXFER and
SCNTL3 registers */
#define OPTION_NO_ASYNC 0x400000000LL /* Don't automagically send
SDTR for async transfers when
we haven't been told to do
a synchronous transfer. */
#define OPTION_NO_PRINT_RACE 0x800000000LL /* Don't print message when
the reselect/WAIT DISCONNECT
race condition hits */
#if !defined(PERM_OPTIONS)
#define PERM_OPTIONS 0
#endif
struct NCR53c7x0_synchronous {
u32 select_indirect; /* Value used for indirect selection */
u32 script[8]; /* Size ?? Script used when target is
reselected */
unsigned char synchronous_want[5]; /* Per target desired SDTR */
/*
* Set_synchronous programs these, select_indirect and current settings after
* int_debug_should show a match.
*/
unsigned char sxfer_sanity, scntl3_sanity;
};
#define CMD_FLAG_SDTR 1 /* Initiating synchronous
transfer negotiation */
#define CMD_FLAG_WDTR 2 /* Initiating wide transfer
negotiation */
#define CMD_FLAG_DID_SDTR 4 /* did SDTR */
#define CMD_FLAG_DID_WDTR 8 /* did WDTR */
struct NCR53c7x0_table_indirect {
u32 count;
void *address;
};
enum ncr_event {
EVENT_NONE = 0,
/*
* Order is IMPORTANT, since these must correspond to the event interrupts
* in 53c7,8xx.scr
*/
EVENT_ISSUE_QUEUE = 0x5000000, /* Command was added to issue queue */
EVENT_START_QUEUE, /* Command moved to start queue */
EVENT_SELECT, /* Command completed selection */
EVENT_DISCONNECT, /* Command disconnected */
EVENT_RESELECT, /* Command reselected */
EVENT_COMPLETE, /* Command completed */
EVENT_IDLE,
EVENT_SELECT_FAILED,
EVENT_BEFORE_SELECT,
EVENT_RESELECT_FAILED
};
struct NCR53c7x0_event {
enum ncr_event event; /* What type of event */
unsigned char target;
unsigned char lun;
struct timeval time;
u32 *dsa; /* What's in the DSA register now (virt) */
/*
* A few things from that SCSI pid so we know what happened after
* the Scsi_Cmnd structure in question may have disappeared.
*/
unsigned long pid; /* The SCSI PID which caused this
event */
unsigned char cmnd[12];
};
/*
* Things in the NCR53c7x0_cmd structure are split into two parts :
*
* 1. A fixed portion, for things which are not accessed directly by static NCR
* code (ie, are referenced only by the Linux side of the driver,
* or only by dynamically generated code).
*
* 2. The DSA portion, for things which are accessed directly by static NCR
* code.
*
* This is a little ugly, but it
* 1. Avoids conflicts between the NCR code's picture of the structure, and
* Linux code's idea of what it looks like.
*
* 2. Minimizes the pain in the Linux side of the code needed
* to calculate real dsa locations for things, etc.
*
*/
struct NCR53c7x0_cmd {
void *real; /* Real, unaligned address for
free function */
void (* free)(void *, int); /* Command to deallocate; NULL
for structures allocated with
scsi_register, etc. */
Scsi_Cmnd *cmd; /* Associated Scsi_Cmnd
structure, Scsi_Cmnd points
at NCR53c7x0_cmd using
host_scribble structure */
int size; /* scsi_malloc'd size of this
structure */
int flags; /* CMD_* flags */
/*
* SDTR and WIDE messages are an either/or affair
* in this message, since we will go into message out and send
* _the whole mess_ without dropping out of message out to
* let the target go into message in after sending the first
* message.
*/
unsigned char select[11]; /* Select message, includes
IDENTIFY
(optional) QUEUE TAG
(optional) SDTR or WDTR
*/
volatile struct NCR53c7x0_cmd *next; /* Linux maintained lists (free,
running, eventually finished */
u32 *data_transfer_start; /* Start of data transfer routines */
u32 *data_transfer_end; /* Address after end of data transfer o
routines */
/*
* The following three fields were moved from the DSA proper to here
* since only dynamically generated NCR code refers to them, meaning
* we don't need dsa_* absolutes, and it is simpler to let the
* host code refer to them directly.
*/
/*
* HARD CODED : residual and saved_residual need to agree with the sizes
* used in NCR53c7,8xx.scr.
*
* FIXME: we want to consider the case where we have odd-length
* scatter/gather buffers and a WIDE transfer, in which case
* we'll need to use the CHAIN MOVE instruction. Ick.
*/
u32 residual[6]; /* Residual data transfer which
allows pointer code to work
right.
[0-1] : Conditional call to
appropriate other transfer
routine.
[2-3] : Residual block transfer
instruction.
[4-5] : Jump to instruction
after splice.
*/
u32 saved_residual[6]; /* Copy of old residual, so we
can get another partial
transfer and still recover
*/
u32 saved_data_pointer; /* Saved data pointer */
u32 dsa_next_addr; /* _Address_ of dsa_next field
in this dsa for RISCy
style constant. */
u32 dsa_addr; /* Address of dsa; RISCy style
constant */
u32 dsa[0]; /* Variable length (depending
on host type, number of scatter /
gather buffers, etc). */
};
struct NCR53c7x0_break {
u32 *address, old_instruction[2];
struct NCR53c7x0_break *next;
unsigned char old_size; /* Size of old instruction */
};
/* Indicates that the NCR is not executing code */
#define STATE_HALTED 0
/*
* Indicates that the NCR is executing the wait for select / reselect
* script. Only used when running NCR53c700 compatible scripts, only
* state during which an ABORT is _not_ considered an error condition.
*/
#define STATE_WAITING 1
/* Indicates that the NCR is executing other code. */
#define STATE_RUNNING 2
/*
* Indicates that the NCR was being aborted.
*/
#define STATE_ABORTING 3
/* Indicates that the NCR was successfully aborted. */
#define STATE_ABORTED 4
/* Indicates that the NCR has been disabled due to a fatal error */
#define STATE_DISABLED 5
/*
* Where knowledge of SCSI SCRIPT(tm) specified values are needed
* in an interrupt handler, an interrupt handler exists for each
* different SCSI script so we don't have name space problems.
*
* Return values of these handlers are as follows :
*/
#define SPECIFIC_INT_NOTHING 0 /* don't even restart */
#define SPECIFIC_INT_RESTART 1 /* restart at the next instruction */
#define SPECIFIC_INT_ABORT 2 /* recoverable error, abort cmd */
#define SPECIFIC_INT_PANIC 3 /* unrecoverable error, panic */
#define SPECIFIC_INT_DONE 4 /* normal command completion */
#define SPECIFIC_INT_BREAK 5 /* break point encountered */
struct NCR53c7x0_hostdata {
int size; /* Size of entire Scsi_Host
structure */
int board; /* set to board type, useful if
we have host specific things,
ie, a general purpose I/O
bit is being used to enable
termination, etc. */
int chip; /* set to chip type; 700-66 is
700-66, rest are last three
digits of part number */
/*
* PCI device, only for NCR53c8x0 chips.
* pci_valid indicates that the PCI configuration information
* is valid, and we can twiddle MAX_LAT, etc. as recommended
* for maximum performance in the NCR documentation.
*/
struct pci_dev *pci_dev;
unsigned pci_valid:1;
u32 *dsp; /* dsp to restart with after
all stacked interrupts are
handled. */
unsigned dsp_changed:1; /* Has dsp changed within this
set of stacked interrupts ? */
unsigned char dstat; /* Most recent value of dstat */
unsigned dstat_valid:1;
unsigned expecting_iid:1; /* Expect IID interrupt */
unsigned expecting_sto:1; /* Expect STO interrupt */
/*
* The code stays cleaner if we use variables with function
* pointers and offsets that are unique for the different
* scripts rather than having a slew of switch(hostdata->chip)
* statements.
*
* It also means that the #defines from the SCSI SCRIPTS(tm)
* don't have to be visible outside of the script-specific
* instructions, preventing name space pollution.
*/
void (* init_fixup)(struct Scsi_Host *host);
void (* init_save_regs)(struct Scsi_Host *host);
void (* dsa_fixup)(struct NCR53c7x0_cmd *cmd);
void (* soft_reset)(struct Scsi_Host *host);
int (* run_tests)(struct Scsi_Host *host);
/*
* Called when DSTAT_SIR is set, indicating an interrupt generated
* by the INT instruction, where values are unique for each SCSI
* script. Should return one of the SPEC_* values.
*/
int (* dstat_sir_intr)(struct Scsi_Host *host, struct NCR53c7x0_cmd *cmd);
int dsa_len; /* Size of DSA structure */
/*
* Location of DSA fields for the SCSI SCRIPT corresponding to this
* chip.
*/
s32 dsa_start;
s32 dsa_end;
s32 dsa_next;
s32 dsa_prev;
s32 dsa_cmnd;
s32 dsa_select;
s32 dsa_msgout;
s32 dsa_cmdout;
s32 dsa_dataout;
s32 dsa_datain;
s32 dsa_msgin;
s32 dsa_msgout_other;
s32 dsa_write_sync;
s32 dsa_write_resume;
s32 dsa_check_reselect;
s32 dsa_status;
s32 dsa_saved_pointer;
s32 dsa_jump_dest;
/*
* Important entry points that generic fixup code needs
* to know about, fixed up.
*/
s32 E_accept_message;
s32 E_command_complete;
s32 E_data_transfer;
s32 E_dsa_code_template;
s32 E_dsa_code_template_end;
s32 E_end_data_transfer;
s32 E_msg_in;
s32 E_initiator_abort;
s32 E_other_transfer;
s32 E_other_in;
s32 E_other_out;
s32 E_target_abort;
s32 E_debug_break;
s32 E_reject_message;
s32 E_respond_message;
s32 E_select;
s32 E_select_msgout;
s32 E_test_0;
s32 E_test_1;
s32 E_test_2;
s32 E_test_3;
s32 E_dsa_zero;
s32 E_cmdout_cmdout;
s32 E_wait_reselect;
s32 E_dsa_code_begin;
long long options; /* Bitfielded set of options enabled */
volatile u32 test_completed; /* Test completed */
int test_running; /* Test currently running */
s32 test_source;
volatile s32 test_dest;
volatile int state; /* state of driver, only used for
OPTION_700 */
unsigned char dmode; /*
* set to the address of the DMODE
* register for this chip.
*/
unsigned char istat; /*
* set to the address of the ISTAT
* register for this chip.
*/
int scsi_clock; /*
* SCSI clock in HZ. 0 may be used
* for unknown, although this will
* disable synchronous negotiation.
*/
volatile int intrs; /* Number of interrupts */
volatile int resets; /* Number of SCSI resets */
unsigned char saved_dmode;
unsigned char saved_ctest4;
unsigned char saved_ctest7;
unsigned char saved_dcntl;
unsigned char saved_scntl3;
unsigned char this_id_mask;
/* Debugger information */
struct NCR53c7x0_break *breakpoints, /* Linked list of all break points */
*breakpoint_current; /* Current breakpoint being stepped
through, NULL if we are running
normally. */
#ifdef NCR_DEBUG
int debug_size; /* Size of debug buffer */
volatile int debug_count; /* Current data count */
volatile char *debug_buf; /* Output ring buffer */
volatile char *debug_write; /* Current write pointer */
volatile char *debug_read; /* Current read pointer */
#endif /* def NCR_DEBUG */
/* XXX - primitive debugging junk, remove when working ? */
int debug_print_limit; /* Number of commands to print
out exhaustive debugging
information for if
OPTION_DEBUG_DUMP is set */
unsigned char debug_lun_limit[16]; /* If OPTION_DEBUG_TARGET_LIMIT
set, puke if commands are sent
to other target/lun combinations */
int debug_count_limit; /* Number of commands to execute
before puking to limit debugging
output */
volatile unsigned idle:1; /* set to 1 if idle */
/*
* Table of synchronous+wide transfer parameters set on a per-target
* basis.
*/
volatile struct NCR53c7x0_synchronous sync[16];
volatile Scsi_Cmnd *issue_queue;
/* waiting to be issued by
Linux driver */
volatile struct NCR53c7x0_cmd *running_list;
/* commands running, maintained
by Linux driver */
volatile struct NCR53c7x0_cmd *curr; /* currently connected
nexus, ONLY valid for
NCR53c700/NCR53c700-66
*/
volatile struct NCR53c7x0_cmd *spare; /* pointer to spare,
allocated at probe time,
which we can use for
initialization */
volatile struct NCR53c7x0_cmd *free;
int max_cmd_size; /* Maximum size of NCR53c7x0_cmd
based on number of
scatter/gather segments, etc.
*/
volatile int num_cmds; /* Number of commands
allocated */
volatile int extra_allocate;
volatile unsigned char cmd_allocated[16]; /* Have we allocated commands
for this target yet? If not,
do so ASAP */
volatile unsigned char busy[16][8]; /* number of commands
executing on each target
*/
/*
* Eventually, I'll switch to a coroutine for calling
* cmd->done(cmd), etc. so that we can overlap interrupt
* processing with this code for maximum performance.
*/
volatile struct NCR53c7x0_cmd *finished_queue;
/* Shared variables between SCRIPT and host driver */
volatile u32 *schedule; /* Array of JUMPs to dsa_begin
routines of various DSAs.
When not in use, replace
with jump to next slot */
volatile unsigned char msg_buf[16]; /* buffer for messages
other than the command
complete message */
/* Per-target default synchronous and WIDE messages */
volatile unsigned char synchronous_want[16][5];
volatile unsigned char wide_want[16][4];
/* Bit fielded set of targets we want to speak synchronously with */
volatile u16 initiate_sdtr;
/* Bit fielded set of targets we want to speak wide with */
volatile u16 initiate_wdtr;
/* Bit fielded list of targets we've talked to. */
volatile u16 talked_to;
/* Array of bit-fielded lun lists that we need to request_sense */
volatile unsigned char request_sense[16];
u32 addr_reconnect_dsa_head; /* RISCy style constant,
address of following */
volatile u32 reconnect_dsa_head;
/* Data identifying nexus we are trying to match during reselection */
volatile unsigned char reselected_identify; /* IDENTIFY message */
volatile unsigned char reselected_tag; /* second byte of queue tag
message or 0 */
/* These were static variables before we moved them */
s32 NCR53c7xx_zero;
s32 NCR53c7xx_sink;
u32 NOP_insn;
char NCR53c7xx_msg_reject;
char NCR53c7xx_msg_abort;
char NCR53c7xx_msg_nop;
volatile int event_size, event_index;
volatile struct NCR53c7x0_event *events;
/* If we need to generate code to kill off the currently connected
command, this is where we do it. Should have a BMI instruction
to source or sink the current data, followed by a JUMP
to abort_connected */
u32 *abort_script;
int script_count; /* Size of script in words */
u32 script[0]; /* Relocated SCSI script */
};
#define IRQ_NONE 255
#define DMA_NONE 255
#define IRQ_AUTO 254
#define DMA_AUTO 254
#define BOARD_GENERIC 0
#define NCR53c7x0_insn_size(insn) \
(((insn) & DCMD_TYPE_MASK) == DCMD_TYPE_MMI ? 3 : 2)
#define NCR53c7x0_local_declare() \
volatile unsigned char *NCR53c7x0_address_memory; \
unsigned int NCR53c7x0_address_io; \
int NCR53c7x0_memory_mapped
#define NCR53c7x0_local_setup(host) \
NCR53c7x0_address_memory = (void *) (host)->base; \
NCR53c7x0_address_io = (unsigned int) (host)->io_port; \
NCR53c7x0_memory_mapped = ((struct NCR53c7x0_hostdata *) \
host->hostdata)-> options & OPTION_MEMORY_MAPPED
#define NCR53c7x0_read8(address) \
(NCR53c7x0_memory_mapped ? \
(unsigned int)readb(NCR53c7x0_address_memory + (address)) : \
inb(NCR53c7x0_address_io + (address)))
#define NCR53c7x0_read16(address) \
(NCR53c7x0_memory_mapped ? \
(unsigned int)readw(NCR53c7x0_address_memory + (address)) : \
inw(NCR53c7x0_address_io + (address)))
#define NCR53c7x0_read32(address) \
(NCR53c7x0_memory_mapped ? \
(unsigned int) readl(NCR53c7x0_address_memory + (address)) : \
inl(NCR53c7x0_address_io + (address)))
#define NCR53c7x0_write8(address,value) \
(NCR53c7x0_memory_mapped ? \
({writeb((value), NCR53c7x0_address_memory + (address)); mb();}) : \
outb((value), NCR53c7x0_address_io + (address)))
#define NCR53c7x0_write16(address,value) \
(NCR53c7x0_memory_mapped ? \
({writew((value), NCR53c7x0_address_memory + (address)); mb();}) : \
outw((value), NCR53c7x0_address_io + (address)))
#define NCR53c7x0_write32(address,value) \
(NCR53c7x0_memory_mapped ? \
({writel((value), NCR53c7x0_address_memory + (address)); mb();}) : \
outl((value), NCR53c7x0_address_io + (address)))
/* Patch arbitrary 32 bit words in the script */
#define patch_abs_32(script, offset, symbol, value) \
for (i = 0; i < (sizeof (A_##symbol##_used) / sizeof \
(u32)); ++i) { \
(script)[A_##symbol##_used[i] - (offset)] += (value); \
if (hostdata->options & OPTION_DEBUG_FIXUP) \
printk("scsi%d : %s reference %d at 0x%x in %s is now 0x%x\n",\
host->host_no, #symbol, i, A_##symbol##_used[i] - \
(int)(offset), #script, (script)[A_##symbol##_used[i] - \
(offset)]); \
}
/* Patch read/write instruction immediate field */
#define patch_abs_rwri_data(script, offset, symbol, value) \
for (i = 0; i < (sizeof (A_##symbol##_used) / sizeof \
(u32)); ++i) \
(script)[A_##symbol##_used[i] - (offset)] = \
((script)[A_##symbol##_used[i] - (offset)] & \
~DBC_RWRI_IMMEDIATE_MASK) | \
(((value) << DBC_RWRI_IMMEDIATE_SHIFT) & \
DBC_RWRI_IMMEDIATE_MASK)
/* Patch transfer control instruction data field */
#define patch_abs_tci_data(script, offset, symbol, value) \
for (i = 0; i < (sizeof (A_##symbol##_used) / sizeof \
(u32)); ++i) \
(script)[A_##symbol##_used[i] - (offset)] = \
((script)[A_##symbol##_used[i] - (offset)] & \
~DBC_TCI_DATA_MASK) | \
(((value) << DBC_TCI_DATA_SHIFT) & \
DBC_TCI_DATA_MASK)
/* Patch field in dsa structure (assignment should be +=?) */
#define patch_dsa_32(dsa, symbol, word, value) \
{ \
(dsa)[(hostdata->symbol - hostdata->dsa_start) / sizeof(u32) \
+ (word)] = (value); \
if (hostdata->options & OPTION_DEBUG_DSA) \
printk("scsi : dsa %s symbol %s(%d) word %d now 0x%x\n", \
#dsa, #symbol, hostdata->symbol, \
(word), (u32) le32_to_cpu(value)); \
}
/* Paranoid people could use panic() here. */
#define FATAL(host) shutdown((host));
#endif /* NCR53c7x0_C */
#endif /* NCR53c7x0_H */
drivers/scsi/53c7,8xx.scr deleted 100644 → 0
View file @ 53e20c84
#undef DEBUG
#undef EVENTS
; NCR 53c810 driver, main script
; Sponsored by
; iX Multiuser Multitasking Magazine
; hm@ix.de
;
; Copyright 1993, 1994, 1995 Drew Eckhardt
; Visionary Computing
; (Unix and Linux consulting and custom programming)
; drew@PoohSticks.ORG
; +1 (303) 786-7975
;
; TolerANT and SCSI SCRIPTS are registered trademarks of NCR Corporation.
;
; PRE-ALPHA
;
; For more information, please consult
;
; NCR 53C810
; PCI-SCSI I/O Processor
; Data Manual
;
; NCR 53C710
; SCSI I/O Processor
; Programmers Guide
;
; NCR Microelectronics
; 1635 Aeroplaza Drive
; Colorado Springs, CO 80916
; 1+ (719) 578-3400
;
; Toll free literature number
; +1 (800) 334-5454
;
; IMPORTANT : This code is self modifying due to the limitations of
; the NCR53c7,8xx series chips. Persons debugging this code with
; the remote debugger should take this into account, and NOT set
; breakpoints in modified instructions.
;
; Design:
; The NCR53c7,8xx family of SCSI chips are busmasters with an onboard
; microcontroller using a simple instruction set.
;
; So, to minimize the effects of interrupt latency, and to maximize
; throughput, this driver offloads the practical maximum amount
; of processing to the SCSI chip while still maintaining a common
; structure.
;
; Where tradeoffs were needed between efficiency on the older
; chips and the newer NCR53c800 series, the NCR53c800 series
; was chosen.
;
; While the NCR53c700 and NCR53c700-66 lacked the facilities to fully
; automate SCSI transfers without host processor intervention, this
; isn't the case with the NCR53c710 and newer chips which allow
;
; - reads and writes to the internal registers from within the SCSI
; scripts, allowing the SCSI SCRIPTS(tm) code to save processor
; state so that multiple threads of execution are possible, and also
; provide an ALU for loop control, etc.
;
; - table indirect addressing for some instructions. This allows
; pointers to be located relative to the DSA ((Data Structure
; Address) register.
;
; These features make it possible to implement a mailbox style interface,
; where the same piece of code is run to handle I/O for multiple threads
; at once minimizing our need to relocate code. Since the NCR53c700/
; NCR53c800 series have a unique combination of features, making a
; a standard ingoing/outgoing mailbox system, costly, I've modified it.
;
; - Mailboxes are a mixture of code and data. This lets us greatly
; simplify the NCR53c810 code and do things that would otherwise
; not be possible.
;
; The saved data pointer is now implemented as follows :
;
; Control flow has been architected such that if control reaches
; munge_save_data_pointer, on a restore pointers message or
; reconnection, a jump to the address formerly in the TEMP register
; will allow the SCSI command to resume execution.
;
;
; Note : the DSA structures must be aligned on 32 bit boundaries,
; since the source and destination of MOVE MEMORY instructions
; must share the same alignment and this is the alignment of the
; NCR registers.
;
ABSOLUTE dsa_temp_lun = 0 ; Patch to lun for current dsa
ABSOLUTE dsa_temp_next = 0 ; Patch to dsa next for current dsa
ABSOLUTE dsa_temp_addr_next = 0 ; Patch to address of dsa next address
; for current dsa
ABSOLUTE dsa_temp_sync = 0 ; Patch to address of per-target
; sync routine
ABSOLUTE dsa_temp_target = 0 ; Patch to id for current dsa
ABSOLUTE dsa_temp_addr_saved_pointer = 0; Patch to address of per-command
; saved data pointer
ABSOLUTE dsa_temp_addr_residual = 0 ; Patch to address of per-command
; current residual code
ABSOLUTE dsa_temp_addr_saved_residual = 0; Patch to address of per-command
; saved residual code
ABSOLUTE dsa_temp_addr_new_value = 0 ; Address of value for JUMP operand
ABSOLUTE dsa_temp_addr_array_value = 0 ; Address to copy to
ABSOLUTE dsa_temp_addr_dsa_value = 0 ; Address of this DSA value
;
; Once a device has initiated reselection, we need to compare it
; against the singly linked list of commands which have disconnected
; and are pending reselection. These commands are maintained in
; an unordered singly linked list of DSA structures, through the
; DSA pointers at their 'centers' headed by the reconnect_dsa_head
; pointer.
;
; To avoid complications in removing commands from the list,
; I minimize the amount of expensive (at eight operations per
; addition @ 500-600ns each) pointer operations which must
; be done in the NCR driver by precomputing them on the
; host processor during dsa structure generation.
;
; The fixed-up per DSA code knows how to recognize the nexus
; associated with the corresponding SCSI command, and modifies
; the source and destination pointers for the MOVE MEMORY
; instruction which is executed when reselected_ok is called
; to remove the command from the list. Similarly, DSA is
; loaded with the address of the next DSA structure and
; reselected_check_next is called if a failure occurs.
;
; Perhaps more concisely, the net effect of the mess is
;
; for (dsa = reconnect_dsa_head, dest = &reconnect_dsa_head,
; src = NULL; dsa; dest = &dsa->next, dsa = dsa->next) {
; src = &dsa->next;
; if (target_id == dsa->id && target_lun == dsa->lun) {
; *dest = *src;
; break;
; }
; }
;
; if (!dsa)
; error (int_err_unexpected_reselect);
; else
; longjmp (dsa->jump_resume, 0);
;
;
#if (CHIP != 700) && (CHIP != 70066)
; Define DSA structure used for mailboxes
ENTRY dsa_code_template
dsa_code_template:
ENTRY dsa_code_begin
dsa_code_begin:
MOVE dmode_memory_to_ncr TO DMODE
MOVE MEMORY 4, dsa_temp_addr_dsa_value, addr_scratch
MOVE dmode_memory_to_memory TO DMODE
CALL scratch_to_dsa
CALL select
; Handle the phase mismatch which may have resulted from the
; MOVE FROM dsa_msgout if we returned here. The CLEAR ATN
; may or may not be necessary, and we should update script_asm.pl
; to handle multiple pieces.
CLEAR ATN
CLEAR ACK
; Replace second operand with address of JUMP instruction dest operand
; in schedule table for this DSA. Becomes dsa_jump_dest in 53c7,8xx.c.
ENTRY dsa_code_fix_jump
dsa_code_fix_jump:
MOVE MEMORY 4, NOP_insn, 0
JUMP select_done
; wrong_dsa loads the DSA register with the value of the dsa_next
; field.
;
wrong_dsa:
; Patch the MOVE MEMORY INSTRUCTION such that
; the destination address is the address of the OLD
; next pointer.
;
MOVE MEMORY 4, dsa_temp_addr_next, reselected_ok + 8
MOVE dmode_memory_to_ncr TO DMODE
;
; Move the _contents_ of the next pointer into the DSA register as
; the next I_T_L or I_T_L_Q tupple to check against the established
; nexus.
;
MOVE MEMORY 4, dsa_temp_next, addr_scratch
MOVE dmode_memory_to_memory TO DMODE
CALL scratch_to_dsa
JUMP reselected_check_next
ABSOLUTE dsa_save_data_pointer = 0
ENTRY dsa_code_save_data_pointer
dsa_code_save_data_pointer:
MOVE dmode_ncr_to_memory TO DMODE
MOVE MEMORY 4, addr_temp, dsa_temp_addr_saved_pointer
MOVE dmode_memory_to_memory TO DMODE
; HARD CODED : 24 bytes needs to agree with 53c7,8xx.h
MOVE MEMORY 24, dsa_temp_addr_residual, dsa_temp_addr_saved_residual
CLEAR ACK
#ifdef DEBUG
INT int_debug_saved
#endif
RETURN
ABSOLUTE dsa_restore_pointers = 0
ENTRY dsa_code_restore_pointers
dsa_code_restore_pointers:
MOVE dmode_memory_to_ncr TO DMODE
MOVE MEMORY 4, dsa_temp_addr_saved_pointer, addr_temp
MOVE dmode_memory_to_memory TO DMODE
; HARD CODED : 24 bytes needs to agree with 53c7,8xx.h
MOVE MEMORY 24, dsa_temp_addr_saved_residual, dsa_temp_addr_residual
CLEAR ACK
#ifdef DEBUG
INT int_debug_restored
#endif
RETURN
ABSOLUTE dsa_check_reselect = 0
; dsa_check_reselect determines whether or not the current target and
; lun match the current DSA
ENTRY dsa_code_check_reselect
dsa_code_check_reselect:
MOVE SSID TO SFBR ; SSID contains 3 bit target ID
; FIXME : we need to accommodate bit fielded and binary here for '7xx/'8xx chips
JUMP REL (wrong_dsa), IF NOT dsa_temp_target, AND MASK 0xf8
;
; Hack - move to scratch first, since SFBR is not writeable
; via the CPU and hence a MOVE MEMORY instruction.
;
MOVE dmode_memory_to_ncr TO DMODE
MOVE MEMORY 1, reselected_identify, addr_scratch
MOVE dmode_memory_to_memory TO DMODE
MOVE SCRATCH0 TO SFBR
; FIXME : we need to accommodate bit fielded and binary here for '7xx/'8xx chips
JUMP REL (wrong_dsa), IF NOT dsa_temp_lun, AND MASK 0xf8
; Patch the MOVE MEMORY INSTRUCTION such that
; the source address is the address of this dsa's
; next pointer.
MOVE MEMORY 4, dsa_temp_addr_next, reselected_ok + 4
CALL reselected_ok
CALL dsa_temp_sync
; Release ACK on the IDENTIFY message _after_ we've set the synchronous
; transfer parameters!
CLEAR ACK
; Implicitly restore pointers on reselection, so a RETURN
; will transfer control back to the right spot.
CALL REL (dsa_code_restore_pointers)
RETURN
ENTRY dsa_zero
dsa_zero:
ENTRY dsa_code_template_end
dsa_code_template_end:
; Perform sanity check for dsa_fields_start == dsa_code_template_end -
; dsa_zero, puke.
ABSOLUTE dsa_fields_start = 0 ; Sanity marker
; pad 48 bytes (fix this RSN)
ABSOLUTE dsa_next = 48 ; len 4 Next DSA
; del 4 Previous DSA address
ABSOLUTE dsa_cmnd = 56 ; len 4 Scsi_Cmnd * for this thread.
ABSOLUTE dsa_select = 60 ; len 4 Device ID, Period, Offset for
; table indirect select
ABSOLUTE dsa_msgout = 64 ; len 8 table indirect move parameter for
; select message
ABSOLUTE dsa_cmdout = 72 ; len 8 table indirect move parameter for
; command
ABSOLUTE dsa_dataout = 80 ; len 4 code pointer for dataout
ABSOLUTE dsa_datain = 84 ; len 4 code pointer for datain
ABSOLUTE dsa_msgin = 88 ; len 8 table indirect move for msgin
ABSOLUTE dsa_status = 96 ; len 8 table indirect move for status byte
ABSOLUTE dsa_msgout_other = 104 ; len 8 table indirect for normal message out
; (Synchronous transfer negotiation, etc).
ABSOLUTE dsa_end = 112
ABSOLUTE schedule = 0 ; Array of JUMP dsa_begin or JUMP (next),
; terminated by a call to JUMP wait_reselect
; Linked lists of DSA structures
ABSOLUTE reconnect_dsa_head = 0 ; Link list of DSAs which can reconnect
ABSOLUTE addr_reconnect_dsa_head = 0 ; Address of variable containing
; address of reconnect_dsa_head
; These select the source and destination of a MOVE MEMORY instruction
ABSOLUTE dmode_memory_to_memory = 0x0
ABSOLUTE dmode_memory_to_ncr = 0x0
ABSOLUTE dmode_ncr_to_memory = 0x0
ABSOLUTE addr_scratch = 0x0
ABSOLUTE addr_temp = 0x0
#endif /* CHIP != 700 && CHIP != 70066 */
; Interrupts -
; MSB indicates type
; 0 handle error condition
; 1 handle message
; 2 handle normal condition
; 3 debugging interrupt
; 4 testing interrupt
; Next byte indicates specific error
; XXX not yet implemented, I'm not sure if I want to -
; Next byte indicates the routine the error occurred in
; The LSB indicates the specific place the error occurred
ABSOLUTE int_err_unexpected_phase = 0x00000000 ; Unexpected phase encountered
ABSOLUTE int_err_selected = 0x00010000 ; SELECTED (nee RESELECTED)
ABSOLUTE int_err_unexpected_reselect = 0x00020000
ABSOLUTE int_err_check_condition = 0x00030000
ABSOLUTE int_err_no_phase = 0x00040000
ABSOLUTE int_msg_wdtr = 0x01000000 ; WDTR message received
ABSOLUTE int_msg_sdtr = 0x01010000 ; SDTR received
ABSOLUTE int_msg_1 = 0x01020000 ; single byte special message
; received
ABSOLUTE int_norm_select_complete = 0x02000000 ; Select complete, reprogram
; registers.
ABSOLUTE int_norm_reselect_complete = 0x02010000 ; Nexus established
ABSOLUTE int_norm_command_complete = 0x02020000 ; Command complete
ABSOLUTE int_norm_disconnected = 0x02030000 ; Disconnected
ABSOLUTE int_norm_aborted =0x02040000 ; Aborted *dsa
ABSOLUTE int_norm_reset = 0x02050000 ; Generated BUS reset.
ABSOLUTE int_debug_break = 0x03000000 ; Break point
#ifdef DEBUG
ABSOLUTE int_debug_scheduled = 0x03010000 ; new I/O scheduled
ABSOLUTE int_debug_idle = 0x03020000 ; scheduler is idle
ABSOLUTE int_debug_dsa_loaded = 0x03030000 ; dsa reloaded
ABSOLUTE int_debug_reselected = 0x03040000 ; NCR reselected
ABSOLUTE int_debug_head = 0x03050000 ; issue head overwritten
ABSOLUTE int_debug_disconnected = 0x03060000 ; disconnected
ABSOLUTE int_debug_disconnect_msg = 0x03070000 ; got message to disconnect
ABSOLUTE int_debug_dsa_schedule = 0x03080000 ; in dsa_schedule
ABSOLUTE int_debug_reselect_check = 0x03090000 ; Check for reselection of DSA
ABSOLUTE int_debug_reselected_ok = 0x030a0000 ; Reselection accepted
#endif
ABSOLUTE int_debug_panic = 0x030b0000 ; Panic driver
#ifdef DEBUG
ABSOLUTE int_debug_saved = 0x030c0000 ; save/restore pointers
ABSOLUTE int_debug_restored = 0x030d0000
ABSOLUTE int_debug_sync = 0x030e0000 ; Sanity check synchronous
; parameters.
ABSOLUTE int_debug_datain = 0x030f0000 ; going into data in phase
; now.
ABSOLUTE int_debug_check_dsa = 0x03100000 ; Sanity check DSA against
; SDID.
#endif
ABSOLUTE int_test_1 = 0x04000000 ; Test 1 complete
ABSOLUTE int_test_2 = 0x04010000 ; Test 2 complete
ABSOLUTE int_test_3 = 0x04020000 ; Test 3 complete
; These should start with 0x05000000, with low bits incrementing for
; each one.
#ifdef EVENTS
ABSOLUTE int_EVENT_SELECT = 0
ABSOLUTE int_EVENT_DISCONNECT = 0
ABSOLUTE int_EVENT_RESELECT = 0
ABSOLUTE int_EVENT_COMPLETE = 0
ABSOLUTE int_EVENT_IDLE = 0
ABSOLUTE int_EVENT_SELECT_FAILED = 0
ABSOLUTE int_EVENT_BEFORE_SELECT = 0
ABSOLUTE int_EVENT_RESELECT_FAILED = 0
#endif
ABSOLUTE NCR53c7xx_msg_abort = 0 ; Pointer to abort message
ABSOLUTE NCR53c7xx_msg_reject = 0 ; Pointer to reject message
ABSOLUTE NCR53c7xx_zero = 0 ; long with zero in it, use for source
ABSOLUTE NCR53c7xx_sink = 0 ; long to dump worthless data in
ABSOLUTE NOP_insn = 0 ; NOP instruction
; Pointer to message, potentially multi-byte
ABSOLUTE msg_buf = 0
; Pointer to holding area for reselection information
ABSOLUTE reselected_identify = 0
ABSOLUTE reselected_tag = 0
; Request sense command pointer, it's a 6 byte command, should
; be constant for all commands since we always want 16 bytes of
; sense and we don't need to change any fields as we did under
; SCSI-I when we actually cared about the LUN field.
;EXTERNAL NCR53c7xx_sense ; Request sense command
#if (CHIP != 700) && (CHIP != 70066)
; dsa_schedule
; PURPOSE : after a DISCONNECT message has been received, and pointers
; saved, insert the current DSA structure at the head of the
; disconnected queue and fall through to the scheduler.
;
; CALLS : OK
;
; INPUTS : dsa - current DSA structure, reconnect_dsa_head - list
; of disconnected commands
;
; MODIFIES : SCRATCH, reconnect_dsa_head
;
; EXITS : always passes control to schedule
ENTRY dsa_schedule
dsa_schedule:
#if 0
INT int_debug_dsa_schedule
#endif
;
; Calculate the address of the next pointer within the DSA
; structure of the command that is currently disconnecting
;
CALL dsa_to_scratch
MOVE SCRATCH0 + dsa_next TO SCRATCH0
MOVE SCRATCH1 + 0 TO SCRATCH1 WITH CARRY
MOVE SCRATCH2 + 0 TO SCRATCH2 WITH CARRY
MOVE SCRATCH3 + 0 TO SCRATCH3 WITH CARRY
; Point the next field of this DSA structure at the current disconnected
; list
MOVE dmode_ncr_to_memory TO DMODE
MOVE MEMORY 4, addr_scratch, dsa_schedule_insert + 8
MOVE dmode_memory_to_memory TO DMODE
dsa_schedule_insert:
MOVE MEMORY 4, reconnect_dsa_head, 0
; And update the head pointer.
CALL dsa_to_scratch
MOVE dmode_ncr_to_memory TO DMODE
MOVE MEMORY 4, addr_scratch, reconnect_dsa_head
MOVE dmode_memory_to_memory TO DMODE
/* Temporarily, see what happens. */
#ifndef ORIGINAL
MOVE SCNTL2 & 0x7f TO SCNTL2
CLEAR ACK
#endif
WAIT DISCONNECT
#ifdef EVENTS
INT int_EVENT_DISCONNECT;
#endif
#if 0
INT int_debug_disconnected
#endif
JUMP schedule
#endif
;
; select
;
; PURPOSE : establish a nexus for the SCSI command referenced by DSA.
; On success, the current DSA structure is removed from the issue
; queue. Usually, this is entered as a fall-through from schedule,
; although the contingent allegiance handling code will write
; the select entry address to the DSP to restart a command as a
; REQUEST SENSE. A message is sent (usually IDENTIFY, although
; additional SDTR or WDTR messages may be sent). COMMAND OUT
; is handled.
;
; INPUTS : DSA - SCSI command, issue_dsa_head
;
; CALLS : NOT OK
;
; MODIFIES : SCRATCH, issue_dsa_head
;
; EXITS : on reselection or selection, go to select_failed
; otherwise, RETURN so control is passed back to
; dsa_begin.
;
ENTRY select
select:
#if 0
#ifdef EVENTS
INT int_EVENT_BEFORE_SELECT
#endif
#endif
#if 0
#ifdef DEBUG
INT int_debug_scheduled
#endif
#endif
CLEAR TARGET
; XXX
;
; In effect, SELECTION operations are backgrounded, with execution
; continuing until code which waits for REQ or a fatal interrupt is
; encountered.
;
; So, for more performance, we could overlap the code which removes
; the command from the NCRs issue queue with the selection, but
; at this point I don't want to deal with the error recovery.
;
#if (CHIP != 700) && (CHIP != 70066)
SELECT ATN FROM dsa_select, select_failed
JUMP select_msgout, WHEN MSG_OUT
ENTRY select_msgout
select_msgout:
MOVE FROM dsa_msgout, WHEN MSG_OUT
#else
ENTRY select_msgout
SELECT ATN 0, select_failed
select_msgout:
MOVE 0, 0, WHEN MSGOUT
#endif
#ifdef EVENTS
INT int_EVENT_SELECT
#endif
RETURN
;
; select_done
;
; PURPOSE: continue on to normal data transfer; called as the exit
; point from dsa_begin.
;
; INPUTS: dsa
;
; CALLS: OK
;
;
select_done:
#ifdef DEBUG
ENTRY select_check_dsa
select_check_dsa:
INT int_debug_check_dsa
#endif
; After a successful selection, we should get either a CMD phase or
; some transfer request negotiation message.
JUMP cmdout, WHEN CMD
INT int_err_unexpected_phase, WHEN NOT MSG_IN
select_msg_in:
CALL msg_in, WHEN MSG_IN
JUMP select_msg_in, WHEN MSG_IN
cmdout:
INT int_err_unexpected_phase, WHEN NOT CMD
#if (CHIP == 700)
INT int_norm_selected
#endif
ENTRY cmdout_cmdout
cmdout_cmdout:
#if (CHIP != 700) && (CHIP != 70066)
MOVE FROM dsa_cmdout, WHEN CMD
#else
MOVE 0, 0, WHEN CMD
#endif /* (CHIP != 700) && (CHIP != 70066) */
;
; data_transfer
; other_out
; other_in
; other_transfer
;
; PURPOSE : handle the main data transfer for a SCSI command in
; several parts. In the first part, data_transfer, DATA_IN
; and DATA_OUT phases are allowed, with the user provided
; code (usually dynamically generated based on the scatter/gather
; list associated with a SCSI command) called to handle these
; phases.
;
; After control has passed to one of the user provided
; DATA_IN or DATA_OUT routines, back calls are made to
; other_transfer_in or other_transfer_out to handle non-DATA IN
; and DATA OUT phases respectively, with the state of the active
; data pointer being preserved in TEMP.
;
; On completion, the user code passes control to other_transfer
; which causes DATA_IN and DATA_OUT to result in unexpected_phase
; interrupts so that data overruns may be trapped.
;
; INPUTS : DSA - SCSI command
;
; CALLS : OK in data_transfer_start, not ok in other_out and other_in, ok in
; other_transfer
;
; MODIFIES : SCRATCH
;
; EXITS : if STATUS IN is detected, signifying command completion,
; the NCR jumps to command_complete. If MSG IN occurs, a
; CALL is made to msg_in. Otherwise, other_transfer runs in
; an infinite loop.
;
ENTRY data_transfer
data_transfer:
JUMP cmdout_cmdout, WHEN CMD
CALL msg_in, WHEN MSG_IN
INT int_err_unexpected_phase, WHEN MSG_OUT
JUMP do_dataout, WHEN DATA_OUT
JUMP do_datain, WHEN DATA_IN
JUMP command_complete, WHEN STATUS
JUMP data_transfer
ENTRY end_data_transfer
end_data_transfer:
;
; FIXME: On NCR53c700 and NCR53c700-66 chips, do_dataout/do_datain
; should be fixed up whenever the nexus changes so it can point to the
; correct routine for that command.
;
#if (CHIP != 700) && (CHIP != 70066)
; Nasty jump to dsa->dataout
do_dataout:
CALL dsa_to_scratch
MOVE SCRATCH0 + dsa_dataout TO SCRATCH0
MOVE SCRATCH1 + 0 TO SCRATCH1 WITH CARRY
MOVE SCRATCH2 + 0 TO SCRATCH2 WITH CARRY
MOVE SCRATCH3 + 0 TO SCRATCH3 WITH CARRY
MOVE dmode_ncr_to_memory TO DMODE
MOVE MEMORY 4, addr_scratch, dataout_to_jump + 4
MOVE dmode_memory_to_memory TO DMODE
dataout_to_jump:
MOVE MEMORY 4, 0, dataout_jump + 4
dataout_jump:
JUMP 0
; Nasty jump to dsa->dsain
do_datain:
CALL dsa_to_scratch
MOVE SCRATCH0 + dsa_datain TO SCRATCH0
MOVE SCRATCH1 + 0 TO SCRATCH1 WITH CARRY
MOVE SCRATCH2 + 0 TO SCRATCH2 WITH CARRY
MOVE SCRATCH3 + 0 TO SCRATCH3 WITH CARRY
MOVE dmode_ncr_to_memory TO DMODE
MOVE MEMORY 4, addr_scratch, datain_to_jump + 4
MOVE dmode_memory_to_memory TO DMODE
ENTRY datain_to_jump
datain_to_jump:
MOVE MEMORY 4, 0, datain_jump + 4
#if 0
INT int_debug_datain
#endif
datain_jump:
JUMP 0
#endif /* (CHIP != 700) && (CHIP != 70066) */
; Note that other_out and other_in loop until a non-data phase
; is discovered, so we only execute return statements when we
; can go on to the next data phase block move statement.
ENTRY other_out
other_out:
#if 0
INT 0x03ffdead
#endif
INT int_err_unexpected_phase, WHEN CMD
JUMP msg_in_restart, WHEN MSG_IN
INT int_err_unexpected_phase, WHEN MSG_OUT
INT int_err_unexpected_phase, WHEN DATA_IN
JUMP command_complete, WHEN STATUS
JUMP other_out, WHEN NOT DATA_OUT
RETURN
ENTRY other_in
other_in:
#if 0
INT 0x03ffdead
#endif
INT int_err_unexpected_phase, WHEN CMD
JUMP msg_in_restart, WHEN MSG_IN
INT int_err_unexpected_phase, WHEN MSG_OUT
INT int_err_unexpected_phase, WHEN DATA_OUT
JUMP command_complete, WHEN STATUS
JUMP other_in, WHEN NOT DATA_IN
RETURN
ENTRY other_transfer
other_transfer:
INT int_err_unexpected_phase, WHEN CMD
CALL msg_in, WHEN MSG_IN
INT int_err_unexpected_phase, WHEN MSG_OUT
INT int_err_unexpected_phase, WHEN DATA_OUT
INT int_err_unexpected_phase, WHEN DATA_IN
JUMP command_complete, WHEN STATUS
JUMP other_transfer
;
; msg_in_restart
; msg_in
; munge_msg
;
; PURPOSE : process messages from a target. msg_in is called when the
; caller hasn't read the first byte of the message. munge_message
; is called when the caller has read the first byte of the message,
; and left it in SFBR. msg_in_restart is called when the caller
; hasn't read the first byte of the message, and wishes RETURN
; to transfer control back to the address of the conditional
; CALL instruction rather than to the instruction after it.
;
; Various int_* interrupts are generated when the host system
; needs to intervene, as is the case with SDTR, WDTR, and
; INITIATE RECOVERY messages.
;
; When the host system handles one of these interrupts,
; it can respond by reentering at reject_message,
; which rejects the message and returns control to
; the caller of msg_in or munge_msg, accept_message
; which clears ACK and returns control, or reply_message
; which sends the message pointed to by the DSA
; msgout_other table indirect field.
;
; DISCONNECT messages are handled by moving the command
; to the reconnect_dsa_queue.
;
; INPUTS : DSA - SCSI COMMAND, SFBR - first byte of message (munge_msg
; only)
;
; CALLS : NO. The TEMP register isn't backed up to allow nested calls.
;
; MODIFIES : SCRATCH, DSA on DISCONNECT
;
; EXITS : On receipt of SAVE DATA POINTER, RESTORE POINTERS,
; and normal return from message handlers running under
; Linux, control is returned to the caller. Receipt
; of DISCONNECT messages pass control to dsa_schedule.
;
ENTRY msg_in_restart
msg_in_restart:
; XXX - hackish
;
; Since it's easier to debug changes to the statically
; compiled code, rather than the dynamically generated
; stuff, such as
;
; MOVE x, y, WHEN data_phase
; CALL other_z, WHEN NOT data_phase
; MOVE x, y, WHEN data_phase
;
; I'd like to have certain routines (notably the message handler)
; restart on the conditional call rather than the next instruction.
;
; So, subtract 8 from the return address
MOVE TEMP0 + 0xf8 TO TEMP0
MOVE TEMP1 + 0xff TO TEMP1 WITH CARRY
MOVE TEMP2 + 0xff TO TEMP2 WITH CARRY
MOVE TEMP3 + 0xff TO TEMP3 WITH CARRY
ENTRY msg_in
msg_in:
MOVE 1, msg_buf, WHEN MSG_IN
munge_msg:
JUMP munge_extended, IF 0x01 ; EXTENDED MESSAGE
JUMP munge_2, IF 0x20, AND MASK 0xdf ; two byte message
;
; XXX - I've seen a handful of broken SCSI devices which fail to issue
; a SAVE POINTERS message before disconnecting in the middle of
; a transfer, assuming that the DATA POINTER will be implicitly
; restored.
;
; Historically, I've often done an implicit save when the DISCONNECT
; message is processed. We may want to consider having the option of
; doing that here.
;
JUMP munge_save_data_pointer, IF 0x02 ; SAVE DATA POINTER
JUMP munge_restore_pointers, IF 0x03 ; RESTORE POINTERS
JUMP munge_disconnect, IF 0x04 ; DISCONNECT
INT int_msg_1, IF 0x07 ; MESSAGE REJECT
INT int_msg_1, IF 0x0f ; INITIATE RECOVERY
#ifdef EVENTS
INT int_EVENT_SELECT_FAILED
#endif
JUMP reject_message
munge_2:
JUMP reject_message
;
; The SCSI standard allows targets to recover from transient
; error conditions by backing up the data pointer with a
; RESTORE POINTERS message.
;
; So, we must save and restore the _residual_ code as well as
; the current instruction pointer. Because of this messiness,
; it is simpler to put dynamic code in the dsa for this and to
; just do a simple jump down there.
;
munge_save_data_pointer:
MOVE DSA0 + dsa_save_data_pointer TO SFBR
MOVE SFBR TO SCRATCH0
MOVE DSA1 + 0xff TO SFBR WITH CARRY
MOVE SFBR TO SCRATCH1
MOVE DSA2 + 0xff TO SFBR WITH CARRY
MOVE SFBR TO SCRATCH2
MOVE DSA3 + 0xff TO SFBR WITH CARRY
MOVE SFBR TO SCRATCH3
MOVE dmode_ncr_to_memory TO DMODE
MOVE MEMORY 4, addr_scratch, jump_dsa_save + 4
MOVE dmode_memory_to_memory TO DMODE
jump_dsa_save:
JUMP 0
munge_restore_pointers:
MOVE DSA0 + dsa_restore_pointers TO SFBR
MOVE SFBR TO SCRATCH0
MOVE DSA1 + 0xff TO SFBR WITH CARRY
MOVE SFBR TO SCRATCH1
MOVE DSA2 + 0xff TO SFBR WITH CARRY
MOVE SFBR TO SCRATCH2
MOVE DSA3 + 0xff TO SFBR WITH CARRY
MOVE SFBR TO SCRATCH3
MOVE dmode_ncr_to_memory TO DMODE
MOVE MEMORY 4, addr_scratch, jump_dsa_restore + 4
MOVE dmode_memory_to_memory TO DMODE
jump_dsa_restore:
JUMP 0
munge_disconnect:
#if 0
INT int_debug_disconnect_msg
#endif
/*
* Before, we overlapped processing with waiting for disconnect, but
* debugging was beginning to appear messy. Temporarily move things
* to just before the WAIT DISCONNECT.
*/
#ifdef ORIGINAL
MOVE SCNTL2 & 0x7f TO SCNTL2
CLEAR ACK
#endif
#if (CHIP != 700) && (CHIP != 70066)
JUMP dsa_schedule
#else
WAIT DISCONNECT
INT int_norm_disconnected
#endif
munge_extended:
CLEAR ACK
INT int_err_unexpected_phase, WHEN NOT MSG_IN
MOVE 1, msg_buf + 1, WHEN MSG_IN
JUMP munge_extended_2, IF 0x02
JUMP munge_extended_3, IF 0x03
JUMP reject_message
munge_extended_2:
CLEAR ACK
MOVE 1, msg_buf + 2, WHEN MSG_IN
JUMP reject_message, IF NOT 0x02 ; Must be WDTR
CLEAR ACK
MOVE 1, msg_buf + 3, WHEN MSG_IN
INT int_msg_wdtr
munge_extended_3:
CLEAR ACK
MOVE 1, msg_buf + 2, WHEN MSG_IN
JUMP reject_message, IF NOT 0x01 ; Must be SDTR
CLEAR ACK
MOVE 2, msg_buf + 3, WHEN MSG_IN
INT int_msg_sdtr
ENTRY reject_message
reject_message:
SET ATN
CLEAR ACK
MOVE 1, NCR53c7xx_msg_reject, WHEN MSG_OUT
RETURN
ENTRY accept_message
accept_message:
CLEAR ATN
CLEAR ACK
RETURN
ENTRY respond_message
respond_message:
SET ATN
CLEAR ACK
MOVE FROM dsa_msgout_other, WHEN MSG_OUT
RETURN
;
; command_complete
;
; PURPOSE : handle command termination when STATUS IN is detected by reading
; a status byte followed by a command termination message.
;
; Normal termination results in an INTFLY instruction, and
; the host system can pick out which command terminated by
; examining the MESSAGE and STATUS buffers of all currently
; executing commands;
;
; Abnormal (CHECK_CONDITION) termination results in an
; int_err_check_condition interrupt so that a REQUEST SENSE
; command can be issued out-of-order so that no other command
; clears the contingent allegiance condition.
;
;
; INPUTS : DSA - command
;
; CALLS : OK
;
; EXITS : On successful termination, control is passed to schedule.
; On abnormal termination, the user will usually modify the
; DSA fields and corresponding buffers and return control
; to select.
;
ENTRY command_complete
command_complete:
MOVE FROM dsa_status, WHEN STATUS
#if (CHIP != 700) && (CHIP != 70066)
MOVE SFBR TO SCRATCH0 ; Save status
#endif /* (CHIP != 700) && (CHIP != 70066) */
ENTRY command_complete_msgin
command_complete_msgin:
MOVE FROM dsa_msgin, WHEN MSG_IN
; Indicate that we should be expecting a disconnect
MOVE SCNTL2 & 0x7f TO SCNTL2
CLEAR ACK
#if (CHIP != 700) && (CHIP != 70066)
WAIT DISCONNECT
;
; The SCSI specification states that when a UNIT ATTENTION condition
; is pending, as indicated by a CHECK CONDITION status message,
; the target shall revert to asynchronous transfers. Since
; synchronous transfers parameters are maintained on a per INITIATOR/TARGET
; basis, and returning control to our scheduler could work on a command
; running on another lun on that target using the old parameters, we must
; interrupt the host processor to get them changed, or change them ourselves.
;
; Once SCSI-II tagged queueing is implemented, things will be even more
; hairy, since contingent allegiance conditions exist on a per-target/lun
; basis, and issuing a new command with a different tag would clear it.
; In these cases, we must interrupt the host processor to get a request
; added to the HEAD of the queue with the request sense command, or we
; must automatically issue the request sense command.
#if 0
MOVE SCRATCH0 TO SFBR
JUMP command_failed, IF 0x02
#endif
INTFLY
#endif /* (CHIP != 700) && (CHIP != 70066) */
#ifdef EVENTS
INT int_EVENT_COMPLETE
#endif
#if (CHIP != 700) && (CHIP != 70066)
JUMP schedule
command_failed:
INT int_err_check_condition
#else
INT int_norm_command_complete
#endif
;
; wait_reselect
;
; PURPOSE : This is essentially the idle routine, where control lands
; when there are no new processes to schedule. wait_reselect
; waits for reselection, selection, and new commands.
;
; When a successful reselection occurs, with the aid
; of fixed up code in each DSA, wait_reselect walks the
; reconnect_dsa_queue, asking each dsa if the target ID
; and LUN match its.
;
; If a match is found, a call is made back to reselected_ok,
; which through the miracles of self modifying code, extracts
; the found DSA from the reconnect_dsa_queue and then
; returns control to the DSAs thread of execution.
;
; INPUTS : NONE
;
; CALLS : OK
;
; MODIFIES : DSA,
;
; EXITS : On successful reselection, control is returned to the
; DSA which called reselected_ok. If the WAIT RESELECT
; was interrupted by a new commands arrival signaled by
; SIG_P, control is passed to schedule. If the NCR is
; selected, the host system is interrupted with an
; int_err_selected which is usually responded to by
; setting DSP to the target_abort address.
ENTRY wait_reselect
wait_reselect:
#ifdef EVENTS
int int_EVENT_IDLE
#endif
#if 0
int int_debug_idle
#endif
WAIT RESELECT wait_reselect_failed
reselected:
#ifdef EVENTS
int int_EVENT_RESELECT
#endif
CLEAR TARGET
MOVE dmode_memory_to_memory TO DMODE
; Read all data needed to reestablish the nexus -
MOVE 1, reselected_identify, WHEN MSG_IN
; We used to CLEAR ACK here.
#if (CHIP != 700) && (CHIP != 70066)
#if 0
int int_debug_reselected
#endif
; Point DSA at the current head of the disconnected queue.
MOVE dmode_memory_to_ncr TO DMODE
MOVE MEMORY 4, reconnect_dsa_head, addr_scratch
MOVE dmode_memory_to_memory TO DMODE
CALL scratch_to_dsa
; Fix the update-next pointer so that the reconnect_dsa_head
; pointer is the one that will be updated if this DSA is a hit
; and we remove it from the queue.
MOVE MEMORY 4, addr_reconnect_dsa_head, reselected_ok + 8
ENTRY reselected_check_next
reselected_check_next:
#if 0
INT int_debug_reselect_check
#endif
; Check for a NULL pointer.
MOVE DSA0 TO SFBR
JUMP reselected_not_end, IF NOT 0
MOVE DSA1 TO SFBR
JUMP reselected_not_end, IF NOT 0
MOVE DSA2 TO SFBR
JUMP reselected_not_end, IF NOT 0
MOVE DSA3 TO SFBR
JUMP reselected_not_end, IF NOT 0
INT int_err_unexpected_reselect
reselected_not_end:
;
; XXX the ALU is only eight bits wide, and the assembler
; wont do the dirt work for us. As long as dsa_check_reselect
; is negative, we need to sign extend with 1 bits to the full
; 32 bit width of the address.
;
; A potential work around would be to have a known alignment
; of the DSA structure such that the base address plus
; dsa_check_reselect doesn't require carrying from bytes
; higher than the LSB.
;
MOVE DSA0 TO SFBR
MOVE SFBR + dsa_check_reselect TO SCRATCH0
MOVE DSA1 TO SFBR
MOVE SFBR + 0xff TO SCRATCH1 WITH CARRY
MOVE DSA2 TO SFBR
MOVE SFBR + 0xff TO SCRATCH2 WITH CARRY
MOVE DSA3 TO SFBR
MOVE SFBR + 0xff TO SCRATCH3 WITH CARRY
MOVE dmode_ncr_to_memory TO DMODE
MOVE MEMORY 4, addr_scratch, reselected_check + 4
MOVE dmode_memory_to_memory TO DMODE
reselected_check:
JUMP 0
;
;
ENTRY reselected_ok
reselected_ok:
MOVE MEMORY 4, 0, 0 ; Patched : first word
; is address of
; successful dsa_next
; Second word is last
; unsuccessful dsa_next,
; starting with
; dsa_reconnect_head
; We used to CLEAR ACK here.
#if 0
INT int_debug_reselected_ok
#endif
#ifdef DEBUG
INT int_debug_check_dsa
#endif
RETURN ; Return control to where
#else
INT int_norm_reselected
#endif /* (CHIP != 700) && (CHIP != 70066) */
selected:
INT int_err_selected;
;
; A select or reselect failure can be caused by one of two conditions :
; 1. SIG_P was set. This will be the case if the user has written
; a new value to a previously NULL head of the issue queue.
;
; 2. The NCR53c810 was selected or reselected by another device.
;
; 3. The bus was already busy since we were selected or reselected
; before starting the command.
wait_reselect_failed:
#ifdef EVENTS
INT int_EVENT_RESELECT_FAILED
#endif
; Check selected bit.
MOVE SIST0 & 0x20 TO SFBR
JUMP selected, IF 0x20
; Reading CTEST2 clears the SIG_P bit in the ISTAT register.
MOVE CTEST2 & 0x40 TO SFBR
JUMP schedule, IF 0x40
; Check connected bit.
; FIXME: this needs to change if we support target mode
MOVE ISTAT & 0x08 TO SFBR
JUMP reselected, IF 0x08
; FIXME : Something bogus happened, and we shouldn't fail silently.
#if 0
JUMP schedule
#else
INT int_debug_panic
#endif
select_failed:
#ifdef EVENTS
int int_EVENT_SELECT_FAILED
#endif
; Otherwise, mask the selected and reselected bits off SIST0
MOVE SIST0 & 0x30 TO SFBR
JUMP selected, IF 0x20
JUMP reselected, IF 0x10
; If SIGP is set, the user just gave us another command, and
; we should restart or return to the scheduler.
; Reading CTEST2 clears the SIG_P bit in the ISTAT register.
MOVE CTEST2 & 0x40 TO SFBR
JUMP select, IF 0x40
; Check connected bit.
; FIXME: this needs to change if we support target mode
; FIXME: is this really necessary?
MOVE ISTAT & 0x08 TO SFBR
JUMP reselected, IF 0x08
; FIXME : Something bogus happened, and we shouldn't fail silently.
#if 0
JUMP schedule
#else
INT int_debug_panic
#endif
;
; test_1
; test_2
;
; PURPOSE : run some verification tests on the NCR. test_1
; copies test_src to test_dest and interrupts the host
; processor, testing for cache coherency and interrupt
; problems in the processes.
;
; test_2 runs a command with offsets relative to the
; DSA on entry, and is useful for miscellaneous experimentation.
;
; Verify that interrupts are working correctly and that we don't
; have a cache invalidation problem.
ABSOLUTE test_src = 0, test_dest = 0
ENTRY test_1
test_1:
MOVE MEMORY 4, test_src, test_dest
INT int_test_1
;
; Run arbitrary commands, with test code establishing a DSA
;
ENTRY test_2
test_2:
CLEAR TARGET
SELECT ATN FROM 0, test_2_fail
JUMP test_2_msgout, WHEN MSG_OUT
ENTRY test_2_msgout
test_2_msgout:
MOVE FROM 8, WHEN MSG_OUT
MOVE FROM 16, WHEN CMD
MOVE FROM 24, WHEN DATA_IN
MOVE FROM 32, WHEN STATUS
MOVE FROM 40, WHEN MSG_IN
MOVE SCNTL2 & 0x7f TO SCNTL2
CLEAR ACK
WAIT DISCONNECT
test_2_fail:
INT int_test_2
ENTRY debug_break
debug_break:
INT int_debug_break
;
; initiator_abort
; target_abort
;
; PURPOSE : Abort the currently established nexus from with initiator
; or target mode.
;
;
ENTRY target_abort
target_abort:
SET TARGET
DISCONNECT
CLEAR TARGET
JUMP schedule
ENTRY initiator_abort
initiator_abort:
SET ATN
;
; The SCSI-I specification says that targets may go into MSG out at
; their leisure upon receipt of the ATN single. On all versions of the
; specification, we can't change phases until REQ transitions true->false,
; so we need to sink/source one byte of data to allow the transition.
;
; For the sake of safety, we'll only source one byte of data in all
; cases, but to accommodate the SCSI-I dain bramage, we'll sink an
; arbitrary number of bytes.
JUMP spew_cmd, WHEN CMD
JUMP eat_msgin, WHEN MSG_IN
JUMP eat_datain, WHEN DATA_IN
JUMP eat_status, WHEN STATUS
JUMP spew_dataout, WHEN DATA_OUT
JUMP sated
spew_cmd:
MOVE 1, NCR53c7xx_zero, WHEN CMD
JUMP sated
eat_msgin:
MOVE 1, NCR53c7xx_sink, WHEN MSG_IN
JUMP eat_msgin, WHEN MSG_IN
JUMP sated
eat_status:
MOVE 1, NCR53c7xx_sink, WHEN STATUS
JUMP eat_status, WHEN STATUS
JUMP sated
eat_datain:
MOVE 1, NCR53c7xx_sink, WHEN DATA_IN
JUMP eat_datain, WHEN DATA_IN
JUMP sated
spew_dataout:
MOVE 1, NCR53c7xx_zero, WHEN DATA_OUT
sated:
MOVE SCNTL2 & 0x7f TO SCNTL2
MOVE 1, NCR53c7xx_msg_abort, WHEN MSG_OUT
WAIT DISCONNECT
INT int_norm_aborted
;
; dsa_to_scratch
; scratch_to_dsa
;
; PURPOSE :
; The NCR chips cannot do a move memory instruction with the DSA register
; as the source or destination. So, we provide a couple of subroutines
; that let us switch between the DSA register and scratch register.
;
; Memory moves to/from the DSPS register also don't work, but we
; don't use them.
;
;
dsa_to_scratch:
MOVE DSA0 TO SFBR
MOVE SFBR TO SCRATCH0
MOVE DSA1 TO SFBR
MOVE SFBR TO SCRATCH1
MOVE DSA2 TO SFBR
MOVE SFBR TO SCRATCH2
MOVE DSA3 TO SFBR
MOVE SFBR TO SCRATCH3
RETURN
scratch_to_dsa:
MOVE SCRATCH0 TO SFBR
MOVE SFBR TO DSA0
MOVE SCRATCH1 TO SFBR
MOVE SFBR TO DSA1
MOVE SCRATCH2 TO SFBR
MOVE SFBR TO DSA2
MOVE SCRATCH3 TO SFBR
MOVE SFBR TO DSA3
RETURN
drivers/scsi/53c8xx_d.h_shipped deleted 100644 → 0
View file @ 53e20c84
/* DO NOT EDIT - Generated automatically by script_asm.pl */
static u32 SCRIPT[] = {
/*
; NCR 53c810 driver, main script
; Sponsored by
; iX Multiuser Multitasking Magazine
; hm@ix.de
;
; Copyright 1993, 1994, 1995 Drew Eckhardt
; Visionary Computing
; (Unix and Linux consulting and custom programming)
; drew@PoohSticks.ORG
; +1 (303) 786-7975
;
; TolerANT and SCSI SCRIPTS are registered trademarks of NCR Corporation.
;
; PRE-ALPHA
;
; For more information, please consult
;
; NCR 53C810
; PCI-SCSI I/O Processor
; Data Manual
;
; NCR 53C710
; SCSI I/O Processor
; Programmers Guide
;
; NCR Microelectronics
; 1635 Aeroplaza Drive
; Colorado Springs, CO 80916
; 1+ (719) 578-3400
;
; Toll free literature number
; +1 (800) 334-5454
;
; IMPORTANT : This code is self modifying due to the limitations of
; the NCR53c7,8xx series chips. Persons debugging this code with
; the remote debugger should take this into account, and NOT set
; breakpoints in modified instructions.
;
; Design:
; The NCR53c7,8xx family of SCSI chips are busmasters with an onboard
; microcontroller using a simple instruction set.
;
; So, to minimize the effects of interrupt latency, and to maximize
; throughput, this driver offloads the practical maximum amount
; of processing to the SCSI chip while still maintaining a common
; structure.
;
; Where tradeoffs were needed between efficiency on the older
; chips and the newer NCR53c800 series, the NCR53c800 series
; was chosen.
;
; While the NCR53c700 and NCR53c700-66 lacked the facilities to fully
; automate SCSI transfers without host processor intervention, this
; isn't the case with the NCR53c710 and newer chips which allow
;
; - reads and writes to the internal registers from within the SCSI
; scripts, allowing the SCSI SCRIPTS(tm) code to save processor
; state so that multiple threads of execution are possible, and also
; provide an ALU for loop control, etc.
;
; - table indirect addressing for some instructions. This allows
; pointers to be located relative to the DSA ((Data Structure
; Address) register.
;
; These features make it possible to implement a mailbox style interface,
; where the same piece of code is run to handle I/O for multiple threads
; at once minimizing our need to relocate code. Since the NCR53c700/
; NCR53c800 series have a unique combination of features, making a
; a standard ingoing/outgoing mailbox system, costly, I've modified it.
;
; - Mailboxes are a mixture of code and data. This lets us greatly
; simplify the NCR53c810 code and do things that would otherwise
; not be possible.
;
; The saved data pointer is now implemented as follows :
;
; Control flow has been architected such that if control reaches
; munge_save_data_pointer, on a restore pointers message or
; reconnection, a jump to the address formerly in the TEMP register
; will allow the SCSI command to resume execution.
;
;
; Note : the DSA structures must be aligned on 32 bit boundaries,
; since the source and destination of MOVE MEMORY instructions
; must share the same alignment and this is the alignment of the
; NCR registers.
;
ABSOLUTE dsa_temp_lun = 0 ; Patch to lun for current dsa
ABSOLUTE dsa_temp_next = 0 ; Patch to dsa next for current dsa
ABSOLUTE dsa_temp_addr_next = 0 ; Patch to address of dsa next address
; for current dsa
ABSOLUTE dsa_temp_sync = 0 ; Patch to address of per-target
; sync routine
ABSOLUTE dsa_temp_target = 0 ; Patch to id for current dsa
ABSOLUTE dsa_temp_addr_saved_pointer = 0; Patch to address of per-command
; saved data pointer
ABSOLUTE dsa_temp_addr_residual = 0 ; Patch to address of per-command
; current residual code
ABSOLUTE dsa_temp_addr_saved_residual = 0; Patch to address of per-command
; saved residual code
ABSOLUTE dsa_temp_addr_new_value = 0 ; Address of value for JUMP operand
ABSOLUTE dsa_temp_addr_array_value = 0 ; Address to copy to
ABSOLUTE dsa_temp_addr_dsa_value = 0 ; Address of this DSA value
;
; Once a device has initiated reselection, we need to compare it
; against the singly linked list of commands which have disconnected
; and are pending reselection. These commands are maintained in
; an unordered singly linked list of DSA structures, through the
; DSA pointers at their 'centers' headed by the reconnect_dsa_head
; pointer.
;
; To avoid complications in removing commands from the list,
; I minimize the amount of expensive (at eight operations per
; addition @ 500-600ns each) pointer operations which must
; be done in the NCR driver by precomputing them on the
; host processor during dsa structure generation.
;
; The fixed-up per DSA code knows how to recognize the nexus
; associated with the corresponding SCSI command, and modifies
; the source and destination pointers for the MOVE MEMORY
; instruction which is executed when reselected_ok is called
; to remove the command from the list. Similarly, DSA is
; loaded with the address of the next DSA structure and
; reselected_check_next is called if a failure occurs.
;
; Perhaps more concisely, the net effect of the mess is
;
; for (dsa = reconnect_dsa_head, dest = &reconnect_dsa_head,
; src = NULL; dsa; dest = &dsa->next, dsa = dsa->next) {
; src = &dsa->next;
; if (target_id == dsa->id && target_lun == dsa->lun) {
; *dest = *src;
; break;
; }
; }
;
; if (!dsa)
; error (int_err_unexpected_reselect);
; else
; longjmp (dsa->jump_resume, 0);
;
;
; Define DSA structure used for mailboxes
ENTRY dsa_code_template
dsa_code_template:
ENTRY dsa_code_begin
dsa_code_begin:
MOVE dmode_memory_to_ncr TO DMODE
at 0x00000000 : */ 0x78380000,0x00000000,
/*
MOVE MEMORY 4, dsa_temp_addr_dsa_value, addr_scratch
at 0x00000002 : */ 0xc0000004,0x00000000,0x00000000,
/*
MOVE dmode_memory_to_memory TO DMODE
at 0x00000005 : */ 0x78380000,0x00000000,
/*
CALL scratch_to_dsa
at 0x00000007 : */ 0x88080000,0x00000980,
/*
CALL select
at 0x00000009 : */ 0x88080000,0x000001fc,
/*
; Handle the phase mismatch which may have resulted from the
; MOVE FROM dsa_msgout if we returned here. The CLEAR ATN
; may or may not be necessary, and we should update script_asm.pl
; to handle multiple pieces.
CLEAR ATN
at 0x0000000b : */ 0x60000008,0x00000000,
/*
CLEAR ACK
at 0x0000000d : */ 0x60000040,0x00000000,
/*
; Replace second operand with address of JUMP instruction dest operand
; in schedule table for this DSA. Becomes dsa_jump_dest in 53c7,8xx.c.
ENTRY dsa_code_fix_jump
dsa_code_fix_jump:
MOVE MEMORY 4, NOP_insn, 0
at 0x0000000f : */ 0xc0000004,0x00000000,0x00000000,
/*
JUMP select_done
at 0x00000012 : */ 0x80080000,0x00000224,
/*
; wrong_dsa loads the DSA register with the value of the dsa_next
; field.
;
wrong_dsa:
; Patch the MOVE MEMORY INSTRUCTION such that
; the destination address is the address of the OLD
; next pointer.
;
MOVE MEMORY 4, dsa_temp_addr_next, reselected_ok + 8
at 0x00000014 : */ 0xc0000004,0x00000000,0x00000758,
/*
MOVE dmode_memory_to_ncr TO DMODE
at 0x00000017 : */ 0x78380000,0x00000000,
/*
;
; Move the _contents_ of the next pointer into the DSA register as
; the next I_T_L or I_T_L_Q tupple to check against the established
; nexus.
;
MOVE MEMORY 4, dsa_temp_next, addr_scratch
at 0x00000019 : */ 0xc0000004,0x00000000,0x00000000,
/*
MOVE dmode_memory_to_memory TO DMODE
at 0x0000001c : */ 0x78380000,0x00000000,
/*
CALL scratch_to_dsa
at 0x0000001e : */ 0x88080000,0x00000980,
/*
JUMP reselected_check_next
at 0x00000020 : */ 0x80080000,0x000006a4,
/*
ABSOLUTE dsa_save_data_pointer = 0
ENTRY dsa_code_save_data_pointer
dsa_code_save_data_pointer:
MOVE dmode_ncr_to_memory TO DMODE
at 0x00000022 : */ 0x78380000,0x00000000,
/*
MOVE MEMORY 4, addr_temp, dsa_temp_addr_saved_pointer
at 0x00000024 : */ 0xc0000004,0x00000000,0x00000000,
/*
MOVE dmode_memory_to_memory TO DMODE
at 0x00000027 : */ 0x78380000,0x00000000,
/*
; HARD CODED : 24 bytes needs to agree with 53c7,8xx.h
MOVE MEMORY 24, dsa_temp_addr_residual, dsa_temp_addr_saved_residual
at 0x00000029 : */ 0xc0000018,0x00000000,0x00000000,
/*
CLEAR ACK
at 0x0000002c : */ 0x60000040,0x00000000,
/*
RETURN
at 0x0000002e : */ 0x90080000,0x00000000,
/*
ABSOLUTE dsa_restore_pointers = 0
ENTRY dsa_code_restore_pointers
dsa_code_restore_pointers:
MOVE dmode_memory_to_ncr TO DMODE
at 0x00000030 : */ 0x78380000,0x00000000,
/*
MOVE MEMORY 4, dsa_temp_addr_saved_pointer, addr_temp
at 0x00000032 : */ 0xc0000004,0x00000000,0x00000000,
/*
MOVE dmode_memory_to_memory TO DMODE
at 0x00000035 : */ 0x78380000,0x00000000,
/*
; HARD CODED : 24 bytes needs to agree with 53c7,8xx.h
MOVE MEMORY 24, dsa_temp_addr_saved_residual, dsa_temp_addr_residual
at 0x00000037 : */ 0xc0000018,0x00000000,0x00000000,
/*
CLEAR ACK
at 0x0000003a : */ 0x60000040,0x00000000,
/*
RETURN
at 0x0000003c : */ 0x90080000,0x00000000,
/*
ABSOLUTE dsa_check_reselect = 0
; dsa_check_reselect determines whether or not the current target and
; lun match the current DSA
ENTRY dsa_code_check_reselect
dsa_code_check_reselect:
MOVE SSID TO SFBR ; SSID contains 3 bit target ID
at 0x0000003e : */ 0x720a0000,0x00000000,
/*
; FIXME : we need to accommodate bit fielded and binary here for '7xx/'8xx chips
JUMP REL (wrong_dsa), IF NOT dsa_temp_target, AND MASK 0xf8
at 0x00000040 : */ 0x8084f800,0x00ffff48,
/*
;
; Hack - move to scratch first, since SFBR is not writeable
; via the CPU and hence a MOVE MEMORY instruction.
;
MOVE dmode_memory_to_ncr TO DMODE
at 0x00000042 : */ 0x78380000,0x00000000,
/*
MOVE MEMORY 1, reselected_identify, addr_scratch
at 0x00000044 : */ 0xc0000001,0x00000000,0x00000000,
/*
MOVE dmode_memory_to_memory TO DMODE
at 0x00000047 : */ 0x78380000,0x00000000,
/*
MOVE SCRATCH0 TO SFBR
at 0x00000049 : */ 0x72340000,0x00000000,
/*
; FIXME : we need to accommodate bit fielded and binary here for '7xx/'8xx chips
JUMP REL (wrong_dsa), IF NOT dsa_temp_lun, AND MASK 0xf8
at 0x0000004b : */ 0x8084f800,0x00ffff1c,
/*
; Patch the MOVE MEMORY INSTRUCTION such that
; the source address is the address of this dsa's
; next pointer.
MOVE MEMORY 4, dsa_temp_addr_next, reselected_ok + 4
at 0x0000004d : */ 0xc0000004,0x00000000,0x00000754,
/*
CALL reselected_ok
at 0x00000050 : */ 0x88080000,0x00000750,
/*
CALL dsa_temp_sync
at 0x00000052 : */ 0x88080000,0x00000000,
/*
; Release ACK on the IDENTIFY message _after_ we've set the synchronous
; transfer parameters!
CLEAR ACK
at 0x00000054 : */ 0x60000040,0x00000000,
/*
; Implicitly restore pointers on reselection, so a RETURN
; will transfer control back to the right spot.
CALL REL (dsa_code_restore_pointers)
at 0x00000056 : */ 0x88880000,0x00ffff60,
/*
RETURN
at 0x00000058 : */ 0x90080000,0x00000000,
/*
ENTRY dsa_zero
dsa_zero:
ENTRY dsa_code_template_end
dsa_code_template_end:
; Perform sanity check for dsa_fields_start == dsa_code_template_end -
; dsa_zero, puke.
ABSOLUTE dsa_fields_start = 0 ; Sanity marker
; pad 48 bytes (fix this RSN)
ABSOLUTE dsa_next = 48 ; len 4 Next DSA
; del 4 Previous DSA address
ABSOLUTE dsa_cmnd = 56 ; len 4 Scsi_Cmnd * for this thread.
ABSOLUTE dsa_select = 60 ; len 4 Device ID, Period, Offset for
; table indirect select
ABSOLUTE dsa_msgout = 64 ; len 8 table indirect move parameter for
; select message
ABSOLUTE dsa_cmdout = 72 ; len 8 table indirect move parameter for
; command
ABSOLUTE dsa_dataout = 80 ; len 4 code pointer for dataout
ABSOLUTE dsa_datain = 84 ; len 4 code pointer for datain
ABSOLUTE dsa_msgin = 88 ; len 8 table indirect move for msgin
ABSOLUTE dsa_status = 96 ; len 8 table indirect move for status byte
ABSOLUTE dsa_msgout_other = 104 ; len 8 table indirect for normal message out
; (Synchronous transfer negotiation, etc).
ABSOLUTE dsa_end = 112
ABSOLUTE schedule = 0 ; Array of JUMP dsa_begin or JUMP (next),
; terminated by a call to JUMP wait_reselect
; Linked lists of DSA structures
ABSOLUTE reconnect_dsa_head = 0 ; Link list of DSAs which can reconnect
ABSOLUTE addr_reconnect_dsa_head = 0 ; Address of variable containing
; address of reconnect_dsa_head
; These select the source and destination of a MOVE MEMORY instruction
ABSOLUTE dmode_memory_to_memory = 0x0
ABSOLUTE dmode_memory_to_ncr = 0x0
ABSOLUTE dmode_ncr_to_memory = 0x0
ABSOLUTE addr_scratch = 0x0
ABSOLUTE addr_temp = 0x0
; Interrupts -
; MSB indicates type
; 0 handle error condition
; 1 handle message
; 2 handle normal condition
; 3 debugging interrupt
; 4 testing interrupt
; Next byte indicates specific error
; XXX not yet implemented, I'm not sure if I want to -
; Next byte indicates the routine the error occurred in
; The LSB indicates the specific place the error occurred
ABSOLUTE int_err_unexpected_phase = 0x00000000 ; Unexpected phase encountered
ABSOLUTE int_err_selected = 0x00010000 ; SELECTED (nee RESELECTED)
ABSOLUTE int_err_unexpected_reselect = 0x00020000
ABSOLUTE int_err_check_condition = 0x00030000
ABSOLUTE int_err_no_phase = 0x00040000
ABSOLUTE int_msg_wdtr = 0x01000000 ; WDTR message received
ABSOLUTE int_msg_sdtr = 0x01010000 ; SDTR received
ABSOLUTE int_msg_1 = 0x01020000 ; single byte special message
; received
ABSOLUTE int_norm_select_complete = 0x02000000 ; Select complete, reprogram
; registers.
ABSOLUTE int_norm_reselect_complete = 0x02010000 ; Nexus established
ABSOLUTE int_norm_command_complete = 0x02020000 ; Command complete
ABSOLUTE int_norm_disconnected = 0x02030000 ; Disconnected
ABSOLUTE int_norm_aborted =0x02040000 ; Aborted *dsa
ABSOLUTE int_norm_reset = 0x02050000 ; Generated BUS reset.
ABSOLUTE int_debug_break = 0x03000000 ; Break point
ABSOLUTE int_debug_panic = 0x030b0000 ; Panic driver
ABSOLUTE int_test_1 = 0x04000000 ; Test 1 complete
ABSOLUTE int_test_2 = 0x04010000 ; Test 2 complete
ABSOLUTE int_test_3 = 0x04020000 ; Test 3 complete
; These should start with 0x05000000, with low bits incrementing for
; each one.
ABSOLUTE NCR53c7xx_msg_abort = 0 ; Pointer to abort message
ABSOLUTE NCR53c7xx_msg_reject = 0 ; Pointer to reject message
ABSOLUTE NCR53c7xx_zero = 0 ; long with zero in it, use for source
ABSOLUTE NCR53c7xx_sink = 0 ; long to dump worthless data in
ABSOLUTE NOP_insn = 0 ; NOP instruction
; Pointer to message, potentially multi-byte
ABSOLUTE msg_buf = 0
; Pointer to holding area for reselection information
ABSOLUTE reselected_identify = 0
ABSOLUTE reselected_tag = 0
; Request sense command pointer, it's a 6 byte command, should
; be constant for all commands since we always want 16 bytes of
; sense and we don't need to change any fields as we did under
; SCSI-I when we actually cared about the LUN field.
;EXTERNAL NCR53c7xx_sense ; Request sense command
; dsa_schedule
; PURPOSE : after a DISCONNECT message has been received, and pointers
; saved, insert the current DSA structure at the head of the
; disconnected queue and fall through to the scheduler.
;
; CALLS : OK
;
; INPUTS : dsa - current DSA structure, reconnect_dsa_head - list
; of disconnected commands
;
; MODIFIES : SCRATCH, reconnect_dsa_head
;
; EXITS : always passes control to schedule
ENTRY dsa_schedule
dsa_schedule:
;
; Calculate the address of the next pointer within the DSA
; structure of the command that is currently disconnecting
;
CALL dsa_to_scratch
at 0x0000005a : */ 0x88080000,0x00000938,
/*
MOVE SCRATCH0 + dsa_next TO SCRATCH0
at 0x0000005c : */ 0x7e343000,0x00000000,
/*
MOVE SCRATCH1 + 0 TO SCRATCH1 WITH CARRY
at 0x0000005e : */ 0x7f350000,0x00000000,
/*
MOVE SCRATCH2 + 0 TO SCRATCH2 WITH CARRY
at 0x00000060 : */ 0x7f360000,0x00000000,
/*
MOVE SCRATCH3 + 0 TO SCRATCH3 WITH CARRY
at 0x00000062 : */ 0x7f370000,0x00000000,
/*
; Point the next field of this DSA structure at the current disconnected
; list
MOVE dmode_ncr_to_memory TO DMODE
at 0x00000064 : */ 0x78380000,0x00000000,
/*
MOVE MEMORY 4, addr_scratch, dsa_schedule_insert + 8
at 0x00000066 : */ 0xc0000004,0x00000000,0x000001b4,
/*
MOVE dmode_memory_to_memory TO DMODE
at 0x00000069 : */ 0x78380000,0x00000000,
/*
dsa_schedule_insert:
MOVE MEMORY 4, reconnect_dsa_head, 0
at 0x0000006b : */ 0xc0000004,0x00000000,0x00000000,
/*
; And update the head pointer.
CALL dsa_to_scratch
at 0x0000006e : */ 0x88080000,0x00000938,
/*
MOVE dmode_ncr_to_memory TO DMODE
at 0x00000070 : */ 0x78380000,0x00000000,
/*
MOVE MEMORY 4, addr_scratch, reconnect_dsa_head
at 0x00000072 : */ 0xc0000004,0x00000000,0x00000000,
/*
MOVE dmode_memory_to_memory TO DMODE
at 0x00000075 : */ 0x78380000,0x00000000,
/*
MOVE SCNTL2 & 0x7f TO SCNTL2
at 0x00000077 : */ 0x7c027f00,0x00000000,
/*
CLEAR ACK
at 0x00000079 : */ 0x60000040,0x00000000,
/*
WAIT DISCONNECT
at 0x0000007b : */ 0x48000000,0x00000000,
/*
JUMP schedule
at 0x0000007d : */ 0x80080000,0x00000000,
/*
;
; select
;
; PURPOSE : establish a nexus for the SCSI command referenced by DSA.
; On success, the current DSA structure is removed from the issue
; queue. Usually, this is entered as a fall-through from schedule,
; although the contingent allegiance handling code will write
; the select entry address to the DSP to restart a command as a
; REQUEST SENSE. A message is sent (usually IDENTIFY, although
; additional SDTR or WDTR messages may be sent). COMMAND OUT
; is handled.
;
; INPUTS : DSA - SCSI command, issue_dsa_head
;
; CALLS : NOT OK
;
; MODIFIES : SCRATCH, issue_dsa_head
;
; EXITS : on reselection or selection, go to select_failed
; otherwise, RETURN so control is passed back to
; dsa_begin.
;
ENTRY select
select:
CLEAR TARGET
at 0x0000007f : */ 0x60000200,0x00000000,
/*
; XXX
;
; In effect, SELECTION operations are backgrounded, with execution
; continuing until code which waits for REQ or a fatal interrupt is
; encountered.
;
; So, for more performance, we could overlap the code which removes
; the command from the NCRs issue queue with the selection, but
; at this point I don't want to deal with the error recovery.
;
SELECT ATN FROM dsa_select, select_failed
at 0x00000081 : */ 0x4300003c,0x000007a4,
/*
JUMP select_msgout, WHEN MSG_OUT
at 0x00000083 : */ 0x860b0000,0x00000214,
/*
ENTRY select_msgout
select_msgout:
MOVE FROM dsa_msgout, WHEN MSG_OUT
at 0x00000085 : */ 0x1e000000,0x00000040,
/*
RETURN
at 0x00000087 : */ 0x90080000,0x00000000,
/*
;
; select_done
;
; PURPOSE: continue on to normal data transfer; called as the exit
; point from dsa_begin.
;
; INPUTS: dsa
;
; CALLS: OK
;
;
select_done:
; After a successful selection, we should get either a CMD phase or
; some transfer request negotiation message.
JUMP cmdout, WHEN CMD
at 0x00000089 : */ 0x820b0000,0x00000244,
/*
INT int_err_unexpected_phase, WHEN NOT MSG_IN
at 0x0000008b : */ 0x9f030000,0x00000000,
/*
select_msg_in:
CALL msg_in, WHEN MSG_IN
at 0x0000008d : */ 0x8f0b0000,0x00000404,
/*
JUMP select_msg_in, WHEN MSG_IN
at 0x0000008f : */ 0x870b0000,0x00000234,
/*
cmdout:
INT int_err_unexpected_phase, WHEN NOT CMD
at 0x00000091 : */ 0x9a030000,0x00000000,
/*
ENTRY cmdout_cmdout
cmdout_cmdout:
MOVE FROM dsa_cmdout, WHEN CMD
at 0x00000093 : */ 0x1a000000,0x00000048,
/*
;
; data_transfer
; other_out
; other_in
; other_transfer
;
; PURPOSE : handle the main data transfer for a SCSI command in
; several parts. In the first part, data_transfer, DATA_IN
; and DATA_OUT phases are allowed, with the user provided
; code (usually dynamically generated based on the scatter/gather
; list associated with a SCSI command) called to handle these
; phases.
;
; After control has passed to one of the user provided
; DATA_IN or DATA_OUT routines, back calls are made to
; other_transfer_in or other_transfer_out to handle non-DATA IN
; and DATA OUT phases respectively, with the state of the active
; data pointer being preserved in TEMP.
;
; On completion, the user code passes control to other_transfer
; which causes DATA_IN and DATA_OUT to result in unexpected_phase
; interrupts so that data overruns may be trapped.
;
; INPUTS : DSA - SCSI command
;
; CALLS : OK in data_transfer_start, not ok in other_out and other_in, ok in
; other_transfer
;
; MODIFIES : SCRATCH
;
; EXITS : if STATUS IN is detected, signifying command completion,
; the NCR jumps to command_complete. If MSG IN occurs, a
; CALL is made to msg_in. Otherwise, other_transfer runs in
; an infinite loop.
;
ENTRY data_transfer
data_transfer:
JUMP cmdout_cmdout, WHEN CMD
at 0x00000095 : */ 0x820b0000,0x0000024c,
/*
CALL msg_in, WHEN MSG_IN
at 0x00000097 : */ 0x8f0b0000,0x00000404,
/*
INT int_err_unexpected_phase, WHEN MSG_OUT
at 0x00000099 : */ 0x9e0b0000,0x00000000,
/*
JUMP do_dataout, WHEN DATA_OUT
at 0x0000009b : */ 0x800b0000,0x0000028c,
/*
JUMP do_datain, WHEN DATA_IN
at 0x0000009d : */ 0x810b0000,0x000002e4,
/*
JUMP command_complete, WHEN STATUS
at 0x0000009f : */ 0x830b0000,0x0000060c,
/*
JUMP data_transfer
at 0x000000a1 : */ 0x80080000,0x00000254,
/*
ENTRY end_data_transfer
end_data_transfer:
;
; FIXME: On NCR53c700 and NCR53c700-66 chips, do_dataout/do_datain
; should be fixed up whenever the nexus changes so it can point to the
; correct routine for that command.
;
; Nasty jump to dsa->dataout
do_dataout:
CALL dsa_to_scratch
at 0x000000a3 : */ 0x88080000,0x00000938,
/*
MOVE SCRATCH0 + dsa_dataout TO SCRATCH0
at 0x000000a5 : */ 0x7e345000,0x00000000,
/*
MOVE SCRATCH1 + 0 TO SCRATCH1 WITH CARRY
at 0x000000a7 : */ 0x7f350000,0x00000000,
/*
MOVE SCRATCH2 + 0 TO SCRATCH2 WITH CARRY
at 0x000000a9 : */ 0x7f360000,0x00000000,
/*
MOVE SCRATCH3 + 0 TO SCRATCH3 WITH CARRY
at 0x000000ab : */ 0x7f370000,0x00000000,
/*
MOVE dmode_ncr_to_memory TO DMODE
at 0x000000ad : */ 0x78380000,0x00000000,
/*
MOVE MEMORY 4, addr_scratch, dataout_to_jump + 4
at 0x000000af : */ 0xc0000004,0x00000000,0x000002d4,
/*
MOVE dmode_memory_to_memory TO DMODE
at 0x000000b2 : */ 0x78380000,0x00000000,
/*
dataout_to_jump:
MOVE MEMORY 4, 0, dataout_jump + 4
at 0x000000b4 : */ 0xc0000004,0x00000000,0x000002e0,
/*
dataout_jump:
JUMP 0
at 0x000000b7 : */ 0x80080000,0x00000000,
/*
; Nasty jump to dsa->dsain
do_datain:
CALL dsa_to_scratch
at 0x000000b9 : */ 0x88080000,0x00000938,
/*
MOVE SCRATCH0 + dsa_datain TO SCRATCH0
at 0x000000bb : */ 0x7e345400,0x00000000,
/*
MOVE SCRATCH1 + 0 TO SCRATCH1 WITH CARRY
at 0x000000bd : */ 0x7f350000,0x00000000,
/*
MOVE SCRATCH2 + 0 TO SCRATCH2 WITH CARRY
at 0x000000bf : */ 0x7f360000,0x00000000,
/*
MOVE SCRATCH3 + 0 TO SCRATCH3 WITH CARRY
at 0x000000c1 : */ 0x7f370000,0x00000000,
/*
MOVE dmode_ncr_to_memory TO DMODE
at 0x000000c3 : */ 0x78380000,0x00000000,
/*
MOVE MEMORY 4, addr_scratch, datain_to_jump + 4
at 0x000000c5 : */ 0xc0000004,0x00000000,0x0000032c,
/*
MOVE dmode_memory_to_memory TO DMODE
at 0x000000c8 : */ 0x78380000,0x00000000,
/*
ENTRY datain_to_jump
datain_to_jump:
MOVE MEMORY 4, 0, datain_jump + 4
at 0x000000ca : */ 0xc0000004,0x00000000,0x00000338,
/*
datain_jump:
JUMP 0
at 0x000000cd : */ 0x80080000,0x00000000,
/*
; Note that other_out and other_in loop until a non-data phase
; is discovered, so we only execute return statements when we
; can go on to the next data phase block move statement.
ENTRY other_out
other_out:
INT int_err_unexpected_phase, WHEN CMD
at 0x000000cf : */ 0x9a0b0000,0x00000000,
/*
JUMP msg_in_restart, WHEN MSG_IN
at 0x000000d1 : */ 0x870b0000,0x000003e4,
/*
INT int_err_unexpected_phase, WHEN MSG_OUT
at 0x000000d3 : */ 0x9e0b0000,0x00000000,
/*
INT int_err_unexpected_phase, WHEN DATA_IN
at 0x000000d5 : */ 0x990b0000,0x00000000,
/*
JUMP command_complete, WHEN STATUS
at 0x000000d7 : */ 0x830b0000,0x0000060c,
/*
JUMP other_out, WHEN NOT DATA_OUT
at 0x000000d9 : */ 0x80030000,0x0000033c,
/*
RETURN
at 0x000000db : */ 0x90080000,0x00000000,
/*
ENTRY other_in
other_in:
INT int_err_unexpected_phase, WHEN CMD
at 0x000000dd : */ 0x9a0b0000,0x00000000,
/*
JUMP msg_in_restart, WHEN MSG_IN
at 0x000000df : */ 0x870b0000,0x000003e4,
/*
INT int_err_unexpected_phase, WHEN MSG_OUT
at 0x000000e1 : */ 0x9e0b0000,0x00000000,
/*
INT int_err_unexpected_phase, WHEN DATA_OUT
at 0x000000e3 : */ 0x980b0000,0x00000000,
/*
JUMP command_complete, WHEN STATUS
at 0x000000e5 : */ 0x830b0000,0x0000060c,
/*
JUMP other_in, WHEN NOT DATA_IN
at 0x000000e7 : */ 0x81030000,0x00000374,
/*
RETURN
at 0x000000e9 : */ 0x90080000,0x00000000,
/*
ENTRY other_transfer
other_transfer:
INT int_err_unexpected_phase, WHEN CMD
at 0x000000eb : */ 0x9a0b0000,0x00000000,
/*
CALL msg_in, WHEN MSG_IN
at 0x000000ed : */ 0x8f0b0000,0x00000404,
/*
INT int_err_unexpected_phase, WHEN MSG_OUT
at 0x000000ef : */ 0x9e0b0000,0x00000000,
/*
INT int_err_unexpected_phase, WHEN DATA_OUT
at 0x000000f1 : */ 0x980b0000,0x00000000,
/*
INT int_err_unexpected_phase, WHEN DATA_IN
at 0x000000f3 : */ 0x990b0000,0x00000000,
/*
JUMP command_complete, WHEN STATUS
at 0x000000f5 : */ 0x830b0000,0x0000060c,
/*
JUMP other_transfer
at 0x000000f7 : */ 0x80080000,0x000003ac,
/*
;
; msg_in_restart
; msg_in
; munge_msg
;
; PURPOSE : process messages from a target. msg_in is called when the
; caller hasn't read the first byte of the message. munge_message
; is called when the caller has read the first byte of the message,
; and left it in SFBR. msg_in_restart is called when the caller
; hasn't read the first byte of the message, and wishes RETURN
; to transfer control back to the address of the conditional
; CALL instruction rather than to the instruction after it.
;
; Various int_* interrupts are generated when the host system
; needs to intervene, as is the case with SDTR, WDTR, and
; INITIATE RECOVERY messages.
;
; When the host system handles one of these interrupts,
; it can respond by reentering at reject_message,
; which rejects the message and returns control to
; the caller of msg_in or munge_msg, accept_message
; which clears ACK and returns control, or reply_message
; which sends the message pointed to by the DSA
; msgout_other table indirect field.
;
; DISCONNECT messages are handled by moving the command
; to the reconnect_dsa_queue.
;
; INPUTS : DSA - SCSI COMMAND, SFBR - first byte of message (munge_msg
; only)
;
; CALLS : NO. The TEMP register isn't backed up to allow nested calls.
;
; MODIFIES : SCRATCH, DSA on DISCONNECT
;
; EXITS : On receipt of SAVE DATA POINTER, RESTORE POINTERS,
; and normal return from message handlers running under
; Linux, control is returned to the caller. Receipt
; of DISCONNECT messages pass control to dsa_schedule.
;
ENTRY msg_in_restart
msg_in_restart:
; XXX - hackish
;
; Since it's easier to debug changes to the statically
; compiled code, rather than the dynamically generated
; stuff, such as
;
; MOVE x, y, WHEN data_phase
; CALL other_z, WHEN NOT data_phase
; MOVE x, y, WHEN data_phase
;
; I'd like to have certain routines (notably the message handler)
; restart on the conditional call rather than the next instruction.
;
; So, subtract 8 from the return address
MOVE TEMP0 + 0xf8 TO TEMP0
at 0x000000f9 : */ 0x7e1cf800,0x00000000,
/*
MOVE TEMP1 + 0xff TO TEMP1 WITH CARRY
at 0x000000fb : */ 0x7f1dff00,0x00000000,
/*
MOVE TEMP2 + 0xff TO TEMP2 WITH CARRY
at 0x000000fd : */ 0x7f1eff00,0x00000000,
/*
MOVE TEMP3 + 0xff TO TEMP3 WITH CARRY
at 0x000000ff : */ 0x7f1fff00,0x00000000,
/*
ENTRY msg_in
msg_in:
MOVE 1, msg_buf, WHEN MSG_IN
at 0x00000101 : */ 0x0f000001,0x00000000,
/*
munge_msg:
JUMP munge_extended, IF 0x01 ; EXTENDED MESSAGE
at 0x00000103 : */ 0x800c0001,0x00000524,
/*
JUMP munge_2, IF 0x20, AND MASK 0xdf ; two byte message
at 0x00000105 : */ 0x800cdf20,0x0000044c,
/*
;
; XXX - I've seen a handful of broken SCSI devices which fail to issue
; a SAVE POINTERS message before disconnecting in the middle of
; a transfer, assuming that the DATA POINTER will be implicitly
; restored.
;
; Historically, I've often done an implicit save when the DISCONNECT
; message is processed. We may want to consider having the option of
; doing that here.
;
JUMP munge_save_data_pointer, IF 0x02 ; SAVE DATA POINTER
at 0x00000107 : */ 0x800c0002,0x00000454,
/*
JUMP munge_restore_pointers, IF 0x03 ; RESTORE POINTERS
at 0x00000109 : */ 0x800c0003,0x000004b8,
/*
JUMP munge_disconnect, IF 0x04 ; DISCONNECT
at 0x0000010b : */ 0x800c0004,0x0000051c,
/*
INT int_msg_1, IF 0x07 ; MESSAGE REJECT
at 0x0000010d : */ 0x980c0007,0x01020000,
/*
INT int_msg_1, IF 0x0f ; INITIATE RECOVERY
at 0x0000010f : */ 0x980c000f,0x01020000,
/*
JUMP reject_message
at 0x00000111 : */ 0x80080000,0x000005b4,
/*
munge_2:
JUMP reject_message
at 0x00000113 : */ 0x80080000,0x000005b4,
/*
;
; The SCSI standard allows targets to recover from transient
; error conditions by backing up the data pointer with a
; RESTORE POINTERS message.
;
; So, we must save and restore the _residual_ code as well as
; the current instruction pointer. Because of this messiness,
; it is simpler to put dynamic code in the dsa for this and to
; just do a simple jump down there.
;
munge_save_data_pointer:
MOVE DSA0 + dsa_save_data_pointer TO SFBR
at 0x00000115 : */ 0x76100000,0x00000000,
/*
MOVE SFBR TO SCRATCH0
at 0x00000117 : */ 0x6a340000,0x00000000,
/*
MOVE DSA1 + 0xff TO SFBR WITH CARRY
at 0x00000119 : */ 0x7711ff00,0x00000000,
/*
MOVE SFBR TO SCRATCH1
at 0x0000011b : */ 0x6a350000,0x00000000,
/*
MOVE DSA2 + 0xff TO SFBR WITH CARRY
at 0x0000011d : */ 0x7712ff00,0x00000000,
/*
MOVE SFBR TO SCRATCH2
at 0x0000011f : */ 0x6a360000,0x00000000,
/*
MOVE DSA3 + 0xff TO SFBR WITH CARRY
at 0x00000121 : */ 0x7713ff00,0x00000000,
/*
MOVE SFBR TO SCRATCH3
at 0x00000123 : */ 0x6a370000,0x00000000,
/*
MOVE dmode_ncr_to_memory TO DMODE
at 0x00000125 : */ 0x78380000,0x00000000,
/*
MOVE MEMORY 4, addr_scratch, jump_dsa_save + 4
at 0x00000127 : */ 0xc0000004,0x00000000,0x000004b4,
/*
MOVE dmode_memory_to_memory TO DMODE
at 0x0000012a : */ 0x78380000,0x00000000,
/*
jump_dsa_save:
JUMP 0
at 0x0000012c : */ 0x80080000,0x00000000,
/*
munge_restore_pointers:
MOVE DSA0 + dsa_restore_pointers TO SFBR
at 0x0000012e : */ 0x76100000,0x00000000,
/*
MOVE SFBR TO SCRATCH0
at 0x00000130 : */ 0x6a340000,0x00000000,
/*
MOVE DSA1 + 0xff TO SFBR WITH CARRY
at 0x00000132 : */ 0x7711ff00,0x00000000,
/*
MOVE SFBR TO SCRATCH1
at 0x00000134 : */ 0x6a350000,0x00000000,
/*
MOVE DSA2 + 0xff TO SFBR WITH CARRY
at 0x00000136 : */ 0x7712ff00,0x00000000,
/*
MOVE SFBR TO SCRATCH2
at 0x00000138 : */ 0x6a360000,0x00000000,
/*
MOVE DSA3 + 0xff TO SFBR WITH CARRY
at 0x0000013a : */ 0x7713ff00,0x00000000,
/*
MOVE SFBR TO SCRATCH3
at 0x0000013c : */ 0x6a370000,0x00000000,
/*
MOVE dmode_ncr_to_memory TO DMODE
at 0x0000013e : */ 0x78380000,0x00000000,
/*
MOVE MEMORY 4, addr_scratch, jump_dsa_restore + 4
at 0x00000140 : */ 0xc0000004,0x00000000,0x00000518,
/*
MOVE dmode_memory_to_memory TO DMODE
at 0x00000143 : */ 0x78380000,0x00000000,
/*
jump_dsa_restore:
JUMP 0
at 0x00000145 : */ 0x80080000,0x00000000,
/*
munge_disconnect:
JUMP dsa_schedule
at 0x00000147 : */ 0x80080000,0x00000168,
/*
munge_extended:
CLEAR ACK
at 0x00000149 : */ 0x60000040,0x00000000,
/*
INT int_err_unexpected_phase, WHEN NOT MSG_IN
at 0x0000014b : */ 0x9f030000,0x00000000,
/*
MOVE 1, msg_buf + 1, WHEN MSG_IN
at 0x0000014d : */ 0x0f000001,0x00000001,
/*
JUMP munge_extended_2, IF 0x02
at 0x0000014f : */ 0x800c0002,0x00000554,
/*
JUMP munge_extended_3, IF 0x03
at 0x00000151 : */ 0x800c0003,0x00000584,
/*
JUMP reject_message
at 0x00000153 : */ 0x80080000,0x000005b4,
/*
munge_extended_2:
CLEAR ACK
at 0x00000155 : */ 0x60000040,0x00000000,
/*
MOVE 1, msg_buf + 2, WHEN MSG_IN
at 0x00000157 : */ 0x0f000001,0x00000002,
/*
JUMP reject_message, IF NOT 0x02 ; Must be WDTR
at 0x00000159 : */ 0x80040002,0x000005b4,
/*
CLEAR ACK
at 0x0000015b : */ 0x60000040,0x00000000,
/*
MOVE 1, msg_buf + 3, WHEN MSG_IN
at 0x0000015d : */ 0x0f000001,0x00000003,
/*
INT int_msg_wdtr
at 0x0000015f : */ 0x98080000,0x01000000,
/*
munge_extended_3:
CLEAR ACK
at 0x00000161 : */ 0x60000040,0x00000000,
/*
MOVE 1, msg_buf + 2, WHEN MSG_IN
at 0x00000163 : */ 0x0f000001,0x00000002,
/*
JUMP reject_message, IF NOT 0x01 ; Must be SDTR
at 0x00000165 : */ 0x80040001,0x000005b4,
/*
CLEAR ACK
at 0x00000167 : */ 0x60000040,0x00000000,
/*
MOVE 2, msg_buf + 3, WHEN MSG_IN
at 0x00000169 : */ 0x0f000002,0x00000003,
/*
INT int_msg_sdtr
at 0x0000016b : */ 0x98080000,0x01010000,
/*
ENTRY reject_message
reject_message:
SET ATN
at 0x0000016d : */ 0x58000008,0x00000000,
/*
CLEAR ACK
at 0x0000016f : */ 0x60000040,0x00000000,
/*
MOVE 1, NCR53c7xx_msg_reject, WHEN MSG_OUT
at 0x00000171 : */ 0x0e000001,0x00000000,
/*
RETURN
at 0x00000173 : */ 0x90080000,0x00000000,
/*
ENTRY accept_message
accept_message:
CLEAR ATN
at 0x00000175 : */ 0x60000008,0x00000000,
/*
CLEAR ACK
at 0x00000177 : */ 0x60000040,0x00000000,
/*
RETURN
at 0x00000179 : */ 0x90080000,0x00000000,
/*
ENTRY respond_message
respond_message:
SET ATN
at 0x0000017b : */ 0x58000008,0x00000000,
/*
CLEAR ACK
at 0x0000017d : */ 0x60000040,0x00000000,
/*
MOVE FROM dsa_msgout_other, WHEN MSG_OUT
at 0x0000017f : */ 0x1e000000,0x00000068,
/*
RETURN
at 0x00000181 : */ 0x90080000,0x00000000,
/*
;
; command_complete
;
; PURPOSE : handle command termination when STATUS IN is detected by reading
; a status byte followed by a command termination message.
;
; Normal termination results in an INTFLY instruction, and
; the host system can pick out which command terminated by
; examining the MESSAGE and STATUS buffers of all currently
; executing commands;
;
; Abnormal (CHECK_CONDITION) termination results in an
; int_err_check_condition interrupt so that a REQUEST SENSE
; command can be issued out-of-order so that no other command
; clears the contingent allegiance condition.
;
;
; INPUTS : DSA - command
;
; CALLS : OK
;
; EXITS : On successful termination, control is passed to schedule.
; On abnormal termination, the user will usually modify the
; DSA fields and corresponding buffers and return control
; to select.
;
ENTRY command_complete
command_complete:
MOVE FROM dsa_status, WHEN STATUS
at 0x00000183 : */ 0x1b000000,0x00000060,
/*
MOVE SFBR TO SCRATCH0 ; Save status
at 0x00000185 : */ 0x6a340000,0x00000000,
/*
ENTRY command_complete_msgin
command_complete_msgin:
MOVE FROM dsa_msgin, WHEN MSG_IN
at 0x00000187 : */ 0x1f000000,0x00000058,
/*
; Indicate that we should be expecting a disconnect
MOVE SCNTL2 & 0x7f TO SCNTL2
at 0x00000189 : */ 0x7c027f00,0x00000000,
/*
CLEAR ACK
at 0x0000018b : */ 0x60000040,0x00000000,
/*
WAIT DISCONNECT
at 0x0000018d : */ 0x48000000,0x00000000,
/*
;
; The SCSI specification states that when a UNIT ATTENTION condition
; is pending, as indicated by a CHECK CONDITION status message,
; the target shall revert to asynchronous transfers. Since
; synchronous transfers parameters are maintained on a per INITIATOR/TARGET
; basis, and returning control to our scheduler could work on a command
; running on another lun on that target using the old parameters, we must
; interrupt the host processor to get them changed, or change them ourselves.
;
; Once SCSI-II tagged queueing is implemented, things will be even more
; hairy, since contingent allegiance conditions exist on a per-target/lun
; basis, and issuing a new command with a different tag would clear it.
; In these cases, we must interrupt the host processor to get a request
; added to the HEAD of the queue with the request sense command, or we
; must automatically issue the request sense command.
INTFLY
at 0x0000018f : */ 0x98180000,0x00000000,
/*
JUMP schedule
at 0x00000191 : */ 0x80080000,0x00000000,
/*
command_failed:
INT int_err_check_condition
at 0x00000193 : */ 0x98080000,0x00030000,
/*
;
; wait_reselect
;
; PURPOSE : This is essentially the idle routine, where control lands
; when there are no new processes to schedule. wait_reselect
; waits for reselection, selection, and new commands.
;
; When a successful reselection occurs, with the aid
; of fixed up code in each DSA, wait_reselect walks the
; reconnect_dsa_queue, asking each dsa if the target ID
; and LUN match its.
;
; If a match is found, a call is made back to reselected_ok,
; which through the miracles of self modifying code, extracts
; the found DSA from the reconnect_dsa_queue and then
; returns control to the DSAs thread of execution.
;
; INPUTS : NONE
;
; CALLS : OK
;
; MODIFIES : DSA,
;
; EXITS : On successful reselection, control is returned to the
; DSA which called reselected_ok. If the WAIT RESELECT
; was interrupted by a new commands arrival signaled by
; SIG_P, control is passed to schedule. If the NCR is
; selected, the host system is interrupted with an
; int_err_selected which is usually responded to by
; setting DSP to the target_abort address.
ENTRY wait_reselect
wait_reselect:
WAIT RESELECT wait_reselect_failed
at 0x00000195 : */ 0x50000000,0x0000076c,
/*
reselected:
CLEAR TARGET
at 0x00000197 : */ 0x60000200,0x00000000,
/*
MOVE dmode_memory_to_memory TO DMODE
at 0x00000199 : */ 0x78380000,0x00000000,
/*
; Read all data needed to reestablish the nexus -
MOVE 1, reselected_identify, WHEN MSG_IN
at 0x0000019b : */ 0x0f000001,0x00000000,
/*
; We used to CLEAR ACK here.
; Point DSA at the current head of the disconnected queue.
MOVE dmode_memory_to_ncr TO DMODE
at 0x0000019d : */ 0x78380000,0x00000000,
/*
MOVE MEMORY 4, reconnect_dsa_head, addr_scratch
at 0x0000019f : */ 0xc0000004,0x00000000,0x00000000,
/*
MOVE dmode_memory_to_memory TO DMODE
at 0x000001a2 : */ 0x78380000,0x00000000,
/*
CALL scratch_to_dsa
at 0x000001a4 : */ 0x88080000,0x00000980,
/*
; Fix the update-next pointer so that the reconnect_dsa_head
; pointer is the one that will be updated if this DSA is a hit
; and we remove it from the queue.
MOVE MEMORY 4, addr_reconnect_dsa_head, reselected_ok + 8
at 0x000001a6 : */ 0xc0000004,0x00000000,0x00000758,
/*
ENTRY reselected_check_next
reselected_check_next:
; Check for a NULL pointer.
MOVE DSA0 TO SFBR
at 0x000001a9 : */ 0x72100000,0x00000000,
/*
JUMP reselected_not_end, IF NOT 0
at 0x000001ab : */ 0x80040000,0x000006ec,
/*
MOVE DSA1 TO SFBR
at 0x000001ad : */ 0x72110000,0x00000000,
/*
JUMP reselected_not_end, IF NOT 0
at 0x000001af : */ 0x80040000,0x000006ec,
/*
MOVE DSA2 TO SFBR
at 0x000001b1 : */ 0x72120000,0x00000000,
/*
JUMP reselected_not_end, IF NOT 0
at 0x000001b3 : */ 0x80040000,0x000006ec,
/*
MOVE DSA3 TO SFBR
at 0x000001b5 : */ 0x72130000,0x00000000,
/*
JUMP reselected_not_end, IF NOT 0
at 0x000001b7 : */ 0x80040000,0x000006ec,
/*
INT int_err_unexpected_reselect
at 0x000001b9 : */ 0x98080000,0x00020000,
/*
reselected_not_end:
;
; XXX the ALU is only eight bits wide, and the assembler
; wont do the dirt work for us. As long as dsa_check_reselect
; is negative, we need to sign extend with 1 bits to the full
; 32 bit width of the address.
;
; A potential work around would be to have a known alignment
; of the DSA structure such that the base address plus
; dsa_check_reselect doesn't require carrying from bytes
; higher than the LSB.
;
MOVE DSA0 TO SFBR
at 0x000001bb : */ 0x72100000,0x00000000,
/*
MOVE SFBR + dsa_check_reselect TO SCRATCH0
at 0x000001bd : */ 0x6e340000,0x00000000,
/*
MOVE DSA1 TO SFBR
at 0x000001bf : */ 0x72110000,0x00000000,
/*
MOVE SFBR + 0xff TO SCRATCH1 WITH CARRY
at 0x000001c1 : */ 0x6f35ff00,0x00000000,
/*
MOVE DSA2 TO SFBR
at 0x000001c3 : */ 0x72120000,0x00000000,
/*
MOVE SFBR + 0xff TO SCRATCH2 WITH CARRY
at 0x000001c5 : */ 0x6f36ff00,0x00000000,
/*
MOVE DSA3 TO SFBR
at 0x000001c7 : */ 0x72130000,0x00000000,
/*
MOVE SFBR + 0xff TO SCRATCH3 WITH CARRY
at 0x000001c9 : */ 0x6f37ff00,0x00000000,
/*
MOVE dmode_ncr_to_memory TO DMODE
at 0x000001cb : */ 0x78380000,0x00000000,
/*
MOVE MEMORY 4, addr_scratch, reselected_check + 4
at 0x000001cd : */ 0xc0000004,0x00000000,0x0000074c,
/*
MOVE dmode_memory_to_memory TO DMODE
at 0x000001d0 : */ 0x78380000,0x00000000,
/*
reselected_check:
JUMP 0
at 0x000001d2 : */ 0x80080000,0x00000000,
/*
;
;
ENTRY reselected_ok
reselected_ok:
MOVE MEMORY 4, 0, 0 ; Patched : first word
at 0x000001d4 : */ 0xc0000004,0x00000000,0x00000000,
/*
; is address of
; successful dsa_next
; Second word is last
; unsuccessful dsa_next,
; starting with
; dsa_reconnect_head
; We used to CLEAR ACK here.
RETURN ; Return control to where
at 0x000001d7 : */ 0x90080000,0x00000000,
/*
selected:
INT int_err_selected;
at 0x000001d9 : */ 0x98080000,0x00010000,
/*
;
; A select or reselect failure can be caused by one of two conditions :
; 1. SIG_P was set. This will be the case if the user has written
; a new value to a previously NULL head of the issue queue.
;
; 2. The NCR53c810 was selected or reselected by another device.
;
; 3. The bus was already busy since we were selected or reselected
; before starting the command.
wait_reselect_failed:
; Check selected bit.
MOVE SIST0 & 0x20 TO SFBR
at 0x000001db : */ 0x74422000,0x00000000,
/*
JUMP selected, IF 0x20
at 0x000001dd : */ 0x800c0020,0x00000764,
/*
; Reading CTEST2 clears the SIG_P bit in the ISTAT register.
MOVE CTEST2 & 0x40 TO SFBR
at 0x000001df : */ 0x741a4000,0x00000000,
/*
JUMP schedule, IF 0x40
at 0x000001e1 : */ 0x800c0040,0x00000000,
/*
; Check connected bit.
; FIXME: this needs to change if we support target mode
MOVE ISTAT & 0x08 TO SFBR
at 0x000001e3 : */ 0x74140800,0x00000000,
/*
JUMP reselected, IF 0x08
at 0x000001e5 : */ 0x800c0008,0x0000065c,
/*
; FIXME : Something bogus happened, and we shouldn't fail silently.
INT int_debug_panic
at 0x000001e7 : */ 0x98080000,0x030b0000,
/*
select_failed:
; Otherwise, mask the selected and reselected bits off SIST0
MOVE SIST0 & 0x30 TO SFBR
at 0x000001e9 : */ 0x74423000,0x00000000,
/*
JUMP selected, IF 0x20
at 0x000001eb : */ 0x800c0020,0x00000764,
/*
JUMP reselected, IF 0x10
at 0x000001ed : */ 0x800c0010,0x0000065c,
/*
; If SIGP is set, the user just gave us another command, and
; we should restart or return to the scheduler.
; Reading CTEST2 clears the SIG_P bit in the ISTAT register.
MOVE CTEST2 & 0x40 TO SFBR
at 0x000001ef : */ 0x741a4000,0x00000000,
/*
JUMP select, IF 0x40
at 0x000001f1 : */ 0x800c0040,0x000001fc,
/*
; Check connected bit.
; FIXME: this needs to change if we support target mode
; FIXME: is this really necessary?
MOVE ISTAT & 0x08 TO SFBR
at 0x000001f3 : */ 0x74140800,0x00000000,
/*
JUMP reselected, IF 0x08
at 0x000001f5 : */ 0x800c0008,0x0000065c,
/*
; FIXME : Something bogus happened, and we shouldn't fail silently.
INT int_debug_panic
at 0x000001f7 : */ 0x98080000,0x030b0000,
/*
;
; test_1
; test_2
;
; PURPOSE : run some verification tests on the NCR. test_1
; copies test_src to test_dest and interrupts the host
; processor, testing for cache coherency and interrupt
; problems in the processes.
;
; test_2 runs a command with offsets relative to the
; DSA on entry, and is useful for miscellaneous experimentation.
;
; Verify that interrupts are working correctly and that we don't
; have a cache invalidation problem.
ABSOLUTE test_src = 0, test_dest = 0
ENTRY test_1
test_1:
MOVE MEMORY 4, test_src, test_dest
at 0x000001f9 : */ 0xc0000004,0x00000000,0x00000000,
/*
INT int_test_1
at 0x000001fc : */ 0x98080000,0x04000000,
/*
;
; Run arbitrary commands, with test code establishing a DSA
;
ENTRY test_2
test_2:
CLEAR TARGET
at 0x000001fe : */ 0x60000200,0x00000000,
/*
SELECT ATN FROM 0, test_2_fail
at 0x00000200 : */ 0x43000000,0x00000850,
/*
JUMP test_2_msgout, WHEN MSG_OUT
at 0x00000202 : */ 0x860b0000,0x00000810,
/*
ENTRY test_2_msgout
test_2_msgout:
MOVE FROM 8, WHEN MSG_OUT
at 0x00000204 : */ 0x1e000000,0x00000008,
/*
MOVE FROM 16, WHEN CMD
at 0x00000206 : */ 0x1a000000,0x00000010,
/*
MOVE FROM 24, WHEN DATA_IN
at 0x00000208 : */ 0x19000000,0x00000018,
/*
MOVE FROM 32, WHEN STATUS
at 0x0000020a : */ 0x1b000000,0x00000020,
/*
MOVE FROM 40, WHEN MSG_IN
at 0x0000020c : */ 0x1f000000,0x00000028,
/*
MOVE SCNTL2 & 0x7f TO SCNTL2
at 0x0000020e : */ 0x7c027f00,0x00000000,
/*
CLEAR ACK
at 0x00000210 : */ 0x60000040,0x00000000,
/*
WAIT DISCONNECT
at 0x00000212 : */ 0x48000000,0x00000000,
/*
test_2_fail:
INT int_test_2
at 0x00000214 : */ 0x98080000,0x04010000,
/*
ENTRY debug_break
debug_break:
INT int_debug_break
at 0x00000216 : */ 0x98080000,0x03000000,
/*
;
; initiator_abort
; target_abort
;
; PURPOSE : Abort the currently established nexus from with initiator
; or target mode.
;
;
ENTRY target_abort
target_abort:
SET TARGET
at 0x00000218 : */ 0x58000200,0x00000000,
/*
DISCONNECT
at 0x0000021a : */ 0x48000000,0x00000000,
/*
CLEAR TARGET
at 0x0000021c : */ 0x60000200,0x00000000,
/*
JUMP schedule
at 0x0000021e : */ 0x80080000,0x00000000,
/*
ENTRY initiator_abort
initiator_abort:
SET ATN
at 0x00000220 : */ 0x58000008,0x00000000,
/*
;
; The SCSI-I specification says that targets may go into MSG out at
; their leisure upon receipt of the ATN single. On all versions of the
; specification, we can't change phases until REQ transitions true->false,
; so we need to sink/source one byte of data to allow the transition.
;
; For the sake of safety, we'll only source one byte of data in all
; cases, but to accommodate the SCSI-I dain bramage, we'll sink an
; arbitrary number of bytes.
JUMP spew_cmd, WHEN CMD
at 0x00000222 : */ 0x820b0000,0x000008b8,
/*
JUMP eat_msgin, WHEN MSG_IN
at 0x00000224 : */ 0x870b0000,0x000008c8,
/*
JUMP eat_datain, WHEN DATA_IN
at 0x00000226 : */ 0x810b0000,0x000008f8,
/*
JUMP eat_status, WHEN STATUS
at 0x00000228 : */ 0x830b0000,0x000008e0,
/*
JUMP spew_dataout, WHEN DATA_OUT
at 0x0000022a : */ 0x800b0000,0x00000910,
/*
JUMP sated
at 0x0000022c : */ 0x80080000,0x00000918,
/*
spew_cmd:
MOVE 1, NCR53c7xx_zero, WHEN CMD
at 0x0000022e : */ 0x0a000001,0x00000000,
/*
JUMP sated
at 0x00000230 : */ 0x80080000,0x00000918,
/*
eat_msgin:
MOVE 1, NCR53c7xx_sink, WHEN MSG_IN
at 0x00000232 : */ 0x0f000001,0x00000000,
/*
JUMP eat_msgin, WHEN MSG_IN
at 0x00000234 : */ 0x870b0000,0x000008c8,
/*
JUMP sated
at 0x00000236 : */ 0x80080000,0x00000918,
/*
eat_status:
MOVE 1, NCR53c7xx_sink, WHEN STATUS
at 0x00000238 : */ 0x0b000001,0x00000000,
/*
JUMP eat_status, WHEN STATUS
at 0x0000023a : */ 0x830b0000,0x000008e0,
/*
JUMP sated
at 0x0000023c : */ 0x80080000,0x00000918,
/*
eat_datain:
MOVE 1, NCR53c7xx_sink, WHEN DATA_IN
at 0x0000023e : */ 0x09000001,0x00000000,
/*
JUMP eat_datain, WHEN DATA_IN
at 0x00000240 : */ 0x810b0000,0x000008f8,
/*
JUMP sated
at 0x00000242 : */ 0x80080000,0x00000918,
/*
spew_dataout:
MOVE 1, NCR53c7xx_zero, WHEN DATA_OUT
at 0x00000244 : */ 0x08000001,0x00000000,
/*
sated:
MOVE SCNTL2 & 0x7f TO SCNTL2
at 0x00000246 : */ 0x7c027f00,0x00000000,
/*
MOVE 1, NCR53c7xx_msg_abort, WHEN MSG_OUT
at 0x00000248 : */ 0x0e000001,0x00000000,
/*
WAIT DISCONNECT
at 0x0000024a : */ 0x48000000,0x00000000,
/*
INT int_norm_aborted
at 0x0000024c : */ 0x98080000,0x02040000,
/*
;
; dsa_to_scratch
; scratch_to_dsa
;
; PURPOSE :
; The NCR chips cannot do a move memory instruction with the DSA register
; as the source or destination. So, we provide a couple of subroutines
; that let us switch between the DSA register and scratch register.
;
; Memory moves to/from the DSPS register also don't work, but we
; don't use them.
;
;
dsa_to_scratch:
MOVE DSA0 TO SFBR
at 0x0000024e : */ 0x72100000,0x00000000,
/*
MOVE SFBR TO SCRATCH0
at 0x00000250 : */ 0x6a340000,0x00000000,
/*
MOVE DSA1 TO SFBR
at 0x00000252 : */ 0x72110000,0x00000000,
/*
MOVE SFBR TO SCRATCH1
at 0x00000254 : */ 0x6a350000,0x00000000,
/*
MOVE DSA2 TO SFBR
at 0x00000256 : */ 0x72120000,0x00000000,
/*
MOVE SFBR TO SCRATCH2
at 0x00000258 : */ 0x6a360000,0x00000000,
/*
MOVE DSA3 TO SFBR
at 0x0000025a : */ 0x72130000,0x00000000,
/*
MOVE SFBR TO SCRATCH3
at 0x0000025c : */ 0x6a370000,0x00000000,
/*
RETURN
at 0x0000025e : */ 0x90080000,0x00000000,
/*
scratch_to_dsa:
MOVE SCRATCH0 TO SFBR
at 0x00000260 : */ 0x72340000,0x00000000,
/*
MOVE SFBR TO DSA0
at 0x00000262 : */ 0x6a100000,0x00000000,
/*
MOVE SCRATCH1 TO SFBR
at 0x00000264 : */ 0x72350000,0x00000000,
/*
MOVE SFBR TO DSA1
at 0x00000266 : */ 0x6a110000,0x00000000,
/*
MOVE SCRATCH2 TO SFBR
at 0x00000268 : */ 0x72360000,0x00000000,
/*
MOVE SFBR TO DSA2
at 0x0000026a : */ 0x6a120000,0x00000000,
/*
MOVE SCRATCH3 TO SFBR
at 0x0000026c : */ 0x72370000,0x00000000,
/*
MOVE SFBR TO DSA3
at 0x0000026e : */ 0x6a130000,0x00000000,
/*
RETURN
at 0x00000270 : */ 0x90080000,0x00000000,
};
#define A_NCR53c7xx_msg_abort 0x00000000
static u32 A_NCR53c7xx_msg_abort_used[] __attribute((unused)) = {
0x00000249,
};
#define A_NCR53c7xx_msg_reject 0x00000000
static u32 A_NCR53c7xx_msg_reject_used[] __attribute((unused)) = {
0x00000172,
};
#define A_NCR53c7xx_sink 0x00000000
static u32 A_NCR53c7xx_sink_used[] __attribute((unused)) = {
0x00000233,
0x00000239,
0x0000023f,
};
#define A_NCR53c7xx_zero 0x00000000
static u32 A_NCR53c7xx_zero_used[] __attribute((unused)) = {
0x0000022f,
0x00000245,
};
#define A_NOP_insn 0x00000000
static u32 A_NOP_insn_used[] __attribute((unused)) = {
0x00000010,
};
#define A_addr_reconnect_dsa_head 0x00000000
static u32 A_addr_reconnect_dsa_head_used[] __attribute((unused)) = {
0x000001a7,
};
#define A_addr_scratch 0x00000000
static u32 A_addr_scratch_used[] __attribute((unused)) = {
0x00000004,
0x0000001b,
0x00000046,
0x00000067,
0x00000073,
0x000000b0,
0x000000c6,
0x00000128,
0x00000141,
0x000001a1,
0x000001ce,
};
#define A_addr_temp 0x00000000
static u32 A_addr_temp_used[] __attribute((unused)) = {
0x00000025,
0x00000034,
};
#define A_dmode_memory_to_memory 0x00000000
static u32 A_dmode_memory_to_memory_used[] __attribute((unused)) = {
0x00000005,
0x0000001c,
0x00000027,
0x00000035,
0x00000047,
0x00000069,
0x00000075,
0x000000b2,
0x000000c8,
0x0000012a,
0x00000143,
0x00000199,
0x000001a2,
0x000001d0,
};
#define A_dmode_memory_to_ncr 0x00000000
static u32 A_dmode_memory_to_ncr_used[] __attribute((unused)) = {
0x00000000,
0x00000017,
0x00000030,
0x00000042,
0x0000019d,
};
#define A_dmode_ncr_to_memory 0x00000000
static u32 A_dmode_ncr_to_memory_used[] __attribute((unused)) = {
0x00000022,
0x00000064,
0x00000070,
0x000000ad,
0x000000c3,
0x00000125,
0x0000013e,
0x000001cb,
};
#define A_dsa_check_reselect 0x00000000
static u32 A_dsa_check_reselect_used[] __attribute((unused)) = {
0x000001bd,
};
#define A_dsa_cmdout 0x00000048
static u32 A_dsa_cmdout_used[] __attribute((unused)) = {
0x00000094,
};
#define A_dsa_cmnd 0x00000038
static u32 A_dsa_cmnd_used[] __attribute((unused)) = {
};
#define A_dsa_datain 0x00000054
static u32 A_dsa_datain_used[] __attribute((unused)) = {
0x000000bb,
};
#define A_dsa_dataout 0x00000050
static u32 A_dsa_dataout_used[] __attribute((unused)) = {
0x000000a5,
};
#define A_dsa_end 0x00000070
static u32 A_dsa_end_used[] __attribute((unused)) = {
};
#define A_dsa_fields_start 0x00000000
static u32 A_dsa_fields_start_used[] __attribute((unused)) = {
};
#define A_dsa_msgin 0x00000058
static u32 A_dsa_msgin_used[] __attribute((unused)) = {
0x00000188,
};
#define A_dsa_msgout 0x00000040
static u32 A_dsa_msgout_used[] __attribute((unused)) = {
0x00000086,
};
#define A_dsa_msgout_other 0x00000068
static u32 A_dsa_msgout_other_used[] __attribute((unused)) = {
0x00000180,
};
#define A_dsa_next 0x00000030
static u32 A_dsa_next_used[] __attribute((unused)) = {
0x0000005c,
};
#define A_dsa_restore_pointers 0x00000000
static u32 A_dsa_restore_pointers_used[] __attribute((unused)) = {
0x0000012e,
};
#define A_dsa_save_data_pointer 0x00000000
static u32 A_dsa_save_data_pointer_used[] __attribute((unused)) = {
0x00000115,
};
#define A_dsa_select 0x0000003c
static u32 A_dsa_select_used[] __attribute((unused)) = {
0x00000081,
};
#define A_dsa_status 0x00000060
static u32 A_dsa_status_used[] __attribute((unused)) = {
0x00000184,
};
#define A_dsa_temp_addr_array_value 0x00000000
static u32 A_dsa_temp_addr_array_value_used[] __attribute((unused)) = {
};
#define A_dsa_temp_addr_dsa_value 0x00000000
static u32 A_dsa_temp_addr_dsa_value_used[] __attribute((unused)) = {
0x00000003,
};
#define A_dsa_temp_addr_new_value 0x00000000
static u32 A_dsa_temp_addr_new_value_used[] __attribute((unused)) = {
};
#define A_dsa_temp_addr_next 0x00000000
static u32 A_dsa_temp_addr_next_used[] __attribute((unused)) = {
0x00000015,
0x0000004e,
};
#define A_dsa_temp_addr_residual 0x00000000
static u32 A_dsa_temp_addr_residual_used[] __attribute((unused)) = {
0x0000002a,
0x00000039,
};
#define A_dsa_temp_addr_saved_pointer 0x00000000
static u32 A_dsa_temp_addr_saved_pointer_used[] __attribute((unused)) = {
0x00000026,
0x00000033,
};
#define A_dsa_temp_addr_saved_residual 0x00000000
static u32 A_dsa_temp_addr_saved_residual_used[] __attribute((unused)) = {
0x0000002b,
0x00000038,
};
#define A_dsa_temp_lun 0x00000000
static u32 A_dsa_temp_lun_used[] __attribute((unused)) = {
0x0000004b,
};
#define A_dsa_temp_next 0x00000000
static u32 A_dsa_temp_next_used[] __attribute((unused)) = {
0x0000001a,
};
#define A_dsa_temp_sync 0x00000000
static u32 A_dsa_temp_sync_used[] __attribute((unused)) = {
0x00000053,
};
#define A_dsa_temp_target 0x00000000
static u32 A_dsa_temp_target_used[] __attribute((unused)) = {
0x00000040,
};
#define A_int_debug_break 0x03000000
static u32 A_int_debug_break_used[] __attribute((unused)) = {
0x00000217,
};
#define A_int_debug_panic 0x030b0000
static u32 A_int_debug_panic_used[] __attribute((unused)) = {
0x000001e8,
0x000001f8,
};
#define A_int_err_check_condition 0x00030000
static u32 A_int_err_check_condition_used[] __attribute((unused)) = {
0x00000194,
};
#define A_int_err_no_phase 0x00040000
static u32 A_int_err_no_phase_used[] __attribute((unused)) = {
};
#define A_int_err_selected 0x00010000
static u32 A_int_err_selected_used[] __attribute((unused)) = {
0x000001da,
};
#define A_int_err_unexpected_phase 0x00000000
static u32 A_int_err_unexpected_phase_used[] __attribute((unused)) = {
0x0000008c,
0x00000092,
0x0000009a,
0x000000d0,
0x000000d4,
0x000000d6,
0x000000de,
0x000000e2,
0x000000e4,
0x000000ec,
0x000000f0,
0x000000f2,
0x000000f4,
0x0000014c,
};
#define A_int_err_unexpected_reselect 0x00020000
static u32 A_int_err_unexpected_reselect_used[] __attribute((unused)) = {
0x000001ba,
};
#define A_int_msg_1 0x01020000
static u32 A_int_msg_1_used[] __attribute((unused)) = {
0x0000010e,
0x00000110,
};
#define A_int_msg_sdtr 0x01010000
static u32 A_int_msg_sdtr_used[] __attribute((unused)) = {
0x0000016c,
};
#define A_int_msg_wdtr 0x01000000
static u32 A_int_msg_wdtr_used[] __attribute((unused)) = {
0x00000160,
};
#define A_int_norm_aborted 0x02040000
static u32 A_int_norm_aborted_used[] __attribute((unused)) = {
0x0000024d,
};
#define A_int_norm_command_complete 0x02020000
static u32 A_int_norm_command_complete_used[] __attribute((unused)) = {
};
#define A_int_norm_disconnected 0x02030000
static u32 A_int_norm_disconnected_used[] __attribute((unused)) = {
};
#define A_int_norm_reselect_complete 0x02010000
static u32 A_int_norm_reselect_complete_used[] __attribute((unused)) = {
};
#define A_int_norm_reset 0x02050000
static u32 A_int_norm_reset_used[] __attribute((unused)) = {
};
#define A_int_norm_select_complete 0x02000000
static u32 A_int_norm_select_complete_used[] __attribute((unused)) = {
};
#define A_int_test_1 0x04000000
static u32 A_int_test_1_used[] __attribute((unused)) = {
0x000001fd,
};
#define A_int_test_2 0x04010000
static u32 A_int_test_2_used[] __attribute((unused)) = {
0x00000215,
};
#define A_int_test_3 0x04020000
static u32 A_int_test_3_used[] __attribute((unused)) = {
};
#define A_msg_buf 0x00000000
static u32 A_msg_buf_used[] __attribute((unused)) = {
0x00000102,
0x0000014e,
0x00000158,
0x0000015e,
0x00000164,
0x0000016a,
};
#define A_reconnect_dsa_head 0x00000000
static u32 A_reconnect_dsa_head_used[] __attribute((unused)) = {
0x0000006c,
0x00000074,
0x000001a0,
};
#define A_reselected_identify 0x00000000
static u32 A_reselected_identify_used[] __attribute((unused)) = {
0x00000045,
0x0000019c,
};
#define A_reselected_tag 0x00000000
static u32 A_reselected_tag_used[] __attribute((unused)) = {
};
#define A_schedule 0x00000000
static u32 A_schedule_used[] __attribute((unused)) = {
0x0000007e,
0x00000192,
0x000001e2,
0x0000021f,
};
#define A_test_dest 0x00000000
static u32 A_test_dest_used[] __attribute((unused)) = {
0x000001fb,
};
#define A_test_src 0x00000000
static u32 A_test_src_used[] __attribute((unused)) = {
0x000001fa,
};
#define Ent_accept_message 0x000005d4
#define Ent_cmdout_cmdout 0x0000024c
#define Ent_command_complete 0x0000060c
#define Ent_command_complete_msgin 0x0000061c
#define Ent_data_transfer 0x00000254
#define Ent_datain_to_jump 0x00000328
#define Ent_debug_break 0x00000858
#define Ent_dsa_code_begin 0x00000000
#define Ent_dsa_code_check_reselect 0x000000f8
#define Ent_dsa_code_fix_jump 0x0000003c
#define Ent_dsa_code_restore_pointers 0x000000c0
#define Ent_dsa_code_save_data_pointer 0x00000088
#define Ent_dsa_code_template 0x00000000
#define Ent_dsa_code_template_end 0x00000168
#define Ent_dsa_schedule 0x00000168
#define Ent_dsa_zero 0x00000168
#define Ent_end_data_transfer 0x0000028c
#define Ent_initiator_abort 0x00000880
#define Ent_msg_in 0x00000404
#define Ent_msg_in_restart 0x000003e4
#define Ent_other_in 0x00000374
#define Ent_other_out 0x0000033c
#define Ent_other_transfer 0x000003ac
#define Ent_reject_message 0x000005b4
#define Ent_reselected_check_next 0x000006a4
#define Ent_reselected_ok 0x00000750
#define Ent_respond_message 0x000005ec
#define Ent_select 0x000001fc
#define Ent_select_msgout 0x00000214
#define Ent_target_abort 0x00000860
#define Ent_test_1 0x000007e4
#define Ent_test_2 0x000007f8
#define Ent_test_2_msgout 0x00000810
#define Ent_wait_reselect 0x00000654
static u32 LABELPATCHES[] __attribute((unused)) = {
0x00000008,
0x0000000a,
0x00000013,
0x00000016,
0x0000001f,
0x00000021,
0x0000004f,
0x00000051,
0x0000005b,
0x00000068,
0x0000006f,
0x00000082,
0x00000084,
0x0000008a,
0x0000008e,
0x00000090,
0x00000096,
0x00000098,
0x0000009c,
0x0000009e,
0x000000a0,
0x000000a2,
0x000000a4,
0x000000b1,
0x000000b6,
0x000000ba,
0x000000c7,
0x000000cc,
0x000000d2,
0x000000d8,
0x000000da,
0x000000e0,
0x000000e6,
0x000000e8,
0x000000ee,
0x000000f6,
0x000000f8,
0x00000104,
0x00000106,
0x00000108,
0x0000010a,
0x0000010c,
0x00000112,
0x00000114,
0x00000129,
0x00000142,
0x00000148,
0x00000150,
0x00000152,
0x00000154,
0x0000015a,
0x00000166,
0x00000196,
0x000001a5,
0x000001a8,
0x000001ac,
0x000001b0,
0x000001b4,
0x000001b8,
0x000001cf,
0x000001de,
0x000001e6,
0x000001ec,
0x000001ee,
0x000001f2,
0x000001f6,
0x00000201,
0x00000203,
0x00000223,
0x00000225,
0x00000227,
0x00000229,
0x0000022b,
0x0000022d,
0x00000231,
0x00000235,
0x00000237,
0x0000023b,
0x0000023d,
0x00000241,
0x00000243,
};
static struct {
u32 offset;
void *address;
} EXTERNAL_PATCHES[] __attribute((unused)) = {
};
static u32 INSTRUCTIONS __attribute((unused)) = 301;
static u32 PATCHES __attribute((unused)) = 81;
static u32 EXTERNAL_PATCHES_LEN __attribute((unused)) = 0;
drivers/scsi/53c8xx_u.h_shipped deleted 100644 → 0
View file @ 53e20c84
#undef A_NCR53c7xx_msg_abort
#undef A_NCR53c7xx_msg_reject
#undef A_NCR53c7xx_sink
#undef A_NCR53c7xx_zero
#undef A_NOP_insn
#undef A_addr_reconnect_dsa_head
#undef A_addr_scratch
#undef A_addr_temp
#undef A_dmode_memory_to_memory
#undef A_dmode_memory_to_ncr
#undef A_dmode_ncr_to_memory
#undef A_dsa_check_reselect
#undef A_dsa_cmdout
#undef A_dsa_cmnd
#undef A_dsa_datain
#undef A_dsa_dataout
#undef A_dsa_end
#undef A_dsa_fields_start
#undef A_dsa_msgin
#undef A_dsa_msgout
#undef A_dsa_msgout_other
#undef A_dsa_next
#undef A_dsa_restore_pointers
#undef A_dsa_save_data_pointer
#undef A_dsa_select
#undef A_dsa_status
#undef A_dsa_temp_addr_array_value
#undef A_dsa_temp_addr_dsa_value
#undef A_dsa_temp_addr_new_value
#undef A_dsa_temp_addr_next
#undef A_dsa_temp_addr_residual
#undef A_dsa_temp_addr_saved_pointer
#undef A_dsa_temp_addr_saved_residual
#undef A_dsa_temp_lun
#undef A_dsa_temp_next
#undef A_dsa_temp_sync
#undef A_dsa_temp_target
#undef A_int_debug_break
#undef A_int_debug_panic
#undef A_int_err_check_condition
#undef A_int_err_no_phase
#undef A_int_err_selected
#undef A_int_err_unexpected_phase
#undef A_int_err_unexpected_reselect
#undef A_int_msg_1
#undef A_int_msg_sdtr
#undef A_int_msg_wdtr
#undef A_int_norm_aborted
#undef A_int_norm_command_complete
#undef A_int_norm_disconnected
#undef A_int_norm_reselect_complete
#undef A_int_norm_reset
#undef A_int_norm_select_complete
#undef A_int_test_1
#undef A_int_test_2
#undef A_int_test_3
#undef A_msg_buf
#undef A_reconnect_dsa_head
#undef A_reselected_identify
#undef A_reselected_tag
#undef A_schedule
#undef A_test_dest
#undef A_test_src
#undef Ent_accept_message
#undef Ent_cmdout_cmdout
#undef Ent_command_complete
#undef Ent_command_complete_msgin
#undef Ent_data_transfer
#undef Ent_datain_to_jump
#undef Ent_debug_break
#undef Ent_dsa_code_begin
#undef Ent_dsa_code_check_reselect
#undef Ent_dsa_code_fix_jump
#undef Ent_dsa_code_restore_pointers
#undef Ent_dsa_code_save_data_pointer
#undef Ent_dsa_code_template
#undef Ent_dsa_code_template_end
#undef Ent_dsa_schedule
#undef Ent_dsa_zero
#undef Ent_end_data_transfer
#undef Ent_initiator_abort
#undef Ent_msg_in
#undef Ent_msg_in_restart
#undef Ent_other_in
#undef Ent_other_out
#undef Ent_other_transfer
#undef Ent_reject_message
#undef Ent_reselected_check_next
#undef Ent_reselected_ok
#undef Ent_respond_message
#undef Ent_select
#undef Ent_select_msgout
#undef Ent_target_abort
#undef Ent_test_1
#undef Ent_test_2
#undef Ent_test_2_msgout
#undef Ent_wait_reselect
drivers/scsi/Makefile
View file @ 0b788f20
......@@ -78,7 +78,6 @@ obj-$(CONFIG_SCSI_FD_8xx) += seagate.o
obj-$(CONFIG_SCSI_T128) += t128.o
obj-$(CONFIG_SCSI_DMX3191D) += dmx3191d.o
obj-$(CONFIG_SCSI_DTC3280) += dtc.o
obj-$(CONFIG_SCSI_NCR53C7xx) += 53c7,8xx.o
obj-$(CONFIG_SCSI_SYM53C8XX_2) += sym53c8xx_2/
obj-$(CONFIG_SCSI_SYM53C8XX) += sym53c8xx.o
obj-$(CONFIG_SCSI_NCR53C8XX) += ncr53c8xx.o
......@@ -139,10 +138,9 @@ cpqfc-objs := cpqfcTSinit.o cpqfcTScontrol.o cpqfcTSi2c.o \
cpqfcTSworker.o cpqfcTStrigger.o
# Files generated that shall be removed upon make clean
clean-files := 53c8xx_d.h 53c7xx_d.h 53c700_d.h \
53c8xx_u.h 53c7xx_u.h 53c700_u.h
clean-files := 53c7xx_d.h 53c700_d.h \
53c7xx_u.h 53c700_u.h
$(obj)/53c7,8xx.o: $(obj)/53c8xx_d.h $(obj)/53c8xx_u.h
$(obj)/53c7xx.o: $(obj)/53c7xx_d.h $(obj)/53c7xx_u.h
$(obj)/53c700.o $(MODVERDIR)/$(obj)/53c700.ver: $(obj)/53c700_d.h
......@@ -151,11 +149,6 @@ $(obj)/53c700.o $(MODVERDIR)/$(obj)/53c700.ver: $(obj)/53c700_d.h
ifdef GENERATE_FIRMWARE
$(obj)/53c8xx_d.h: $(src)/53c7,8xx.scr $(src)/script_asm.pl
$(CPP) -traditional -DCHIP=810 - < $< | grep -v '^#' | $(PERL) $(src)/script_asm.pl $@ $(@:_d.h=_u.h)
$(obj)/53c8xx_u.h: $(obj)/53c8xx_d.h
$(obj)/53c7xx_d.h: $(src)/53c7xx.scr $(src)/script_asm.pl
$(CPP) -traditional -DCHIP=710 - < $< | grep -v '^#' | $(PERL) -s $(src)/script_asm.pl -ncr7x0_family $@ $(@:_d.h=_u.h)
......
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