Commit 0bd3fbd4 authored by Linus Torvalds's avatar Linus Torvalds

Merge git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6

Pull crypto updates from Herbert Xu:
 - New cipher/hash driver for ARM ux500.
 - Code clean-up for aesni-intel.
 - Misc fixes.

Fixed up conflicts in arch/arm/mach-ux500/devices-common.h, where quite
frankly some of it made no sense at all (the pull brought in a
declaration for the dbx500_add_platform_device_noirq() function, which
neither exists nor is used anywhere).

Also some trivial add-add context conflicts in the Kconfig file in
drivers/{char/hw_random,crypto}/

* git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6:
  crypto: aesni-intel - move more common code to ablk_init_common
  crypto: aesni-intel - use crypto_[un]register_algs
  crypto: ux500 - Cleanup hardware identification
  crypto: ux500 - Update DMA handling for 3.4
  mach-ux500: crypto - core support for CRYP/HASH module.
  crypto: ux500 - Add driver for HASH hardware
  crypto: ux500 - Add driver for CRYP hardware
  hwrng: Kconfig - modify default state for atmel-rng driver
  hwrng: omap - use devm_request_and_ioremap
  crypto: crypto4xx - move up err_request_irq label
  crypto, xor: Sanitize checksumming function selection output
  crypto: caam - add backward compatible string sec4.0
parents 0b87da68 ef45b834
......@@ -47,6 +47,7 @@
#include <mach/setup.h>
#include <mach/devices.h>
#include <mach/irqs.h>
#include <mach/crypto-ux500.h>
#include "ste-dma40-db8500.h"
#include "devices-db8500.h"
......@@ -417,6 +418,45 @@ static void mop500_prox_deactivate(struct device *dev)
regulator_put(prox_regulator);
}
static struct cryp_platform_data u8500_cryp1_platform_data = {
.mem_to_engine = {
.dir = STEDMA40_MEM_TO_PERIPH,
.src_dev_type = STEDMA40_DEV_SRC_MEMORY,
.dst_dev_type = DB8500_DMA_DEV48_CAC1_TX,
.src_info.data_width = STEDMA40_WORD_WIDTH,
.dst_info.data_width = STEDMA40_WORD_WIDTH,
.mode = STEDMA40_MODE_LOGICAL,
.src_info.psize = STEDMA40_PSIZE_LOG_4,
.dst_info.psize = STEDMA40_PSIZE_LOG_4,
},
.engine_to_mem = {
.dir = STEDMA40_PERIPH_TO_MEM,
.src_dev_type = DB8500_DMA_DEV48_CAC1_RX,
.dst_dev_type = STEDMA40_DEV_DST_MEMORY,
.src_info.data_width = STEDMA40_WORD_WIDTH,
.dst_info.data_width = STEDMA40_WORD_WIDTH,
.mode = STEDMA40_MODE_LOGICAL,
.src_info.psize = STEDMA40_PSIZE_LOG_4,
.dst_info.psize = STEDMA40_PSIZE_LOG_4,
}
};
static struct stedma40_chan_cfg u8500_hash_dma_cfg_tx = {
.dir = STEDMA40_MEM_TO_PERIPH,
.src_dev_type = STEDMA40_DEV_SRC_MEMORY,
.dst_dev_type = DB8500_DMA_DEV50_HAC1_TX,
.src_info.data_width = STEDMA40_WORD_WIDTH,
.dst_info.data_width = STEDMA40_WORD_WIDTH,
.mode = STEDMA40_MODE_LOGICAL,
.src_info.psize = STEDMA40_PSIZE_LOG_16,
.dst_info.psize = STEDMA40_PSIZE_LOG_16,
};
static struct hash_platform_data u8500_hash1_platform_data = {
.mem_to_engine = &u8500_hash_dma_cfg_tx,
.dma_filter = stedma40_filter,
};
/* add any platform devices here - TODO */
static struct platform_device *mop500_platform_devs[] __initdata = {
&mop500_gpio_keys_device,
......@@ -624,6 +664,12 @@ static void __init mop500_uart_init(struct device *parent)
db8500_add_uart2(parent, &uart2_plat);
}
static void __init u8500_cryp1_hash1_init(struct device *parent)
{
db8500_add_cryp1(parent, &u8500_cryp1_platform_data);
db8500_add_hash1(parent, &u8500_hash1_platform_data);
}
static struct platform_device *snowball_platform_devs[] __initdata = {
&snowball_led_dev,
&snowball_key_dev,
......@@ -654,6 +700,8 @@ static void __init mop500_init_machine(void)
mop500_msp_init(parent);
mop500_uart_init(parent);
u8500_cryp1_hash1_init(parent);
i2c0_devs = ARRAY_SIZE(mop500_i2c0_devices);
i2c_register_board_info(0, mop500_i2c0_devices, i2c0_devs);
......
......@@ -381,14 +381,15 @@ static DEFINE_PRCC_CLK(5, usb, 0, 0, NULL);
/* Peripheral Cluster #6 */
/* MTU ID in data */
static DEFINE_PRCC_CLK_CUSTOM(6, mtu1, 8, -1, NULL, clk_mtu_get_rate, 1);
static DEFINE_PRCC_CLK_CUSTOM(6, mtu0, 7, -1, NULL, clk_mtu_get_rate, 0);
static DEFINE_PRCC_CLK(6, cfgreg, 6, 6, NULL);
static DEFINE_PRCC_CLK(6, hash1, 5, -1, NULL);
static DEFINE_PRCC_CLK(6, unipro, 4, 1, &clk_uniproclk);
static DEFINE_PRCC_CLK(6, pka, 3, -1, NULL);
static DEFINE_PRCC_CLK(6, hash0, 2, -1, NULL);
static DEFINE_PRCC_CLK(6, cryp0, 1, -1, NULL);
static DEFINE_PRCC_CLK_CUSTOM(6, mtu1, 9, -1, NULL, clk_mtu_get_rate, 1);
static DEFINE_PRCC_CLK_CUSTOM(6, mtu0, 8, -1, NULL, clk_mtu_get_rate, 0);
static DEFINE_PRCC_CLK(6, cfgreg, 7, 7, NULL);
static DEFINE_PRCC_CLK(6, hash1, 6, -1, NULL);
static DEFINE_PRCC_CLK(6, unipro, 5, 1, &clk_uniproclk);
static DEFINE_PRCC_CLK(6, pka, 4, -1, NULL);
static DEFINE_PRCC_CLK(6, hash0, 3, -1, NULL);
static DEFINE_PRCC_CLK(6, cryp0, 2, -1, NULL);
static DEFINE_PRCC_CLK(6, cryp1, 1, -1, NULL);
static DEFINE_PRCC_CLK(6, rng, 0, 0, &clk_rngclk);
static struct clk clk_dummy_apb_pclk = {
......@@ -430,6 +431,7 @@ static struct clk_lookup u8500_clks[] = {
CLK(pka, "pka", NULL),
CLK(hash0, "hash0", NULL),
CLK(cryp0, "cryp0", NULL),
CLK(cryp1, "cryp1", NULL),
/* PRCMU level clock gating */
......
......@@ -13,6 +13,7 @@
#include <linux/sys_soc.h>
#include <linux/amba/bus.h>
#include <plat/i2c.h>
#include <mach/crypto-ux500.h>
struct spi_master_cntlr;
......@@ -85,6 +86,55 @@ dbx500_add_rtc(struct device *parent, resource_size_t base, int irq)
0, NULL, 0);
}
struct cryp_platform_data;
static inline struct platform_device *
dbx500_add_cryp1(struct device *parent, int id, resource_size_t base, int irq,
struct cryp_platform_data *pdata)
{
struct resource res[] = {
DEFINE_RES_MEM(base, SZ_4K),
DEFINE_RES_IRQ(irq),
};
struct platform_device_info pdevinfo = {
.parent = parent,
.name = "cryp1",
.id = id,
.res = res,
.num_res = ARRAY_SIZE(res),
.data = pdata,
.size_data = sizeof(*pdata),
.dma_mask = DMA_BIT_MASK(32),
};
return platform_device_register_full(&pdevinfo);
}
struct hash_platform_data;
static inline struct platform_device *
dbx500_add_hash1(struct device *parent, int id, resource_size_t base,
struct hash_platform_data *pdata)
{
struct resource res[] = {
DEFINE_RES_MEM(base, SZ_4K),
};
struct platform_device_info pdevinfo = {
.parent = parent,
.name = "hash1",
.id = id,
.res = res,
.num_res = ARRAY_SIZE(res),
.data = pdata,
.size_data = sizeof(*pdata),
.dma_mask = DMA_BIT_MASK(32),
};
return platform_device_register_full(&pdevinfo);
}
struct nmk_gpio_platform_data;
void dbx500_add_gpios(struct device *parent, resource_size_t *base, int num,
......
......@@ -104,6 +104,8 @@ static const dma_addr_t dma40_tx_map[DB8500_DMA_NR_DEV] = {
[DB8500_DMA_DEV14_MSP2_TX] = U8500_MSP2_BASE + MSP_TX_RX_REG_OFFSET,
[DB8500_DMA_DEV30_MSP1_TX] = U8500_MSP1_BASE + MSP_TX_RX_REG_OFFSET,
[DB8500_DMA_DEV31_MSP0_TX_SLIM0_CH0_TX] = U8500_MSP0_BASE + MSP_TX_RX_REG_OFFSET,
[DB8500_DMA_DEV48_CAC1_TX] = U8500_CRYP1_BASE + CRYP1_TX_REG_OFFSET,
[DB8500_DMA_DEV50_HAC1_TX] = U8500_HASH1_BASE + HASH1_TX_REG_OFFSET,
};
/* Mapping between source event lines and physical device address */
......@@ -139,6 +141,7 @@ static const dma_addr_t dma40_rx_map[DB8500_DMA_NR_DEV] = {
[DB8500_DMA_DEV14_MSP2_RX] = U8500_MSP2_BASE + MSP_TX_RX_REG_OFFSET,
[DB8500_DMA_DEV30_MSP3_RX] = U8500_MSP3_BASE + MSP_TX_RX_REG_OFFSET,
[DB8500_DMA_DEV31_MSP0_RX_SLIM0_CH0_RX] = U8500_MSP0_BASE + MSP_TX_RX_REG_OFFSET,
[DB8500_DMA_DEV48_CAC1_RX] = U8500_CRYP1_BASE + CRYP1_RX_REG_OFFSET,
};
/* Reserved event lines for memcpy only */
......
......@@ -114,4 +114,8 @@ db8500_add_ssp(struct device *parent, const char *name, resource_size_t base,
dbx500_add_uart(parent, "uart2", U8500_UART2_BASE, \
IRQ_DB8500_UART2, pdata)
#define db8500_add_cryp1(parent, pdata) \
dbx500_add_cryp1(parent, -1, U8500_CRYP1_BASE, IRQ_DB8500_CRYP1, pdata)
#define db8500_add_hash1(parent, pdata) \
dbx500_add_hash1(parent, -1, U8500_HASH1_BASE, pdata)
#endif
/*
* Copyright (C) ST-Ericsson SA 2011
*
* Author: Joakim Bech <joakim.xx.bech@stericsson.com> for ST-Ericsson
* License terms: GNU General Public License (GPL) version 2
*/
#ifndef _CRYPTO_UX500_H
#define _CRYPTO_UX500_H
#include <linux/dmaengine.h>
#include <plat/ste_dma40.h>
struct hash_platform_data {
void *mem_to_engine;
bool (*dma_filter)(struct dma_chan *chan, void *filter_param);
};
struct cryp_platform_data {
struct stedma40_chan_cfg mem_to_engine;
struct stedma40_chan_cfg engine_to_mem;
};
#endif
......@@ -14,6 +14,9 @@ extern struct platform_device u8500_gpio_devs[];
extern struct amba_device ux500_pl031_device;
extern struct platform_device ux500_hash1_device;
extern struct platform_device ux500_cryp1_device;
extern struct platform_device u8500_dma40_device;
extern struct platform_device ux500_ske_keypad_device;
......
......@@ -33,6 +33,9 @@
#include <mach/db8500-regs.h>
#define MSP_TX_RX_REG_OFFSET 0
#define CRYP1_RX_REG_OFFSET 0x10
#define CRYP1_TX_REG_OFFSET 0x8
#define HASH1_TX_REG_OFFSET 0x4
#ifndef __ASSEMBLY__
......
This diff is collapsed.
......@@ -129,9 +129,9 @@ calibrate_xor_blocks(void)
if (fastest) {
printk(KERN_INFO "xor: automatically using best "
"checksumming function: %s\n",
fastest->name);
"checksumming function:\n");
xor_speed(fastest);
goto out;
} else {
printk(KERN_INFO "xor: measuring software checksum speed\n");
XOR_TRY_TEMPLATES;
......@@ -146,6 +146,7 @@ calibrate_xor_blocks(void)
#undef xor_speed
out:
free_pages((unsigned long)b1, 2);
active_template = fastest;
......
......@@ -63,7 +63,7 @@ config HW_RANDOM_AMD
config HW_RANDOM_ATMEL
tristate "Atmel Random Number Generator support"
depends on HW_RANDOM && HAVE_CLK
default HW_RANDOM
default (HW_RANDOM && ARCH_AT91)
---help---
This driver provides kernel-side support for the Random Number
Generator hardware found on Atmel AT91 devices.
......
......@@ -115,22 +115,12 @@ static int __devinit omap_rng_probe(struct platform_device *pdev)
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!res) {
ret = -ENOENT;
goto err_region;
}
if (!request_mem_region(res->start, resource_size(res), pdev->name)) {
ret = -EBUSY;
goto err_region;
}
dev_set_drvdata(&pdev->dev, res);
rng_base = ioremap(res->start, resource_size(res));
rng_base = devm_request_and_ioremap(&pdev->dev, res);
if (!rng_base) {
ret = -ENOMEM;
goto err_ioremap;
}
dev_set_drvdata(&pdev->dev, res);
ret = hwrng_register(&omap_rng_ops);
if (ret)
......@@ -145,11 +135,8 @@ static int __devinit omap_rng_probe(struct platform_device *pdev)
return 0;
err_register:
iounmap(rng_base);
rng_base = NULL;
err_ioremap:
release_mem_region(res->start, resource_size(res));
err_region:
if (cpu_is_omap24xx()) {
clk_disable(rng_ick);
clk_put(rng_ick);
......@@ -159,20 +146,15 @@ static int __devinit omap_rng_probe(struct platform_device *pdev)
static int __exit omap_rng_remove(struct platform_device *pdev)
{
struct resource *res = dev_get_drvdata(&pdev->dev);
hwrng_unregister(&omap_rng_ops);
omap_rng_write_reg(RNG_MASK_REG, 0x0);
iounmap(rng_base);
if (cpu_is_omap24xx()) {
clk_disable(rng_ick);
clk_put(rng_ick);
}
release_mem_region(res->start, resource_size(res));
rng_base = NULL;
return 0;
......
......@@ -314,4 +314,15 @@ config CRYPTO_DEV_NX
module supports acceleration for AES and SHA2 algorithms. If you
choose 'M' here, this module will be called nx_crypto.
config CRYPTO_DEV_UX500
tristate "Driver for ST-Ericsson UX500 crypto hardware acceleration"
depends on ARCH_U8500
select CRYPTO_ALGAPI
help
Driver for ST-Ericsson UX500 crypto engine.
if CRYPTO_DEV_UX500
source "drivers/crypto/ux500/Kconfig"
endif # if CRYPTO_DEV_UX500
endif # CRYPTO_HW
......@@ -14,3 +14,4 @@ obj-$(CONFIG_CRYPTO_DEV_OMAP_AES) += omap-aes.o
obj-$(CONFIG_CRYPTO_DEV_PICOXCELL) += picoxcell_crypto.o
obj-$(CONFIG_CRYPTO_DEV_S5P) += s5p-sss.o
obj-$(CONFIG_CRYPTO_DEV_TEGRA_AES) += tegra-aes.o
obj-$(CONFIG_CRYPTO_DEV_UX500) += ux500/
\ No newline at end of file
......@@ -1244,9 +1244,9 @@ static int __init crypto4xx_probe(struct platform_device *ofdev)
iounmap(core_dev->dev->ce_base);
err_iomap:
free_irq(core_dev->irq, dev);
err_request_irq:
irq_dispose_mapping(core_dev->irq);
tasklet_kill(&core_dev->tasklet);
err_request_irq:
crypto4xx_destroy_sdr(core_dev->dev);
err_build_sdr:
crypto4xx_destroy_gdr(core_dev->dev);
......
......@@ -2267,8 +2267,11 @@ static void __exit caam_algapi_exit(void)
int i, err;
dev_node = of_find_compatible_node(NULL, NULL, "fsl,sec-v4.0");
if (!dev_node) {
dev_node = of_find_compatible_node(NULL, NULL, "fsl,sec4.0");
if (!dev_node)
return;
}
pdev = of_find_device_by_node(dev_node);
if (!pdev)
......@@ -2350,8 +2353,11 @@ static int __init caam_algapi_init(void)
int i = 0, err = 0;
dev_node = of_find_compatible_node(NULL, NULL, "fsl,sec-v4.0");
if (!dev_node) {
dev_node = of_find_compatible_node(NULL, NULL, "fsl,sec4.0");
if (!dev_node)
return -ENODEV;
}
pdev = of_find_device_by_node(dev_node);
if (!pdev)
......
......@@ -98,6 +98,12 @@ static int caam_probe(struct platform_device *pdev)
rspec = 0;
for_each_compatible_node(np, NULL, "fsl,sec-v4.0-job-ring")
rspec++;
if (!rspec) {
/* for backward compatible with device trees */
for_each_compatible_node(np, NULL, "fsl,sec4.0-job-ring")
rspec++;
}
ctrlpriv->jrdev = kzalloc(sizeof(struct device *) * rspec, GFP_KERNEL);
if (ctrlpriv->jrdev == NULL) {
iounmap(&topregs->ctrl);
......@@ -111,6 +117,13 @@ static int caam_probe(struct platform_device *pdev)
ctrlpriv->total_jobrs++;
ring++;
}
if (!ring) {
for_each_compatible_node(np, NULL, "fsl,sec4.0-job-ring") {
caam_jr_probe(pdev, np, ring);
ctrlpriv->total_jobrs++;
ring++;
}
}
/* Check to see if QI present. If so, enable */
ctrlpriv->qi_present = !!(rd_reg64(&topregs->ctrl.perfmon.comp_parms) &
......@@ -226,6 +239,9 @@ static struct of_device_id caam_match[] = {
{
.compatible = "fsl,sec-v4.0",
},
{
.compatible = "fsl,sec4.0",
},
{},
};
MODULE_DEVICE_TABLE(of, caam_match);
......
#
# Copyright (C) ST-Ericsson SA 2010
# Author: Shujuan Chen (shujuan.chen@stericsson.com)
# License terms: GNU General Public License (GPL) version 2
#
config CRYPTO_DEV_UX500_CRYP
tristate "UX500 crypto driver for CRYP block"
depends on CRYPTO_DEV_UX500
select CRYPTO_DES
help
This selects the crypto driver for the UX500_CRYP hardware. It supports
AES-ECB, CBC and CTR with keys sizes of 128, 192 and 256 bit sizes.
config CRYPTO_DEV_UX500_HASH
tristate "UX500 crypto driver for HASH block"
depends on CRYPTO_DEV_UX500
select CRYPTO_HASH
select CRYPTO_HMAC
help
This selects the hash driver for the UX500_HASH hardware.
Depends on UX500/STM DMA if running in DMA mode.
config CRYPTO_DEV_UX500_DEBUG
bool "Activate ux500 platform debug-mode for crypto and hash block"
depends on CRYPTO_DEV_UX500_CRYP || CRYPTO_DEV_UX500_HASH
default n
help
Say Y if you want to add debug prints to ux500_hash and
ux500_cryp devices.
#
# Copyright (C) ST-Ericsson SA 2010
# Author: Shujuan Chen (shujuan.chen@stericsson.com)
# License terms: GNU General Public License (GPL) version 2
#
obj-$(CONFIG_CRYPTO_DEV_UX500_HASH) += hash/
obj-$(CONFIG_CRYPTO_DEV_UX500_CRYP) += cryp/
#/*
# * Copyright (C) ST-Ericsson SA 2010
# * Author: shujuan.chen@stericsson.com for ST-Ericsson.
# * License terms: GNU General Public License (GPL) version 2 */
ifdef CONFIG_CRYPTO_DEV_UX500_DEBUG
CFLAGS_cryp_core.o := -DDEBUG -O0
CFLAGS_cryp.o := -DDEBUG -O0
CFLAGS_cryp_irq.o := -DDEBUG -O0
endif
obj-$(CONFIG_CRYPTO_DEV_UX500_CRYP) += ux500_cryp.o
ux500_cryp-objs := cryp.o cryp_irq.o cryp_core.o
This diff is collapsed.
/**
* Copyright (C) ST-Ericsson SA 2010
* Author: Shujuan Chen <shujuan.chen@stericsson.com> for ST-Ericsson.
* Author: Jonas Linde <jonas.linde@stericsson.com> for ST-Ericsson.
* Author: Joakim Bech <joakim.xx.bech@stericsson.com> for ST-Ericsson.
* Author: Berne Hebark <berne.herbark@stericsson.com> for ST-Ericsson.
* Author: Niklas Hernaeus <niklas.hernaeus@stericsson.com> for ST-Ericsson.
* License terms: GNU General Public License (GPL) version 2
*/
#ifndef _CRYP_H_
#define _CRYP_H_
#include <linux/completion.h>
#include <linux/dmaengine.h>
#include <linux/klist.h>
#include <linux/mutex.h>
#define DEV_DBG_NAME "crypX crypX:"
/* CRYP enable/disable */
enum cryp_crypen {
CRYP_CRYPEN_DISABLE = 0,
CRYP_CRYPEN_ENABLE = 1
};
/* CRYP Start Computation enable/disable */
enum cryp_start {
CRYP_START_DISABLE = 0,
CRYP_START_ENABLE = 1
};
/* CRYP Init Signal enable/disable */
enum cryp_init {
CRYP_INIT_DISABLE = 0,
CRYP_INIT_ENABLE = 1
};
/* Cryp State enable/disable */
enum cryp_state {
CRYP_STATE_DISABLE = 0,
CRYP_STATE_ENABLE = 1
};
/* Key preparation bit enable */
enum cryp_key_prep {
KSE_DISABLED = 0,
KSE_ENABLED = 1
};
/* Key size for AES */
#define CRYP_KEY_SIZE_128 (0)
#define CRYP_KEY_SIZE_192 (1)
#define CRYP_KEY_SIZE_256 (2)
/* AES modes */
enum cryp_algo_mode {
CRYP_ALGO_TDES_ECB,
CRYP_ALGO_TDES_CBC,
CRYP_ALGO_DES_ECB,
CRYP_ALGO_DES_CBC,
CRYP_ALGO_AES_ECB,
CRYP_ALGO_AES_CBC,
CRYP_ALGO_AES_CTR,
CRYP_ALGO_AES_XTS
};
/* Cryp Encryption or Decryption */
enum cryp_algorithm_dir {
CRYP_ALGORITHM_ENCRYPT,
CRYP_ALGORITHM_DECRYPT
};
/* Hardware access method */
enum cryp_mode {
CRYP_MODE_POLLING,
CRYP_MODE_INTERRUPT,
CRYP_MODE_DMA
};
/**
* struct cryp_config -
* @keysize: Key size for AES
* @algomode: AES modes
* @algodir: Cryp Encryption or Decryption
*
* CRYP configuration structure to be passed to set configuration
*/
struct cryp_config {
int keysize;
enum cryp_algo_mode algomode;
enum cryp_algorithm_dir algodir;
};
/**
* struct cryp_protection_config -
* @privilege_access: Privileged cryp state enable/disable
* @secure_access: Secure cryp state enable/disable
*
* Protection configuration structure for setting privilage access
*/
struct cryp_protection_config {
enum cryp_state privilege_access;
enum cryp_state secure_access;
};
/* Cryp status */
enum cryp_status_id {
CRYP_STATUS_BUSY = 0x10,
CRYP_STATUS_OUTPUT_FIFO_FULL = 0x08,
CRYP_STATUS_OUTPUT_FIFO_NOT_EMPTY = 0x04,
CRYP_STATUS_INPUT_FIFO_NOT_FULL = 0x02,
CRYP_STATUS_INPUT_FIFO_EMPTY = 0x01
};
/* Cryp DMA interface */
enum cryp_dma_req_type {
CRYP_DMA_DISABLE_BOTH,
CRYP_DMA_ENABLE_IN_DATA,
CRYP_DMA_ENABLE_OUT_DATA,
CRYP_DMA_ENABLE_BOTH_DIRECTIONS
};
enum cryp_dma_channel {
CRYP_DMA_RX = 0,
CRYP_DMA_TX
};
/* Key registers */
enum cryp_key_reg_index {
CRYP_KEY_REG_1,
CRYP_KEY_REG_2,
CRYP_KEY_REG_3,
CRYP_KEY_REG_4
};
/* Key register left and right */
struct cryp_key_value {
u32 key_value_left;
u32 key_value_right;
};
/* Cryp Initialization structure */
enum cryp_init_vector_index {
CRYP_INIT_VECTOR_INDEX_0,
CRYP_INIT_VECTOR_INDEX_1
};
/* struct cryp_init_vector_value -
* @init_value_left
* @init_value_right
* */
struct cryp_init_vector_value {
u32 init_value_left;
u32 init_value_right;
};
/**
* struct cryp_device_context - structure for a cryp context.
* @cr: control register
* @dmacr: DMA control register
* @imsc: Interrupt mask set/clear register
* @key_1_l: Key 1l register
* @key_1_r: Key 1r register
* @key_2_l: Key 2l register
* @key_2_r: Key 2r register
* @key_3_l: Key 3l register
* @key_3_r: Key 3r register
* @key_4_l: Key 4l register
* @key_4_r: Key 4r register
* @init_vect_0_l: Initialization vector 0l register
* @init_vect_0_r: Initialization vector 0r register
* @init_vect_1_l: Initialization vector 1l register
* @init_vect_1_r: Initialization vector 0r register
* @din: Data in register
* @dout: Data out register
*
* CRYP power management specifc structure.
*/
struct cryp_device_context {
u32 cr;
u32 dmacr;
u32 imsc;
u32 key_1_l;
u32 key_1_r;
u32 key_2_l;
u32 key_2_r;
u32 key_3_l;
u32 key_3_r;
u32 key_4_l;
u32 key_4_r;
u32 init_vect_0_l;
u32 init_vect_0_r;
u32 init_vect_1_l;
u32 init_vect_1_r;
u32 din;
u32 dout;
};
struct cryp_dma {
dma_cap_mask_t mask;
struct completion cryp_dma_complete;
struct dma_chan *chan_cryp2mem;
struct dma_chan *chan_mem2cryp;
struct stedma40_chan_cfg *cfg_cryp2mem;
struct stedma40_chan_cfg *cfg_mem2cryp;
int sg_src_len;
int sg_dst_len;
struct scatterlist *sg_src;
struct scatterlist *sg_dst;
int nents_src;
int nents_dst;
};
/**
* struct cryp_device_data - structure for a cryp device.
* @base: Pointer to the hardware base address.
* @dev: Pointer to the devices dev structure.
* @clk: Pointer to the device's clock control.
* @pwr_regulator: Pointer to the device's power control.
* @power_status: Current status of the power.
* @ctx_lock: Lock for current_ctx.
* @current_ctx: Pointer to the currently allocated context.
* @list_node: For inclusion into a klist.
* @dma: The dma structure holding channel configuration.
* @power_state: TRUE = power state on, FALSE = power state off.
* @power_state_spinlock: Spinlock for power_state.
* @restore_dev_ctx: TRUE = saved ctx, FALSE = no saved ctx.
*/
struct cryp_device_data {
struct cryp_register __iomem *base;
struct device *dev;
struct clk *clk;
struct regulator *pwr_regulator;
int power_status;
struct spinlock ctx_lock;
struct cryp_ctx *current_ctx;
struct klist_node list_node;
struct cryp_dma dma;
bool power_state;
struct spinlock power_state_spinlock;
bool restore_dev_ctx;
};
void cryp_wait_until_done(struct cryp_device_data *device_data);
/* Initialization functions */
int cryp_check(struct cryp_device_data *device_data);
void cryp_activity(struct cryp_device_data *device_data,
enum cryp_crypen cryp_crypen);
void cryp_flush_inoutfifo(struct cryp_device_data *device_data);
int cryp_set_configuration(struct cryp_device_data *device_data,
struct cryp_config *cryp_config,
u32 *control_register);
void cryp_configure_for_dma(struct cryp_device_data *device_data,
enum cryp_dma_req_type dma_req);
int cryp_configure_key_values(struct cryp_device_data *device_data,
enum cryp_key_reg_index key_reg_index,
struct cryp_key_value key_value);
int cryp_configure_init_vector(struct cryp_device_data *device_data,
enum cryp_init_vector_index
init_vector_index,
struct cryp_init_vector_value
init_vector_value);
int cryp_configure_protection(struct cryp_device_data *device_data,
struct cryp_protection_config *p_protect_config);
/* Power management funtions */
void cryp_save_device_context(struct cryp_device_data *device_data,
struct cryp_device_context *ctx,
int cryp_mode);
void cryp_restore_device_context(struct cryp_device_data *device_data,
struct cryp_device_context *ctx);
/* Data transfer and status bits. */
int cryp_is_logic_busy(struct cryp_device_data *device_data);
int cryp_get_status(struct cryp_device_data *device_data);
/**
* cryp_write_indata - This routine writes 32 bit data into the data input
* register of the cryptography IP.
* @device_data: Pointer to the device data struct for base address.
* @write_data: Data to write.
*/
int cryp_write_indata(struct cryp_device_data *device_data, u32 write_data);
/**
* cryp_read_outdata - This routine reads the data from the data output
* register of the CRYP logic
* @device_data: Pointer to the device data struct for base address.
* @read_data: Read the data from the output FIFO.
*/
int cryp_read_outdata(struct cryp_device_data *device_data, u32 *read_data);
#endif /* _CRYP_H_ */
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/**
* Copyright (C) ST-Ericsson SA 2010
* Author: Shujuan Chen <shujuan.chen@stericsson.com> for ST-Ericsson.
* Author: Jonas Linde <jonas.linde@stericsson.com> for ST-Ericsson.
* Author: Joakim Bech <joakim.xx.bech@stericsson.com> for ST-Ericsson.
* Author: Berne Hebark <berne.herbark@stericsson.com> for ST-Ericsson.
* Author: Niklas Hernaeus <niklas.hernaeus@stericsson.com> for ST-Ericsson.
* License terms: GNU General Public License (GPL) version 2.
*/
#include <linux/kernel.h>
#include <linux/bitmap.h>
#include <linux/device.h>
#include "cryp.h"
#include "cryp_p.h"
#include "cryp_irq.h"
#include "cryp_irqp.h"
void cryp_enable_irq_src(struct cryp_device_data *device_data, u32 irq_src)
{
u32 i;
dev_dbg(device_data->dev, "[%s]", __func__);
i = readl_relaxed(&device_data->base->imsc);
i = i | irq_src;
writel_relaxed(i, &device_data->base->imsc);
}
void cryp_disable_irq_src(struct cryp_device_data *device_data, u32 irq_src)
{
u32 i;
dev_dbg(device_data->dev, "[%s]", __func__);
i = readl_relaxed(&device_data->base->imsc);
i = i & ~irq_src;
writel_relaxed(i, &device_data->base->imsc);
}
bool cryp_pending_irq_src(struct cryp_device_data *device_data, u32 irq_src)
{
return (readl_relaxed(&device_data->base->mis) & irq_src) > 0;
}
/**
* Copyright (C) ST-Ericsson SA 2010
* Author: Shujuan Chen <shujuan.chen@stericsson.com> for ST-Ericsson.
* Author: Jonas Linde <jonas.linde@stericsson.com> for ST-Ericsson.
* Author: Joakim Bech <joakim.xx.bech@stericsson.com> for ST-Ericsson.
* Author: Berne Hebark <berne.herbark@stericsson.com> for ST-Ericsson.
* Author: Niklas Hernaeus <niklas.hernaeus@stericsson.com> for ST-Ericsson.
* License terms: GNU General Public License (GPL) version 2
*/
#ifndef _CRYP_IRQ_H_
#define _CRYP_IRQ_H_
#include "cryp.h"
enum cryp_irq_src_id {
CRYP_IRQ_SRC_INPUT_FIFO = 0x1,
CRYP_IRQ_SRC_OUTPUT_FIFO = 0x2,
CRYP_IRQ_SRC_ALL = 0x3
};
/**
* M0 Funtions
*/
void cryp_enable_irq_src(struct cryp_device_data *device_data, u32 irq_src);
void cryp_disable_irq_src(struct cryp_device_data *device_data, u32 irq_src);
bool cryp_pending_irq_src(struct cryp_device_data *device_data, u32 irq_src);
#endif /* _CRYP_IRQ_H_ */
/**
* Copyright (C) ST-Ericsson SA 2010
* Author: Shujuan Chen <shujuan.chen@stericsson.com> for ST-Ericsson.
* Author: Jonas Linde <jonas.linde@stericsson.com> for ST-Ericsson.
* Author: Joakim Bech <joakim.xx.bech@stericsson.com> for ST-Ericsson.
* Author: Berne Hebark <berne.herbark@stericsson.com> for ST-Ericsson.
* Author: Niklas Hernaeus <niklas.hernaeus@stericsson.com> for ST-Ericsson.
* License terms: GNU General Public License (GPL) version 2
*/
#ifndef __CRYP_IRQP_H_
#define __CRYP_IRQP_H_
#include "cryp_irq.h"
/**
*
* CRYP Registers - Offset mapping
* +-----------------+
* 00h | CRYP_CR | Configuration register
* +-----------------+
* 04h | CRYP_SR | Status register
* +-----------------+
* 08h | CRYP_DIN | Data In register
* +-----------------+
* 0ch | CRYP_DOUT | Data out register
* +-----------------+
* 10h | CRYP_DMACR | DMA control register
* +-----------------+
* 14h | CRYP_IMSC | IMSC
* +-----------------+
* 18h | CRYP_RIS | Raw interrupt status
* +-----------------+
* 1ch | CRYP_MIS | Masked interrupt status.
* +-----------------+
* Key registers
* IVR registers
* Peripheral
* Cell IDs
*
* Refer data structure for other register map
*/
/**
* struct cryp_register
* @cr - Configuration register
* @status - Status register
* @din - Data input register
* @din_size - Data input size register
* @dout - Data output register
* @dout_size - Data output size register
* @dmacr - Dma control register
* @imsc - Interrupt mask set/clear register
* @ris - Raw interrupt status
* @mis - Masked interrupt statu register
* @key_1_l - Key register 1 L
* @key_1_r - Key register 1 R
* @key_2_l - Key register 2 L
* @key_2_r - Key register 2 R
* @key_3_l - Key register 3 L
* @key_3_r - Key register 3 R
* @key_4_l - Key register 4 L
* @key_4_r - Key register 4 R
* @init_vect_0_l - init vector 0 L
* @init_vect_0_r - init vector 0 R
* @init_vect_1_l - init vector 1 L
* @init_vect_1_r - init vector 1 R
* @cryp_unused1 - unused registers
* @itcr - Integration test control register
* @itip - Integration test input register
* @itop - Integration test output register
* @cryp_unused2 - unused registers
* @periphId0 - FE0 CRYP Peripheral Identication Register
* @periphId1 - FE4
* @periphId2 - FE8
* @periphId3 - FEC
* @pcellId0 - FF0 CRYP PCell Identication Register
* @pcellId1 - FF4
* @pcellId2 - FF8
* @pcellId3 - FFC
*/
struct cryp_register {
u32 cr; /* Configuration register */
u32 sr; /* Status register */
u32 din; /* Data input register */
u32 din_size; /* Data input size register */
u32 dout; /* Data output register */
u32 dout_size; /* Data output size register */
u32 dmacr; /* Dma control register */
u32 imsc; /* Interrupt mask set/clear register */
u32 ris; /* Raw interrupt status */
u32 mis; /* Masked interrupt statu register */
u32 key_1_l; /*Key register 1 L */
u32 key_1_r; /*Key register 1 R */
u32 key_2_l; /*Key register 2 L */
u32 key_2_r; /*Key register 2 R */
u32 key_3_l; /*Key register 3 L */
u32 key_3_r; /*Key register 3 R */
u32 key_4_l; /*Key register 4 L */
u32 key_4_r; /*Key register 4 R */
u32 init_vect_0_l; /*init vector 0 L */
u32 init_vect_0_r; /*init vector 0 R */
u32 init_vect_1_l; /*init vector 1 L */
u32 init_vect_1_r; /*init vector 1 R */
u32 cryp_unused1[(0x80 - 0x58) / sizeof(u32)]; /* unused registers */
u32 itcr; /*Integration test control register */
u32 itip; /*Integration test input register */
u32 itop; /*Integration test output register */
u32 cryp_unused2[(0xFE0 - 0x8C) / sizeof(u32)]; /* unused registers */
u32 periphId0; /* FE0 CRYP Peripheral Identication Register */
u32 periphId1; /* FE4 */
u32 periphId2; /* FE8 */
u32 periphId3; /* FEC */
u32 pcellId0; /* FF0 CRYP PCell Identication Register */
u32 pcellId1; /* FF4 */
u32 pcellId2; /* FF8 */
u32 pcellId3; /* FFC */
};
#endif
/**
* Copyright (C) ST-Ericsson SA 2010
* Author: Shujuan Chen <shujuan.chen@stericsson.com> for ST-Ericsson.
* Author: Jonas Linde <jonas.linde@stericsson.com> for ST-Ericsson.
* Author: Joakim Bech <joakim.xx.bech@stericsson.com> for ST-Ericsson.
* Author: Berne Hebark <berne.herbark@stericsson.com> for ST-Ericsson.
* Author: Niklas Hernaeus <niklas.hernaeus@stericsson.com> for ST-Ericsson.
* License terms: GNU General Public License (GPL) version 2
*/
#ifndef _CRYP_P_H_
#define _CRYP_P_H_
#include <linux/io.h>
#include <linux/bitops.h>
#include "cryp.h"
#include "cryp_irqp.h"
/**
* Generic Macros
*/
#define CRYP_SET_BITS(reg_name, mask) \
writel_relaxed((readl_relaxed(reg_name) | mask), reg_name)
#define CRYP_WRITE_BIT(reg_name, val, mask) \
writel_relaxed(((readl_relaxed(reg_name) & ~(mask)) |\
((val) & (mask))), reg_name)
#define CRYP_TEST_BITS(reg_name, val) \
(readl_relaxed(reg_name) & (val))
#define CRYP_PUT_BITS(reg, val, shift, mask) \
writel_relaxed(((readl_relaxed(reg) & ~(mask)) | \
(((u32)val << shift) & (mask))), reg)
/**
* CRYP specific Macros
*/
#define CRYP_PERIPHERAL_ID0 0xE3
#define CRYP_PERIPHERAL_ID1 0x05
#define CRYP_PERIPHERAL_ID2_DB8500 0x28
#define CRYP_PERIPHERAL_ID3 0x00
#define CRYP_PCELL_ID0 0x0D
#define CRYP_PCELL_ID1 0xF0
#define CRYP_PCELL_ID2 0x05
#define CRYP_PCELL_ID3 0xB1
/**
* CRYP register default values
*/
#define MAX_DEVICE_SUPPORT 2
/* Priv set, keyrden set and datatype 8bits swapped set as default. */
#define CRYP_CR_DEFAULT 0x0482
#define CRYP_DMACR_DEFAULT 0x0
#define CRYP_IMSC_DEFAULT 0x0
#define CRYP_DIN_DEFAULT 0x0
#define CRYP_DOUT_DEFAULT 0x0
#define CRYP_KEY_DEFAULT 0x0
#define CRYP_INIT_VECT_DEFAULT 0x0
/**
* CRYP Control register specific mask
*/
#define CRYP_CR_SECURE_MASK BIT(0)
#define CRYP_CR_PRLG_MASK BIT(1)
#define CRYP_CR_ALGODIR_MASK BIT(2)
#define CRYP_CR_ALGOMODE_MASK (BIT(5) | BIT(4) | BIT(3))
#define CRYP_CR_DATATYPE_MASK (BIT(7) | BIT(6))
#define CRYP_CR_KEYSIZE_MASK (BIT(9) | BIT(8))
#define CRYP_CR_KEYRDEN_MASK BIT(10)
#define CRYP_CR_KSE_MASK BIT(11)
#define CRYP_CR_START_MASK BIT(12)
#define CRYP_CR_INIT_MASK BIT(13)
#define CRYP_CR_FFLUSH_MASK BIT(14)
#define CRYP_CR_CRYPEN_MASK BIT(15)
#define CRYP_CR_CONTEXT_SAVE_MASK (CRYP_CR_SECURE_MASK |\
CRYP_CR_PRLG_MASK |\
CRYP_CR_ALGODIR_MASK |\
CRYP_CR_ALGOMODE_MASK |\
CRYP_CR_DATATYPE_MASK |\
CRYP_CR_KEYSIZE_MASK |\
CRYP_CR_KEYRDEN_MASK |\
CRYP_CR_DATATYPE_MASK)
#define CRYP_SR_INFIFO_READY_MASK (BIT(0) | BIT(1))
#define CRYP_SR_IFEM_MASK BIT(0)
#define CRYP_SR_BUSY_MASK BIT(4)
/**
* Bit position used while setting bits in register
*/
#define CRYP_CR_PRLG_POS 1
#define CRYP_CR_ALGODIR_POS 2
#define CRYP_CR_ALGOMODE_POS 3
#define CRYP_CR_DATATYPE_POS 6
#define CRYP_CR_KEYSIZE_POS 8
#define CRYP_CR_KEYRDEN_POS 10
#define CRYP_CR_KSE_POS 11
#define CRYP_CR_START_POS 12
#define CRYP_CR_INIT_POS 13
#define CRYP_CR_CRYPEN_POS 15
#define CRYP_SR_BUSY_POS 4
/**
* CRYP PCRs------PC_NAND control register
* BIT_MASK
*/
#define CRYP_DMA_REQ_MASK (BIT(1) | BIT(0))
#define CRYP_DMA_REQ_MASK_POS 0
struct cryp_system_context {
/* CRYP Register structure */
struct cryp_register *p_cryp_reg[MAX_DEVICE_SUPPORT];
};
#endif
#
# Copyright (C) ST-Ericsson SA 2010
# Author: Shujuan Chen (shujuan.chen@stericsson.com)
# License terms: GNU General Public License (GPL) version 2
#
ifdef CONFIG_CRYPTO_DEV_UX500_DEBUG
CFLAGS_hash_core.o := -DDEBUG -O0
endif
obj-$(CONFIG_CRYPTO_DEV_UX500_HASH) += ux500_hash.o
ux500_hash-objs := hash_core.o
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