Commit 0ecb40ca authored by Barry Song's avatar Barry Song Committed by Barry Song

ARM: PRIMA2: rstc: enable the support for Marco

marco has SET/CLEAR registers pair for rstc to avoid read-modify-write,
this patch detects the mach typer and access registers based on SoC.
Signed-off-by: default avatarBarry Song <Baohua.Song@csr.com>
parent 0d5983a6
...@@ -19,6 +19,7 @@ static DEFINE_MUTEX(rstc_lock); ...@@ -19,6 +19,7 @@ static DEFINE_MUTEX(rstc_lock);
static struct of_device_id rstc_ids[] = { static struct of_device_id rstc_ids[] = {
{ .compatible = "sirf,prima2-rstc" }, { .compatible = "sirf,prima2-rstc" },
{ .compatible = "sirf,marco-rstc" },
{}, {},
}; };
...@@ -42,16 +43,14 @@ early_initcall(sirfsoc_of_rstc_init); ...@@ -42,16 +43,14 @@ early_initcall(sirfsoc_of_rstc_init);
int sirfsoc_reset_device(struct device *dev) int sirfsoc_reset_device(struct device *dev)
{ {
const unsigned int *prop = of_get_property(dev->of_node, "reset-bit", NULL); u32 reset_bit;
unsigned int reset_bit;
if (!prop) if (of_property_read_u32(dev->of_node, "reset-bit", &reset_bit))
return -ENODEV; return -EINVAL;
reset_bit = be32_to_cpup(prop);
mutex_lock(&rstc_lock); mutex_lock(&rstc_lock);
if (of_device_is_compatible(dev->of_node, "sirf,prima2-rstc")) {
/* /*
* Writing 1 to this bit resets corresponding block. Writing 0 to this * Writing 1 to this bit resets corresponding block. Writing 0 to this
* bit de-asserts reset signal of the corresponding block. * bit de-asserts reset signal of the corresponding block.
...@@ -63,6 +62,18 @@ int sirfsoc_reset_device(struct device *dev) ...@@ -63,6 +62,18 @@ int sirfsoc_reset_device(struct device *dev)
msleep(10); msleep(10);
writel(readl(sirfsoc_rstc_base + (reset_bit / 32) * 4) & ~reset_bit, writel(readl(sirfsoc_rstc_base + (reset_bit / 32) * 4) & ~reset_bit,
sirfsoc_rstc_base + (reset_bit / 32) * 4); sirfsoc_rstc_base + (reset_bit / 32) * 4);
} else {
/*
* For MARCO and POLO
* Writing 1 to SET register resets corresponding block. Writing 1 to CLEAR
* register de-asserts reset signal of the corresponding block.
* datasheet doesn't require explicit delay between the set and clear
* of reset bit. it could be shorter if tests pass.
*/
writel(reset_bit, sirfsoc_rstc_base + (reset_bit / 32) * 8);
msleep(10);
writel(reset_bit, sirfsoc_rstc_base + (reset_bit / 32) * 8 + 4);
}
mutex_unlock(&rstc_lock); mutex_unlock(&rstc_lock);
......
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