Commit 11238099 authored by Qi Hu's avatar Qi Hu Committed by Huacai Chen

LoongArch: Remove obsolete mentions of vcsr

The `vcsr` only exists in the old hardware design, it isn't used in any
shipped hardware from Loongson-3A5000 on. Both scalar FP and LSX/LASX
instructions use the `fcsr` as their control and status registers now.
For example, the RM control bit in fcsr0 is shared by FP, LSX and LASX
instructions.

Particularly, fcsr16 to fcsr31 are reserved for LSX/LASX now, access to
these registers has no visible effect if LSX/LASX is enabled, and will
cause SXD/ASXD exceptions if LSX/LASX is not enabled.

So, mentions of vcsr are obsolete in the first place (it was just used
for debugging), let's remove them.
Reviewed-by: default avatarWANG Xuerui <git@xen0n.name>
Signed-off-by: default avatarQi Hu <huqi@loongson.cn>
Signed-off-by: default avatarHuacai Chen <chenhuacai@loongson.cn>
parent 7fd6ef61
...@@ -48,6 +48,5 @@ ...@@ -48,6 +48,5 @@
#define fcsr1 $r1 #define fcsr1 $r1
#define fcsr2 $r2 #define fcsr2 $r2
#define fcsr3 $r3 #define fcsr3 $r3
#define vcsr16 $r16
#endif /* _ASM_FPREGDEF_H */ #endif /* _ASM_FPREGDEF_H */
...@@ -80,7 +80,6 @@ BUILD_FPR_ACCESS(64) ...@@ -80,7 +80,6 @@ BUILD_FPR_ACCESS(64)
struct loongarch_fpu { struct loongarch_fpu {
unsigned int fcsr; unsigned int fcsr;
unsigned int vcsr;
uint64_t fcc; /* 8x8 */ uint64_t fcc; /* 8x8 */
union fpureg fpr[NUM_FPU_REGS]; union fpureg fpr[NUM_FPU_REGS];
}; };
...@@ -161,7 +160,6 @@ struct thread_struct { ...@@ -161,7 +160,6 @@ struct thread_struct {
*/ \ */ \
.fpu = { \ .fpu = { \
.fcsr = 0, \ .fcsr = 0, \
.vcsr = 0, \
.fcc = 0, \ .fcc = 0, \
.fpr = {{{0,},},}, \ .fpr = {{{0,},},}, \
}, \ }, \
......
...@@ -166,7 +166,6 @@ void output_thread_fpu_defines(void) ...@@ -166,7 +166,6 @@ void output_thread_fpu_defines(void)
OFFSET(THREAD_FCSR, loongarch_fpu, fcsr); OFFSET(THREAD_FCSR, loongarch_fpu, fcsr);
OFFSET(THREAD_FCC, loongarch_fpu, fcc); OFFSET(THREAD_FCC, loongarch_fpu, fcc);
OFFSET(THREAD_VCSR, loongarch_fpu, vcsr);
BLANK(); BLANK();
} }
......
...@@ -146,16 +146,6 @@ ...@@ -146,16 +146,6 @@
movgr2fcsr fcsr0, \tmp0 movgr2fcsr fcsr0, \tmp0
.endm .endm
.macro sc_save_vcsr base, tmp0
movfcsr2gr \tmp0, vcsr16
EX st.w \tmp0, \base, 0
.endm
.macro sc_restore_vcsr base, tmp0
EX ld.w \tmp0, \base, 0
movgr2fcsr vcsr16, \tmp0
.endm
/* /*
* Save a thread's fp context. * Save a thread's fp context.
*/ */
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment