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Commit 12526b0d authored by Michael Ellerman's avatar Michael Ellerman
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Merge branch 'next' of https://git.kernel.org/pub/scm/linux/kernel/git/scottwood/linux into next 

Freescale updates from Scott:

"Highlights include elimination of legacy clock bindings use from dts
 files, an 83xx watchdog handler, fixes to old dts interrupt errors, and
 some minor cleanup."
parents 9bbc7e4c 63d86876
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Showing with 216 additions and 550 deletions
Documentation/devicetree/bindings/clock/qoriq-clock.txt
View file @ 12526b0d
...@@ -28,6 +28,12 @@ Required properties: ...@@ -28,6 +28,12 @@ Required properties:
* "fsl,p4080-clockgen" * "fsl,p4080-clockgen"
* "fsl,p5020-clockgen" * "fsl,p5020-clockgen"
* "fsl,p5040-clockgen" * "fsl,p5040-clockgen"
* "fsl,t1023-clockgen"
* "fsl,t1024-clockgen"
* "fsl,t1040-clockgen"
* "fsl,t1042-clockgen"
* "fsl,t2080-clockgen"
* "fsl,t2081-clockgen"
* "fsl,t4240-clockgen" * "fsl,t4240-clockgen"
* "fsl,b4420-clockgen" * "fsl,b4420-clockgen"
* "fsl,b4860-clockgen" * "fsl,b4860-clockgen"
......
arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi
View file @ 12526b0d
...@@ -70,14 +70,14 @@ cpus { ...@@ -70,14 +70,14 @@ cpus {
cpu0: PowerPC,e6500@0 { cpu0: PowerPC,e6500@0 {
device_type = "cpu"; device_type = "cpu";
reg = <0 1>; reg = <0 1>;
clocks = <&mux0>; clocks = <&clockgen 1 0>;
next-level-cache = <&L2_1>; next-level-cache = <&L2_1>;
fsl,portid-mapping = <0x80000000>; fsl,portid-mapping = <0x80000000>;
}; };
cpu1: PowerPC,e6500@2 { cpu1: PowerPC,e6500@2 {
device_type = "cpu"; device_type = "cpu";
reg = <2 3>; reg = <2 3>;
clocks = <&mux0>; clocks = <&clockgen 1 0>;
next-level-cache = <&L2_1>; next-level-cache = <&L2_1>;
fsl,portid-mapping = <0x80000000>; fsl,portid-mapping = <0x80000000>;
}; };
......
arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi
View file @ 12526b0d
...@@ -75,28 +75,28 @@ cpus { ...@@ -75,28 +75,28 @@ cpus {
cpu0: PowerPC,e6500@0 { cpu0: PowerPC,e6500@0 {
device_type = "cpu"; device_type = "cpu";
reg = <0 1>; reg = <0 1>;
clocks = <&mux0>; clocks = <&clockgen 1 0>;
next-level-cache = <&L2_1>; next-level-cache = <&L2_1>;
fsl,portid-mapping = <0x80000000>; fsl,portid-mapping = <0x80000000>;
}; };
cpu1: PowerPC,e6500@2 { cpu1: PowerPC,e6500@2 {
device_type = "cpu"; device_type = "cpu";
reg = <2 3>; reg = <2 3>;
clocks = <&mux0>; clocks = <&clockgen 1 0>;
next-level-cache = <&L2_1>; next-level-cache = <&L2_1>;
fsl,portid-mapping = <0x80000000>; fsl,portid-mapping = <0x80000000>;
}; };
cpu2: PowerPC,e6500@4 { cpu2: PowerPC,e6500@4 {
device_type = "cpu"; device_type = "cpu";
reg = <4 5>; reg = <4 5>;
clocks = <&mux0>; clocks = <&clockgen 1 0>;
next-level-cache = <&L2_1>; next-level-cache = <&L2_1>;
fsl,portid-mapping = <0x80000000>; fsl,portid-mapping = <0x80000000>;
}; };
cpu3: PowerPC,e6500@6 { cpu3: PowerPC,e6500@6 {
device_type = "cpu"; device_type = "cpu";
reg = <6 7>; reg = <6 7>;
clocks = <&mux0>; clocks = <&clockgen 1 0>;
next-level-cache = <&L2_1>; next-level-cache = <&L2_1>;
fsl,portid-mapping = <0x80000000>; fsl,portid-mapping = <0x80000000>;
}; };
......
arch/powerpc/boot/dts/fsl/b4si-post.dtsi
View file @ 12526b0d
...@@ -398,21 +398,6 @@ guts: global-utilities@e0000 { ...@@ -398,21 +398,6 @@ guts: global-utilities@e0000 {
}; };
/include/ "qoriq-clockgen2.dtsi" /include/ "qoriq-clockgen2.dtsi"
clockgen: global-utilities@e1000 {
compatible = "fsl,b4-clockgen", "fsl,qoriq-clockgen-2.0";
reg = <0xe1000 0x1000>;
mux0: mux0@0 {
#clock-cells = <0>;
reg = <0x0 0x4>;
compatible = "fsl,qoriq-core-mux-2.0";
clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>,
<&pll1 0>, <&pll1 1>, <&pll1 2>;
clock-names = "pll0", "pll0-div2", "pll0-div4",
"pll1", "pll1-div2", "pll1-div4";
clock-output-names = "cmux0";
};
};
rcpm: global-utilities@e2000 { rcpm: global-utilities@e2000 {
compatible = "fsl,b4-rcpm", "fsl,qoriq-rcpm-2.0"; compatible = "fsl,b4-rcpm", "fsl,qoriq-rcpm-2.0";
......
arch/powerpc/boot/dts/fsl/mpc8641_hpcn.dts
View file @ 12526b0d
...@@ -169,100 +169,100 @@ pci0: pcie@ffe08000 { ...@@ -169,100 +169,100 @@ pci0: pcie@ffe08000 {
interrupt-map-mask = <0xff00 0 0 7>; interrupt-map-mask = <0xff00 0 0 7>;
interrupt-map = < interrupt-map = <
/* IDSEL 0x11 func 0 - PCI slot 1 */ /* IDSEL 0x11 func 0 - PCI slot 1 */
0x8800 0 0 1 &mpic 2 1 0x8800 0 0 1 &mpic 2 1 0 0
0x8800 0 0 2 &mpic 3 1 0x8800 0 0 2 &mpic 3 1 0 0
0x8800 0 0 3 &mpic 4 1 0x8800 0 0 3 &mpic 4 1 0 0
0x8800 0 0 4 &mpic 1 1 0x8800 0 0 4 &mpic 1 1 0 0
/* IDSEL 0x11 func 1 - PCI slot 1 */ /* IDSEL 0x11 func 1 - PCI slot 1 */
0x8900 0 0 1 &mpic 2 1 0x8900 0 0 1 &mpic 2 1 0 0
0x8900 0 0 2 &mpic 3 1 0x8900 0 0 2 &mpic 3 1 0 0
0x8900 0 0 3 &mpic 4 1 0x8900 0 0 3 &mpic 4 1 0 0
0x8900 0 0 4 &mpic 1 1 0x8900 0 0 4 &mpic 1 1 0 0
/* IDSEL 0x11 func 2 - PCI slot 1 */ /* IDSEL 0x11 func 2 - PCI slot 1 */
0x8a00 0 0 1 &mpic 2 1 0x8a00 0 0 1 &mpic 2 1 0 0
0x8a00 0 0 2 &mpic 3 1 0x8a00 0 0 2 &mpic 3 1 0 0
0x8a00 0 0 3 &mpic 4 1 0x8a00 0 0 3 &mpic 4 1 0 0
0x8a00 0 0 4 &mpic 1 1 0x8a00 0 0 4 &mpic 1 1 0 0
/* IDSEL 0x11 func 3 - PCI slot 1 */ /* IDSEL 0x11 func 3 - PCI slot 1 */
0x8b00 0 0 1 &mpic 2 1 0x8b00 0 0 1 &mpic 2 1 0 0
0x8b00 0 0 2 &mpic 3 1 0x8b00 0 0 2 &mpic 3 1 0 0
0x8b00 0 0 3 &mpic 4 1 0x8b00 0 0 3 &mpic 4 1 0 0
0x8b00 0 0 4 &mpic 1 1 0x8b00 0 0 4 &mpic 1 1 0 0
/* IDSEL 0x11 func 4 - PCI slot 1 */ /* IDSEL 0x11 func 4 - PCI slot 1 */
0x8c00 0 0 1 &mpic 2 1 0x8c00 0 0 1 &mpic 2 1 0 0
0x8c00 0 0 2 &mpic 3 1 0x8c00 0 0 2 &mpic 3 1 0 0
0x8c00 0 0 3 &mpic 4 1 0x8c00 0 0 3 &mpic 4 1 0 0
0x8c00 0 0 4 &mpic 1 1 0x8c00 0 0 4 &mpic 1 1 0 0
/* IDSEL 0x11 func 5 - PCI slot 1 */ /* IDSEL 0x11 func 5 - PCI slot 1 */
0x8d00 0 0 1 &mpic 2 1 0x8d00 0 0 1 &mpic 2 1 0 0
0x8d00 0 0 2 &mpic 3 1 0x8d00 0 0 2 &mpic 3 1 0 0
0x8d00 0 0 3 &mpic 4 1 0x8d00 0 0 3 &mpic 4 1 0 0
0x8d00 0 0 4 &mpic 1 1 0x8d00 0 0 4 &mpic 1 1 0 0
/* IDSEL 0x11 func 6 - PCI slot 1 */ /* IDSEL 0x11 func 6 - PCI slot 1 */
0x8e00 0 0 1 &mpic 2 1 0x8e00 0 0 1 &mpic 2 1 0 0
0x8e00 0 0 2 &mpic 3 1 0x8e00 0 0 2 &mpic 3 1 0 0
0x8e00 0 0 3 &mpic 4 1 0x8e00 0 0 3 &mpic 4 1 0 0
0x8e00 0 0 4 &mpic 1 1 0x8e00 0 0 4 &mpic 1 1 0 0
/* IDSEL 0x11 func 7 - PCI slot 1 */ /* IDSEL 0x11 func 7 - PCI slot 1 */
0x8f00 0 0 1 &mpic 2 1 0x8f00 0 0 1 &mpic 2 1 0 0
0x8f00 0 0 2 &mpic 3 1 0x8f00 0 0 2 &mpic 3 1 0 0
0x8f00 0 0 3 &mpic 4 1 0x8f00 0 0 3 &mpic 4 1 0 0
0x8f00 0 0 4 &mpic 1 1 0x8f00 0 0 4 &mpic 1 1 0 0
/* IDSEL 0x12 func 0 - PCI slot 2 */ /* IDSEL 0x12 func 0 - PCI slot 2 */
0x9000 0 0 1 &mpic 3 1 0x9000 0 0 1 &mpic 3 1 0 0
0x9000 0 0 2 &mpic 4 1 0x9000 0 0 2 &mpic 4 1 0 0
0x9000 0 0 3 &mpic 1 1 0x9000 0 0 3 &mpic 1 1 0 0
0x9000 0 0 4 &mpic 2 1 0x9000 0 0 4 &mpic 2 1 0 0
/* IDSEL 0x12 func 1 - PCI slot 2 */ /* IDSEL 0x12 func 1 - PCI slot 2 */
0x9100 0 0 1 &mpic 3 1 0x9100 0 0 1 &mpic 3 1 0 0
0x9100 0 0 2 &mpic 4 1 0x9100 0 0 2 &mpic 4 1 0 0
0x9100 0 0 3 &mpic 1 1 0x9100 0 0 3 &mpic 1 1 0 0
0x9100 0 0 4 &mpic 2 1 0x9100 0 0 4 &mpic 2 1 0 0
/* IDSEL 0x12 func 2 - PCI slot 2 */ /* IDSEL 0x12 func 2 - PCI slot 2 */
0x9200 0 0 1 &mpic 3 1 0x9200 0 0 1 &mpic 3 1 0 0
0x9200 0 0 2 &mpic 4 1 0x9200 0 0 2 &mpic 4 1 0 0
0x9200 0 0 3 &mpic 1 1 0x9200 0 0 3 &mpic 1 1 0 0
0x9200 0 0 4 &mpic 2 1 0x9200 0 0 4 &mpic 2 1 0 0
/* IDSEL 0x12 func 3 - PCI slot 2 */ /* IDSEL 0x12 func 3 - PCI slot 2 */
0x9300 0 0 1 &mpic 3 1 0x9300 0 0 1 &mpic 3 1 0 0
0x9300 0 0 2 &mpic 4 1 0x9300 0 0 2 &mpic 4 1 0 0
0x9300 0 0 3 &mpic 1 1 0x9300 0 0 3 &mpic 1 1 0 0
0x9300 0 0 4 &mpic 2 1 0x9300 0 0 4 &mpic 2 1 0 0
/* IDSEL 0x12 func 4 - PCI slot 2 */ /* IDSEL 0x12 func 4 - PCI slot 2 */
0x9400 0 0 1 &mpic 3 1 0x9400 0 0 1 &mpic 3 1 0 0
0x9400 0 0 2 &mpic 4 1 0x9400 0 0 2 &mpic 4 1 0 0
0x9400 0 0 3 &mpic 1 1 0x9400 0 0 3 &mpic 1 1 0 0
0x9400 0 0 4 &mpic 2 1 0x9400 0 0 4 &mpic 2 1 0 0
/* IDSEL 0x12 func 5 - PCI slot 2 */ /* IDSEL 0x12 func 5 - PCI slot 2 */
0x9500 0 0 1 &mpic 3 1 0x9500 0 0 1 &mpic 3 1 0 0
0x9500 0 0 2 &mpic 4 1 0x9500 0 0 2 &mpic 4 1 0 0
0x9500 0 0 3 &mpic 1 1 0x9500 0 0 3 &mpic 1 1 0 0
0x9500 0 0 4 &mpic 2 1 0x9500 0 0 4 &mpic 2 1 0 0
/* IDSEL 0x12 func 6 - PCI slot 2 */ /* IDSEL 0x12 func 6 - PCI slot 2 */
0x9600 0 0 1 &mpic 3 1 0x9600 0 0 1 &mpic 3 1 0 0
0x9600 0 0 2 &mpic 4 1 0x9600 0 0 2 &mpic 4 1 0 0
0x9600 0 0 3 &mpic 1 1 0x9600 0 0 3 &mpic 1 1 0 0
0x9600 0 0 4 &mpic 2 1 0x9600 0 0 4 &mpic 2 1 0 0
/* IDSEL 0x12 func 7 - PCI slot 2 */ /* IDSEL 0x12 func 7 - PCI slot 2 */
0x9700 0 0 1 &mpic 3 1 0x9700 0 0 1 &mpic 3 1 0 0
0x9700 0 0 2 &mpic 4 1 0x9700 0 0 2 &mpic 4 1 0 0
0x9700 0 0 3 &mpic 1 1 0x9700 0 0 3 &mpic 1 1 0 0
0x9700 0 0 4 &mpic 2 1 0x9700 0 0 4 &mpic 2 1 0 0
// IDSEL 0x1c USB // IDSEL 0x1c USB
0xe000 0 0 1 &i8259 12 2 0xe000 0 0 1 &i8259 12 2
......
arch/powerpc/boot/dts/fsl/mpc8641_hpcn_36b.dts
View file @ 12526b0d
...@@ -136,100 +136,100 @@ pci0: pcie@fffe08000 { ...@@ -136,100 +136,100 @@ pci0: pcie@fffe08000 {
interrupt-map-mask = <0xff00 0 0 7>; interrupt-map-mask = <0xff00 0 0 7>;
interrupt-map = < interrupt-map = <
/* IDSEL 0x11 func 0 - PCI slot 1 */ /* IDSEL 0x11 func 0 - PCI slot 1 */
0x8800 0 0 1 &mpic 2 1 0x8800 0 0 1 &mpic 2 1 0 0
0x8800 0 0 2 &mpic 3 1 0x8800 0 0 2 &mpic 3 1 0 0
0x8800 0 0 3 &mpic 4 1 0x8800 0 0 3 &mpic 4 1 0 0
0x8800 0 0 4 &mpic 1 1 0x8800 0 0 4 &mpic 1 1 0 0
/* IDSEL 0x11 func 1 - PCI slot 1 */ /* IDSEL 0x11 func 1 - PCI slot 1 */
0x8900 0 0 1 &mpic 2 1 0x8900 0 0 1 &mpic 2 1 0 0
0x8900 0 0 2 &mpic 3 1 0x8900 0 0 2 &mpic 3 1 0 0
0x8900 0 0 3 &mpic 4 1 0x8900 0 0 3 &mpic 4 1 0 0
0x8900 0 0 4 &mpic 1 1 0x8900 0 0 4 &mpic 1 1 0 0
/* IDSEL 0x11 func 2 - PCI slot 1 */ /* IDSEL 0x11 func 2 - PCI slot 1 */
0x8a00 0 0 1 &mpic 2 1 0x8a00 0 0 1 &mpic 2 1 0 0
0x8a00 0 0 2 &mpic 3 1 0x8a00 0 0 2 &mpic 3 1 0 0
0x8a00 0 0 3 &mpic 4 1 0x8a00 0 0 3 &mpic 4 1 0 0
0x8a00 0 0 4 &mpic 1 1 0x8a00 0 0 4 &mpic 1 1 0 0
/* IDSEL 0x11 func 3 - PCI slot 1 */ /* IDSEL 0x11 func 3 - PCI slot 1 */
0x8b00 0 0 1 &mpic 2 1 0x8b00 0 0 1 &mpic 2 1 0 0
0x8b00 0 0 2 &mpic 3 1 0x8b00 0 0 2 &mpic 3 1 0 0
0x8b00 0 0 3 &mpic 4 1 0x8b00 0 0 3 &mpic 4 1 0 0
0x8b00 0 0 4 &mpic 1 1 0x8b00 0 0 4 &mpic 1 1 0 0
/* IDSEL 0x11 func 4 - PCI slot 1 */ /* IDSEL 0x11 func 4 - PCI slot 1 */
0x8c00 0 0 1 &mpic 2 1 0x8c00 0 0 1 &mpic 2 1 0 0
0x8c00 0 0 2 &mpic 3 1 0x8c00 0 0 2 &mpic 3 1 0 0
0x8c00 0 0 3 &mpic 4 1 0x8c00 0 0 3 &mpic 4 1 0 0
0x8c00 0 0 4 &mpic 1 1 0x8c00 0 0 4 &mpic 1 1 0 0
/* IDSEL 0x11 func 5 - PCI slot 1 */ /* IDSEL 0x11 func 5 - PCI slot 1 */
0x8d00 0 0 1 &mpic 2 1 0x8d00 0 0 1 &mpic 2 1 0 0
0x8d00 0 0 2 &mpic 3 1 0x8d00 0 0 2 &mpic 3 1 0 0
0x8d00 0 0 3 &mpic 4 1 0x8d00 0 0 3 &mpic 4 1 0 0
0x8d00 0 0 4 &mpic 1 1 0x8d00 0 0 4 &mpic 1 1 0 0
/* IDSEL 0x11 func 6 - PCI slot 1 */ /* IDSEL 0x11 func 6 - PCI slot 1 */
0x8e00 0 0 1 &mpic 2 1 0x8e00 0 0 1 &mpic 2 1 0 0
0x8e00 0 0 2 &mpic 3 1 0x8e00 0 0 2 &mpic 3 1 0 0
0x8e00 0 0 3 &mpic 4 1 0x8e00 0 0 3 &mpic 4 1 0 0
0x8e00 0 0 4 &mpic 1 1 0x8e00 0 0 4 &mpic 1 1 0 0
/* IDSEL 0x11 func 7 - PCI slot 1 */ /* IDSEL 0x11 func 7 - PCI slot 1 */
0x8f00 0 0 1 &mpic 2 1 0x8f00 0 0 1 &mpic 2 1 0 0
0x8f00 0 0 2 &mpic 3 1 0x8f00 0 0 2 &mpic 3 1 0 0
0x8f00 0 0 3 &mpic 4 1 0x8f00 0 0 3 &mpic 4 1 0 0
0x8f00 0 0 4 &mpic 1 1 0x8f00 0 0 4 &mpic 1 1 0 0
/* IDSEL 0x12 func 0 - PCI slot 2 */ /* IDSEL 0x12 func 0 - PCI slot 2 */
0x9000 0 0 1 &mpic 3 1 0x9000 0 0 1 &mpic 3 1 0 0
0x9000 0 0 2 &mpic 4 1 0x9000 0 0 2 &mpic 4 1 0 0
0x9000 0 0 3 &mpic 1 1 0x9000 0 0 3 &mpic 1 1 0 0
0x9000 0 0 4 &mpic 2 1 0x9000 0 0 4 &mpic 2 1 0 0
/* IDSEL 0x12 func 1 - PCI slot 2 */ /* IDSEL 0x12 func 1 - PCI slot 2 */
0x9100 0 0 1 &mpic 3 1 0x9100 0 0 1 &mpic 3 1 0 0
0x9100 0 0 2 &mpic 4 1 0x9100 0 0 2 &mpic 4 1 0 0
0x9100 0 0 3 &mpic 1 1 0x9100 0 0 3 &mpic 1 1 0 0
0x9100 0 0 4 &mpic 2 1 0x9100 0 0 4 &mpic 2 1 0 0
/* IDSEL 0x12 func 2 - PCI slot 2 */ /* IDSEL 0x12 func 2 - PCI slot 2 */
0x9200 0 0 1 &mpic 3 1 0x9200 0 0 1 &mpic 3 1 0 0
0x9200 0 0 2 &mpic 4 1 0x9200 0 0 2 &mpic 4 1 0 0
0x9200 0 0 3 &mpic 1 1 0x9200 0 0 3 &mpic 1 1 0 0
0x9200 0 0 4 &mpic 2 1 0x9200 0 0 4 &mpic 2 1 0 0
/* IDSEL 0x12 func 3 - PCI slot 2 */ /* IDSEL 0x12 func 3 - PCI slot 2 */
0x9300 0 0 1 &mpic 3 1 0x9300 0 0 1 &mpic 3 1 0 0
0x9300 0 0 2 &mpic 4 1 0x9300 0 0 2 &mpic 4 1 0 0
0x9300 0 0 3 &mpic 1 1 0x9300 0 0 3 &mpic 1 1 0 0
0x9300 0 0 4 &mpic 2 1 0x9300 0 0 4 &mpic 2 1 0 0
/* IDSEL 0x12 func 4 - PCI slot 2 */ /* IDSEL 0x12 func 4 - PCI slot 2 */
0x9400 0 0 1 &mpic 3 1 0x9400 0 0 1 &mpic 3 1 0 0
0x9400 0 0 2 &mpic 4 1 0x9400 0 0 2 &mpic 4 1 0 0
0x9400 0 0 3 &mpic 1 1 0x9400 0 0 3 &mpic 1 1 0 0
0x9400 0 0 4 &mpic 2 1 0x9400 0 0 4 &mpic 2 1 0 0
/* IDSEL 0x12 func 5 - PCI slot 2 */ /* IDSEL 0x12 func 5 - PCI slot 2 */
0x9500 0 0 1 &mpic 3 1 0x9500 0 0 1 &mpic 3 1 0 0
0x9500 0 0 2 &mpic 4 1 0x9500 0 0 2 &mpic 4 1 0 0
0x9500 0 0 3 &mpic 1 1 0x9500 0 0 3 &mpic 1 1 0 0
0x9500 0 0 4 &mpic 2 1 0x9500 0 0 4 &mpic 2 1 0 0
/* IDSEL 0x12 func 6 - PCI slot 2 */ /* IDSEL 0x12 func 6 - PCI slot 2 */
0x9600 0 0 1 &mpic 3 1 0x9600 0 0 1 &mpic 3 1 0 0
0x9600 0 0 2 &mpic 4 1 0x9600 0 0 2 &mpic 4 1 0 0
0x9600 0 0 3 &mpic 1 1 0x9600 0 0 3 &mpic 1 1 0 0
0x9600 0 0 4 &mpic 2 1 0x9600 0 0 4 &mpic 2 1 0 0
/* IDSEL 0x12 func 7 - PCI slot 2 */ /* IDSEL 0x12 func 7 - PCI slot 2 */
0x9700 0 0 1 &mpic 3 1 0x9700 0 0 1 &mpic 3 1 0 0
0x9700 0 0 2 &mpic 4 1 0x9700 0 0 2 &mpic 4 1 0 0
0x9700 0 0 3 &mpic 1 1 0x9700 0 0 3 &mpic 1 1 0 0
0x9700 0 0 4 &mpic 2 1 0x9700 0 0 4 &mpic 2 1 0 0
// IDSEL 0x1c USB // IDSEL 0x1c USB
0xe000 0 0 1 &i8259 12 2 0xe000 0 0 1 &i8259 12 2
......
arch/powerpc/boot/dts/fsl/mpc8641si-post.dtsi
View file @ 12526b0d
...@@ -97,6 +97,7 @@ global-utilities@e0000 { ...@@ -97,6 +97,7 @@ global-utilities@e0000 {
&pci0 { &pci0 {
compatible = "fsl,mpc8641-pcie"; compatible = "fsl,mpc8641-pcie";
device_type = "pci"; device_type = "pci";
#interrupt-cells = <1>;
#size-cells = <2>; #size-cells = <2>;
#address-cells = <3>; #address-cells = <3>;
bus-range = <0x0 0xff>; bus-range = <0x0 0xff>;
...@@ -123,6 +124,7 @@ pcie@0 { ...@@ -123,6 +124,7 @@ pcie@0 {
&pci1 { &pci1 {
compatible = "fsl,mpc8641-pcie"; compatible = "fsl,mpc8641-pcie";
device_type = "pci"; device_type = "pci";
#interrupt-cells = <1>;
#size-cells = <2>; #size-cells = <2>;
#address-cells = <3>; #address-cells = <3>;
bus-range = <0x0 0xff>; bus-range = <0x0 0xff>;
......
arch/powerpc/boot/dts/fsl/p1020rdb-pc.dtsi
View file @ 12526b0d
...@@ -205,13 +205,13 @@ usb@23000 { ...@@ -205,13 +205,13 @@ usb@23000 {
mdio@24000 { mdio@24000 {
phy0: ethernet-phy@0 { phy0: ethernet-phy@0 {
interrupt-parent = <&mpic>; interrupt-parent = <&mpic>;
interrupts = <3 1>; interrupts = <3 1 0 0>;
reg = <0x0>; reg = <0x0>;
}; };
phy1: ethernet-phy@1 { phy1: ethernet-phy@1 {
interrupt-parent = <&mpic>; interrupt-parent = <&mpic>;
interrupts = <2 1>; interrupts = <2 1 0 0>;
reg = <0x1>; reg = <0x1>;
}; };
......
arch/powerpc/boot/dts/fsl/p2041si-post.dtsi
View file @ 12526b0d
...@@ -327,24 +327,6 @@ pins: global-utilities@e0e00 { ...@@ -327,24 +327,6 @@ pins: global-utilities@e0e00 {
/include/ "qoriq-clockgen1.dtsi" /include/ "qoriq-clockgen1.dtsi"
global-utilities@e1000 { global-utilities@e1000 {
compatible = "fsl,p2041-clockgen", "fsl,qoriq-clockgen-1.0"; compatible = "fsl,p2041-clockgen", "fsl,qoriq-clockgen-1.0";
mux2: mux2@40 {
#clock-cells = <0>;
reg = <0x40 0x4>;
compatible = "fsl,qoriq-core-mux-1.0";
clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
clock-output-names = "cmux2";
};
mux3: mux3@60 {
#clock-cells = <0>;
reg = <0x60 0x4>;
compatible = "fsl,qoriq-core-mux-1.0";
clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
clock-output-names = "cmux3";
};
}; };
rcpm: global-utilities@e2000 { rcpm: global-utilities@e2000 {
......
arch/powerpc/boot/dts/fsl/p2041si-pre.dtsi
View file @ 12526b0d
...@@ -89,7 +89,7 @@ cpus { ...@@ -89,7 +89,7 @@ cpus {
cpu0: PowerPC,e500mc@0 { cpu0: PowerPC,e500mc@0 {
device_type = "cpu"; device_type = "cpu";
reg = <0>; reg = <0>;
clocks = <&mux0>; clocks = <&clockgen 1 0>;
next-level-cache = <&L2_0>; next-level-cache = <&L2_0>;
fsl,portid-mapping = <0x80000000>; fsl,portid-mapping = <0x80000000>;
L2_0: l2-cache { L2_0: l2-cache {
...@@ -99,7 +99,7 @@ L2_0: l2-cache { ...@@ -99,7 +99,7 @@ L2_0: l2-cache {
cpu1: PowerPC,e500mc@1 { cpu1: PowerPC,e500mc@1 {
device_type = "cpu"; device_type = "cpu";
reg = <1>; reg = <1>;
clocks = <&mux1>; clocks = <&clockgen 1 1>;
next-level-cache = <&L2_1>; next-level-cache = <&L2_1>;
fsl,portid-mapping = <0x40000000>; fsl,portid-mapping = <0x40000000>;
L2_1: l2-cache { L2_1: l2-cache {
...@@ -109,7 +109,7 @@ L2_1: l2-cache { ...@@ -109,7 +109,7 @@ L2_1: l2-cache {
cpu2: PowerPC,e500mc@2 { cpu2: PowerPC,e500mc@2 {
device_type = "cpu"; device_type = "cpu";
reg = <2>; reg = <2>;
clocks = <&mux2>; clocks = <&clockgen 1 2>;
next-level-cache = <&L2_2>; next-level-cache = <&L2_2>;
fsl,portid-mapping = <0x20000000>; fsl,portid-mapping = <0x20000000>;
L2_2: l2-cache { L2_2: l2-cache {
...@@ -119,7 +119,7 @@ L2_2: l2-cache { ...@@ -119,7 +119,7 @@ L2_2: l2-cache {
cpu3: PowerPC,e500mc@3 { cpu3: PowerPC,e500mc@3 {
device_type = "cpu"; device_type = "cpu";
reg = <3>; reg = <3>;
clocks = <&mux3>; clocks = <&clockgen 1 3>;
next-level-cache = <&L2_3>; next-level-cache = <&L2_3>;
fsl,portid-mapping = <0x10000000>; fsl,portid-mapping = <0x10000000>;
L2_3: l2-cache { L2_3: l2-cache {
......
arch/powerpc/boot/dts/fsl/p3041si-post.dtsi
View file @ 12526b0d
...@@ -354,24 +354,6 @@ pins: global-utilities@e0e00 { ...@@ -354,24 +354,6 @@ pins: global-utilities@e0e00 {
/include/ "qoriq-clockgen1.dtsi" /include/ "qoriq-clockgen1.dtsi"
global-utilities@e1000 { global-utilities@e1000 {
compatible = "fsl,p3041-clockgen", "fsl,qoriq-clockgen-1.0"; compatible = "fsl,p3041-clockgen", "fsl,qoriq-clockgen-1.0";
mux2: mux2@40 {
#clock-cells = <0>;
reg = <0x40 0x4>;
compatible = "fsl,qoriq-core-mux-1.0";
clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
clock-output-names = "cmux2";
};
mux3: mux3@60 {
#clock-cells = <0>;
reg = <0x60 0x4>;
compatible = "fsl,qoriq-core-mux-1.0";
clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
clock-output-names = "cmux3";
};
}; };
rcpm: global-utilities@e2000 { rcpm: global-utilities@e2000 {
......
arch/powerpc/boot/dts/fsl/p3041si-pre.dtsi
View file @ 12526b0d
...@@ -90,7 +90,7 @@ cpus { ...@@ -90,7 +90,7 @@ cpus {
cpu0: PowerPC,e500mc@0 { cpu0: PowerPC,e500mc@0 {
device_type = "cpu"; device_type = "cpu";
reg = <0>; reg = <0>;
clocks = <&mux0>; clocks = <&clockgen 1 0>;
next-level-cache = <&L2_0>; next-level-cache = <&L2_0>;
fsl,portid-mapping = <0x80000000>; fsl,portid-mapping = <0x80000000>;
L2_0: l2-cache { L2_0: l2-cache {
...@@ -100,7 +100,7 @@ L2_0: l2-cache { ...@@ -100,7 +100,7 @@ L2_0: l2-cache {
cpu1: PowerPC,e500mc@1 { cpu1: PowerPC,e500mc@1 {
device_type = "cpu"; device_type = "cpu";
reg = <1>; reg = <1>;
clocks = <&mux1>; clocks = <&clockgen 1 1>;
next-level-cache = <&L2_1>; next-level-cache = <&L2_1>;
fsl,portid-mapping = <0x40000000>; fsl,portid-mapping = <0x40000000>;
L2_1: l2-cache { L2_1: l2-cache {
...@@ -110,7 +110,7 @@ L2_1: l2-cache { ...@@ -110,7 +110,7 @@ L2_1: l2-cache {
cpu2: PowerPC,e500mc@2 { cpu2: PowerPC,e500mc@2 {
device_type = "cpu"; device_type = "cpu";
reg = <2>; reg = <2>;
clocks = <&mux2>; clocks = <&clockgen 1 2>;
next-level-cache = <&L2_2>; next-level-cache = <&L2_2>;
fsl,portid-mapping = <0x20000000>; fsl,portid-mapping = <0x20000000>;
L2_2: l2-cache { L2_2: l2-cache {
...@@ -120,7 +120,7 @@ L2_2: l2-cache { ...@@ -120,7 +120,7 @@ L2_2: l2-cache {
cpu3: PowerPC,e500mc@3 { cpu3: PowerPC,e500mc@3 {
device_type = "cpu"; device_type = "cpu";
reg = <3>; reg = <3>;
clocks = <&mux3>; clocks = <&clockgen 1 3>;
next-level-cache = <&L2_3>; next-level-cache = <&L2_3>;
fsl,portid-mapping = <0x10000000>; fsl,portid-mapping = <0x10000000>;
L2_3: l2-cache { L2_3: l2-cache {
......
arch/powerpc/boot/dts/fsl/p4080si-post.dtsi
View file @ 12526b0d
...@@ -374,76 +374,6 @@ pins: global-utilities@e0e00 { ...@@ -374,76 +374,6 @@ pins: global-utilities@e0e00 {
/include/ "qoriq-clockgen1.dtsi" /include/ "qoriq-clockgen1.dtsi"
global-utilities@e1000 { global-utilities@e1000 {
compatible = "fsl,p4080-clockgen", "fsl,qoriq-clockgen-1.0"; compatible = "fsl,p4080-clockgen", "fsl,qoriq-clockgen-1.0";
pll2: pll2@840 {
#clock-cells = <1>;
reg = <0x840 0x4>;
compatible = "fsl,qoriq-core-pll-1.0";
clocks = <&sysclk>;
clock-output-names = "pll2", "pll2-div2";
};
pll3: pll3@860 {
#clock-cells = <1>;
reg = <0x860 0x4>;
compatible = "fsl,qoriq-core-pll-1.0";
clocks = <&sysclk>;
clock-output-names = "pll3", "pll3-div2";
};
mux2: mux2@40 {
#clock-cells = <0>;
reg = <0x40 0x4>;
compatible = "fsl,qoriq-core-mux-1.0";
clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
clock-output-names = "cmux2";
};
mux3: mux3@60 {
#clock-cells = <0>;
reg = <0x60 0x4>;
compatible = "fsl,qoriq-core-mux-1.0";
clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
clock-output-names = "cmux3";
};
mux4: mux4@80 {
#clock-cells = <0>;
reg = <0x80 0x4>;
compatible = "fsl,qoriq-core-mux-1.0";
clocks = <&pll2 0>, <&pll2 1>, <&pll3 0>, <&pll3 1>;
clock-names = "pll2", "pll2-div2", "pll3", "pll3-div2";
clock-output-names = "cmux4";
};
mux5: mux5@a0 {
#clock-cells = <0>;
reg = <0xa0 0x4>;
compatible = "fsl,qoriq-core-mux-1.0";
clocks = <&pll2 0>, <&pll2 1>, <&pll3 0>, <&pll3 1>;
clock-names = "pll2", "pll2-div2", "pll3", "pll3-div2";
clock-output-names = "cmux5";
};
mux6: mux6@c0 {
#clock-cells = <0>;
reg = <0xc0 0x4>;
compatible = "fsl,qoriq-core-mux-1.0";
clocks = <&pll2 0>, <&pll2 1>, <&pll3 0>, <&pll3 1>;
clock-names = "pll2", "pll2-div2", "pll3", "pll3-div2";
clock-output-names = "cmux6";
};
mux7: mux7@e0 {
#clock-cells = <0>;
reg = <0xe0 0x4>;
compatible = "fsl,qoriq-core-mux-1.0";
clocks = <&pll2 0>, <&pll2 1>, <&pll3 0>, <&pll3 1>;
clock-names = "pll2", "pll2-div2", "pll3", "pll3-div2";
clock-output-names = "cmux7";
};
}; };
rcpm: global-utilities@e2000 { rcpm: global-utilities@e2000 {
......
arch/powerpc/boot/dts/fsl/p4080si-pre.dtsi
View file @ 12526b0d
...@@ -94,7 +94,7 @@ cpus { ...@@ -94,7 +94,7 @@ cpus {
cpu0: PowerPC,e500mc@0 { cpu0: PowerPC,e500mc@0 {
device_type = "cpu"; device_type = "cpu";
reg = <0>; reg = <0>;
clocks = <&mux0>; clocks = <&clockgen 1 0>;
next-level-cache = <&L2_0>; next-level-cache = <&L2_0>;
fsl,portid-mapping = <0x80000000>; fsl,portid-mapping = <0x80000000>;
L2_0: l2-cache { L2_0: l2-cache {
...@@ -104,7 +104,7 @@ L2_0: l2-cache { ...@@ -104,7 +104,7 @@ L2_0: l2-cache {
cpu1: PowerPC,e500mc@1 { cpu1: PowerPC,e500mc@1 {
device_type = "cpu"; device_type = "cpu";
reg = <1>; reg = <1>;
clocks = <&mux1>; clocks = <&clockgen 1 1>;
next-level-cache = <&L2_1>; next-level-cache = <&L2_1>;
fsl,portid-mapping = <0x40000000>; fsl,portid-mapping = <0x40000000>;
L2_1: l2-cache { L2_1: l2-cache {
...@@ -114,7 +114,7 @@ L2_1: l2-cache { ...@@ -114,7 +114,7 @@ L2_1: l2-cache {
cpu2: PowerPC,e500mc@2 { cpu2: PowerPC,e500mc@2 {
device_type = "cpu"; device_type = "cpu";
reg = <2>; reg = <2>;
clocks = <&mux2>; clocks = <&clockgen 1 2>;
next-level-cache = <&L2_2>; next-level-cache = <&L2_2>;
fsl,portid-mapping = <0x20000000>; fsl,portid-mapping = <0x20000000>;
L2_2: l2-cache { L2_2: l2-cache {
...@@ -124,7 +124,7 @@ L2_2: l2-cache { ...@@ -124,7 +124,7 @@ L2_2: l2-cache {
cpu3: PowerPC,e500mc@3 { cpu3: PowerPC,e500mc@3 {
device_type = "cpu"; device_type = "cpu";
reg = <3>; reg = <3>;
clocks = <&mux3>; clocks = <&clockgen 1 3>;
next-level-cache = <&L2_3>; next-level-cache = <&L2_3>;
fsl,portid-mapping = <0x10000000>; fsl,portid-mapping = <0x10000000>;
L2_3: l2-cache { L2_3: l2-cache {
...@@ -134,7 +134,7 @@ L2_3: l2-cache { ...@@ -134,7 +134,7 @@ L2_3: l2-cache {
cpu4: PowerPC,e500mc@4 { cpu4: PowerPC,e500mc@4 {
device_type = "cpu"; device_type = "cpu";
reg = <4>; reg = <4>;
clocks = <&mux4>; clocks = <&clockgen 1 4>;
next-level-cache = <&L2_4>; next-level-cache = <&L2_4>;
fsl,portid-mapping = <0x08000000>; fsl,portid-mapping = <0x08000000>;
L2_4: l2-cache { L2_4: l2-cache {
...@@ -144,7 +144,7 @@ L2_4: l2-cache { ...@@ -144,7 +144,7 @@ L2_4: l2-cache {
cpu5: PowerPC,e500mc@5 { cpu5: PowerPC,e500mc@5 {
device_type = "cpu"; device_type = "cpu";
reg = <5>; reg = <5>;
clocks = <&mux5>; clocks = <&clockgen 1 5>;
next-level-cache = <&L2_5>; next-level-cache = <&L2_5>;
fsl,portid-mapping = <0x04000000>; fsl,portid-mapping = <0x04000000>;
L2_5: l2-cache { L2_5: l2-cache {
...@@ -154,7 +154,7 @@ L2_5: l2-cache { ...@@ -154,7 +154,7 @@ L2_5: l2-cache {
cpu6: PowerPC,e500mc@6 { cpu6: PowerPC,e500mc@6 {
device_type = "cpu"; device_type = "cpu";
reg = <6>; reg = <6>;
clocks = <&mux6>; clocks = <&clockgen 1 6>;
next-level-cache = <&L2_6>; next-level-cache = <&L2_6>;
fsl,portid-mapping = <0x02000000>; fsl,portid-mapping = <0x02000000>;
L2_6: l2-cache { L2_6: l2-cache {
...@@ -164,7 +164,7 @@ L2_6: l2-cache { ...@@ -164,7 +164,7 @@ L2_6: l2-cache {
cpu7: PowerPC,e500mc@7 { cpu7: PowerPC,e500mc@7 {
device_type = "cpu"; device_type = "cpu";
reg = <7>; reg = <7>;
clocks = <&mux7>; clocks = <&clockgen 1 7>;
next-level-cache = <&L2_7>; next-level-cache = <&L2_7>;
fsl,portid-mapping = <0x01000000>; fsl,portid-mapping = <0x01000000>;
L2_7: l2-cache { L2_7: l2-cache {
......
arch/powerpc/boot/dts/fsl/p5020si-pre.dtsi
View file @ 12526b0d
...@@ -96,7 +96,7 @@ cpus { ...@@ -96,7 +96,7 @@ cpus {
cpu0: PowerPC,e5500@0 { cpu0: PowerPC,e5500@0 {
device_type = "cpu"; device_type = "cpu";
reg = <0>; reg = <0>;
clocks = <&mux0>; clocks = <&clockgen 1 0>;
next-level-cache = <&L2_0>; next-level-cache = <&L2_0>;
fsl,portid-mapping = <0x80000000>; fsl,portid-mapping = <0x80000000>;
L2_0: l2-cache { L2_0: l2-cache {
...@@ -106,7 +106,7 @@ L2_0: l2-cache { ...@@ -106,7 +106,7 @@ L2_0: l2-cache {
cpu1: PowerPC,e5500@1 { cpu1: PowerPC,e5500@1 {
device_type = "cpu"; device_type = "cpu";
reg = <1>; reg = <1>;
clocks = <&mux1>; clocks = <&clockgen 1 1>;
next-level-cache = <&L2_1>; next-level-cache = <&L2_1>;
fsl,portid-mapping = <0x40000000>; fsl,portid-mapping = <0x40000000>;
L2_1: l2-cache { L2_1: l2-cache {
......
arch/powerpc/boot/dts/fsl/p5040si-post.dtsi
View file @ 12526b0d
...@@ -319,24 +319,6 @@ pins: global-utilities@e0e00 { ...@@ -319,24 +319,6 @@ pins: global-utilities@e0e00 {
/include/ "qoriq-clockgen1.dtsi" /include/ "qoriq-clockgen1.dtsi"
global-utilities@e1000 { global-utilities@e1000 {
compatible = "fsl,p5040-clockgen", "fsl,qoriq-clockgen-1.0"; compatible = "fsl,p5040-clockgen", "fsl,qoriq-clockgen-1.0";
mux2: mux2@40 {
#clock-cells = <0>;
reg = <0x40 0x4>;
compatible = "fsl,qoriq-core-mux-1.0";
clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
clock-output-names = "cmux2";
};
mux3: mux3@60 {
#clock-cells = <0>;
reg = <0x60 0x4>;
compatible = "fsl,qoriq-core-mux-1.0";
clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
clock-output-names = "cmux3";
};
}; };
rcpm: global-utilities@e2000 { rcpm: global-utilities@e2000 {
......
arch/powerpc/boot/dts/fsl/p5040si-pre.dtsi
View file @ 12526b0d
...@@ -102,7 +102,7 @@ cpus { ...@@ -102,7 +102,7 @@ cpus {
cpu0: PowerPC,e5500@0 { cpu0: PowerPC,e5500@0 {
device_type = "cpu"; device_type = "cpu";
reg = <0>; reg = <0>;
clocks = <&mux0>; clocks = <&clockgen 1 0>;
next-level-cache = <&L2_0>; next-level-cache = <&L2_0>;
fsl,portid-mapping = <0x80000000>; fsl,portid-mapping = <0x80000000>;
L2_0: l2-cache { L2_0: l2-cache {
...@@ -112,7 +112,7 @@ L2_0: l2-cache { ...@@ -112,7 +112,7 @@ L2_0: l2-cache {
cpu1: PowerPC,e5500@1 { cpu1: PowerPC,e5500@1 {
device_type = "cpu"; device_type = "cpu";
reg = <1>; reg = <1>;
clocks = <&mux1>; clocks = <&clockgen 1 1>;
next-level-cache = <&L2_1>; next-level-cache = <&L2_1>;
fsl,portid-mapping = <0x40000000>; fsl,portid-mapping = <0x40000000>;
L2_1: l2-cache { L2_1: l2-cache {
...@@ -122,7 +122,7 @@ L2_1: l2-cache { ...@@ -122,7 +122,7 @@ L2_1: l2-cache {
cpu2: PowerPC,e5500@2 { cpu2: PowerPC,e5500@2 {
device_type = "cpu"; device_type = "cpu";
reg = <2>; reg = <2>;
clocks = <&mux2>; clocks = <&clockgen 1 2>;
next-level-cache = <&L2_2>; next-level-cache = <&L2_2>;
fsl,portid-mapping = <0x20000000>; fsl,portid-mapping = <0x20000000>;
L2_2: l2-cache { L2_2: l2-cache {
...@@ -132,7 +132,7 @@ L2_2: l2-cache { ...@@ -132,7 +132,7 @@ L2_2: l2-cache {
cpu3: PowerPC,e5500@3 { cpu3: PowerPC,e5500@3 {
device_type = "cpu"; device_type = "cpu";
reg = <3>; reg = <3>;
clocks = <&mux3>; clocks = <&clockgen 1 3>;
next-level-cache = <&L2_3>; next-level-cache = <&L2_3>;
fsl,portid-mapping = <0x10000000>; fsl,portid-mapping = <0x10000000>;
L2_3: l2-cache { L2_3: l2-cache {
......
arch/powerpc/boot/dts/fsl/qoriq-clockgen1.dtsi
View file @ 12526b0d
...@@ -34,53 +34,6 @@ ...@@ -34,53 +34,6 @@
clockgen: global-utilities@e1000 { clockgen: global-utilities@e1000 {
compatible = "fsl,qoriq-clockgen-1.0"; compatible = "fsl,qoriq-clockgen-1.0";
ranges = <0x0 0xe1000 0x1000>;
reg = <0xe1000 0x1000>; reg = <0xe1000 0x1000>;
clock-frequency = <0>;
#address-cells = <1>;
#size-cells = <1>;
#clock-cells = <2>; #clock-cells = <2>;
sysclk: sysclk {
#clock-cells = <0>;
compatible = "fsl,qoriq-sysclk-1.0", "fixed-clock";
clock-output-names = "sysclk";
};
pll0: pll0@800 {
#clock-cells = <1>;
reg = <0x800 0x4>;
compatible = "fsl,qoriq-core-pll-1.0";
clocks = <&sysclk>;
clock-output-names = "pll0", "pll0-div2";
};
pll1: pll1@820 {
#clock-cells = <1>;
reg = <0x820 0x4>;
compatible = "fsl,qoriq-core-pll-1.0";
clocks = <&sysclk>;
clock-output-names = "pll1", "pll1-div2";
};
mux0: mux0@0 {
#clock-cells = <0>;
reg = <0x0 0x4>;
compatible = "fsl,qoriq-core-mux-1.0";
clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
clock-output-names = "cmux0";
};
mux1: mux1@20 {
#clock-cells = <0>;
reg = <0x20 0x4>;
compatible = "fsl,qoriq-core-mux-1.0";
clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
clock-output-names = "cmux1";
};
platform_pll: platform-pll@c00 {
#clock-cells = <1>;
reg = <0xc00 0x4>;
compatible = "fsl,qoriq-platform-pll-1.0";
clocks = <&sysclk>;
clock-output-names = "platform-pll", "platform-pll-div2";
};
}; };
arch/powerpc/boot/dts/fsl/qoriq-clockgen2.dtsi
View file @ 12526b0d
...@@ -34,36 +34,6 @@ ...@@ -34,36 +34,6 @@
clockgen: global-utilities@e1000 { clockgen: global-utilities@e1000 {
compatible = "fsl,qoriq-clockgen-2.0"; compatible = "fsl,qoriq-clockgen-2.0";
ranges = <0x0 0xe1000 0x1000>;
reg = <0xe1000 0x1000>; reg = <0xe1000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
#clock-cells = <2>; #clock-cells = <2>;
sysclk: sysclk {
#clock-cells = <0>;
compatible = "fsl,qoriq-sysclk-2.0", "fixed-clock";
clock-output-names = "sysclk";
};
pll0: pll0@800 {
#clock-cells = <1>;
reg = <0x800 0x4>;
compatible = "fsl,qoriq-core-pll-2.0";
clocks = <&sysclk>;
clock-output-names = "pll0", "pll0-div2", "pll0-div4";
};
pll1: pll1@820 {
#clock-cells = <1>;
reg = <0x820 0x4>;
compatible = "fsl,qoriq-core-pll-2.0";
clocks = <&sysclk>;
clock-output-names = "pll1", "pll1-div2", "pll1-div4";
};
platform_pll: platform-pll@c00 {
#clock-cells = <1>;
reg = <0xc00 0x4>;
compatible = "fsl,qoriq-platform-pll-2.0";
clocks = <&sysclk>;
clock-output-names = "platform-pll", "platform-pll-div2";
};
}; };
arch/powerpc/boot/dts/fsl/t1023si-post.dtsi
View file @ 12526b0d
...@@ -345,22 +345,6 @@ guts: global-utilities@e0000 { ...@@ -345,22 +345,6 @@ guts: global-utilities@e0000 {
/include/ "qoriq-clockgen2.dtsi" /include/ "qoriq-clockgen2.dtsi"
global-utilities@e1000 { global-utilities@e1000 {
compatible = "fsl,t1023-clockgen", "fsl,qoriq-clockgen-2.0"; compatible = "fsl,t1023-clockgen", "fsl,qoriq-clockgen-2.0";
mux0: mux0@0 {
#clock-cells = <0>;
reg = <0x0 4>;
compatible = "fsl,core-mux-clock";
clocks = <&pll0 0>, <&pll0 1>;
clock-names = "pll0_0", "pll0_1";
clock-output-names = "cmux0";
};
mux1: mux1@20 {
#clock-cells = <0>;
reg = <0x20 4>;
compatible = "fsl,core-mux-clock";
clocks = <&pll0 0>, <&pll0 1>;
clock-names = "pll0_0", "pll0_1";
clock-output-names = "cmux1";
};
}; };
rcpm: global-utilities@e2000 { rcpm: global-utilities@e2000 {
......
arch/powerpc/boot/dts/fsl/t102xsi-pre.dtsi
View file @ 12526b0d
...@@ -74,7 +74,7 @@ cpus { ...@@ -74,7 +74,7 @@ cpus {
cpu0: PowerPC,e5500@0 { cpu0: PowerPC,e5500@0 {
device_type = "cpu"; device_type = "cpu";
reg = <0>; reg = <0>;
clocks = <&mux0>; clocks = <&clockgen 1 0>;
next-level-cache = <&L2_1>; next-level-cache = <&L2_1>;
#cooling-cells = <2>; #cooling-cells = <2>;
L2_1: l2-cache { L2_1: l2-cache {
...@@ -84,7 +84,7 @@ L2_1: l2-cache { ...@@ -84,7 +84,7 @@ L2_1: l2-cache {
cpu1: PowerPC,e5500@1 { cpu1: PowerPC,e5500@1 {
device_type = "cpu"; device_type = "cpu";
reg = <1>; reg = <1>;
clocks = <&mux1>; clocks = <&clockgen 1 1>;
next-level-cache = <&L2_2>; next-level-cache = <&L2_2>;
#cooling-cells = <2>; #cooling-cells = <2>;
L2_2: l2-cache { L2_2: l2-cache {
......
arch/powerpc/boot/dts/fsl/t1040si-post.dtsi
View file @ 12526b0d
...@@ -425,50 +425,6 @@ guts: global-utilities@e0000 { ...@@ -425,50 +425,6 @@ guts: global-utilities@e0000 {
/include/ "qoriq-clockgen2.dtsi" /include/ "qoriq-clockgen2.dtsi"
global-utilities@e1000 { global-utilities@e1000 {
compatible = "fsl,t1040-clockgen", "fsl,qoriq-clockgen-2.0"; compatible = "fsl,t1040-clockgen", "fsl,qoriq-clockgen-2.0";
mux0: mux0@0 {
#clock-cells = <0>;
reg = <0x0 4>;
compatible = "fsl,qoriq-core-mux-2.0";
clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>,
<&pll1 0>, <&pll1 1>, <&pll1 2>;
clock-names = "pll0", "pll0-div2", "pll1-div4",
"pll1", "pll1-div2", "pll1-div4";
clock-output-names = "cmux0";
};
mux1: mux1@20 {
#clock-cells = <0>;
reg = <0x20 4>;
compatible = "fsl,qoriq-core-mux-2.0";
clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>,
<&pll1 0>, <&pll1 1>, <&pll1 2>;
clock-names = "pll0", "pll0-div2", "pll1-div4",
"pll1", "pll1-div2", "pll1-div4";
clock-output-names = "cmux1";
};
mux2: mux2@40 {
#clock-cells = <0>;
reg = <0x40 4>;
compatible = "fsl,qoriq-core-mux-2.0";
clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>,
<&pll1 0>, <&pll1 1>, <&pll1 2>;
clock-names = "pll0", "pll0-div2", "pll1-div4",
"pll1", "pll1-div2", "pll1-div4";
clock-output-names = "cmux2";
};
mux3: mux3@60 {
#clock-cells = <0>;
reg = <0x60 4>;
compatible = "fsl,qoriq-core-mux-2.0";
clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>,
<&pll1 0>, <&pll1 1>, <&pll1 2>;
clock-names = "pll0_0", "pll0_1", "pll0_2",
"pll1_0", "pll1_1", "pll1_2";
clock-output-names = "cmux3";
};
}; };
rcpm: global-utilities@e2000 { rcpm: global-utilities@e2000 {
......
arch/powerpc/boot/dts/fsl/t104xsi-pre.dtsi
View file @ 12526b0d
...@@ -74,7 +74,7 @@ cpus { ...@@ -74,7 +74,7 @@ cpus {
cpu0: PowerPC,e5500@0 { cpu0: PowerPC,e5500@0 {
device_type = "cpu"; device_type = "cpu";
reg = <0>; reg = <0>;
clocks = <&mux0>; clocks = <&clockgen 1 0>;
next-level-cache = <&L2_1>; next-level-cache = <&L2_1>;
#cooling-cells = <2>; #cooling-cells = <2>;
L2_1: l2-cache { L2_1: l2-cache {
...@@ -84,7 +84,7 @@ L2_1: l2-cache { ...@@ -84,7 +84,7 @@ L2_1: l2-cache {
cpu1: PowerPC,e5500@1 { cpu1: PowerPC,e5500@1 {
device_type = "cpu"; device_type = "cpu";
reg = <1>; reg = <1>;
clocks = <&mux1>; clocks = <&clockgen 1 1>;
next-level-cache = <&L2_2>; next-level-cache = <&L2_2>;
#cooling-cells = <2>; #cooling-cells = <2>;
L2_2: l2-cache { L2_2: l2-cache {
...@@ -94,7 +94,7 @@ L2_2: l2-cache { ...@@ -94,7 +94,7 @@ L2_2: l2-cache {
cpu2: PowerPC,e5500@2 { cpu2: PowerPC,e5500@2 {
device_type = "cpu"; device_type = "cpu";
reg = <2>; reg = <2>;
clocks = <&mux2>; clocks = <&clockgen 1 2>;
next-level-cache = <&L2_3>; next-level-cache = <&L2_3>;
#cooling-cells = <2>; #cooling-cells = <2>;
L2_3: l2-cache { L2_3: l2-cache {
...@@ -104,7 +104,7 @@ L2_3: l2-cache { ...@@ -104,7 +104,7 @@ L2_3: l2-cache {
cpu3: PowerPC,e5500@3 { cpu3: PowerPC,e5500@3 {
device_type = "cpu"; device_type = "cpu";
reg = <3>; reg = <3>;
clocks = <&mux3>; clocks = <&clockgen 1 3>;
next-level-cache = <&L2_4>; next-level-cache = <&L2_4>;
#cooling-cells = <2>; #cooling-cells = <2>;
L2_4: l2-cache { L2_4: l2-cache {
......
arch/powerpc/boot/dts/fsl/t2081si-post.dtsi
View file @ 12526b0d
...@@ -535,28 +535,6 @@ guts: global-utilities@e0000 { ...@@ -535,28 +535,6 @@ guts: global-utilities@e0000 {
/include/ "qoriq-clockgen2.dtsi" /include/ "qoriq-clockgen2.dtsi"
global-utilities@e1000 { global-utilities@e1000 {
compatible = "fsl,t2080-clockgen", "fsl,qoriq-clockgen-2.0"; compatible = "fsl,t2080-clockgen", "fsl,qoriq-clockgen-2.0";
mux0: mux0@0 {
#clock-cells = <0>;
reg = <0x0 4>;
compatible = "fsl,qoriq-core-mux-2.0";
clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>,
<&pll1 0>, <&pll1 1>, <&pll1 2>;
clock-names = "pll0", "pll0-div2", "pll0-div4",
"pll1", "pll1-div2", "pll1-div4";
clock-output-names = "cmux0";
};
mux1: mux1@20 {
#clock-cells = <0>;
reg = <0x20 4>;
compatible = "fsl,qoriq-core-mux-2.0";
clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>,
<&pll1 0>, <&pll1 1>, <&pll1 2>;
clock-names = "pll0", "pll0-div2", "pll0-div4",
"pll1", "pll1-div2", "pll1-div4";
clock-output-names = "cmux1";
};
}; };
rcpm: global-utilities@e2000 { rcpm: global-utilities@e2000 {
......
arch/powerpc/boot/dts/fsl/t208xsi-pre.dtsi
View file @ 12526b0d
...@@ -81,28 +81,28 @@ cpus { ...@@ -81,28 +81,28 @@ cpus {
cpu0: PowerPC,e6500@0 { cpu0: PowerPC,e6500@0 {
device_type = "cpu"; device_type = "cpu";
reg = <0 1>; reg = <0 1>;
clocks = <&mux0>; clocks = <&clockgen 1 0>;
next-level-cache = <&L2_1>; next-level-cache = <&L2_1>;
fsl,portid-mapping = <0x80000000>; fsl,portid-mapping = <0x80000000>;
}; };
cpu1: PowerPC,e6500@2 { cpu1: PowerPC,e6500@2 {
device_type = "cpu"; device_type = "cpu";
reg = <2 3>; reg = <2 3>;
clocks = <&mux0>; clocks = <&clockgen 1 0>;
next-level-cache = <&L2_1>; next-level-cache = <&L2_1>;
fsl,portid-mapping = <0x80000000>; fsl,portid-mapping = <0x80000000>;
}; };
cpu2: PowerPC,e6500@4 { cpu2: PowerPC,e6500@4 {
device_type = "cpu"; device_type = "cpu";
reg = <4 5>; reg = <4 5>;
clocks = <&mux0>; clocks = <&clockgen 1 0>;
next-level-cache = <&L2_1>; next-level-cache = <&L2_1>;
fsl,portid-mapping = <0x80000000>; fsl,portid-mapping = <0x80000000>;
}; };
cpu3: PowerPC,e6500@6 { cpu3: PowerPC,e6500@6 {
device_type = "cpu"; device_type = "cpu";
reg = <6 7>; reg = <6 7>;
clocks = <&mux0>; clocks = <&clockgen 1 0>;
next-level-cache = <&L2_1>; next-level-cache = <&L2_1>;
fsl,portid-mapping = <0x80000000>; fsl,portid-mapping = <0x80000000>;
}; };
......
arch/powerpc/boot/dts/fsl/t4240si-post.dtsi
View file @ 12526b0d
...@@ -950,67 +950,6 @@ guts: global-utilities@e0000 { ...@@ -950,67 +950,6 @@ guts: global-utilities@e0000 {
/include/ "qoriq-clockgen2.dtsi" /include/ "qoriq-clockgen2.dtsi"
global-utilities@e1000 { global-utilities@e1000 {
compatible = "fsl,t4240-clockgen", "fsl,qoriq-clockgen-2.0"; compatible = "fsl,t4240-clockgen", "fsl,qoriq-clockgen-2.0";
pll2: pll2@840 {
#clock-cells = <1>;
reg = <0x840 0x4>;
compatible = "fsl,qoriq-core-pll-2.0";
clocks = <&sysclk>;
clock-output-names = "pll2", "pll2-div2", "pll2-div4";
};
pll3: pll3@860 {
#clock-cells = <1>;
reg = <0x860 0x4>;
compatible = "fsl,qoriq-core-pll-2.0";
clocks = <&sysclk>;
clock-output-names = "pll3", "pll3-div2", "pll3-div4";
};
pll4: pll4@880 {
#clock-cells = <1>;
reg = <0x880 0x4>;
compatible = "fsl,qoriq-core-pll-2.0";
clocks = <&sysclk>;
clock-output-names = "pll4", "pll4-div2", "pll4-div4";
};
mux0: mux0@0 {
#clock-cells = <0>;
reg = <0x0 0x4>;
compatible = "fsl,qoriq-core-mux-2.0";
clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>,
<&pll1 0>, <&pll1 1>, <&pll1 2>,
<&pll2 0>, <&pll2 1>, <&pll2 2>;
clock-names = "pll0", "pll0-div2", "pll0-div4",
"pll1", "pll1-div2", "pll1-div4",
"pll2", "pll2-div2", "pll2-div4";
clock-output-names = "cmux0";
};
mux1: mux1@20 {
#clock-cells = <0>;
reg = <0x20 0x4>;
compatible = "fsl,qoriq-core-mux-2.0";
clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>,
<&pll1 0>, <&pll1 1>, <&pll1 2>,
<&pll2 0>, <&pll2 1>, <&pll2 2>;
clock-names = "pll0", "pll0-div2", "pll0-div4",
"pll1", "pll1-div2", "pll1-div4",
"pll2", "pll2-div2", "pll2-div4";
clock-output-names = "cmux1";
};
mux2: mux2@40 {
#clock-cells = <0>;
reg = <0x40 0x4>;
compatible = "fsl,qoriq-core-mux-2.0";
clocks = <&pll3 0>, <&pll3 1>, <&pll3 2>,
<&pll4 0>, <&pll4 1>, <&pll4 2>;
clock-names = "pll3", "pll3-div2", "pll3-div4",
"pll4", "pll4-div2", "pll4-div4";
clock-output-names = "cmux2";
};
}; };
rcpm: global-utilities@e2000 { rcpm: global-utilities@e2000 {
......
arch/powerpc/boot/dts/fsl/t4240si-pre.dtsi
View file @ 12526b0d
...@@ -90,84 +90,84 @@ cpus { ...@@ -90,84 +90,84 @@ cpus {
cpu0: PowerPC,e6500@0 { cpu0: PowerPC,e6500@0 {
device_type = "cpu"; device_type = "cpu";
reg = <0 1>; reg = <0 1>;
clocks = <&mux0>; clocks = <&clockgen 1 0>;
next-level-cache = <&L2_1>; next-level-cache = <&L2_1>;
fsl,portid-mapping = <0x80000000>; fsl,portid-mapping = <0x80000000>;
}; };
cpu1: PowerPC,e6500@2 { cpu1: PowerPC,e6500@2 {
device_type = "cpu"; device_type = "cpu";
reg = <2 3>; reg = <2 3>;
clocks = <&mux0>; clocks = <&clockgen 1 0>;
next-level-cache = <&L2_1>; next-level-cache = <&L2_1>;
fsl,portid-mapping = <0x80000000>; fsl,portid-mapping = <0x80000000>;
}; };
cpu2: PowerPC,e6500@4 { cpu2: PowerPC,e6500@4 {
device_type = "cpu"; device_type = "cpu";
reg = <4 5>; reg = <4 5>;
clocks = <&mux0>; clocks = <&clockgen 1 0>;
next-level-cache = <&L2_1>; next-level-cache = <&L2_1>;
fsl,portid-mapping = <0x80000000>; fsl,portid-mapping = <0x80000000>;
}; };
cpu3: PowerPC,e6500@6 { cpu3: PowerPC,e6500@6 {
device_type = "cpu"; device_type = "cpu";
reg = <6 7>; reg = <6 7>;
clocks = <&mux0>; clocks = <&clockgen 1 0>;
next-level-cache = <&L2_1>; next-level-cache = <&L2_1>;
fsl,portid-mapping = <0x80000000>; fsl,portid-mapping = <0x80000000>;
}; };
cpu4: PowerPC,e6500@8 { cpu4: PowerPC,e6500@8 {
device_type = "cpu"; device_type = "cpu";
reg = <8 9>; reg = <8 9>;
clocks = <&mux1>; clocks = <&clockgen 1 1>;
next-level-cache = <&L2_2>; next-level-cache = <&L2_2>;
fsl,portid-mapping = <0x40000000>; fsl,portid-mapping = <0x40000000>;
}; };
cpu5: PowerPC,e6500@10 { cpu5: PowerPC,e6500@10 {
device_type = "cpu"; device_type = "cpu";
reg = <10 11>; reg = <10 11>;
clocks = <&mux1>; clocks = <&clockgen 1 1>;
next-level-cache = <&L2_2>; next-level-cache = <&L2_2>;
fsl,portid-mapping = <0x40000000>; fsl,portid-mapping = <0x40000000>;
}; };
cpu6: PowerPC,e6500@12 { cpu6: PowerPC,e6500@12 {
device_type = "cpu"; device_type = "cpu";
reg = <12 13>; reg = <12 13>;
clocks = <&mux1>; clocks = <&clockgen 1 1>;
next-level-cache = <&L2_2>; next-level-cache = <&L2_2>;
fsl,portid-mapping = <0x40000000>; fsl,portid-mapping = <0x40000000>;
}; };
cpu7: PowerPC,e6500@14 { cpu7: PowerPC,e6500@14 {
device_type = "cpu"; device_type = "cpu";
reg = <14 15>; reg = <14 15>;
clocks = <&mux1>; clocks = <&clockgen 1 1>;
next-level-cache = <&L2_2>; next-level-cache = <&L2_2>;
fsl,portid-mapping = <0x40000000>; fsl,portid-mapping = <0x40000000>;
}; };
cpu8: PowerPC,e6500@16 { cpu8: PowerPC,e6500@16 {
device_type = "cpu"; device_type = "cpu";
reg = <16 17>; reg = <16 17>;
clocks = <&mux2>; clocks = <&clockgen 1 2>;
next-level-cache = <&L2_3>; next-level-cache = <&L2_3>;
fsl,portid-mapping = <0x20000000>; fsl,portid-mapping = <0x20000000>;
}; };
cpu9: PowerPC,e6500@18 { cpu9: PowerPC,e6500@18 {
device_type = "cpu"; device_type = "cpu";
reg = <18 19>; reg = <18 19>;
clocks = <&mux2>; clocks = <&clockgen 1 2>;
next-level-cache = <&L2_3>; next-level-cache = <&L2_3>;
fsl,portid-mapping = <0x20000000>; fsl,portid-mapping = <0x20000000>;
}; };
cpu10: PowerPC,e6500@20 { cpu10: PowerPC,e6500@20 {
device_type = "cpu"; device_type = "cpu";
reg = <20 21>; reg = <20 21>;
clocks = <&mux2>; clocks = <&clockgen 1 2>;
next-level-cache = <&L2_3>; next-level-cache = <&L2_3>;
fsl,portid-mapping = <0x20000000>; fsl,portid-mapping = <0x20000000>;
}; };
cpu11: PowerPC,e6500@22 { cpu11: PowerPC,e6500@22 {
device_type = "cpu"; device_type = "cpu";
reg = <22 23>; reg = <22 23>;
clocks = <&mux2>; clocks = <&clockgen 1 2>;
next-level-cache = <&L2_3>; next-level-cache = <&L2_3>;
fsl,portid-mapping = <0x20000000>; fsl,portid-mapping = <0x20000000>;
}; };
......
arch/powerpc/boot/dts/mpc832x_rdb.dts
View file @ 12526b0d
...@@ -311,13 +311,9 @@ mdio@3120 { ...@@ -311,13 +311,9 @@ mdio@3120 {
compatible = "fsl,ucc-mdio"; compatible = "fsl,ucc-mdio";
phy00:ethernet-phy@0 { phy00:ethernet-phy@0 {
interrupt-parent = <&ipic>;
interrupts = <0>;
reg = <0x0>; reg = <0x0>;
}; };
phy04:ethernet-phy@4 { phy04:ethernet-phy@4 {
interrupt-parent = <&ipic>;
interrupts = <0>;
reg = <0x4>; reg = <0x4>;
}; };
}; };
......
arch/powerpc/configs/fsl-emb-nonhw.config
View file @ 12526b0d
...@@ -25,6 +25,7 @@ CONFIG_CRYPTO_SHA256=y ...@@ -25,6 +25,7 @@ CONFIG_CRYPTO_SHA256=y
CONFIG_CRYPTO_SHA512=y CONFIG_CRYPTO_SHA512=y
CONFIG_DEBUG_FS=y CONFIG_DEBUG_FS=y
CONFIG_DEBUG_INFO=y CONFIG_DEBUG_INFO=y
CONFIG_DEBUG_KERNEL=y
CONFIG_DEBUG_SHIRQ=y CONFIG_DEBUG_SHIRQ=y
CONFIG_DETECT_HUNG_TASK=y CONFIG_DETECT_HUNG_TASK=y
CONFIG_DEVTMPFS_MOUNT=y CONFIG_DEVTMPFS_MOUNT=y
......
arch/powerpc/include/asm/cputable.h
View file @ 12526b0d
...@@ -44,6 +44,7 @@ extern int machine_check_e500(struct pt_regs *regs); ...@@ -44,6 +44,7 @@ extern int machine_check_e500(struct pt_regs *regs);
extern int machine_check_e200(struct pt_regs *regs); extern int machine_check_e200(struct pt_regs *regs);
extern int machine_check_47x(struct pt_regs *regs); extern int machine_check_47x(struct pt_regs *regs);
int machine_check_8xx(struct pt_regs *regs); int machine_check_8xx(struct pt_regs *regs);
int machine_check_83xx(struct pt_regs *regs);
extern void cpu_down_flush_e500v2(void); extern void cpu_down_flush_e500v2(void);
extern void cpu_down_flush_e500mc(void); extern void cpu_down_flush_e500mc(void);
......
arch/powerpc/include/asm/reg.h
View file @ 12526b0d
...@@ -769,6 +769,8 @@ ...@@ -769,6 +769,8 @@
#define SRR1_PROGTRAP 0x00020000 /* Trap */ #define SRR1_PROGTRAP 0x00020000 /* Trap */
#define SRR1_PROGADDR 0x00010000 /* SRR0 contains subsequent addr */ #define SRR1_PROGADDR 0x00010000 /* SRR0 contains subsequent addr */
#define SRR1_MCE_MCP 0x00080000 /* Machine check signal caused interrupt */
#define SPRN_HSRR0 0x13A /* Save/Restore Register 0 */ #define SPRN_HSRR0 0x13A /* Save/Restore Register 0 */
#define SPRN_HSRR1 0x13B /* Save/Restore Register 1 */ #define SPRN_HSRR1 0x13B /* Save/Restore Register 1 */
#define HSRR1_DENORM 0x00100000 /* Denorm exception */ #define HSRR1_DENORM 0x00100000 /* Denorm exception */
......
arch/powerpc/kernel/cputable.c
View file @ 12526b0d
...@@ -1141,6 +1141,7 @@ static struct cpu_spec __initdata cpu_specs[] = { ...@@ -1141,6 +1141,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
.machine_check = machine_check_generic, .machine_check = machine_check_generic,
.platform = "ppc603", .platform = "ppc603",
}, },
#ifdef CONFIG_PPC_83xx
{ /* e300c1 (a 603e core, plus some) on 83xx */ { /* e300c1 (a 603e core, plus some) on 83xx */
.pvr_mask = 0x7fff0000, .pvr_mask = 0x7fff0000,
.pvr_value = 0x00830000, .pvr_value = 0x00830000,
...@@ -1151,7 +1152,7 @@ static struct cpu_spec __initdata cpu_specs[] = { ...@@ -1151,7 +1152,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
.icache_bsize = 32, .icache_bsize = 32,
.dcache_bsize = 32, .dcache_bsize = 32,
.cpu_setup = __setup_cpu_603, .cpu_setup = __setup_cpu_603,
.machine_check = machine_check_generic, .machine_check = machine_check_83xx,
.platform = "ppc603", .platform = "ppc603",
}, },
{ /* e300c2 (an e300c1 core, plus some, minus FPU) on 83xx */ { /* e300c2 (an e300c1 core, plus some, minus FPU) on 83xx */
...@@ -1165,7 +1166,7 @@ static struct cpu_spec __initdata cpu_specs[] = { ...@@ -1165,7 +1166,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
.icache_bsize = 32, .icache_bsize = 32,
.dcache_bsize = 32, .dcache_bsize = 32,
.cpu_setup = __setup_cpu_603, .cpu_setup = __setup_cpu_603,
.machine_check = machine_check_generic, .machine_check = machine_check_83xx,
.platform = "ppc603", .platform = "ppc603",
}, },
{ /* e300c3 (e300c1, plus one IU, half cache size) on 83xx */ { /* e300c3 (e300c1, plus one IU, half cache size) on 83xx */
...@@ -1179,7 +1180,7 @@ static struct cpu_spec __initdata cpu_specs[] = { ...@@ -1179,7 +1180,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
.icache_bsize = 32, .icache_bsize = 32,
.dcache_bsize = 32, .dcache_bsize = 32,
.cpu_setup = __setup_cpu_603, .cpu_setup = __setup_cpu_603,
.machine_check = machine_check_generic, .machine_check = machine_check_83xx,
.num_pmcs = 4, .num_pmcs = 4,
.oprofile_cpu_type = "ppc/e300", .oprofile_cpu_type = "ppc/e300",
.oprofile_type = PPC_OPROFILE_FSL_EMB, .oprofile_type = PPC_OPROFILE_FSL_EMB,
...@@ -1196,12 +1197,13 @@ static struct cpu_spec __initdata cpu_specs[] = { ...@@ -1196,12 +1197,13 @@ static struct cpu_spec __initdata cpu_specs[] = {
.icache_bsize = 32, .icache_bsize = 32,
.dcache_bsize = 32, .dcache_bsize = 32,
.cpu_setup = __setup_cpu_603, .cpu_setup = __setup_cpu_603,
.machine_check = machine_check_generic, .machine_check = machine_check_83xx,
.num_pmcs = 4, .num_pmcs = 4,
.oprofile_cpu_type = "ppc/e300", .oprofile_cpu_type = "ppc/e300",
.oprofile_type = PPC_OPROFILE_FSL_EMB, .oprofile_type = PPC_OPROFILE_FSL_EMB,
.platform = "ppc603", .platform = "ppc603",
}, },
#endif
{ /* default match, we assume split I/D cache & TB (non-601)... */ { /* default match, we assume split I/D cache & TB (non-601)... */
.pvr_mask = 0x00000000, .pvr_mask = 0x00000000,
.pvr_value = 0x00000000, .pvr_value = 0x00000000,
......
arch/powerpc/platforms/83xx/misc.c
View file @ 12526b0d
...@@ -14,6 +14,7 @@ ...@@ -14,6 +14,7 @@
#include <linux/of_platform.h> #include <linux/of_platform.h>
#include <linux/pci.h> #include <linux/pci.h>
#include <asm/debug.h>
#include <asm/io.h> #include <asm/io.h>
#include <asm/hw_irq.h> #include <asm/hw_irq.h>
#include <asm/ipic.h> #include <asm/ipic.h>
...@@ -150,3 +151,19 @@ void __init mpc83xx_setup_arch(void) ...@@ -150,3 +151,19 @@ void __init mpc83xx_setup_arch(void)
mpc83xx_setup_pci(); mpc83xx_setup_pci();
} }
int machine_check_83xx(struct pt_regs *regs)
{
u32 mask = 1 << (31 - IPIC_MCP_WDT);
if (!(regs->msr & SRR1_MCE_MCP) || !(ipic_get_mcp_status() & mask))
return machine_check_generic(regs);
ipic_clear_mcp_status(mask);
if (debugger_fault_handler(regs))
return 1;
die("Watchdog NMI Reset", regs, 0);
return 1;
}
arch/powerpc/sysdev/fsl_rmu.c
View file @ 12526b0d
...@@ -756,15 +756,13 @@ fsl_open_outb_mbox(struct rio_mport *mport, void *dev_id, int mbox, int entries) ...@@ -756,15 +756,13 @@ fsl_open_outb_mbox(struct rio_mport *mport, void *dev_id, int mbox, int entries)
} }
/* Initialize outbound message descriptor ring */ /* Initialize outbound message descriptor ring */
rmu->msg_tx_ring.virt = dma_alloc_coherent(priv->dev, rmu->msg_tx_ring.virt = dma_zalloc_coherent(priv->dev,
rmu->msg_tx_ring.size * RIO_MSG_DESC_SIZE, rmu->msg_tx_ring.size * RIO_MSG_DESC_SIZE,
&rmu->msg_tx_ring.phys, GFP_KERNEL); &rmu->msg_tx_ring.phys, GFP_KERNEL);
if (!rmu->msg_tx_ring.virt) { if (!rmu->msg_tx_ring.virt) {
rc = -ENOMEM; rc = -ENOMEM;
goto out_dma; goto out_dma;
} }
memset(rmu->msg_tx_ring.virt, 0,
rmu->msg_tx_ring.size * RIO_MSG_DESC_SIZE);
rmu->msg_tx_ring.tx_slot = 0; rmu->msg_tx_ring.tx_slot = 0;
/* Point dequeue/enqueue pointers at first entry in ring */ /* Point dequeue/enqueue pointers at first entry in ring */
......
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