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Commit 1283c617 authored by Kalle Valo's avatar Kalle Valo
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Merge ath-next from git://git.kernel.org/pub/scm/linux/kernel/git/kvalo/ath.git 

ath.git patches for 4.14. Major changes:

ath10k

* preparation for wcn3990 support
parents 6e9aae17 75e0dde2
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Showing with 393 additions and 176 deletions
drivers/net/wireless/ath/ath10k/ahb.c
View file @ 1283c617
...@@ -787,8 +787,9 @@ static int ath10k_ahb_probe(struct platform_device *pdev) ...@@ -787,8 +787,9 @@ static int ath10k_ahb_probe(struct platform_device *pdev)
ar_pci->mem = ar_ahb->mem; ar_pci->mem = ar_ahb->mem;
ar_pci->mem_len = ar_ahb->mem_len; ar_pci->mem_len = ar_ahb->mem_len;
ar_pci->ar = ar; ar_pci->ar = ar;
ar_pci->bus_ops = &ath10k_ahb_bus_ops; ar_pci->ce.bus_ops = &ath10k_ahb_bus_ops;
ar_pci->targ_cpu_to_ce_addr = ath10k_ahb_qca4019_targ_cpu_to_ce_addr; ar_pci->targ_cpu_to_ce_addr = ath10k_ahb_qca4019_targ_cpu_to_ce_addr;
ar->ce_priv = &ar_pci->ce;
ret = ath10k_pci_setup_resource(ar); ret = ath10k_pci_setup_resource(ar);
if (ret) { if (ret) {
......
drivers/net/wireless/ath/ath10k/ce.c
View file @ 1283c617
...@@ -16,7 +16,6 @@ ...@@ -16,7 +16,6 @@
*/ */
#include "hif.h" #include "hif.h"
#include "pci.h"
#include "ce.h" #include "ce.h"
#include "debug.h" #include "debug.h"
...@@ -33,7 +32,7 @@ ...@@ -33,7 +32,7 @@
* Each ring consists of a number of descriptors which specify * Each ring consists of a number of descriptors which specify
* an address, length, and meta-data. * an address, length, and meta-data.
* *
* Typically, one side of the PCIe interconnect (Host or Target) * Typically, one side of the PCIe/AHB/SNOC interconnect (Host or Target)
* controls one ring and the other side controls the other ring. * controls one ring and the other side controls the other ring.
* The source side chooses when to initiate a transfer and it * The source side chooses when to initiate a transfer and it
* chooses what to send (buffer address, length). The destination * chooses what to send (buffer address, length). The destination
...@@ -73,18 +72,32 @@ ath10k_get_ring_byte(unsigned int offset, ...@@ -73,18 +72,32 @@ ath10k_get_ring_byte(unsigned int offset,
return ((offset & addr_map->mask) >> (addr_map->lsb)); return ((offset & addr_map->mask) >> (addr_map->lsb));
} }
static inline u32 ath10k_ce_read32(struct ath10k *ar, u32 offset)
{
struct ath10k_ce *ce = ath10k_ce_priv(ar);
return ce->bus_ops->read32(ar, offset);
}
static inline void ath10k_ce_write32(struct ath10k *ar, u32 offset, u32 value)
{
struct ath10k_ce *ce = ath10k_ce_priv(ar);
ce->bus_ops->write32(ar, offset, value);
}
static inline void ath10k_ce_dest_ring_write_index_set(struct ath10k *ar, static inline void ath10k_ce_dest_ring_write_index_set(struct ath10k *ar,
u32 ce_ctrl_addr, u32 ce_ctrl_addr,
unsigned int n) unsigned int n)
{ {
ath10k_pci_write32(ar, ce_ctrl_addr + ath10k_ce_write32(ar, ce_ctrl_addr +
ar->hw_ce_regs->dst_wr_index_addr, n); ar->hw_ce_regs->dst_wr_index_addr, n);
} }
static inline u32 ath10k_ce_dest_ring_write_index_get(struct ath10k *ar, static inline u32 ath10k_ce_dest_ring_write_index_get(struct ath10k *ar,
u32 ce_ctrl_addr) u32 ce_ctrl_addr)
{ {
return ath10k_pci_read32(ar, ce_ctrl_addr + return ath10k_ce_read32(ar, ce_ctrl_addr +
ar->hw_ce_regs->dst_wr_index_addr); ar->hw_ce_regs->dst_wr_index_addr);
} }
...@@ -92,21 +105,21 @@ static inline void ath10k_ce_src_ring_write_index_set(struct ath10k *ar, ...@@ -92,21 +105,21 @@ static inline void ath10k_ce_src_ring_write_index_set(struct ath10k *ar,
u32 ce_ctrl_addr, u32 ce_ctrl_addr,
unsigned int n) unsigned int n)
{ {
ath10k_pci_write32(ar, ce_ctrl_addr + ath10k_ce_write32(ar, ce_ctrl_addr +
ar->hw_ce_regs->sr_wr_index_addr, n); ar->hw_ce_regs->sr_wr_index_addr, n);
} }
static inline u32 ath10k_ce_src_ring_write_index_get(struct ath10k *ar, static inline u32 ath10k_ce_src_ring_write_index_get(struct ath10k *ar,
u32 ce_ctrl_addr) u32 ce_ctrl_addr)
{ {
return ath10k_pci_read32(ar, ce_ctrl_addr + return ath10k_ce_read32(ar, ce_ctrl_addr +
ar->hw_ce_regs->sr_wr_index_addr); ar->hw_ce_regs->sr_wr_index_addr);
} }
static inline u32 ath10k_ce_src_ring_read_index_get(struct ath10k *ar, static inline u32 ath10k_ce_src_ring_read_index_get(struct ath10k *ar,
u32 ce_ctrl_addr) u32 ce_ctrl_addr)
{ {
return ath10k_pci_read32(ar, ce_ctrl_addr + return ath10k_ce_read32(ar, ce_ctrl_addr +
ar->hw_ce_regs->current_srri_addr); ar->hw_ce_regs->current_srri_addr);
} }
...@@ -114,7 +127,7 @@ static inline void ath10k_ce_src_ring_base_addr_set(struct ath10k *ar, ...@@ -114,7 +127,7 @@ static inline void ath10k_ce_src_ring_base_addr_set(struct ath10k *ar,
u32 ce_ctrl_addr, u32 ce_ctrl_addr,
unsigned int addr) unsigned int addr)
{ {
ath10k_pci_write32(ar, ce_ctrl_addr + ath10k_ce_write32(ar, ce_ctrl_addr +
ar->hw_ce_regs->sr_base_addr, addr); ar->hw_ce_regs->sr_base_addr, addr);
} }
...@@ -122,7 +135,7 @@ static inline void ath10k_ce_src_ring_size_set(struct ath10k *ar, ...@@ -122,7 +135,7 @@ static inline void ath10k_ce_src_ring_size_set(struct ath10k *ar,
u32 ce_ctrl_addr, u32 ce_ctrl_addr,
unsigned int n) unsigned int n)
{ {
ath10k_pci_write32(ar, ce_ctrl_addr + ath10k_ce_write32(ar, ce_ctrl_addr +
ar->hw_ce_regs->sr_size_addr, n); ar->hw_ce_regs->sr_size_addr, n);
} }
...@@ -131,10 +144,11 @@ static inline void ath10k_ce_src_ring_dmax_set(struct ath10k *ar, ...@@ -131,10 +144,11 @@ static inline void ath10k_ce_src_ring_dmax_set(struct ath10k *ar,
unsigned int n) unsigned int n)
{ {
struct ath10k_hw_ce_ctrl1 *ctrl_regs = ar->hw_ce_regs->ctrl1_regs; struct ath10k_hw_ce_ctrl1 *ctrl_regs = ar->hw_ce_regs->ctrl1_regs;
u32 ctrl1_addr = ath10k_pci_read32(ar,
ce_ctrl_addr + ctrl_regs->addr);
ath10k_pci_write32(ar, ce_ctrl_addr + ctrl_regs->addr, u32 ctrl1_addr = ath10k_ce_read32(ar, ce_ctrl_addr +
ctrl_regs->addr);
ath10k_ce_write32(ar, ce_ctrl_addr + ctrl_regs->addr,
(ctrl1_addr & ~(ctrl_regs->dmax->mask)) | (ctrl1_addr & ~(ctrl_regs->dmax->mask)) |
ath10k_set_ring_byte(n, ctrl_regs->dmax)); ath10k_set_ring_byte(n, ctrl_regs->dmax));
} }
...@@ -144,9 +158,11 @@ static inline void ath10k_ce_src_ring_byte_swap_set(struct ath10k *ar, ...@@ -144,9 +158,11 @@ static inline void ath10k_ce_src_ring_byte_swap_set(struct ath10k *ar,
unsigned int n) unsigned int n)
{ {
struct ath10k_hw_ce_ctrl1 *ctrl_regs = ar->hw_ce_regs->ctrl1_regs; struct ath10k_hw_ce_ctrl1 *ctrl_regs = ar->hw_ce_regs->ctrl1_regs;
u32 ctrl1_addr = ath10k_pci_read32(ar, ce_ctrl_addr + ctrl_regs->addr);
ath10k_pci_write32(ar, ce_ctrl_addr + ctrl_regs->addr, u32 ctrl1_addr = ath10k_ce_read32(ar, ce_ctrl_addr +
ctrl_regs->addr);
ath10k_ce_write32(ar, ce_ctrl_addr + ctrl_regs->addr,
(ctrl1_addr & ~(ctrl_regs->src_ring->mask)) | (ctrl1_addr & ~(ctrl_regs->src_ring->mask)) |
ath10k_set_ring_byte(n, ctrl_regs->src_ring)); ath10k_set_ring_byte(n, ctrl_regs->src_ring));
} }
...@@ -156,9 +172,11 @@ static inline void ath10k_ce_dest_ring_byte_swap_set(struct ath10k *ar, ...@@ -156,9 +172,11 @@ static inline void ath10k_ce_dest_ring_byte_swap_set(struct ath10k *ar,
unsigned int n) unsigned int n)
{ {
struct ath10k_hw_ce_ctrl1 *ctrl_regs = ar->hw_ce_regs->ctrl1_regs; struct ath10k_hw_ce_ctrl1 *ctrl_regs = ar->hw_ce_regs->ctrl1_regs;
u32 ctrl1_addr = ath10k_pci_read32(ar, ce_ctrl_addr + ctrl_regs->addr);
ath10k_pci_write32(ar, ce_ctrl_addr + ctrl_regs->addr, u32 ctrl1_addr = ath10k_ce_read32(ar, ce_ctrl_addr +
ctrl_regs->addr);
ath10k_ce_write32(ar, ce_ctrl_addr + ctrl_regs->addr,
(ctrl1_addr & ~(ctrl_regs->dst_ring->mask)) | (ctrl1_addr & ~(ctrl_regs->dst_ring->mask)) |
ath10k_set_ring_byte(n, ctrl_regs->dst_ring)); ath10k_set_ring_byte(n, ctrl_regs->dst_ring));
} }
...@@ -166,7 +184,7 @@ static inline void ath10k_ce_dest_ring_byte_swap_set(struct ath10k *ar, ...@@ -166,7 +184,7 @@ static inline void ath10k_ce_dest_ring_byte_swap_set(struct ath10k *ar,
static inline u32 ath10k_ce_dest_ring_read_index_get(struct ath10k *ar, static inline u32 ath10k_ce_dest_ring_read_index_get(struct ath10k *ar,
u32 ce_ctrl_addr) u32 ce_ctrl_addr)
{ {
return ath10k_pci_read32(ar, ce_ctrl_addr + return ath10k_ce_read32(ar, ce_ctrl_addr +
ar->hw_ce_regs->current_drri_addr); ar->hw_ce_regs->current_drri_addr);
} }
...@@ -174,7 +192,7 @@ static inline void ath10k_ce_dest_ring_base_addr_set(struct ath10k *ar, ...@@ -174,7 +192,7 @@ static inline void ath10k_ce_dest_ring_base_addr_set(struct ath10k *ar,
u32 ce_ctrl_addr, u32 ce_ctrl_addr,
u32 addr) u32 addr)
{ {
ath10k_pci_write32(ar, ce_ctrl_addr + ath10k_ce_write32(ar, ce_ctrl_addr +
ar->hw_ce_regs->dr_base_addr, addr); ar->hw_ce_regs->dr_base_addr, addr);
} }
...@@ -182,7 +200,7 @@ static inline void ath10k_ce_dest_ring_size_set(struct ath10k *ar, ...@@ -182,7 +200,7 @@ static inline void ath10k_ce_dest_ring_size_set(struct ath10k *ar,
u32 ce_ctrl_addr, u32 ce_ctrl_addr,
unsigned int n) unsigned int n)
{ {
ath10k_pci_write32(ar, ce_ctrl_addr + ath10k_ce_write32(ar, ce_ctrl_addr +
ar->hw_ce_regs->dr_size_addr, n); ar->hw_ce_regs->dr_size_addr, n);
} }
...@@ -191,9 +209,9 @@ static inline void ath10k_ce_src_ring_highmark_set(struct ath10k *ar, ...@@ -191,9 +209,9 @@ static inline void ath10k_ce_src_ring_highmark_set(struct ath10k *ar,
unsigned int n) unsigned int n)
{ {
struct ath10k_hw_ce_dst_src_wm_regs *srcr_wm = ar->hw_ce_regs->wm_srcr; struct ath10k_hw_ce_dst_src_wm_regs *srcr_wm = ar->hw_ce_regs->wm_srcr;
u32 addr = ath10k_pci_read32(ar, ce_ctrl_addr + srcr_wm->addr); u32 addr = ath10k_ce_read32(ar, ce_ctrl_addr + srcr_wm->addr);
ath10k_pci_write32(ar, ce_ctrl_addr + srcr_wm->addr, ath10k_ce_write32(ar, ce_ctrl_addr + srcr_wm->addr,
(addr & ~(srcr_wm->wm_high->mask)) | (addr & ~(srcr_wm->wm_high->mask)) |
(ath10k_set_ring_byte(n, srcr_wm->wm_high))); (ath10k_set_ring_byte(n, srcr_wm->wm_high)));
} }
...@@ -203,9 +221,9 @@ static inline void ath10k_ce_src_ring_lowmark_set(struct ath10k *ar, ...@@ -203,9 +221,9 @@ static inline void ath10k_ce_src_ring_lowmark_set(struct ath10k *ar,
unsigned int n) unsigned int n)
{ {
struct ath10k_hw_ce_dst_src_wm_regs *srcr_wm = ar->hw_ce_regs->wm_srcr; struct ath10k_hw_ce_dst_src_wm_regs *srcr_wm = ar->hw_ce_regs->wm_srcr;
u32 addr = ath10k_pci_read32(ar, ce_ctrl_addr + srcr_wm->addr); u32 addr = ath10k_ce_read32(ar, ce_ctrl_addr + srcr_wm->addr);
ath10k_pci_write32(ar, ce_ctrl_addr + srcr_wm->addr, ath10k_ce_write32(ar, ce_ctrl_addr + srcr_wm->addr,
(addr & ~(srcr_wm->wm_low->mask)) | (addr & ~(srcr_wm->wm_low->mask)) |
(ath10k_set_ring_byte(n, srcr_wm->wm_low))); (ath10k_set_ring_byte(n, srcr_wm->wm_low)));
} }
...@@ -215,9 +233,9 @@ static inline void ath10k_ce_dest_ring_highmark_set(struct ath10k *ar, ...@@ -215,9 +233,9 @@ static inline void ath10k_ce_dest_ring_highmark_set(struct ath10k *ar,
unsigned int n) unsigned int n)
{ {
struct ath10k_hw_ce_dst_src_wm_regs *dstr_wm = ar->hw_ce_regs->wm_dstr; struct ath10k_hw_ce_dst_src_wm_regs *dstr_wm = ar->hw_ce_regs->wm_dstr;
u32 addr = ath10k_pci_read32(ar, ce_ctrl_addr + dstr_wm->addr); u32 addr = ath10k_ce_read32(ar, ce_ctrl_addr + dstr_wm->addr);
ath10k_pci_write32(ar, ce_ctrl_addr + dstr_wm->addr, ath10k_ce_write32(ar, ce_ctrl_addr + dstr_wm->addr,
(addr & ~(dstr_wm->wm_high->mask)) | (addr & ~(dstr_wm->wm_high->mask)) |
(ath10k_set_ring_byte(n, dstr_wm->wm_high))); (ath10k_set_ring_byte(n, dstr_wm->wm_high)));
} }
...@@ -227,9 +245,9 @@ static inline void ath10k_ce_dest_ring_lowmark_set(struct ath10k *ar, ...@@ -227,9 +245,9 @@ static inline void ath10k_ce_dest_ring_lowmark_set(struct ath10k *ar,
unsigned int n) unsigned int n)
{ {
struct ath10k_hw_ce_dst_src_wm_regs *dstr_wm = ar->hw_ce_regs->wm_dstr; struct ath10k_hw_ce_dst_src_wm_regs *dstr_wm = ar->hw_ce_regs->wm_dstr;
u32 addr = ath10k_pci_read32(ar, ce_ctrl_addr + dstr_wm->addr); u32 addr = ath10k_ce_read32(ar, ce_ctrl_addr + dstr_wm->addr);
ath10k_pci_write32(ar, ce_ctrl_addr + dstr_wm->addr, ath10k_ce_write32(ar, ce_ctrl_addr + dstr_wm->addr,
(addr & ~(dstr_wm->wm_low->mask)) | (addr & ~(dstr_wm->wm_low->mask)) |
(ath10k_set_ring_byte(n, dstr_wm->wm_low))); (ath10k_set_ring_byte(n, dstr_wm->wm_low)));
} }
...@@ -238,10 +256,11 @@ static inline void ath10k_ce_copy_complete_inter_enable(struct ath10k *ar, ...@@ -238,10 +256,11 @@ static inline void ath10k_ce_copy_complete_inter_enable(struct ath10k *ar,
u32 ce_ctrl_addr) u32 ce_ctrl_addr)
{ {
struct ath10k_hw_ce_host_ie *host_ie = ar->hw_ce_regs->host_ie; struct ath10k_hw_ce_host_ie *host_ie = ar->hw_ce_regs->host_ie;
u32 host_ie_addr = ath10k_pci_read32(ar, ce_ctrl_addr +
u32 host_ie_addr = ath10k_ce_read32(ar, ce_ctrl_addr +
ar->hw_ce_regs->host_ie_addr); ar->hw_ce_regs->host_ie_addr);
ath10k_pci_write32(ar, ce_ctrl_addr + ar->hw_ce_regs->host_ie_addr, ath10k_ce_write32(ar, ce_ctrl_addr + ar->hw_ce_regs->host_ie_addr,
host_ie_addr | host_ie->copy_complete->mask); host_ie_addr | host_ie->copy_complete->mask);
} }
...@@ -249,10 +268,11 @@ static inline void ath10k_ce_copy_complete_intr_disable(struct ath10k *ar, ...@@ -249,10 +268,11 @@ static inline void ath10k_ce_copy_complete_intr_disable(struct ath10k *ar,
u32 ce_ctrl_addr) u32 ce_ctrl_addr)
{ {
struct ath10k_hw_ce_host_ie *host_ie = ar->hw_ce_regs->host_ie; struct ath10k_hw_ce_host_ie *host_ie = ar->hw_ce_regs->host_ie;
u32 host_ie_addr = ath10k_pci_read32(ar, ce_ctrl_addr +
u32 host_ie_addr = ath10k_ce_read32(ar, ce_ctrl_addr +
ar->hw_ce_regs->host_ie_addr); ar->hw_ce_regs->host_ie_addr);
ath10k_pci_write32(ar, ce_ctrl_addr + ar->hw_ce_regs->host_ie_addr, ath10k_ce_write32(ar, ce_ctrl_addr + ar->hw_ce_regs->host_ie_addr,
host_ie_addr & ~(host_ie->copy_complete->mask)); host_ie_addr & ~(host_ie->copy_complete->mask));
} }
...@@ -260,10 +280,11 @@ static inline void ath10k_ce_watermark_intr_disable(struct ath10k *ar, ...@@ -260,10 +280,11 @@ static inline void ath10k_ce_watermark_intr_disable(struct ath10k *ar,
u32 ce_ctrl_addr) u32 ce_ctrl_addr)
{ {
struct ath10k_hw_ce_host_wm_regs *wm_regs = ar->hw_ce_regs->wm_regs; struct ath10k_hw_ce_host_wm_regs *wm_regs = ar->hw_ce_regs->wm_regs;
u32 host_ie_addr = ath10k_pci_read32(ar, ce_ctrl_addr +
u32 host_ie_addr = ath10k_ce_read32(ar, ce_ctrl_addr +
ar->hw_ce_regs->host_ie_addr); ar->hw_ce_regs->host_ie_addr);
ath10k_pci_write32(ar, ce_ctrl_addr + ar->hw_ce_regs->host_ie_addr, ath10k_ce_write32(ar, ce_ctrl_addr + ar->hw_ce_regs->host_ie_addr,
host_ie_addr & ~(wm_regs->wm_mask)); host_ie_addr & ~(wm_regs->wm_mask));
} }
...@@ -271,10 +292,12 @@ static inline void ath10k_ce_error_intr_enable(struct ath10k *ar, ...@@ -271,10 +292,12 @@ static inline void ath10k_ce_error_intr_enable(struct ath10k *ar,
u32 ce_ctrl_addr) u32 ce_ctrl_addr)
{ {
struct ath10k_hw_ce_misc_regs *misc_regs = ar->hw_ce_regs->misc_regs; struct ath10k_hw_ce_misc_regs *misc_regs = ar->hw_ce_regs->misc_regs;
u32 misc_ie_addr = ath10k_pci_read32(ar, ce_ctrl_addr +
u32 misc_ie_addr = ath10k_ce_read32(ar, ce_ctrl_addr +
ar->hw_ce_regs->misc_ie_addr); ar->hw_ce_regs->misc_ie_addr);
ath10k_pci_write32(ar, ce_ctrl_addr + ar->hw_ce_regs->misc_ie_addr, ath10k_ce_write32(ar,
ce_ctrl_addr + ar->hw_ce_regs->misc_ie_addr,
misc_ie_addr | misc_regs->err_mask); misc_ie_addr | misc_regs->err_mask);
} }
...@@ -282,10 +305,12 @@ static inline void ath10k_ce_error_intr_disable(struct ath10k *ar, ...@@ -282,10 +305,12 @@ static inline void ath10k_ce_error_intr_disable(struct ath10k *ar,
u32 ce_ctrl_addr) u32 ce_ctrl_addr)
{ {
struct ath10k_hw_ce_misc_regs *misc_regs = ar->hw_ce_regs->misc_regs; struct ath10k_hw_ce_misc_regs *misc_regs = ar->hw_ce_regs->misc_regs;
u32 misc_ie_addr = ath10k_pci_read32(ar, ce_ctrl_addr +
ar->hw_ce_regs->misc_ie_addr);
ath10k_pci_write32(ar, ce_ctrl_addr + ar->hw_ce_regs->misc_ie_addr, u32 misc_ie_addr = ath10k_ce_read32(ar,
ce_ctrl_addr + ar->hw_ce_regs->misc_ie_addr);
ath10k_ce_write32(ar,
ce_ctrl_addr + ar->hw_ce_regs->misc_ie_addr,
misc_ie_addr & ~(misc_regs->err_mask)); misc_ie_addr & ~(misc_regs->err_mask));
} }
...@@ -295,7 +320,7 @@ static inline void ath10k_ce_engine_int_status_clear(struct ath10k *ar, ...@@ -295,7 +320,7 @@ static inline void ath10k_ce_engine_int_status_clear(struct ath10k *ar,
{ {
struct ath10k_hw_ce_host_wm_regs *wm_regs = ar->hw_ce_regs->wm_regs; struct ath10k_hw_ce_host_wm_regs *wm_regs = ar->hw_ce_regs->wm_regs;
ath10k_pci_write32(ar, ce_ctrl_addr + wm_regs->addr, mask); ath10k_ce_write32(ar, ce_ctrl_addr + wm_regs->addr, mask);
} }
/* /*
...@@ -362,11 +387,11 @@ int ath10k_ce_send_nolock(struct ath10k_ce_pipe *ce_state, ...@@ -362,11 +387,11 @@ int ath10k_ce_send_nolock(struct ath10k_ce_pipe *ce_state,
void __ath10k_ce_send_revert(struct ath10k_ce_pipe *pipe) void __ath10k_ce_send_revert(struct ath10k_ce_pipe *pipe)
{ {
struct ath10k *ar = pipe->ar; struct ath10k *ar = pipe->ar;
struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); struct ath10k_ce *ce = ath10k_ce_priv(ar);
struct ath10k_ce_ring *src_ring = pipe->src_ring; struct ath10k_ce_ring *src_ring = pipe->src_ring;
u32 ctrl_addr = pipe->ctrl_addr; u32 ctrl_addr = pipe->ctrl_addr;
lockdep_assert_held(&ar_pci->ce_lock); lockdep_assert_held(&ce->ce_lock);
/* /*
* This function must be called only if there is an incomplete * This function must be called only if there is an incomplete
...@@ -394,13 +419,13 @@ int ath10k_ce_send(struct ath10k_ce_pipe *ce_state, ...@@ -394,13 +419,13 @@ int ath10k_ce_send(struct ath10k_ce_pipe *ce_state,
unsigned int flags) unsigned int flags)
{ {
struct ath10k *ar = ce_state->ar; struct ath10k *ar = ce_state->ar;
struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); struct ath10k_ce *ce = ath10k_ce_priv(ar);
int ret; int ret;
spin_lock_bh(&ar_pci->ce_lock); spin_lock_bh(&ce->ce_lock);
ret = ath10k_ce_send_nolock(ce_state, per_transfer_context, ret = ath10k_ce_send_nolock(ce_state, per_transfer_context,
buffer, nbytes, transfer_id, flags); buffer, nbytes, transfer_id, flags);
spin_unlock_bh(&ar_pci->ce_lock); spin_unlock_bh(&ce->ce_lock);
return ret; return ret;
} }
...@@ -408,14 +433,14 @@ int ath10k_ce_send(struct ath10k_ce_pipe *ce_state, ...@@ -408,14 +433,14 @@ int ath10k_ce_send(struct ath10k_ce_pipe *ce_state,
int ath10k_ce_num_free_src_entries(struct ath10k_ce_pipe *pipe) int ath10k_ce_num_free_src_entries(struct ath10k_ce_pipe *pipe)
{ {
struct ath10k *ar = pipe->ar; struct ath10k *ar = pipe->ar;
struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); struct ath10k_ce *ce = ath10k_ce_priv(ar);
int delta; int delta;
spin_lock_bh(&ar_pci->ce_lock); spin_lock_bh(&ce->ce_lock);
delta = CE_RING_DELTA(pipe->src_ring->nentries_mask, delta = CE_RING_DELTA(pipe->src_ring->nentries_mask,
pipe->src_ring->write_index, pipe->src_ring->write_index,
pipe->src_ring->sw_index - 1); pipe->src_ring->sw_index - 1);
spin_unlock_bh(&ar_pci->ce_lock); spin_unlock_bh(&ce->ce_lock);
return delta; return delta;
} }
...@@ -423,13 +448,13 @@ int ath10k_ce_num_free_src_entries(struct ath10k_ce_pipe *pipe) ...@@ -423,13 +448,13 @@ int ath10k_ce_num_free_src_entries(struct ath10k_ce_pipe *pipe)
int __ath10k_ce_rx_num_free_bufs(struct ath10k_ce_pipe *pipe) int __ath10k_ce_rx_num_free_bufs(struct ath10k_ce_pipe *pipe)
{ {
struct ath10k *ar = pipe->ar; struct ath10k *ar = pipe->ar;
struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); struct ath10k_ce *ce = ath10k_ce_priv(ar);
struct ath10k_ce_ring *dest_ring = pipe->dest_ring; struct ath10k_ce_ring *dest_ring = pipe->dest_ring;
unsigned int nentries_mask = dest_ring->nentries_mask; unsigned int nentries_mask = dest_ring->nentries_mask;
unsigned int write_index = dest_ring->write_index; unsigned int write_index = dest_ring->write_index;
unsigned int sw_index = dest_ring->sw_index; unsigned int sw_index = dest_ring->sw_index;
lockdep_assert_held(&ar_pci->ce_lock); lockdep_assert_held(&ce->ce_lock);
return CE_RING_DELTA(nentries_mask, write_index, sw_index - 1); return CE_RING_DELTA(nentries_mask, write_index, sw_index - 1);
} }
...@@ -437,7 +462,7 @@ int __ath10k_ce_rx_num_free_bufs(struct ath10k_ce_pipe *pipe) ...@@ -437,7 +462,7 @@ int __ath10k_ce_rx_num_free_bufs(struct ath10k_ce_pipe *pipe)
int __ath10k_ce_rx_post_buf(struct ath10k_ce_pipe *pipe, void *ctx, u32 paddr) int __ath10k_ce_rx_post_buf(struct ath10k_ce_pipe *pipe, void *ctx, u32 paddr)
{ {
struct ath10k *ar = pipe->ar; struct ath10k *ar = pipe->ar;
struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); struct ath10k_ce *ce = ath10k_ce_priv(ar);
struct ath10k_ce_ring *dest_ring = pipe->dest_ring; struct ath10k_ce_ring *dest_ring = pipe->dest_ring;
unsigned int nentries_mask = dest_ring->nentries_mask; unsigned int nentries_mask = dest_ring->nentries_mask;
unsigned int write_index = dest_ring->write_index; unsigned int write_index = dest_ring->write_index;
...@@ -446,7 +471,7 @@ int __ath10k_ce_rx_post_buf(struct ath10k_ce_pipe *pipe, void *ctx, u32 paddr) ...@@ -446,7 +471,7 @@ int __ath10k_ce_rx_post_buf(struct ath10k_ce_pipe *pipe, void *ctx, u32 paddr)
struct ce_desc *desc = CE_DEST_RING_TO_DESC(base, write_index); struct ce_desc *desc = CE_DEST_RING_TO_DESC(base, write_index);
u32 ctrl_addr = pipe->ctrl_addr; u32 ctrl_addr = pipe->ctrl_addr;
lockdep_assert_held(&ar_pci->ce_lock); lockdep_assert_held(&ce->ce_lock);
if ((pipe->id != 5) && if ((pipe->id != 5) &&
CE_RING_DELTA(nentries_mask, write_index, sw_index - 1) == 0) CE_RING_DELTA(nentries_mask, write_index, sw_index - 1) == 0)
...@@ -486,12 +511,12 @@ void ath10k_ce_rx_update_write_idx(struct ath10k_ce_pipe *pipe, u32 nentries) ...@@ -486,12 +511,12 @@ void ath10k_ce_rx_update_write_idx(struct ath10k_ce_pipe *pipe, u32 nentries)
int ath10k_ce_rx_post_buf(struct ath10k_ce_pipe *pipe, void *ctx, u32 paddr) int ath10k_ce_rx_post_buf(struct ath10k_ce_pipe *pipe, void *ctx, u32 paddr)
{ {
struct ath10k *ar = pipe->ar; struct ath10k *ar = pipe->ar;
struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); struct ath10k_ce *ce = ath10k_ce_priv(ar);
int ret; int ret;
spin_lock_bh(&ar_pci->ce_lock); spin_lock_bh(&ce->ce_lock);
ret = __ath10k_ce_rx_post_buf(pipe, ctx, paddr); ret = __ath10k_ce_rx_post_buf(pipe, ctx, paddr);
spin_unlock_bh(&ar_pci->ce_lock); spin_unlock_bh(&ce->ce_lock);
return ret; return ret;
} }
...@@ -554,14 +579,14 @@ int ath10k_ce_completed_recv_next(struct ath10k_ce_pipe *ce_state, ...@@ -554,14 +579,14 @@ int ath10k_ce_completed_recv_next(struct ath10k_ce_pipe *ce_state,
unsigned int *nbytesp) unsigned int *nbytesp)
{ {
struct ath10k *ar = ce_state->ar; struct ath10k *ar = ce_state->ar;
struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); struct ath10k_ce *ce = ath10k_ce_priv(ar);
int ret; int ret;
spin_lock_bh(&ar_pci->ce_lock); spin_lock_bh(&ce->ce_lock);
ret = ath10k_ce_completed_recv_next_nolock(ce_state, ret = ath10k_ce_completed_recv_next_nolock(ce_state,
per_transfer_contextp, per_transfer_contextp,
nbytesp); nbytesp);
spin_unlock_bh(&ar_pci->ce_lock); spin_unlock_bh(&ce->ce_lock);
return ret; return ret;
} }
...@@ -576,7 +601,7 @@ int ath10k_ce_revoke_recv_next(struct ath10k_ce_pipe *ce_state, ...@@ -576,7 +601,7 @@ int ath10k_ce_revoke_recv_next(struct ath10k_ce_pipe *ce_state,
unsigned int write_index; unsigned int write_index;
int ret; int ret;
struct ath10k *ar; struct ath10k *ar;
struct ath10k_pci *ar_pci; struct ath10k_ce *ce;
dest_ring = ce_state->dest_ring; dest_ring = ce_state->dest_ring;
...@@ -584,9 +609,9 @@ int ath10k_ce_revoke_recv_next(struct ath10k_ce_pipe *ce_state, ...@@ -584,9 +609,9 @@ int ath10k_ce_revoke_recv_next(struct ath10k_ce_pipe *ce_state,
return -EIO; return -EIO;
ar = ce_state->ar; ar = ce_state->ar;
ar_pci = ath10k_pci_priv(ar); ce = ath10k_ce_priv(ar);
spin_lock_bh(&ar_pci->ce_lock); spin_lock_bh(&ce->ce_lock);
nentries_mask = dest_ring->nentries_mask; nentries_mask = dest_ring->nentries_mask;
sw_index = dest_ring->sw_index; sw_index = dest_ring->sw_index;
...@@ -614,7 +639,7 @@ int ath10k_ce_revoke_recv_next(struct ath10k_ce_pipe *ce_state, ...@@ -614,7 +639,7 @@ int ath10k_ce_revoke_recv_next(struct ath10k_ce_pipe *ce_state,
ret = -EIO; ret = -EIO;
} }
spin_unlock_bh(&ar_pci->ce_lock); spin_unlock_bh(&ce->ce_lock);
return ret; return ret;
} }
...@@ -686,7 +711,7 @@ int ath10k_ce_cancel_send_next(struct ath10k_ce_pipe *ce_state, ...@@ -686,7 +711,7 @@ int ath10k_ce_cancel_send_next(struct ath10k_ce_pipe *ce_state,
unsigned int write_index; unsigned int write_index;
int ret; int ret;
struct ath10k *ar; struct ath10k *ar;
struct ath10k_pci *ar_pci; struct ath10k_ce *ce;
src_ring = ce_state->src_ring; src_ring = ce_state->src_ring;
...@@ -694,9 +719,9 @@ int ath10k_ce_cancel_send_next(struct ath10k_ce_pipe *ce_state, ...@@ -694,9 +719,9 @@ int ath10k_ce_cancel_send_next(struct ath10k_ce_pipe *ce_state,
return -EIO; return -EIO;
ar = ce_state->ar; ar = ce_state->ar;
ar_pci = ath10k_pci_priv(ar); ce = ath10k_ce_priv(ar);
spin_lock_bh(&ar_pci->ce_lock); spin_lock_bh(&ce->ce_lock);
nentries_mask = src_ring->nentries_mask; nentries_mask = src_ring->nentries_mask;
sw_index = src_ring->sw_index; sw_index = src_ring->sw_index;
...@@ -727,7 +752,7 @@ int ath10k_ce_cancel_send_next(struct ath10k_ce_pipe *ce_state, ...@@ -727,7 +752,7 @@ int ath10k_ce_cancel_send_next(struct ath10k_ce_pipe *ce_state,
ret = -EIO; ret = -EIO;
} }
spin_unlock_bh(&ar_pci->ce_lock); spin_unlock_bh(&ce->ce_lock);
return ret; return ret;
} }
...@@ -736,13 +761,13 @@ int ath10k_ce_completed_send_next(struct ath10k_ce_pipe *ce_state, ...@@ -736,13 +761,13 @@ int ath10k_ce_completed_send_next(struct ath10k_ce_pipe *ce_state,
void **per_transfer_contextp) void **per_transfer_contextp)
{ {
struct ath10k *ar = ce_state->ar; struct ath10k *ar = ce_state->ar;
struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); struct ath10k_ce *ce = ath10k_ce_priv(ar);
int ret; int ret;
spin_lock_bh(&ar_pci->ce_lock); spin_lock_bh(&ce->ce_lock);
ret = ath10k_ce_completed_send_next_nolock(ce_state, ret = ath10k_ce_completed_send_next_nolock(ce_state,
per_transfer_contextp); per_transfer_contextp);
spin_unlock_bh(&ar_pci->ce_lock); spin_unlock_bh(&ce->ce_lock);
return ret; return ret;
} }
...@@ -755,17 +780,18 @@ int ath10k_ce_completed_send_next(struct ath10k_ce_pipe *ce_state, ...@@ -755,17 +780,18 @@ int ath10k_ce_completed_send_next(struct ath10k_ce_pipe *ce_state,
*/ */
void ath10k_ce_per_engine_service(struct ath10k *ar, unsigned int ce_id) void ath10k_ce_per_engine_service(struct ath10k *ar, unsigned int ce_id)
{ {
struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); struct ath10k_ce *ce = ath10k_ce_priv(ar);
struct ath10k_ce_pipe *ce_state = &ar_pci->ce_states[ce_id]; struct ath10k_ce_pipe *ce_state = &ce->ce_states[ce_id];
struct ath10k_hw_ce_host_wm_regs *wm_regs = ar->hw_ce_regs->wm_regs; struct ath10k_hw_ce_host_wm_regs *wm_regs = ar->hw_ce_regs->wm_regs;
u32 ctrl_addr = ce_state->ctrl_addr; u32 ctrl_addr = ce_state->ctrl_addr;
spin_lock_bh(&ar_pci->ce_lock); spin_lock_bh(&ce->ce_lock);
/* Clear the copy-complete interrupts that will be handled here. */ /* Clear the copy-complete interrupts that will be handled here. */
ath10k_ce_engine_int_status_clear(ar, ctrl_addr, wm_regs->cc_mask); ath10k_ce_engine_int_status_clear(ar, ctrl_addr,
wm_regs->cc_mask);
spin_unlock_bh(&ar_pci->ce_lock); spin_unlock_bh(&ce->ce_lock);
if (ce_state->recv_cb) if (ce_state->recv_cb)
ce_state->recv_cb(ce_state); ce_state->recv_cb(ce_state);
...@@ -773,7 +799,7 @@ void ath10k_ce_per_engine_service(struct ath10k *ar, unsigned int ce_id) ...@@ -773,7 +799,7 @@ void ath10k_ce_per_engine_service(struct ath10k *ar, unsigned int ce_id)
if (ce_state->send_cb) if (ce_state->send_cb)
ce_state->send_cb(ce_state); ce_state->send_cb(ce_state);
spin_lock_bh(&ar_pci->ce_lock); spin_lock_bh(&ce->ce_lock);
/* /*
* Misc CE interrupts are not being handled, but still need * Misc CE interrupts are not being handled, but still need
...@@ -781,7 +807,7 @@ void ath10k_ce_per_engine_service(struct ath10k *ar, unsigned int ce_id) ...@@ -781,7 +807,7 @@ void ath10k_ce_per_engine_service(struct ath10k *ar, unsigned int ce_id)
*/ */
ath10k_ce_engine_int_status_clear(ar, ctrl_addr, wm_regs->wm_mask); ath10k_ce_engine_int_status_clear(ar, ctrl_addr, wm_regs->wm_mask);
spin_unlock_bh(&ar_pci->ce_lock); spin_unlock_bh(&ce->ce_lock);
} }
/* /*
...@@ -795,7 +821,7 @@ void ath10k_ce_per_engine_service_any(struct ath10k *ar) ...@@ -795,7 +821,7 @@ void ath10k_ce_per_engine_service_any(struct ath10k *ar)
int ce_id; int ce_id;
u32 intr_summary; u32 intr_summary;
intr_summary = CE_INTERRUPT_SUMMARY(ar); intr_summary = ath10k_ce_interrupt_summary(ar);
for (ce_id = 0; intr_summary && (ce_id < CE_COUNT); ce_id++) { for (ce_id = 0; intr_summary && (ce_id < CE_COUNT); ce_id++) {
if (intr_summary & (1 << ce_id)) if (intr_summary & (1 << ce_id))
...@@ -847,22 +873,25 @@ int ath10k_ce_disable_interrupts(struct ath10k *ar) ...@@ -847,22 +873,25 @@ int ath10k_ce_disable_interrupts(struct ath10k *ar)
void ath10k_ce_enable_interrupts(struct ath10k *ar) void ath10k_ce_enable_interrupts(struct ath10k *ar)
{ {
struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); struct ath10k_ce *ce = ath10k_ce_priv(ar);
int ce_id; int ce_id;
struct ath10k_ce_pipe *ce_state;
/* Skip the last copy engine, CE7 the diagnostic window, as that /* Skip the last copy engine, CE7 the diagnostic window, as that
* uses polling and isn't initialized for interrupts. * uses polling and isn't initialized for interrupts.
*/ */
for (ce_id = 0; ce_id < CE_COUNT - 1; ce_id++) for (ce_id = 0; ce_id < CE_COUNT - 1; ce_id++) {
ath10k_ce_per_engine_handler_adjust(&ar_pci->ce_states[ce_id]); ce_state = &ce->ce_states[ce_id];
ath10k_ce_per_engine_handler_adjust(ce_state);
}
} }
static int ath10k_ce_init_src_ring(struct ath10k *ar, static int ath10k_ce_init_src_ring(struct ath10k *ar,
unsigned int ce_id, unsigned int ce_id,
const struct ce_attr *attr) const struct ce_attr *attr)
{ {
struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); struct ath10k_ce *ce = ath10k_ce_priv(ar);
struct ath10k_ce_pipe *ce_state = &ar_pci->ce_states[ce_id]; struct ath10k_ce_pipe *ce_state = &ce->ce_states[ce_id];
struct ath10k_ce_ring *src_ring = ce_state->src_ring; struct ath10k_ce_ring *src_ring = ce_state->src_ring;
u32 nentries, ctrl_addr = ath10k_ce_base_address(ar, ce_id); u32 nentries, ctrl_addr = ath10k_ce_base_address(ar, ce_id);
...@@ -898,8 +927,8 @@ static int ath10k_ce_init_dest_ring(struct ath10k *ar, ...@@ -898,8 +927,8 @@ static int ath10k_ce_init_dest_ring(struct ath10k *ar,
unsigned int ce_id, unsigned int ce_id,
const struct ce_attr *attr) const struct ce_attr *attr)
{ {
struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); struct ath10k_ce *ce = ath10k_ce_priv(ar);
struct ath10k_ce_pipe *ce_state = &ar_pci->ce_states[ce_id]; struct ath10k_ce_pipe *ce_state = &ce->ce_states[ce_id];
struct ath10k_ce_ring *dest_ring = ce_state->dest_ring; struct ath10k_ce_ring *dest_ring = ce_state->dest_ring;
u32 nentries, ctrl_addr = ath10k_ce_base_address(ar, ce_id); u32 nentries, ctrl_addr = ath10k_ce_base_address(ar, ce_id);
...@@ -1081,8 +1110,8 @@ void ath10k_ce_deinit_pipe(struct ath10k *ar, unsigned int ce_id) ...@@ -1081,8 +1110,8 @@ void ath10k_ce_deinit_pipe(struct ath10k *ar, unsigned int ce_id)
int ath10k_ce_alloc_pipe(struct ath10k *ar, int ce_id, int ath10k_ce_alloc_pipe(struct ath10k *ar, int ce_id,
const struct ce_attr *attr) const struct ce_attr *attr)
{ {
struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); struct ath10k_ce *ce = ath10k_ce_priv(ar);
struct ath10k_ce_pipe *ce_state = &ar_pci->ce_states[ce_id]; struct ath10k_ce_pipe *ce_state = &ce->ce_states[ce_id];
int ret; int ret;
/* /*
...@@ -1138,8 +1167,8 @@ int ath10k_ce_alloc_pipe(struct ath10k *ar, int ce_id, ...@@ -1138,8 +1167,8 @@ int ath10k_ce_alloc_pipe(struct ath10k *ar, int ce_id,
void ath10k_ce_free_pipe(struct ath10k *ar, int ce_id) void ath10k_ce_free_pipe(struct ath10k *ar, int ce_id)
{ {
struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); struct ath10k_ce *ce = ath10k_ce_priv(ar);
struct ath10k_ce_pipe *ce_state = &ar_pci->ce_states[ce_id]; struct ath10k_ce_pipe *ce_state = &ce->ce_states[ce_id];
if (ce_state->src_ring) { if (ce_state->src_ring) {
dma_free_coherent(ar->dev, dma_free_coherent(ar->dev,
...@@ -1168,38 +1197,38 @@ void ath10k_ce_free_pipe(struct ath10k *ar, int ce_id) ...@@ -1168,38 +1197,38 @@ void ath10k_ce_free_pipe(struct ath10k *ar, int ce_id)
void ath10k_ce_dump_registers(struct ath10k *ar, void ath10k_ce_dump_registers(struct ath10k *ar,
struct ath10k_fw_crash_data *crash_data) struct ath10k_fw_crash_data *crash_data)
{ {
struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); struct ath10k_ce *ce = ath10k_ce_priv(ar);
struct ath10k_ce_crash_data ce; struct ath10k_ce_crash_data ce_data;
u32 addr, id; u32 addr, id;
lockdep_assert_held(&ar->data_lock); lockdep_assert_held(&ar->data_lock);
ath10k_err(ar, "Copy Engine register dump:\n"); ath10k_err(ar, "Copy Engine register dump:\n");
spin_lock_bh(&ar_pci->ce_lock); spin_lock_bh(&ce->ce_lock);
for (id = 0; id < CE_COUNT; id++) { for (id = 0; id < CE_COUNT; id++) {
addr = ath10k_ce_base_address(ar, id); addr = ath10k_ce_base_address(ar, id);
ce.base_addr = cpu_to_le32(addr); ce_data.base_addr = cpu_to_le32(addr);
ce.src_wr_idx = ce_data.src_wr_idx =
cpu_to_le32(ath10k_ce_src_ring_write_index_get(ar, addr)); cpu_to_le32(ath10k_ce_src_ring_write_index_get(ar, addr));
ce.src_r_idx = ce_data.src_r_idx =
cpu_to_le32(ath10k_ce_src_ring_read_index_get(ar, addr)); cpu_to_le32(ath10k_ce_src_ring_read_index_get(ar, addr));
ce.dst_wr_idx = ce_data.dst_wr_idx =
cpu_to_le32(ath10k_ce_dest_ring_write_index_get(ar, addr)); cpu_to_le32(ath10k_ce_dest_ring_write_index_get(ar, addr));
ce.dst_r_idx = ce_data.dst_r_idx =
cpu_to_le32(ath10k_ce_dest_ring_read_index_get(ar, addr)); cpu_to_le32(ath10k_ce_dest_ring_read_index_get(ar, addr));
if (crash_data) if (crash_data)
crash_data->ce_crash_data[id] = ce; crash_data->ce_crash_data[id] = ce_data;
ath10k_err(ar, "[%02d]: 0x%08x %3u %3u %3u %3u", id, ath10k_err(ar, "[%02d]: 0x%08x %3u %3u %3u %3u", id,
le32_to_cpu(ce.base_addr), le32_to_cpu(ce_data.base_addr),
le32_to_cpu(ce.src_wr_idx), le32_to_cpu(ce_data.src_wr_idx),
le32_to_cpu(ce.src_r_idx), le32_to_cpu(ce_data.src_r_idx),
le32_to_cpu(ce.dst_wr_idx), le32_to_cpu(ce_data.dst_wr_idx),
le32_to_cpu(ce.dst_r_idx)); le32_to_cpu(ce_data.dst_r_idx));
} }
spin_unlock_bh(&ar_pci->ce_lock); spin_unlock_bh(&ce->ce_lock);
} }
drivers/net/wireless/ath/ath10k/ce.h
View file @ 1283c617
...@@ -122,6 +122,24 @@ struct ath10k_ce_pipe { ...@@ -122,6 +122,24 @@ struct ath10k_ce_pipe {
/* Copy Engine settable attributes */ /* Copy Engine settable attributes */
struct ce_attr; struct ce_attr;
struct ath10k_bus_ops {
u32 (*read32)(struct ath10k *ar, u32 offset);
void (*write32)(struct ath10k *ar, u32 offset, u32 value);
int (*get_num_banks)(struct ath10k *ar);
};
static inline struct ath10k_ce *ath10k_ce_priv(struct ath10k *ar)
{
return (struct ath10k_ce *)ar->ce_priv;
}
struct ath10k_ce {
/* protects CE info */
spinlock_t ce_lock;
const struct ath10k_bus_ops *bus_ops;
struct ath10k_ce_pipe ce_states[CE_COUNT_MAX];
};
/*==================Send====================*/ /*==================Send====================*/
/* ath10k_ce_send flags */ /* ath10k_ce_send flags */
...@@ -291,9 +309,13 @@ static inline u32 ath10k_ce_base_address(struct ath10k *ar, unsigned int ce_id) ...@@ -291,9 +309,13 @@ static inline u32 ath10k_ce_base_address(struct ath10k *ar, unsigned int ce_id)
CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB) CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB)
#define CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS 0x0000 #define CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS 0x0000
#define CE_INTERRUPT_SUMMARY(ar) \ static inline u32 ath10k_ce_interrupt_summary(struct ath10k *ar)
CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_GET( \ {
ath10k_pci_read32((ar), CE_WRAPPER_BASE_ADDRESS + \ struct ath10k_ce *ce = ath10k_ce_priv(ar);
CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS))
return CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_GET(
ce->bus_ops->read32((ar), CE_WRAPPER_BASE_ADDRESS +
CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS));
}
#endif /* _CE_H_ */ #endif /* _CE_H_ */
drivers/net/wireless/ath/ath10k/core.c
View file @ 1283c617
...@@ -2516,6 +2516,11 @@ struct ath10k *ath10k_core_create(size_t priv_size, struct device *dev, ...@@ -2516,6 +2516,11 @@ struct ath10k *ath10k_core_create(size_t priv_size, struct device *dev,
ar->hw_ce_regs = &qcax_ce_regs; ar->hw_ce_regs = &qcax_ce_regs;
ar->hw_values = &qca4019_values; ar->hw_values = &qca4019_values;
break; break;
case ATH10K_HW_WCN3990:
ar->regs = &wcn3990_regs;
ar->hw_ce_regs = &wcn3990_ce_regs;
ar->hw_values = &wcn3990_values;
break;
default: default:
ath10k_err(ar, "unsupported core hardware revision %d\n", ath10k_err(ar, "unsupported core hardware revision %d\n",
hw_rev); hw_rev);
......
drivers/net/wireless/ath/ath10k/core.h
View file @ 1283c617
...@@ -993,6 +993,8 @@ struct ath10k { ...@@ -993,6 +993,8 @@ struct ath10k {
u32 reg_ack_cts_timeout_orig; u32 reg_ack_cts_timeout_orig;
} fw_coverage; } fw_coverage;
void *ce_priv;
/* must be last */ /* must be last */
u8 drv_priv[0] __aligned(sizeof(void *)); u8 drv_priv[0] __aligned(sizeof(void *));
}; };
......
drivers/net/wireless/ath/ath10k/debug.c
View file @ 1283c617
...@@ -237,7 +237,7 @@ static ssize_t ath10k_read_wmi_services(struct file *file, ...@@ -237,7 +237,7 @@ static ssize_t ath10k_read_wmi_services(struct file *file,
{ {
struct ath10k *ar = file->private_data; struct ath10k *ar = file->private_data;
char *buf; char *buf;
size_t len = 0, buf_len = 4096; size_t len = 0, buf_len = 8192;
const char *name; const char *name;
ssize_t ret_cnt; ssize_t ret_cnt;
bool enabled; bool enabled;
......
drivers/net/wireless/ath/ath10k/hw.c
View file @ 1283c617
...@@ -192,6 +192,156 @@ const struct ath10k_hw_values qca4019_values = { ...@@ -192,6 +192,156 @@ const struct ath10k_hw_values qca4019_values = {
.ce_desc_meta_data_lsb = 4, .ce_desc_meta_data_lsb = 4,
}; };
const struct ath10k_hw_regs wcn3990_regs = {
.rtc_soc_base_address = 0x00000000,
.rtc_wmac_base_address = 0x00000000,
.soc_core_base_address = 0x00000000,
.ce_wrapper_base_address = 0x0024C000,
.ce0_base_address = 0x00240000,
.ce1_base_address = 0x00241000,
.ce2_base_address = 0x00242000,
.ce3_base_address = 0x00243000,
.ce4_base_address = 0x00244000,
.ce5_base_address = 0x00245000,
.ce6_base_address = 0x00246000,
.ce7_base_address = 0x00247000,
.ce8_base_address = 0x00248000,
.ce9_base_address = 0x00249000,
.ce10_base_address = 0x0024A000,
.ce11_base_address = 0x0024B000,
.soc_chip_id_address = 0x000000f0,
.soc_reset_control_si0_rst_mask = 0x00000001,
.soc_reset_control_ce_rst_mask = 0x00000100,
.ce_wrap_intr_sum_host_msi_lsb = 0x0000000c,
.ce_wrap_intr_sum_host_msi_mask = 0x00fff000,
.pcie_intr_fw_mask = 0x00100000,
};
static struct ath10k_hw_ce_regs_addr_map wcn3990_src_ring = {
.msb = 0x00000010,
.lsb = 0x00000010,
.mask = GENMASK(17, 17),
};
static struct ath10k_hw_ce_regs_addr_map wcn3990_dst_ring = {
.msb = 0x00000012,
.lsb = 0x00000012,
.mask = GENMASK(18, 18),
};
static struct ath10k_hw_ce_regs_addr_map wcn3990_dmax = {
.msb = 0x00000000,
.lsb = 0x00000000,
.mask = GENMASK(15, 0),
};
static struct ath10k_hw_ce_ctrl1 wcn3990_ctrl1 = {
.addr = 0x00000018,
.src_ring = &wcn3990_src_ring,
.dst_ring = &wcn3990_dst_ring,
.dmax = &wcn3990_dmax,
};
static struct ath10k_hw_ce_regs_addr_map wcn3990_host_ie_cc = {
.mask = GENMASK(0, 0),
};
static struct ath10k_hw_ce_host_ie wcn3990_host_ie = {
.copy_complete = &wcn3990_host_ie_cc,
};
static struct ath10k_hw_ce_host_wm_regs wcn3990_wm_reg = {
.dstr_lmask = 0x00000010,
.dstr_hmask = 0x00000008,
.srcr_lmask = 0x00000004,
.srcr_hmask = 0x00000002,
.cc_mask = 0x00000001,
.wm_mask = 0x0000001E,
.addr = 0x00000030,
};
static struct ath10k_hw_ce_misc_regs wcn3990_misc_reg = {
.axi_err = 0x00000100,
.dstr_add_err = 0x00000200,
.srcr_len_err = 0x00000100,
.dstr_mlen_vio = 0x00000080,
.dstr_overflow = 0x00000040,
.srcr_overflow = 0x00000020,
.err_mask = 0x000003E0,
.addr = 0x00000038,
};
static struct ath10k_hw_ce_regs_addr_map wcn3990_src_wm_low = {
.msb = 0x00000000,
.lsb = 0x00000010,
.mask = GENMASK(31, 16),
};
static struct ath10k_hw_ce_regs_addr_map wcn3990_src_wm_high = {
.msb = 0x0000000f,
.lsb = 0x00000000,
.mask = GENMASK(15, 0),
};
static struct ath10k_hw_ce_dst_src_wm_regs wcn3990_wm_src_ring = {
.addr = 0x0000004c,
.low_rst = 0x00000000,
.high_rst = 0x00000000,
.wm_low = &wcn3990_src_wm_low,
.wm_high = &wcn3990_src_wm_high,
};
static struct ath10k_hw_ce_regs_addr_map wcn3990_dst_wm_low = {
.lsb = 0x00000010,
.mask = GENMASK(31, 16),
};
static struct ath10k_hw_ce_regs_addr_map wcn3990_dst_wm_high = {
.msb = 0x0000000f,
.lsb = 0x00000000,
.mask = GENMASK(15, 0),
};
static struct ath10k_hw_ce_dst_src_wm_regs wcn3990_wm_dst_ring = {
.addr = 0x00000050,
.low_rst = 0x00000000,
.high_rst = 0x00000000,
.wm_low = &wcn3990_dst_wm_low,
.wm_high = &wcn3990_dst_wm_high,
};
struct ath10k_hw_ce_regs wcn3990_ce_regs = {
.sr_base_addr = 0x00000000,
.sr_size_addr = 0x00000008,
.dr_base_addr = 0x0000000c,
.dr_size_addr = 0x00000014,
.misc_ie_addr = 0x00000034,
.sr_wr_index_addr = 0x0000003c,
.dst_wr_index_addr = 0x00000040,
.current_srri_addr = 0x00000044,
.current_drri_addr = 0x00000048,
.ddr_addr_for_rri_low = 0x00000004,
.ddr_addr_for_rri_high = 0x00000008,
.ce_rri_low = 0x0024C004,
.ce_rri_high = 0x0024C008,
.host_ie_addr = 0x0000002c,
.ctrl1_regs = &wcn3990_ctrl1,
.host_ie = &wcn3990_host_ie,
.wm_regs = &wcn3990_wm_reg,
.misc_regs = &wcn3990_misc_reg,
.wm_srcr = &wcn3990_wm_src_ring,
.wm_dstr = &wcn3990_wm_dst_ring,
};
const struct ath10k_hw_values wcn3990_values = {
.rtc_state_val_on = 5,
.ce_count = 12,
.msi_assign_ce_max = 12,
.num_target_ce_config_wlan = 12,
.ce_desc_meta_data_mask = 0xFFF0,
.ce_desc_meta_data_lsb = 4,
};
static struct ath10k_hw_ce_regs_addr_map qcax_src_ring = { static struct ath10k_hw_ce_regs_addr_map qcax_src_ring = {
.msb = 0x00000010, .msb = 0x00000010,
.lsb = 0x00000010, .lsb = 0x00000010,
......
drivers/net/wireless/ath/ath10k/hw.h
View file @ 1283c617
...@@ -231,6 +231,7 @@ enum ath10k_hw_rev { ...@@ -231,6 +231,7 @@ enum ath10k_hw_rev {
ATH10K_HW_QCA9377, ATH10K_HW_QCA9377,
ATH10K_HW_QCA4019, ATH10K_HW_QCA4019,
ATH10K_HW_QCA9887, ATH10K_HW_QCA9887,
ATH10K_HW_WCN3990,
}; };
struct ath10k_hw_regs { struct ath10k_hw_regs {
...@@ -247,6 +248,10 @@ struct ath10k_hw_regs { ...@@ -247,6 +248,10 @@ struct ath10k_hw_regs {
u32 ce5_base_address; u32 ce5_base_address;
u32 ce6_base_address; u32 ce6_base_address;
u32 ce7_base_address; u32 ce7_base_address;
u32 ce8_base_address;
u32 ce9_base_address;
u32 ce10_base_address;
u32 ce11_base_address;
u32 soc_reset_control_si0_rst_mask; u32 soc_reset_control_si0_rst_mask;
u32 soc_reset_control_ce_rst_mask; u32 soc_reset_control_ce_rst_mask;
u32 soc_chip_id_address; u32 soc_chip_id_address;
...@@ -267,6 +272,7 @@ extern const struct ath10k_hw_regs qca988x_regs; ...@@ -267,6 +272,7 @@ extern const struct ath10k_hw_regs qca988x_regs;
extern const struct ath10k_hw_regs qca6174_regs; extern const struct ath10k_hw_regs qca6174_regs;
extern const struct ath10k_hw_regs qca99x0_regs; extern const struct ath10k_hw_regs qca99x0_regs;
extern const struct ath10k_hw_regs qca4019_regs; extern const struct ath10k_hw_regs qca4019_regs;
extern const struct ath10k_hw_regs wcn3990_regs;
struct ath10k_hw_ce_regs_addr_map { struct ath10k_hw_ce_regs_addr_map {
u32 msb; u32 msb;
...@@ -362,6 +368,8 @@ extern const struct ath10k_hw_values qca6174_values; ...@@ -362,6 +368,8 @@ extern const struct ath10k_hw_values qca6174_values;
extern const struct ath10k_hw_values qca99x0_values; extern const struct ath10k_hw_values qca99x0_values;
extern const struct ath10k_hw_values qca9888_values; extern const struct ath10k_hw_values qca9888_values;
extern const struct ath10k_hw_values qca4019_values; extern const struct ath10k_hw_values qca4019_values;
extern const struct ath10k_hw_values wcn3990_values;
extern struct ath10k_hw_ce_regs wcn3990_ce_regs;
extern struct ath10k_hw_ce_regs qcax_ce_regs; extern struct ath10k_hw_ce_regs qcax_ce_regs;
void ath10k_hw_fill_survey_time(struct ath10k *ar, struct survey_info *survey, void ath10k_hw_fill_survey_time(struct ath10k *ar, struct survey_info *survey,
...@@ -375,6 +383,7 @@ void ath10k_hw_fill_survey_time(struct ath10k *ar, struct survey_info *survey, ...@@ -375,6 +383,7 @@ void ath10k_hw_fill_survey_time(struct ath10k *ar, struct survey_info *survey,
#define QCA_REV_9984(ar) ((ar)->hw_rev == ATH10K_HW_QCA9984) #define QCA_REV_9984(ar) ((ar)->hw_rev == ATH10K_HW_QCA9984)
#define QCA_REV_9377(ar) ((ar)->hw_rev == ATH10K_HW_QCA9377) #define QCA_REV_9377(ar) ((ar)->hw_rev == ATH10K_HW_QCA9377)
#define QCA_REV_40XX(ar) ((ar)->hw_rev == ATH10K_HW_QCA4019) #define QCA_REV_40XX(ar) ((ar)->hw_rev == ATH10K_HW_QCA4019)
#define QCA_REV_WCN3990(ar) ((ar)->hw_rev == ATH10K_HW_WCN3990)
/* Known peculiarities: /* Known peculiarities:
* - raw appears in nwifi decap, raw and nwifi appear in ethernet decap * - raw appears in nwifi decap, raw and nwifi appear in ethernet decap
......
drivers/net/wireless/ath/ath10k/pci.c
View file @ 1283c617
...@@ -672,16 +672,16 @@ static u32 ath10k_bus_pci_read32(struct ath10k *ar, u32 offset) ...@@ -672,16 +672,16 @@ static u32 ath10k_bus_pci_read32(struct ath10k *ar, u32 offset)
inline void ath10k_pci_write32(struct ath10k *ar, u32 offset, u32 value) inline void ath10k_pci_write32(struct ath10k *ar, u32 offset, u32 value)
{ {
struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); struct ath10k_ce *ce = ath10k_ce_priv(ar);
ar_pci->bus_ops->write32(ar, offset, value); ce->bus_ops->write32(ar, offset, value);
} }
inline u32 ath10k_pci_read32(struct ath10k *ar, u32 offset) inline u32 ath10k_pci_read32(struct ath10k *ar, u32 offset)
{ {
struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); struct ath10k_ce *ce = ath10k_ce_priv(ar);
return ar_pci->bus_ops->read32(ar, offset); return ce->bus_ops->read32(ar, offset);
} }
u32 ath10k_pci_soc_read32(struct ath10k *ar, u32 addr) u32 ath10k_pci_soc_read32(struct ath10k *ar, u32 addr)
...@@ -761,7 +761,7 @@ static inline const char *ath10k_pci_get_irq_method(struct ath10k *ar) ...@@ -761,7 +761,7 @@ static inline const char *ath10k_pci_get_irq_method(struct ath10k *ar)
static int __ath10k_pci_rx_post_buf(struct ath10k_pci_pipe *pipe) static int __ath10k_pci_rx_post_buf(struct ath10k_pci_pipe *pipe)
{ {
struct ath10k *ar = pipe->hif_ce_state; struct ath10k *ar = pipe->hif_ce_state;
struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); struct ath10k_ce *ce = ath10k_ce_priv(ar);
struct ath10k_ce_pipe *ce_pipe = pipe->ce_hdl; struct ath10k_ce_pipe *ce_pipe = pipe->ce_hdl;
struct sk_buff *skb; struct sk_buff *skb;
dma_addr_t paddr; dma_addr_t paddr;
...@@ -784,9 +784,9 @@ static int __ath10k_pci_rx_post_buf(struct ath10k_pci_pipe *pipe) ...@@ -784,9 +784,9 @@ static int __ath10k_pci_rx_post_buf(struct ath10k_pci_pipe *pipe)
ATH10K_SKB_RXCB(skb)->paddr = paddr; ATH10K_SKB_RXCB(skb)->paddr = paddr;
spin_lock_bh(&ar_pci->ce_lock); spin_lock_bh(&ce->ce_lock);
ret = __ath10k_ce_rx_post_buf(ce_pipe, skb, paddr); ret = __ath10k_ce_rx_post_buf(ce_pipe, skb, paddr);
spin_unlock_bh(&ar_pci->ce_lock); spin_unlock_bh(&ce->ce_lock);
if (ret) { if (ret) {
dma_unmap_single(ar->dev, paddr, skb->len + skb_tailroom(skb), dma_unmap_single(ar->dev, paddr, skb->len + skb_tailroom(skb),
DMA_FROM_DEVICE); DMA_FROM_DEVICE);
...@@ -801,6 +801,7 @@ static void ath10k_pci_rx_post_pipe(struct ath10k_pci_pipe *pipe) ...@@ -801,6 +801,7 @@ static void ath10k_pci_rx_post_pipe(struct ath10k_pci_pipe *pipe)
{ {
struct ath10k *ar = pipe->hif_ce_state; struct ath10k *ar = pipe->hif_ce_state;
struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
struct ath10k_ce *ce = ath10k_ce_priv(ar);
struct ath10k_ce_pipe *ce_pipe = pipe->ce_hdl; struct ath10k_ce_pipe *ce_pipe = pipe->ce_hdl;
int ret, num; int ret, num;
...@@ -810,9 +811,9 @@ static void ath10k_pci_rx_post_pipe(struct ath10k_pci_pipe *pipe) ...@@ -810,9 +811,9 @@ static void ath10k_pci_rx_post_pipe(struct ath10k_pci_pipe *pipe)
if (!ce_pipe->dest_ring) if (!ce_pipe->dest_ring)
return; return;
spin_lock_bh(&ar_pci->ce_lock); spin_lock_bh(&ce->ce_lock);
num = __ath10k_ce_rx_num_free_bufs(ce_pipe); num = __ath10k_ce_rx_num_free_bufs(ce_pipe);
spin_unlock_bh(&ar_pci->ce_lock); spin_unlock_bh(&ce->ce_lock);
while (num >= 0) { while (num >= 0) {
ret = __ath10k_pci_rx_post_buf(pipe); ret = __ath10k_pci_rx_post_buf(pipe);
...@@ -882,6 +883,7 @@ static int ath10k_pci_diag_read_mem(struct ath10k *ar, u32 address, void *data, ...@@ -882,6 +883,7 @@ static int ath10k_pci_diag_read_mem(struct ath10k *ar, u32 address, void *data,
int nbytes) int nbytes)
{ {
struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
struct ath10k_ce *ce = ath10k_ce_priv(ar);
int ret = 0; int ret = 0;
u32 *buf; u32 *buf;
unsigned int completed_nbytes, alloc_nbytes, remaining_bytes; unsigned int completed_nbytes, alloc_nbytes, remaining_bytes;
...@@ -892,7 +894,7 @@ static int ath10k_pci_diag_read_mem(struct ath10k *ar, u32 address, void *data, ...@@ -892,7 +894,7 @@ static int ath10k_pci_diag_read_mem(struct ath10k *ar, u32 address, void *data,
void *data_buf = NULL; void *data_buf = NULL;
int i; int i;
spin_lock_bh(&ar_pci->ce_lock); spin_lock_bh(&ce->ce_lock);
ce_diag = ar_pci->ce_diag; ce_diag = ar_pci->ce_diag;
...@@ -986,7 +988,7 @@ static int ath10k_pci_diag_read_mem(struct ath10k *ar, u32 address, void *data, ...@@ -986,7 +988,7 @@ static int ath10k_pci_diag_read_mem(struct ath10k *ar, u32 address, void *data,
dma_free_coherent(ar->dev, alloc_nbytes, data_buf, dma_free_coherent(ar->dev, alloc_nbytes, data_buf,
ce_data_base); ce_data_base);
spin_unlock_bh(&ar_pci->ce_lock); spin_unlock_bh(&ce->ce_lock);
return ret; return ret;
} }
...@@ -1034,6 +1036,7 @@ int ath10k_pci_diag_write_mem(struct ath10k *ar, u32 address, ...@@ -1034,6 +1036,7 @@ int ath10k_pci_diag_write_mem(struct ath10k *ar, u32 address,
const void *data, int nbytes) const void *data, int nbytes)
{ {
struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
struct ath10k_ce *ce = ath10k_ce_priv(ar);
int ret = 0; int ret = 0;
u32 *buf; u32 *buf;
unsigned int completed_nbytes, orig_nbytes, remaining_bytes; unsigned int completed_nbytes, orig_nbytes, remaining_bytes;
...@@ -1043,7 +1046,7 @@ int ath10k_pci_diag_write_mem(struct ath10k *ar, u32 address, ...@@ -1043,7 +1046,7 @@ int ath10k_pci_diag_write_mem(struct ath10k *ar, u32 address,
dma_addr_t ce_data_base = 0; dma_addr_t ce_data_base = 0;
int i; int i;
spin_lock_bh(&ar_pci->ce_lock); spin_lock_bh(&ce->ce_lock);
ce_diag = ar_pci->ce_diag; ce_diag = ar_pci->ce_diag;
...@@ -1147,7 +1150,7 @@ int ath10k_pci_diag_write_mem(struct ath10k *ar, u32 address, ...@@ -1147,7 +1150,7 @@ int ath10k_pci_diag_write_mem(struct ath10k *ar, u32 address,
ath10k_warn(ar, "failed to write diag value at 0x%x: %d\n", ath10k_warn(ar, "failed to write diag value at 0x%x: %d\n",
address, ret); address, ret);
spin_unlock_bh(&ar_pci->ce_lock); spin_unlock_bh(&ce->ce_lock);
return ret; return ret;
} }
...@@ -1342,6 +1345,7 @@ int ath10k_pci_hif_tx_sg(struct ath10k *ar, u8 pipe_id, ...@@ -1342,6 +1345,7 @@ int ath10k_pci_hif_tx_sg(struct ath10k *ar, u8 pipe_id,
struct ath10k_hif_sg_item *items, int n_items) struct ath10k_hif_sg_item *items, int n_items)
{ {
struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
struct ath10k_ce *ce = ath10k_ce_priv(ar);
struct ath10k_pci_pipe *pci_pipe = &ar_pci->pipe_info[pipe_id]; struct ath10k_pci_pipe *pci_pipe = &ar_pci->pipe_info[pipe_id];
struct ath10k_ce_pipe *ce_pipe = pci_pipe->ce_hdl; struct ath10k_ce_pipe *ce_pipe = pci_pipe->ce_hdl;
struct ath10k_ce_ring *src_ring = ce_pipe->src_ring; struct ath10k_ce_ring *src_ring = ce_pipe->src_ring;
...@@ -1350,7 +1354,7 @@ int ath10k_pci_hif_tx_sg(struct ath10k *ar, u8 pipe_id, ...@@ -1350,7 +1354,7 @@ int ath10k_pci_hif_tx_sg(struct ath10k *ar, u8 pipe_id,
unsigned int write_index; unsigned int write_index;
int err, i = 0; int err, i = 0;
spin_lock_bh(&ar_pci->ce_lock); spin_lock_bh(&ce->ce_lock);
nentries_mask = src_ring->nentries_mask; nentries_mask = src_ring->nentries_mask;
sw_index = src_ring->sw_index; sw_index = src_ring->sw_index;
...@@ -1396,14 +1400,14 @@ int ath10k_pci_hif_tx_sg(struct ath10k *ar, u8 pipe_id, ...@@ -1396,14 +1400,14 @@ int ath10k_pci_hif_tx_sg(struct ath10k *ar, u8 pipe_id,
if (err) if (err)
goto err; goto err;
spin_unlock_bh(&ar_pci->ce_lock); spin_unlock_bh(&ce->ce_lock);
return 0; return 0;
err: err:
for (; i > 0; i--) for (; i > 0; i--)
__ath10k_ce_send_revert(ce_pipe); __ath10k_ce_send_revert(ce_pipe);
spin_unlock_bh(&ar_pci->ce_lock); spin_unlock_bh(&ce->ce_lock);
return err; return err;
} }
...@@ -1593,6 +1597,8 @@ void ath10k_pci_irq_msi_fw_mask(struct ath10k *ar) ...@@ -1593,6 +1597,8 @@ void ath10k_pci_irq_msi_fw_mask(struct ath10k *ar)
* to mask irq/MSI. * to mask irq/MSI.
*/ */
break; break;
case ATH10K_HW_WCN3990:
break;
} }
} }
...@@ -1619,6 +1625,8 @@ static void ath10k_pci_irq_msi_fw_unmask(struct ath10k *ar) ...@@ -1619,6 +1625,8 @@ static void ath10k_pci_irq_msi_fw_unmask(struct ath10k *ar)
* to unmask irq/MSI. * to unmask irq/MSI.
*/ */
break; break;
case ATH10K_HW_WCN3990:
break;
} }
} }
...@@ -2000,9 +2008,9 @@ static int ath10k_pci_get_num_banks(struct ath10k *ar) ...@@ -2000,9 +2008,9 @@ static int ath10k_pci_get_num_banks(struct ath10k *ar)
static int ath10k_bus_get_num_banks(struct ath10k *ar) static int ath10k_bus_get_num_banks(struct ath10k *ar)
{ {
struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); struct ath10k_ce *ce = ath10k_ce_priv(ar);
return ar_pci->bus_ops->get_num_banks(ar); return ce->bus_ops->get_num_banks(ar);
} }
int ath10k_pci_init_config(struct ath10k *ar) int ath10k_pci_init_config(struct ath10k *ar)
...@@ -2173,11 +2181,12 @@ int ath10k_pci_alloc_pipes(struct ath10k *ar) ...@@ -2173,11 +2181,12 @@ int ath10k_pci_alloc_pipes(struct ath10k *ar)
{ {
struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
struct ath10k_pci_pipe *pipe; struct ath10k_pci_pipe *pipe;
struct ath10k_ce *ce = ath10k_ce_priv(ar);
int i, ret; int i, ret;
for (i = 0; i < CE_COUNT; i++) { for (i = 0; i < CE_COUNT; i++) {
pipe = &ar_pci->pipe_info[i]; pipe = &ar_pci->pipe_info[i];
pipe->ce_hdl = &ar_pci->ce_states[i]; pipe->ce_hdl = &ce->ce_states[i];
pipe->pipe_num = i; pipe->pipe_num = i;
pipe->hif_ce_state = ar; pipe->hif_ce_state = ar;
...@@ -2825,7 +2834,7 @@ static int ath10k_pci_napi_poll(struct napi_struct *ctx, int budget) ...@@ -2825,7 +2834,7 @@ static int ath10k_pci_napi_poll(struct napi_struct *ctx, int budget)
* interrupts safer to check for pending interrupts for * interrupts safer to check for pending interrupts for
* immediate servicing. * immediate servicing.
*/ */
if (CE_INTERRUPT_SUMMARY(ar)) { if (ath10k_ce_interrupt_summary(ar)) {
napi_reschedule(ctx); napi_reschedule(ctx);
goto out; goto out;
} }
...@@ -3142,9 +3151,10 @@ static bool ath10k_pci_chip_is_supported(u32 dev_id, u32 chip_id) ...@@ -3142,9 +3151,10 @@ static bool ath10k_pci_chip_is_supported(u32 dev_id, u32 chip_id)
int ath10k_pci_setup_resource(struct ath10k *ar) int ath10k_pci_setup_resource(struct ath10k *ar)
{ {
struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
struct ath10k_ce *ce = ath10k_ce_priv(ar);
int ret; int ret;
spin_lock_init(&ar_pci->ce_lock); spin_lock_init(&ce->ce_lock);
spin_lock_init(&ar_pci->ps_lock); spin_lock_init(&ar_pci->ps_lock);
setup_timer(&ar_pci->rx_post_retry, ath10k_pci_rx_replenish_retry, setup_timer(&ar_pci->rx_post_retry, ath10k_pci_rx_replenish_retry,
...@@ -3263,10 +3273,11 @@ static int ath10k_pci_probe(struct pci_dev *pdev, ...@@ -3263,10 +3273,11 @@ static int ath10k_pci_probe(struct pci_dev *pdev,
ar_pci->ar = ar; ar_pci->ar = ar;
ar->dev_id = pci_dev->device; ar->dev_id = pci_dev->device;
ar_pci->pci_ps = pci_ps; ar_pci->pci_ps = pci_ps;
ar_pci->bus_ops = &ath10k_pci_bus_ops; ar_pci->ce.bus_ops = &ath10k_pci_bus_ops;
ar_pci->pci_soft_reset = pci_soft_reset; ar_pci->pci_soft_reset = pci_soft_reset;
ar_pci->pci_hard_reset = pci_hard_reset; ar_pci->pci_hard_reset = pci_hard_reset;
ar_pci->targ_cpu_to_ce_addr = targ_cpu_to_ce_addr; ar_pci->targ_cpu_to_ce_addr = targ_cpu_to_ce_addr;
ar->ce_priv = &ar_pci->ce;
ar->id.vendor = pdev->vendor; ar->id.vendor = pdev->vendor;
ar->id.device = pdev->device; ar->id.device = pdev->device;
......
drivers/net/wireless/ath/ath10k/pci.h
View file @ 1283c617
...@@ -150,12 +150,6 @@ struct ath10k_pci_supp_chip { ...@@ -150,12 +150,6 @@ struct ath10k_pci_supp_chip {
u32 rev_id; u32 rev_id;
}; };
struct ath10k_bus_ops {
u32 (*read32)(struct ath10k *ar, u32 offset);
void (*write32)(struct ath10k *ar, u32 offset, u32 value);
int (*get_num_banks)(struct ath10k *ar);
};
enum ath10k_pci_irq_mode { enum ath10k_pci_irq_mode {
ATH10K_PCI_IRQ_AUTO = 0, ATH10K_PCI_IRQ_AUTO = 0,
ATH10K_PCI_IRQ_LEGACY = 1, ATH10K_PCI_IRQ_LEGACY = 1,
...@@ -177,11 +171,7 @@ struct ath10k_pci { ...@@ -177,11 +171,7 @@ struct ath10k_pci {
/* Copy Engine used for Diagnostic Accesses */ /* Copy Engine used for Diagnostic Accesses */
struct ath10k_ce_pipe *ce_diag; struct ath10k_ce_pipe *ce_diag;
/* FIXME: document what this really protects */ struct ath10k_ce ce;
spinlock_t ce_lock;
/* Map CE id to ce_state */
struct ath10k_ce_pipe ce_states[CE_COUNT_MAX];
struct timer_list rx_post_retry; struct timer_list rx_post_retry;
/* Due to HW quirks it is recommended to disable ASPM during device /* Due to HW quirks it is recommended to disable ASPM during device
...@@ -225,8 +215,6 @@ struct ath10k_pci { ...@@ -225,8 +215,6 @@ struct ath10k_pci {
*/ */
bool pci_ps; bool pci_ps;
const struct ath10k_bus_ops *bus_ops;
/* Chip specific pci reset routine used to do a safe reset */ /* Chip specific pci reset routine used to do a safe reset */
int (*pci_soft_reset)(struct ath10k *ar); int (*pci_soft_reset)(struct ath10k *ar);
......
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