Commit 12d80bca authored by Paweł Jabłoński's avatar Paweł Jabłoński Committed by Jeff Kirsher

i40e: Fix the polling mechanism of GLGEN_RSTAT.DEVSTATE

This fixes the polling mechanism of GLGEN_RSTAT.DEVSTATE in the
PF Reset path when Global Reset is in progress. While the driver
is polling for the end of the PF Reset and the Global Reset is
triggered, abandon the PF Reset path and prepare for the
upcoming Global Reset.
Signed-off-by: default avatarPaweł Jabłoński <pawel.jablonski@intel.com>
Tested-by: default avatarAndrew Bowers <andrewx.bowers@intel.com>
Signed-off-by: default avatarJeff Kirsher <jeffrey.t.kirsher@intel.com>
parent 6b9a9c26
...@@ -1208,6 +1208,29 @@ static enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw) ...@@ -1208,6 +1208,29 @@ static enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw)
return media; return media;
} }
/**
* i40e_poll_globr - Poll for Global Reset completion
* @hw: pointer to the hardware structure
* @retry_limit: how many times to retry before failure
**/
static i40e_status i40e_poll_globr(struct i40e_hw *hw,
u32 retry_limit)
{
u32 cnt, reg = 0;
for (cnt = 0; cnt < retry_limit; cnt++) {
reg = rd32(hw, I40E_GLGEN_RSTAT);
if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
return 0;
msleep(100);
}
hw_dbg(hw, "Global reset failed.\n");
hw_dbg(hw, "I40E_GLGEN_RSTAT = 0x%x\n", reg);
return I40E_ERR_RESET_FAILED;
}
#define I40E_PF_RESET_WAIT_COUNT_A0 200 #define I40E_PF_RESET_WAIT_COUNT_A0 200
#define I40E_PF_RESET_WAIT_COUNT 200 #define I40E_PF_RESET_WAIT_COUNT 200
/** /**
...@@ -1284,14 +1307,14 @@ i40e_status i40e_pf_reset(struct i40e_hw *hw) ...@@ -1284,14 +1307,14 @@ i40e_status i40e_pf_reset(struct i40e_hw *hw)
if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK)) if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK))
break; break;
reg2 = rd32(hw, I40E_GLGEN_RSTAT); reg2 = rd32(hw, I40E_GLGEN_RSTAT);
if (reg2 & I40E_GLGEN_RSTAT_DEVSTATE_MASK) { if (reg2 & I40E_GLGEN_RSTAT_DEVSTATE_MASK)
hw_dbg(hw, "Core reset upcoming. Skipping PF reset request.\n"); break;
hw_dbg(hw, "I40E_GLGEN_RSTAT = 0x%x\n", reg2);
return I40E_ERR_NOT_READY;
}
usleep_range(1000, 2000); usleep_range(1000, 2000);
} }
if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) { if (reg2 & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
if (i40e_poll_globr(hw, grst_del))
return I40E_ERR_RESET_FAILED;
} else if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) {
hw_dbg(hw, "PF reset polling failed to complete.\n"); hw_dbg(hw, "PF reset polling failed to complete.\n");
return I40E_ERR_RESET_FAILED; return I40E_ERR_RESET_FAILED;
} }
......
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