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Commit 12fdba56 authored by Mauro Carvalho Chehab's avatar Mauro Carvalho Chehab
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Merge tag 'for-5.18-2.6-signed' of git://linuxtv.org/sailus/media_tree into media_stage 

Even yet more V4L2 patches for 5.18

* tag 'for-5.18-2.6-signed' of git://linuxtv.org/sailus/media_tree:
  media: i2c: Fix pixel array positions in ov8865
  media: adv7183: Convert to GPIO descriptors
  media: m5mols: Convert to use GPIO descriptors
  media: noon010p30: Convert to use GPIO descriptors
  media: mt9m111: Drop unused include
  media: adv7511: Drop unused include
  media: i2c: isl7998x: Add driver for Intersil ISL7998x
  media: dt-bindings: Add Intersil ISL79987 DT bindings
  media: media-entity: Clarify media_entity_cleanup() usage
  media: i2c: imx274: Drop surplus includes
  media: i2c: ccs: Drop unused include
  v4l: fwnode: Remove now-redundant loop from v4l2_fwnode_parse_reference()
  v4l: fwnode: Drop redunant -ENODATA check in property reference parsing
  media: media-entity: Simplify media_pipeline_start()
  media: media-entity: Add media_pad_is_streaming() helper function
  media: Add a driver for the og01a1b camera sensor
  media: i2c: ov5648: Fix lockdep error
  media: ov5640: Fix set format, v4l2_mbus_pixelcode not updated
Signed-off-by: default avatarMauro Carvalho Chehab <mchehab@kernel.org>
parents 5ad05eca 3d1e4228
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Documentation/devicetree/bindings/media/i2c/isil,isl79987.yaml 0 → 100644
View file @ 12fdba56
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/media/i2c/isil,isl79987.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Intersil ISL79987 Analog to MIPI CSI-2 decoder
maintainers:
- Michael Tretter <m.tretter@pengutronix.de>
- Marek Vasut <marex@denx.de>
description:
The Intersil ISL79987 is an analog to MIPI CSI-2 decoder which is capable of
receiving up to four analog stream and multiplexing them into up to four MIPI
CSI-2 virtual channels, using one MIPI clock lane and 1/2 data lanes.
properties:
compatible:
enum:
- isil,isl79987
reg:
maxItems: 1
reset-gpios:
maxItems: 1
description:
A GPIO spec for the RSTB pin (active high)
powerdown-gpios:
maxItems: 1
description:
A GPIO spec for the Power Down pin (active high)
ports:
$ref: /schemas/graph.yaml#/properties/ports
properties:
port@0:
$ref: /schemas/graph.yaml#/$defs/port-base
unevaluatedProperties: false
description: Output port
properties:
endpoint:
$ref: /schemas/media/video-interfaces.yaml#
unevaluatedProperties: false
properties:
data-lanes:
minItems: 1
maxItems: 2
required:
- data-lanes
patternProperties:
"^port@[1-4]$":
$ref: /schemas/graph.yaml#/properties/port
description: Input ports
required:
- port@0
additionalProperties: false
required:
- compatible
- reg
- ports
examples:
- |
#include <dt-bindings/gpio/gpio.h>
i2c {
#address-cells = <1>;
#size-cells = <0>;
isl7998x_mipi@44 {
compatible = "isil,isl79987";
reg = <0x44>;
powerdown-gpios = <&gpio3 27 GPIO_ACTIVE_HIGH>;
reset-gpios = <&gpio3 28 GPIO_ACTIVE_HIGH>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
isl79987_out: endpoint {
remote-endpoint = <&mipi_csi2_in>;
data-lanes = <1 2>;
};
};
port@1 {
reg = <1>;
endpoint {
remote-endpoint = <&camera_0>;
};
};
port@2 {
reg = <2>;
endpoint {
remote-endpoint = <&camera_1>;
};
};
};
};
};
MAINTAINERS
View file @ 12fdba56
......@@ -10006,6 +10006,14 @@ L: linux-iio@vger.kernel.org
F: Documentation/devicetree/bindings/counter/interrupt-counter.yaml
F: drivers/counter/interrupt-cnt.c
INTERSIL ISL7998X VIDEO DECODER DRIVER
M: Michael Tretter <m.tretter@pengutronix.de>
R: Pengutronix Kernel Team <kernel@pengutronix.de>
L: linux-media@vger.kernel.org
S: Maintained
F: Documentation/devicetree/bindings/media/i2c/isil,isl79987.yaml
F: drivers/media/i2c/isl7998x.c
INVENSENSE ICM-426xx IMU DRIVER
M: Jean-Baptiste Maneyrol <jmaneyrol@invensense.com>
L: linux-iio@vger.kernel.org
......@@ -14185,6 +14193,12 @@ M: Harald Welte <laforge@gnumonks.org>
S: Maintained
F: drivers/char/pcmcia/cm4040_cs.*
OMNIVISION OG01A1B SENSOR DRIVER
M: Shawn Tu <shawnx.tu@intel.com>
L: linux-media@vger.kernel.org
S: Maintained
F: drivers/media/i2c/og01a1b.c
OMNIVISION OV02A10 SENSOR DRIVER
M: Dongchun Zhu <dongchun.zhu@mediatek.com>
L: linux-media@vger.kernel.org
......
drivers/media/i2c/Kconfig
View file @ 12fdba56
......@@ -325,6 +325,16 @@ config VIDEO_BT866
To compile this driver as a module, choose M here: the
module will be called bt866.
config VIDEO_ISL7998X
tristate "Intersil ISL7998x video decoder"
depends on VIDEO_V4L2 && I2C
depends on OF_GPIO
select MEDIA_CONTROLLER
select VIDEO_V4L2_SUBDEV_API
help
Support for Intersil ISL7998x analog to MIPI-CSI2 or
BT.656 decoder.
config VIDEO_KS0127
tristate "KS0127 video decoder"
depends on VIDEO_V4L2 && I2C
......@@ -912,6 +922,19 @@ config VIDEO_IMX412
To compile this driver as a module, choose M here: the
module will be called imx412.
config VIDEO_OG01A1B
tristate "OmniVision OG01A1B sensor support"
depends on I2C && VIDEO_V4L2
select MEDIA_CONTROLLER
select VIDEO_V4L2_SUBDEV_API
select V4L2_FWNODE
help
This is a Video4Linux2 sensor driver for the OmniVision
OG01A1B camera.
To compile this driver as a module, choose M here: the
module will be called og01a1b.
config VIDEO_OV02A10
tristate "OmniVision OV02A10 sensor support"
depends on VIDEO_V4L2 && I2C
......
drivers/media/i2c/Makefile
View file @ 12fdba56
......@@ -64,6 +64,7 @@ obj-$(CONFIG_VIDEO_VP27SMPX) += vp27smpx.o
obj-$(CONFIG_VIDEO_SONY_BTF_MPX) += sony-btf-mpx.o
obj-$(CONFIG_VIDEO_UPD64031A) += upd64031a.o
obj-$(CONFIG_VIDEO_UPD64083) += upd64083.o
obj-$(CONFIG_VIDEO_OG01A1B) += og01a1b.o
obj-$(CONFIG_VIDEO_OV02A10) += ov02a10.o
obj-$(CONFIG_VIDEO_OV08D10) += ov08d10.o
obj-$(CONFIG_VIDEO_OV2640) += ov2640.o
......@@ -133,6 +134,7 @@ obj-$(CONFIG_VIDEO_IMX334) += imx334.o
obj-$(CONFIG_VIDEO_IMX335) += imx335.o
obj-$(CONFIG_VIDEO_IMX355) += imx355.o
obj-$(CONFIG_VIDEO_IMX412) += imx412.o
obj-$(CONFIG_VIDEO_ISL7998X) += isl7998x.o
obj-$(CONFIG_VIDEO_MAX9286) += max9286.o
obj-$(CONFIG_VIDEO_MAX9271_LIB) += max9271.o
obj-$(CONFIG_VIDEO_RDACM20) += rdacm20.o
......
drivers/media/i2c/adv7183.c
View file @ 12fdba56
......@@ -7,7 +7,7 @@
#include <linux/delay.h>
#include <linux/errno.h>
#include <linux/gpio.h>
#include <linux/gpio/consumer.h>
#include <linux/i2c.h>
#include <linux/init.h>
#include <linux/module.h>
......@@ -28,8 +28,8 @@ struct adv7183 {
v4l2_std_id std; /* Current set standard */
u32 input;
u32 output;
unsigned reset_pin;
unsigned oe_pin;
struct gpio_desc *reset_pin;
struct gpio_desc *oe_pin;
struct v4l2_mbus_framefmt fmt;
};
......@@ -465,9 +465,9 @@ static int adv7183_s_stream(struct v4l2_subdev *sd, int enable)
struct adv7183 *decoder = to_adv7183(sd);
if (enable)
gpio_set_value(decoder->oe_pin, 0);
gpiod_set_value(decoder->oe_pin, 1);
else
gpio_set_value(decoder->oe_pin, 1);
gpiod_set_value(decoder->oe_pin, 0);
udelay(1);
return 0;
}
......@@ -531,7 +531,6 @@ static int adv7183_probe(struct i2c_client *client,
struct v4l2_subdev_format fmt = {
.which = V4L2_SUBDEV_FORMAT_ACTIVE,
};
const unsigned *pin_array;
/* Check if the adapter supports the needed features */
if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
......@@ -540,29 +539,28 @@ static int adv7183_probe(struct i2c_client *client,
v4l_info(client, "chip found @ 0x%02x (%s)\n",
client->addr << 1, client->adapter->name);
pin_array = client->dev.platform_data;
if (pin_array == NULL)
return -EINVAL;
decoder = devm_kzalloc(&client->dev, sizeof(*decoder), GFP_KERNEL);
if (decoder == NULL)
return -ENOMEM;
decoder->reset_pin = pin_array[0];
decoder->oe_pin = pin_array[1];
if (devm_gpio_request_one(&client->dev, decoder->reset_pin,
GPIOF_OUT_INIT_LOW, "ADV7183 Reset")) {
v4l_err(client, "failed to request GPIO %d\n", decoder->reset_pin);
return -EBUSY;
}
if (devm_gpio_request_one(&client->dev, decoder->oe_pin,
GPIOF_OUT_INIT_HIGH,
"ADV7183 Output Enable")) {
v4l_err(client, "failed to request GPIO %d\n", decoder->oe_pin);
return -EBUSY;
}
/*
* Requesting high will assert reset, the line should be
* flagged as active low in descriptor table or machine description.
*/
decoder->reset_pin = devm_gpiod_get(&client->dev, "reset",
GPIOD_OUT_HIGH);
if (IS_ERR(decoder->reset_pin))
return PTR_ERR(decoder->reset_pin);
gpiod_set_consumer_name(decoder->reset_pin, "ADV7183 Reset");
/*
* Requesting low will start with output disabled, the line should be
* flagged as active low in descriptor table or machine description.
*/
decoder->oe_pin = devm_gpiod_get(&client->dev, "oe",
GPIOD_OUT_LOW);
if (IS_ERR(decoder->oe_pin))
return PTR_ERR(decoder->oe_pin);
gpiod_set_consumer_name(decoder->reset_pin, "ADV7183 Output Enable");
sd = &decoder->sd;
v4l2_i2c_subdev_init(sd, client, &adv7183_ops);
......@@ -594,7 +592,8 @@ static int adv7183_probe(struct i2c_client *client,
/* reset chip */
/* reset pulse width at least 5ms */
mdelay(10);
gpio_set_value(decoder->reset_pin, 1);
/* De-assert reset line (descriptor tagged active low) */
gpiod_set_value(decoder->reset_pin, 0);
/* wait 5ms before any further i2c writes are performed */
mdelay(5);
......
drivers/media/i2c/adv7511-v4l2.c
View file @ 12fdba56
......@@ -17,7 +17,6 @@
#include <linux/i2c.h>
#include <linux/delay.h>
#include <linux/videodev2.h>
#include <linux/gpio.h>
#include <linux/workqueue.h>
#include <linux/hdmi.h>
#include <linux/v4l2-dv-timings.h>
......
drivers/media/i2c/ccs/ccs-core.c
View file @ 12fdba56
......@@ -17,7 +17,6 @@
#include <linux/delay.h>
#include <linux/device.h>
#include <linux/firmware.h>
#include <linux/gpio.h>
#include <linux/gpio/consumer.h>
#include <linux/module.h>
#include <linux/pm_runtime.h>
......
drivers/media/i2c/imx274.c
View file @ 12fdba56
......@@ -11,13 +11,11 @@
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/gpio.h>
#include <linux/gpio/consumer.h>
#include <linux/i2c.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of_gpio.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <linux/regulator/consumer.h>
......
drivers/media/i2c/isl7998x.c 0 → 100644
View file @ 12fdba56
// SPDX-License-Identifier: GPL-2.0
/*
* Intersil ISL7998x analog to MIPI CSI-2 or BT.656 decoder driver.
*
* Copyright (C) 2018-2019 Marek Vasut <marex@denx.de>
* Copyright (C) 2021 Michael Tretter <kernel@pengutronix.de>
*/
#include <linux/bitfield.h>
#include <linux/delay.h>
#include <linux/gpio.h>
#include <linux/i2c.h>
#include <linux/module.h>
#include <linux/of_graph.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <linux/slab.h>
#include <linux/v4l2-mediabus.h>
#include <linux/videodev2.h>
#include <media/v4l2-async.h>
#include <media/v4l2-common.h>
#include <media/v4l2-ctrls.h>
#include <media/v4l2-device.h>
#include <media/v4l2-fwnode.h>
#include <media/v4l2-ioctl.h>
/*
* This control allows to activate and deactivate the test pattern on
* selected output channels.
* This value is ISL7998x specific.
*/
#define V4L2_CID_TEST_PATTERN_CHANNELS (V4L2_CID_USER_ISL7998X_BASE + 0)
/*
* This control allows to specify the color of the test pattern.
* This value is ISL7998x specific.
*/
#define V4L2_CID_TEST_PATTERN_COLOR (V4L2_CID_USER_ISL7998X_BASE + 1)
/*
* This control allows to specify the bar pattern in the test pattern.
* This value is ISL7998x specific.
*/
#define V4L2_CID_TEST_PATTERN_BARS (V4L2_CID_USER_ISL7998X_BASE + 2)
#define ISL7998X_INPUTS 4
#define ISL7998X_REG(page, reg) (((page) << 8) | (reg))
#define ISL7998X_REG_PN_SIZE 256
#define ISL7998X_REG_PN_BASE(n) ((n) * ISL7998X_REG_PN_SIZE)
#define ISL7998X_REG_PX_DEC_PAGE(page) ISL7998X_REG((page), 0xff)
#define ISL7998X_REG_PX_DEC_PAGE_MASK 0xf
#define ISL7998X_REG_P0_PRODUCT_ID_CODE ISL7998X_REG(0, 0x00)
#define ISL7998X_REG_P0_PRODUCT_REV_CODE ISL7998X_REG(0, 0x01)
#define ISL7998X_REG_P0_SW_RESET_CTL ISL7998X_REG(0, 0x02)
#define ISL7998X_REG_P0_IO_BUFFER_CTL ISL7998X_REG(0, 0x03)
#define ISL7998X_REG_P0_IO_BUFFER_CTL_1_1 ISL7998X_REG(0, 0x04)
#define ISL7998X_REG_P0_IO_PAD_PULL_EN_CTL ISL7998X_REG(0, 0x05)
#define ISL7998X_REG_P0_IO_BUFFER_CTL_1_2 ISL7998X_REG(0, 0x06)
#define ISL7998X_REG_P0_VIDEO_IN_CHAN_CTL ISL7998X_REG(0, 0x07)
#define ISL7998X_REG_P0_CLK_CTL_1 ISL7998X_REG(0, 0x08)
#define ISL7998X_REG_P0_CLK_CTL_2 ISL7998X_REG(0, 0x09)
#define ISL7998X_REG_P0_CLK_CTL_3 ISL7998X_REG(0, 0x0a)
#define ISL7998X_REG_P0_CLK_CTL_4 ISL7998X_REG(0, 0x0b)
#define ISL7998X_REG_P0_MPP1_SYNC_CTL ISL7998X_REG(0, 0x0c)
#define ISL7998X_REG_P0_MPP2_SYNC_CTL ISL7998X_REG(0, 0x0d)
#define ISL7998X_REG_P0_IRQ_SYNC_CTL ISL7998X_REG(0, 0x0e)
#define ISL7998X_REG_P0_INTERRUPT_STATUS ISL7998X_REG(0, 0x10)
#define ISL7998X_REG_P0_CHAN_1_IRQ ISL7998X_REG(0, 0x11)
#define ISL7998X_REG_P0_CHAN_2_IRQ ISL7998X_REG(0, 0x12)
#define ISL7998X_REG_P0_CHAN_3_IRQ ISL7998X_REG(0, 0x13)
#define ISL7998X_REG_P0_CHAN_4_IRQ ISL7998X_REG(0, 0x14)
#define ISL7998X_REG_P0_SHORT_DIAG_IRQ ISL7998X_REG(0, 0x15)
#define ISL7998X_REG_P0_CHAN_1_IRQ_EN ISL7998X_REG(0, 0x16)
#define ISL7998X_REG_P0_CHAN_2_IRQ_EN ISL7998X_REG(0, 0x17)
#define ISL7998X_REG_P0_CHAN_3_IRQ_EN ISL7998X_REG(0, 0x18)
#define ISL7998X_REG_P0_CHAN_4_IRQ_EN ISL7998X_REG(0, 0x19)
#define ISL7998X_REG_P0_SHORT_DIAG_IRQ_EN ISL7998X_REG(0, 0x1a)
#define ISL7998X_REG_P0_CHAN_1_STATUS ISL7998X_REG(0, 0x1b)
#define ISL7998X_REG_P0_CHAN_2_STATUS ISL7998X_REG(0, 0x1c)
#define ISL7998X_REG_P0_CHAN_3_STATUS ISL7998X_REG(0, 0x1d)
#define ISL7998X_REG_P0_CHAN_4_STATUS ISL7998X_REG(0, 0x1e)
#define ISL7998X_REG_P0_SHORT_DIAG_STATUS ISL7998X_REG(0, 0x1f)
#define ISL7998X_REG_P0_CLOCK_DELAY ISL7998X_REG(0, 0x20)
#define ISL7998X_REG_PX_DEC_INPUT_FMT(pg) ISL7998X_REG((pg), 0x02)
#define ISL7998X_REG_PX_DEC_STATUS_1(pg) ISL7998X_REG((pg), 0x03)
#define ISL7998X_REG_PX_DEC_STATUS_1_VDLOSS BIT(7)
#define ISL7998X_REG_PX_DEC_STATUS_1_HLOCK BIT(6)
#define ISL7998X_REG_PX_DEC_STATUS_1_VLOCK BIT(3)
#define ISL7998X_REG_PX_DEC_HS_DELAY_CTL(pg) ISL7998X_REG((pg), 0x04)
#define ISL7998X_REG_PX_DEC_ANCTL(pg) ISL7998X_REG((pg), 0x06)
#define ISL7998X_REG_PX_DEC_CROP_HI(pg) ISL7998X_REG((pg), 0x07)
#define ISL7998X_REG_PX_DEC_VDELAY_LO(pg) ISL7998X_REG((pg), 0x08)
#define ISL7998X_REG_PX_DEC_VACTIVE_LO(pg) ISL7998X_REG((pg), 0x09)
#define ISL7998X_REG_PX_DEC_HDELAY_LO(pg) ISL7998X_REG((pg), 0x0a)
#define ISL7998X_REG_PX_DEC_HACTIVE_LO(pg) ISL7998X_REG((pg), 0x0b)
#define ISL7998X_REG_PX_DEC_CNTRL1(pg) ISL7998X_REG((pg), 0x0c)
#define ISL7998X_REG_PX_DEC_CSC_CTL(pg) ISL7998X_REG((pg), 0x0d)
#define ISL7998X_REG_PX_DEC_BRIGHT(pg) ISL7998X_REG((pg), 0x10)
#define ISL7998X_REG_PX_DEC_CONTRAST(pg) ISL7998X_REG((pg), 0x11)
#define ISL7998X_REG_PX_DEC_SHARPNESS(pg) ISL7998X_REG((pg), 0x12)
#define ISL7998X_REG_PX_DEC_SAT_U(pg) ISL7998X_REG((pg), 0x13)
#define ISL7998X_REG_PX_DEC_SAT_V(pg) ISL7998X_REG((pg), 0x14)
#define ISL7998X_REG_PX_DEC_HUE(pg) ISL7998X_REG((pg), 0x15)
#define ISL7998X_REG_PX_DEC_VERT_PEAK(pg) ISL7998X_REG((pg), 0x17)
#define ISL7998X_REG_PX_DEC_CORING(pg) ISL7998X_REG((pg), 0x18)
#define ISL7998X_REG_PX_DEC_SDT(pg) ISL7998X_REG((pg), 0x1c)
#define ISL7998X_REG_PX_DEC_SDT_DET BIT(7)
#define ISL7998X_REG_PX_DEC_SDT_NOW GENMASK(6, 4)
#define ISL7998X_REG_PX_DEC_SDT_STANDARD GENMASK(2, 0)
#define ISL7998X_REG_PX_DEC_SDT_STANDARD_NTSC_M 0
#define ISL7998X_REG_PX_DEC_SDT_STANDARD_PAL 1
#define ISL7998X_REG_PX_DEC_SDT_STANDARD_SECAM 2
#define ISL7998X_REG_PX_DEC_SDT_STANDARD_NTSC_443 3
#define ISL7998X_REG_PX_DEC_SDT_STANDARD_PAL_M 4
#define ISL7998X_REG_PX_DEC_SDT_STANDARD_PAL_CN 5
#define ISL7998X_REG_PX_DEC_SDT_STANDARD_PAL_60 6
#define ISL7998X_REG_PX_DEC_SDT_STANDARD_UNKNOWN 7
#define ISL7998X_REG_PX_DEC_SDTR(pg) ISL7998X_REG((pg), 0x1d)
#define ISL7998X_REG_PX_DEC_SDTR_ATSTART BIT(7)
#define ISL7998X_REG_PX_DEC_CLMPG(pg) ISL7998X_REG((pg), 0x20)
#define ISL7998X_REG_PX_DEC_IAGC(pg) ISL7998X_REG((pg), 0x21)
#define ISL7998X_REG_PX_DEC_AGCGAIN(pg) ISL7998X_REG((pg), 0x22)
#define ISL7998X_REG_PX_DEC_PEAKWT(pg) ISL7998X_REG((pg), 0x23)
#define ISL7998X_REG_PX_DEC_CLMPL(pg) ISL7998X_REG((pg), 0x24)
#define ISL7998X_REG_PX_DEC_SYNCT(pg) ISL7998X_REG((pg), 0x25)
#define ISL7998X_REG_PX_DEC_MISSCNT(pg) ISL7998X_REG((pg), 0x26)
#define ISL7998X_REG_PX_DEC_PCLAMP(pg) ISL7998X_REG((pg), 0x27)
#define ISL7998X_REG_PX_DEC_VERT_CTL_1(pg) ISL7998X_REG((pg), 0x28)
#define ISL7998X_REG_PX_DEC_VERT_CTL_2(pg) ISL7998X_REG((pg), 0x29)
#define ISL7998X_REG_PX_DEC_CLR_KILL_LVL(pg) ISL7998X_REG((pg), 0x2a)
#define ISL7998X_REG_PX_DEC_COMB_FILTER_CTL(pg) ISL7998X_REG((pg), 0x2b)
#define ISL7998X_REG_PX_DEC_LUMA_DELAY(pg) ISL7998X_REG((pg), 0x2c)
#define ISL7998X_REG_PX_DEC_MISC1(pg) ISL7998X_REG((pg), 0x2d)
#define ISL7998X_REG_PX_DEC_MISC2(pg) ISL7998X_REG((pg), 0x2e)
#define ISL7998X_REG_PX_DEC_MISC3(pg) ISL7998X_REG((pg), 0x2f)
#define ISL7998X_REG_PX_DEC_MVSN(pg) ISL7998X_REG((pg), 0x30)
#define ISL7998X_REG_PX_DEC_CSTATUS2(pg) ISL7998X_REG((pg), 0x31)
#define ISL7998X_REG_PX_DEC_HFREF(pg) ISL7998X_REG((pg), 0x32)
#define ISL7998X_REG_PX_DEC_CLMD(pg) ISL7998X_REG((pg), 0x33)
#define ISL7998X_REG_PX_DEC_ID_DET_CTL(pg) ISL7998X_REG((pg), 0x34)
#define ISL7998X_REG_PX_DEC_CLCNTL(pg) ISL7998X_REG((pg), 0x35)
#define ISL7998X_REG_PX_DEC_DIFF_CLMP_CTL_1(pg) ISL7998X_REG((pg), 0x36)
#define ISL7998X_REG_PX_DEC_DIFF_CLMP_CTL_2(pg) ISL7998X_REG((pg), 0x37)
#define ISL7998X_REG_PX_DEC_DIFF_CLMP_CTL_3(pg) ISL7998X_REG((pg), 0x38)
#define ISL7998X_REG_PX_DEC_DIFF_CLMP_CTL_4(pg) ISL7998X_REG((pg), 0x39)
#define ISL7998X_REG_PX_DEC_SHORT_DET_CTL(pg) ISL7998X_REG((pg), 0x3a)
#define ISL7998X_REG_PX_DEC_SHORT_DET_CTL_1(pg) ISL7998X_REG((pg), 0x3b)
#define ISL7998X_REG_PX_DEC_AFE_TST_MUX_CTL(pg) ISL7998X_REG((pg), 0x3c)
#define ISL7998X_REG_PX_DEC_DATA_CONV(pg) ISL7998X_REG((pg), 0x3d)
#define ISL7998X_REG_PX_DEC_INTERNAL_TEST(pg) ISL7998X_REG((pg), 0x3f)
#define ISL7998X_REG_PX_DEC_H_DELAY_CTL(pg) ISL7998X_REG((pg), 0x43)
#define ISL7998X_REG_PX_DEC_H_DELAY_II_HI(pg) ISL7998X_REG((pg), 0x44)
#define ISL7998X_REG_PX_DEC_H_DELAY_II_LOW(pg) ISL7998X_REG((pg), 0x45)
#define ISL7998X_REG_PX_ACA_CTL_1(pg) ISL7998X_REG((pg), 0x80)
#define ISL7998X_REG_PX_ACA_GAIN_CTL(pg) ISL7998X_REG((pg), 0x81)
#define ISL7998X_REG_PX_ACA_Y_AVG_HI_LIMIT(pg) ISL7998X_REG((pg), 0x82)
#define ISL7998X_REG_PX_ACA_Y_AVG_LO_LIMIT(pg) ISL7998X_REG((pg), 0x83)
#define ISL7998X_REG_PX_ACA_Y_DET_THRESHOLD(pg) ISL7998X_REG((pg), 0x84)
#define ISL7998X_REG_PX_ACA_BLACK_LVL(pg) ISL7998X_REG((pg), 0x85)
#define ISL7998X_REG_PX_ACA_CENTER_LVL(pg) ISL7998X_REG((pg), 0x86)
#define ISL7998X_REG_PX_ACA_WHITE_LVL(pg) ISL7998X_REG((pg), 0x87)
#define ISL7998X_REG_PX_ACA_MEAN_OFF_LIMIT(pg) ISL7998X_REG((pg), 0x88)
#define ISL7998X_REG_PX_ACA_MEAN_OFF_UPGAIN(pg) ISL7998X_REG((pg), 0x89)
#define ISL7998X_REG_PX_ACA_MEAN_OFF_SLOPE(pg) ISL7998X_REG((pg), 0x8a)
#define ISL7998X_REG_PX_ACA_MEAN_OFF_DNGAIN(pg) ISL7998X_REG((pg), 0x8b)
#define ISL7998X_REG_PX_ACA_DELTA_CO_THRES(pg) ISL7998X_REG((pg), 0x8c)
#define ISL7998X_REG_PX_ACA_DELTA_SLOPE(pg) ISL7998X_REG((pg), 0x8d)
#define ISL7998X_REG_PX_ACA_LO_HI_AVG_THRES(pg) ISL7998X_REG((pg), 0x8e)
#define ISL7998X_REG_PX_ACA_LO_MAX_LVL_CTL(pg) ISL7998X_REG((pg), 0x8f)
#define ISL7998X_REG_PX_ACA_HI_MAX_LVL_CTL(pg) ISL7998X_REG((pg), 0x90)
#define ISL7998X_REG_PX_ACA_LO_UPGAIN_CTL(pg) ISL7998X_REG((pg), 0x91)
#define ISL7998X_REG_PX_ACA_LO_DNGAIN_CTL(pg) ISL7998X_REG((pg), 0x92)
#define ISL7998X_REG_PX_ACA_HI_UPGAIN_CTL(pg) ISL7998X_REG((pg), 0x93)
#define ISL7998X_REG_PX_ACA_HI_DNGAIN_CTL(pg) ISL7998X_REG((pg), 0x94)
#define ISL7998X_REG_PX_ACA_LOPASS_FLT_COEF(pg) ISL7998X_REG((pg), 0x95)
#define ISL7998X_REG_PX_ACA_PDF_INDEX(pg) ISL7998X_REG((pg), 0x96)
#define ISL7998X_REG_PX_ACA_HIST_WIN_H_STT(pg) ISL7998X_REG((pg), 0x97)
#define ISL7998X_REG_PX_ACA_HIST_WIN_H_SZ1(pg) ISL7998X_REG((pg), 0x98)
#define ISL7998X_REG_PX_ACA_HIST_WIN_H_SZ2(pg) ISL7998X_REG((pg), 0x99)
#define ISL7998X_REG_PX_ACA_HIST_WIN_V_STT(pg) ISL7998X_REG((pg), 0x9a)
#define ISL7998X_REG_PX_ACA_HIST_WIN_V_SZ1(pg) ISL7998X_REG((pg), 0x9b)
#define ISL7998X_REG_PX_ACA_HIST_WIN_V_SZ2(pg) ISL7998X_REG((pg), 0x9c)
#define ISL7998X_REG_PX_ACA_Y_AVG(pg) ISL7998X_REG((pg), 0xa0)
#define ISL7998X_REG_PX_ACA_Y_AVG_LIM(pg) ISL7998X_REG((pg), 0xa1)
#define ISL7998X_REG_PX_ACA_LO_AVG(pg) ISL7998X_REG((pg), 0xa2)
#define ISL7998X_REG_PX_ACA_HI_AVG(pg) ISL7998X_REG((pg), 0xa3)
#define ISL7998X_REG_PX_ACA_Y_MAX(pg) ISL7998X_REG((pg), 0xa4)
#define ISL7998X_REG_PX_ACA_Y_MIN(pg) ISL7998X_REG((pg), 0xa5)
#define ISL7998X_REG_PX_ACA_MOFFSET(pg) ISL7998X_REG((pg), 0xa6)
#define ISL7998X_REG_PX_ACA_LO_GAIN(pg) ISL7998X_REG((pg), 0xa7)
#define ISL7998X_REG_PX_ACA_HI_GAIN(pg) ISL7998X_REG((pg), 0xa8)
#define ISL7998X_REG_PX_ACA_LL_SLOPE(pg) ISL7998X_REG((pg), 0xa9)
#define ISL7998X_REG_PX_ACA_LH_SLOPE(pg) ISL7998X_REG((pg), 0xaa)
#define ISL7998X_REG_PX_ACA_HL_SLOPE(pg) ISL7998X_REG((pg), 0xab)
#define ISL7998X_REG_PX_ACA_HH_SLOPE(pg) ISL7998X_REG((pg), 0xac)
#define ISL7998X_REG_PX_ACA_X_LOW(pg) ISL7998X_REG((pg), 0xad)
#define ISL7998X_REG_PX_ACA_X_MEAN(pg) ISL7998X_REG((pg), 0xae)
#define ISL7998X_REG_PX_ACA_X_HIGH(pg) ISL7998X_REG((pg), 0xaf)
#define ISL7998X_REG_PX_ACA_Y_LOW(pg) ISL7998X_REG((pg), 0xb0)
#define ISL7998X_REG_PX_ACA_Y_MEAN(pg) ISL7998X_REG((pg), 0xb1)
#define ISL7998X_REG_PX_ACA_Y_HIGH(pg) ISL7998X_REG((pg), 0xb2)
#define ISL7998X_REG_PX_ACA_CTL_2(pg) ISL7998X_REG((pg), 0xb3)
#define ISL7998X_REG_PX_ACA_CTL_3(pg) ISL7998X_REG((pg), 0xb4)
#define ISL7998X_REG_PX_ACA_CTL_4(pg) ISL7998X_REG((pg), 0xb5)
#define ISL7998X_REG_PX_ACA_FLEX_WIN_HIST(pg) ISL7998X_REG((pg), 0xc0)
#define ISL7998X_REG_PX_ACA_FLEX_WIN_X_TL_H(pg) ISL7998X_REG((pg), 0xc1)
#define ISL7998X_REG_PX_ACA_FLEX_WIN_X_TL_L(pg) ISL7998X_REG((pg), 0xc2)
#define ISL7998X_REG_PX_ACA_FLEX_WIN_Y_TL_H(pg) ISL7998X_REG((pg), 0xc3)
#define ISL7998X_REG_PX_ACA_FLEX_WIN_Y_TL_L(pg) ISL7998X_REG((pg), 0xc4)
#define ISL7998X_REG_PX_ACA_FLEX_WIN_X_TR_H(pg) ISL7998X_REG((pg), 0xc5)
#define ISL7998X_REG_PX_ACA_FLEX_WIN_X_TR_L(pg) ISL7998X_REG((pg), 0xc6)
#define ISL7998X_REG_PX_ACA_FLEX_WIN_Y_TR_H(pg) ISL7998X_REG((pg), 0xc7)
#define ISL7998X_REG_PX_ACA_FLEX_WIN_Y_TR_L(pg) ISL7998X_REG((pg), 0xc8)
#define ISL7998X_REG_PX_ACA_FLEX_WIN_X_BL_H(pg) ISL7998X_REG((pg), 0xc9)
#define ISL7998X_REG_PX_ACA_FLEX_WIN_X_BL_L(pg) ISL7998X_REG((pg), 0xca)
#define ISL7998X_REG_PX_ACA_FLEX_WIN_Y_BL_H(pg) ISL7998X_REG((pg), 0xcb)
#define ISL7998X_REG_PX_ACA_FLEX_WIN_Y_BL_L(pg) ISL7998X_REG((pg), 0xcc)
#define ISL7998X_REG_PX_ACA_FLEX_WIN_X_BR_H(pg) ISL7998X_REG((pg), 0xcd)
#define ISL7998X_REG_PX_ACA_FLEX_WIN_X_BR_L(pg) ISL7998X_REG((pg), 0xce)
#define ISL7998X_REG_PX_ACA_FLEX_WIN_Y_BR_H(pg) ISL7998X_REG((pg), 0xcf)
#define ISL7998X_REG_PX_ACA_FLEX_WIN_Y_BR_L(pg) ISL7998X_REG((pg), 0xd0)
#define ISL7998X_REG_PX_ACA_FLEX_WIN_X_LM_H(pg) ISL7998X_REG((pg), 0xd1)
#define ISL7998X_REG_PX_ACA_FLEX_WIN_X_LM_L(pg) ISL7998X_REG((pg), 0xd2)
#define ISL7998X_REG_PX_ACA_FLEX_WIN_Y_LM_H(pg) ISL7998X_REG((pg), 0xd3)
#define ISL7998X_REG_PX_ACA_FLEX_WIN_Y_LM_L(pg) ISL7998X_REG((pg), 0xd4)
#define ISL7998X_REG_PX_ACA_FLEX_WIN_X_TM_H(pg) ISL7998X_REG((pg), 0xd5)
#define ISL7998X_REG_PX_ACA_FLEX_WIN_X_TM_L(pg) ISL7998X_REG((pg), 0xd6)
#define ISL7998X_REG_PX_ACA_FLEX_WIN_Y_TM_H(pg) ISL7998X_REG((pg), 0xd7)
#define ISL7998X_REG_PX_ACA_FLEX_WIN_Y_TM_L(pg) ISL7998X_REG((pg), 0xd8)
#define ISL7998X_REG_PX_ACA_FLEX_WIN_X_BM_H(pg) ISL7998X_REG((pg), 0xd9)
#define ISL7998X_REG_PX_ACA_FLEX_WIN_X_BM_L(pg) ISL7998X_REG((pg), 0xda)
#define ISL7998X_REG_PX_ACA_FLEX_WIN_Y_BM_H(pg) ISL7998X_REG((pg), 0xdb)
#define ISL7998X_REG_PX_ACA_FLEX_WIN_Y_BM_L(pg) ISL7998X_REG((pg), 0xdc)
#define ISL7998X_REG_PX_ACA_FLEX_WIN_X_RM_H(pg) ISL7998X_REG((pg), 0xdd)
#define ISL7998X_REG_PX_ACA_FLEX_WIN_X_RM_L(pg) ISL7998X_REG((pg), 0xde)
#define ISL7998X_REG_PX_ACA_FLEX_WIN_Y_RM_H(pg) ISL7998X_REG((pg), 0xdf)
#define ISL7998X_REG_PX_ACA_FLEX_WIN_Y_RM_L(pg) ISL7998X_REG((pg), 0xe0)
#define ISL7998X_REG_PX_ACA_HIST_DATA_LO(pg) ISL7998X_REG((pg), 0xe1)
#define ISL7998X_REG_PX_ACA_HIST_DATA_MID(pg) ISL7998X_REG((pg), 0xe2)
#define ISL7998X_REG_PX_ACA_HIST_DATA_HI(pg) ISL7998X_REG((pg), 0xe3)
#define ISL7998X_REG_PX_ACA_FLEX_WIN_Y_CLR(pg) ISL7998X_REG((pg), 0xe4)
#define ISL7998X_REG_PX_ACA_FLEX_WIN_CB_CLR(pg) ISL7998X_REG((pg), 0xe5)
#define ISL7998X_REG_PX_ACA_FLEX_WIN_CR_CLR(pg) ISL7998X_REG((pg), 0xe6)
#define ISL7998X_REG_PX_ACA_XFER_HIST_HOST(pg) ISL7998X_REG((pg), 0xe7)
#define ISL7998X_REG_P5_LI_ENGINE_CTL ISL7998X_REG(5, 0x00)
#define ISL7998X_REG_P5_LI_ENGINE_LINE_CTL ISL7998X_REG(5, 0x01)
#define ISL7998X_REG_P5_LI_ENGINE_PIC_WIDTH ISL7998X_REG(5, 0x02)
#define ISL7998X_REG_P5_LI_ENGINE_SYNC_CTL ISL7998X_REG(5, 0x03)
#define ISL7998X_REG_P5_LI_ENGINE_VC_ASSIGNMENT ISL7998X_REG(5, 0x04)
#define ISL7998X_REG_P5_LI_ENGINE_TYPE_CTL ISL7998X_REG(5, 0x05)
#define ISL7998X_REG_P5_LI_ENGINE_FIFO_CTL ISL7998X_REG(5, 0x06)
#define ISL7998X_REG_P5_MIPI_READ_START_CTL ISL7998X_REG(5, 0x07)
#define ISL7998X_REG_P5_PSEUDO_FRM_FIELD_CTL ISL7998X_REG(5, 0x08)
#define ISL7998X_REG_P5_ONE_FIELD_MODE_CTL ISL7998X_REG(5, 0x09)
#define ISL7998X_REG_P5_MIPI_INT_HW_TST_CTR ISL7998X_REG(5, 0x0a)
#define ISL7998X_REG_P5_TP_GEN_BAR_PATTERN ISL7998X_REG(5, 0x0b)
#define ISL7998X_REG_P5_MIPI_PCNT_PSFRM ISL7998X_REG(5, 0x0c)
#define ISL7998X_REG_P5_LI_ENGINE_TP_GEN_CTL ISL7998X_REG(5, 0x0d)
#define ISL7998X_REG_P5_MIPI_VBLANK_PSFRM ISL7998X_REG(5, 0x0e)
#define ISL7998X_REG_P5_LI_ENGINE_CTL_2 ISL7998X_REG(5, 0x0f)
#define ISL7998X_REG_P5_MIPI_WCNT_1 ISL7998X_REG(5, 0x10)
#define ISL7998X_REG_P5_MIPI_WCNT_2 ISL7998X_REG(5, 0x11)
#define ISL7998X_REG_P5_MIPI_DPHY_TIMING_CTL_1 ISL7998X_REG(5, 0x12)
#define ISL7998X_REG_P5_MIPI_DPHY_TIMING_CTL_2 ISL7998X_REG(5, 0x13)
#define ISL7998X_REG_P5_MIPI_DPHY_TIMING_CTL_3 ISL7998X_REG(5, 0x14)
#define ISL7998X_REG_P5_MIPI_DPHY_TIMING_CTL_4 ISL7998X_REG(5, 0x15)
#define ISL7998X_REG_P5_MIPI_DPHY_TIMING_CTL_5 ISL7998X_REG(5, 0x16)
#define ISL7998X_REG_P5_MIPI_DPHY_TIMING_CTL_6 ISL7998X_REG(5, 0x17)
#define ISL7998X_REG_P5_MIPI_DPHY_PARAMS_1 ISL7998X_REG(5, 0x18)
#define ISL7998X_REG_P5_MIPI_DPHY_SOT_PERIOD ISL7998X_REG(5, 0x19)
#define ISL7998X_REG_P5_MIPI_DPHY_EOT_PERIOD ISL7998X_REG(5, 0x1a)
#define ISL7998X_REG_P5_MIPI_DPHY_PARAMS_2 ISL7998X_REG(5, 0x1b)
#define ISL7998X_REG_P5_MIPI_DPHY_TIMING_CTL_7 ISL7998X_REG(5, 0x1c)
#define ISL7998X_REG_P5_MIPI_DPHY_TIMING_CTL_8 ISL7998X_REG(5, 0x1d)
#define ISL7998X_REG_P5_MIPI_DPHY_TIMING_CTL_9 ISL7998X_REG(5, 0x1e)
#define ISL7998X_REG_P5_MIPI_DPHY_TIMING_CTL_10 ISL7998X_REG(5, 0x1f)
#define ISL7998X_REG_P5_TP_GEN_MIPI ISL7998X_REG(5, 0x20)
#define ISL7998X_REG_P5_ESC_MODE_TIME_CTL ISL7998X_REG(5, 0x21)
#define ISL7998X_REG_P5_AUTO_TEST_ERR_DET ISL7998X_REG(5, 0x22)
#define ISL7998X_REG_P5_MIPI_TIMING ISL7998X_REG(5, 0x23)
#define ISL7998X_REG_P5_PIC_HEIGHT_HIGH ISL7998X_REG(5, 0x24)
#define ISL7998X_REG_P5_PIC_HEIGHT_LOW ISL7998X_REG(5, 0x25)
#define ISL7998X_REG_P5_MIPI_SP_HS_TRL_CTL ISL7998X_REG(5, 0x26)
#define ISL7998X_REG_P5_FIFO_THRSH_CNT_1 ISL7998X_REG(5, 0x28)
#define ISL7998X_REG_P5_FIFO_THRSH_CNT_2 ISL7998X_REG(5, 0x29)
#define ISL7998X_REG_P5_TP_GEN_RND_SYNC_CTL_1 ISL7998X_REG(5, 0x2a)
#define ISL7998X_REG_P5_TP_GEN_RND_SYNC_CTL_2 ISL7998X_REG(5, 0x2b)
#define ISL7998X_REG_P5_PSF_FIELD_END_CTL_1 ISL7998X_REG(5, 0x2c)
#define ISL7998X_REG_P5_PSF_FIELD_END_CTL_2 ISL7998X_REG(5, 0x2d)
#define ISL7998X_REG_P5_PSF_FIELD_END_CTL_3 ISL7998X_REG(5, 0x2e)
#define ISL7998X_REG_P5_PSF_FIELD_END_CTL_4 ISL7998X_REG(5, 0x2f)
#define ISL7998X_REG_P5_MIPI_ANA_DATA_CTL_1 ISL7998X_REG(5, 0x30)
#define ISL7998X_REG_P5_MIPI_ANA_DATA_CTL_2 ISL7998X_REG(5, 0x31)
#define ISL7998X_REG_P5_MIPI_ANA_CLK_CTL ISL7998X_REG(5, 0x32)
#define ISL7998X_REG_P5_PLL_ANA_STATUS ISL7998X_REG(5, 0x33)
#define ISL7998X_REG_P5_PLL_ANA_MISC_CTL ISL7998X_REG(5, 0x34)
#define ISL7998X_REG_P5_MIPI_ANA ISL7998X_REG(5, 0x35)
#define ISL7998X_REG_P5_PLL_ANA ISL7998X_REG(5, 0x36)
#define ISL7998X_REG_P5_TOTAL_PF_LINE_CNT_1 ISL7998X_REG(5, 0x38)
#define ISL7998X_REG_P5_TOTAL_PF_LINE_CNT_2 ISL7998X_REG(5, 0x39)
#define ISL7998X_REG_P5_H_LINE_CNT_1 ISL7998X_REG(5, 0x3a)
#define ISL7998X_REG_P5_H_LINE_CNT_2 ISL7998X_REG(5, 0x3b)
#define ISL7998X_REG_P5_HIST_LINE_CNT_1 ISL7998X_REG(5, 0x3c)
#define ISL7998X_REG_P5_HIST_LINE_CNT_2 ISL7998X_REG(5, 0x3d)
static const struct reg_sequence isl7998x_init_seq_1[] = {
{ ISL7998X_REG_P0_SHORT_DIAG_IRQ_EN, 0xff },
{ ISL7998X_REG_PX_DEC_SDT(0x1), 0x00 },
{ ISL7998X_REG_PX_DEC_SHORT_DET_CTL_1(0x1), 0x03 },
{ ISL7998X_REG_PX_DEC_SDT(0x2), 0x00 },
{ ISL7998X_REG_PX_DEC_SHORT_DET_CTL_1(0x2), 0x03 },
{ ISL7998X_REG_PX_DEC_SDT(0x3), 0x00 },
{ ISL7998X_REG_PX_DEC_SHORT_DET_CTL_1(0x3), 0x03 },
{ ISL7998X_REG_PX_DEC_SDT(0x4), 0x00 },
{ ISL7998X_REG_PX_DEC_SHORT_DET_CTL_1(0x4), 0x03 },
{ ISL7998X_REG_P5_LI_ENGINE_CTL, 0x00 },
{ ISL7998X_REG_P0_SW_RESET_CTL, 0x1f, 10 },
{ ISL7998X_REG_P0_IO_BUFFER_CTL, 0x00 },
{ ISL7998X_REG_P0_MPP2_SYNC_CTL, 0xc9 },
{ ISL7998X_REG_P0_IRQ_SYNC_CTL, 0xc9 },
{ ISL7998X_REG_P0_CHAN_1_IRQ, 0x03 },
{ ISL7998X_REG_P0_CHAN_2_IRQ, 0x00 },
{ ISL7998X_REG_P0_CHAN_3_IRQ, 0x00 },
{ ISL7998X_REG_P0_CHAN_4_IRQ, 0x00 },
{ ISL7998X_REG_P5_LI_ENGINE_CTL, 0x02 },
{ ISL7998X_REG_P5_LI_ENGINE_LINE_CTL, 0x85 },
{ ISL7998X_REG_P5_LI_ENGINE_PIC_WIDTH, 0xa0 },
{ ISL7998X_REG_P5_LI_ENGINE_SYNC_CTL, 0x18 },
{ ISL7998X_REG_P5_LI_ENGINE_TYPE_CTL, 0x40 },
{ ISL7998X_REG_P5_LI_ENGINE_FIFO_CTL, 0x40 },
{ ISL7998X_REG_P5_MIPI_WCNT_1, 0x05 },
{ ISL7998X_REG_P5_MIPI_WCNT_2, 0xa0 },
{ ISL7998X_REG_P5_TP_GEN_MIPI, 0x00 },
{ ISL7998X_REG_P5_ESC_MODE_TIME_CTL, 0x0c },
{ ISL7998X_REG_P5_MIPI_SP_HS_TRL_CTL, 0x00 },
{ ISL7998X_REG_P5_TP_GEN_RND_SYNC_CTL_1, 0x00 },
{ ISL7998X_REG_P5_TP_GEN_RND_SYNC_CTL_2, 0x19 },
{ ISL7998X_REG_P5_PSF_FIELD_END_CTL_1, 0x18 },
{ ISL7998X_REG_P5_PSF_FIELD_END_CTL_2, 0xf1 },
{ ISL7998X_REG_P5_PSF_FIELD_END_CTL_3, 0x00 },
{ ISL7998X_REG_P5_PSF_FIELD_END_CTL_4, 0xf1 },
{ ISL7998X_REG_P5_MIPI_ANA_DATA_CTL_1, 0x00 },
{ ISL7998X_REG_P5_MIPI_ANA_DATA_CTL_2, 0x00 },
{ ISL7998X_REG_P5_MIPI_ANA_CLK_CTL, 0x00 },
{ ISL7998X_REG_P5_PLL_ANA_STATUS, 0xc0 },
{ ISL7998X_REG_P5_PLL_ANA_MISC_CTL, 0x18 },
{ ISL7998X_REG_P5_PLL_ANA, 0x00 },
{ ISL7998X_REG_P0_SW_RESET_CTL, 0x10, 10 },
/* Page 0xf means write to all of pages 1,2,3,4 */
{ ISL7998X_REG_PX_DEC_VDELAY_LO(0xf), 0x14 },
{ ISL7998X_REG_PX_DEC_MISC3(0xf), 0xe6 },
{ ISL7998X_REG_PX_DEC_CLMD(0xf), 0x85 },
{ ISL7998X_REG_PX_DEC_H_DELAY_II_LOW(0xf), 0x11 },
{ ISL7998X_REG_PX_ACA_XFER_HIST_HOST(0xf), 0x00 },
{ ISL7998X_REG_P0_CLK_CTL_1, 0x1f },
{ ISL7998X_REG_P0_CLK_CTL_2, 0x43 },
{ ISL7998X_REG_P0_CLK_CTL_3, 0x4f },
};
static const struct reg_sequence isl7998x_init_seq_2[] = {
{ ISL7998X_REG_P5_LI_ENGINE_SYNC_CTL, 0x10 },
{ ISL7998X_REG_P5_LI_ENGINE_VC_ASSIGNMENT, 0xe4 },
{ ISL7998X_REG_P5_LI_ENGINE_TYPE_CTL, 0x00 },
{ ISL7998X_REG_P5_LI_ENGINE_FIFO_CTL, 0x60 },
{ ISL7998X_REG_P5_MIPI_READ_START_CTL, 0x2b },
{ ISL7998X_REG_P5_PSEUDO_FRM_FIELD_CTL, 0x02 },
{ ISL7998X_REG_P5_ONE_FIELD_MODE_CTL, 0x00 },
{ ISL7998X_REG_P5_MIPI_INT_HW_TST_CTR, 0x62 },
{ ISL7998X_REG_P5_TP_GEN_BAR_PATTERN, 0x02 },
{ ISL7998X_REG_P5_MIPI_PCNT_PSFRM, 0x36 },
{ ISL7998X_REG_P5_LI_ENGINE_TP_GEN_CTL, 0x00 },
{ ISL7998X_REG_P5_MIPI_VBLANK_PSFRM, 0x6c },
{ ISL7998X_REG_P5_LI_ENGINE_CTL_2, 0x00 },
{ ISL7998X_REG_P5_MIPI_WCNT_1, 0x05 },
{ ISL7998X_REG_P5_MIPI_WCNT_2, 0xa0 },
{ ISL7998X_REG_P5_MIPI_DPHY_TIMING_CTL_1, 0x77 },
{ ISL7998X_REG_P5_MIPI_DPHY_TIMING_CTL_2, 0x17 },
{ ISL7998X_REG_P5_MIPI_DPHY_TIMING_CTL_3, 0x08 },
{ ISL7998X_REG_P5_MIPI_DPHY_TIMING_CTL_4, 0x38 },
{ ISL7998X_REG_P5_MIPI_DPHY_TIMING_CTL_5, 0x14 },
{ ISL7998X_REG_P5_MIPI_DPHY_TIMING_CTL_6, 0xf6 },
{ ISL7998X_REG_P5_MIPI_DPHY_PARAMS_1, 0x00 },
{ ISL7998X_REG_P5_MIPI_DPHY_SOT_PERIOD, 0x17 },
{ ISL7998X_REG_P5_MIPI_DPHY_EOT_PERIOD, 0x0a },
{ ISL7998X_REG_P5_MIPI_DPHY_PARAMS_2, 0x71 },
{ ISL7998X_REG_P5_MIPI_DPHY_TIMING_CTL_7, 0x7a },
{ ISL7998X_REG_P5_MIPI_DPHY_TIMING_CTL_8, 0x0f },
{ ISL7998X_REG_P5_MIPI_DPHY_TIMING_CTL_9, 0x8c },
{ ISL7998X_REG_P5_MIPI_SP_HS_TRL_CTL, 0x08 },
{ ISL7998X_REG_P5_FIFO_THRSH_CNT_1, 0x01 },
{ ISL7998X_REG_P5_FIFO_THRSH_CNT_2, 0x0e },
{ ISL7998X_REG_P5_TP_GEN_RND_SYNC_CTL_1, 0x00 },
{ ISL7998X_REG_P5_TP_GEN_RND_SYNC_CTL_2, 0x00 },
{ ISL7998X_REG_P5_TOTAL_PF_LINE_CNT_1, 0x03 },
{ ISL7998X_REG_P5_TOTAL_PF_LINE_CNT_2, 0xc0 },
{ ISL7998X_REG_P5_H_LINE_CNT_1, 0x06 },
{ ISL7998X_REG_P5_H_LINE_CNT_2, 0xb3 },
{ ISL7998X_REG_P5_HIST_LINE_CNT_1, 0x00 },
{ ISL7998X_REG_P5_HIST_LINE_CNT_2, 0xf1 },
{ ISL7998X_REG_P5_LI_ENGINE_FIFO_CTL, 0x00 },
{ ISL7998X_REG_P5_MIPI_ANA, 0x00 },
/*
* Wait a bit after reset so that the chip can capture a frame
* and update internal line counters.
*/
{ ISL7998X_REG_P0_SW_RESET_CTL, 0x00, 50 },
};
enum isl7998x_pads {
ISL7998X_PAD_OUT,
ISL7998X_PAD_VIN1,
ISL7998X_PAD_VIN2,
ISL7998X_PAD_VIN3,
ISL7998X_PAD_VIN4,
ISL7998X_NUM_PADS
};
struct isl7998x_datafmt {
u32 code;
enum v4l2_colorspace colorspace;
};
static const struct isl7998x_datafmt isl7998x_colour_fmts[] = {
{ MEDIA_BUS_FMT_UYVY8_2X8, V4L2_COLORSPACE_SRGB },
};
/* Menu items for LINK_FREQ V4L2 control */
static const s64 link_freq_menu_items[] = {
/* 1 channel, 1 lane or 2 channels, 2 lanes */
108000000,
/* 2 channels, 1 lane or 4 channels, 2 lanes */
216000000,
/* 4 channels, 1 lane */
432000000,
};
/* Menu items for TEST_PATTERN V4L2 control */
static const char * const isl7998x_test_pattern_menu[] = {
"Disabled",
"Enabled",
};
static const char * const isl7998x_test_pattern_bars[] = {
"bbbbwb", "bbbwwb", "bbwbwb", "bbwwwb",
};
static const char * const isl7998x_test_pattern_colors[] = {
"Yellow", "Blue", "Green", "Pink",
};
struct isl7998x_mode {
unsigned int width;
unsigned int height;
enum v4l2_field field;
};
static const struct isl7998x_mode supported_modes[] = {
{
.width = 720,
.height = 576,
.field = V4L2_FIELD_SEQ_TB,
},
{
.width = 720,
.height = 480,
.field = V4L2_FIELD_SEQ_BT,
},
};
static const struct isl7998x_video_std {
const v4l2_std_id norm;
unsigned int id;
const struct isl7998x_mode *mode;
} isl7998x_std_res[] = {
{ V4L2_STD_NTSC_443,
ISL7998X_REG_PX_DEC_SDT_STANDARD_NTSC_443,
&supported_modes[1] },
{ V4L2_STD_PAL_M,
ISL7998X_REG_PX_DEC_SDT_STANDARD_PAL_M,
&supported_modes[1] },
{ V4L2_STD_PAL_Nc,
ISL7998X_REG_PX_DEC_SDT_STANDARD_PAL_CN,
&supported_modes[0] },
{ V4L2_STD_PAL_N,
ISL7998X_REG_PX_DEC_SDT_STANDARD_PAL,
&supported_modes[0] },
{ V4L2_STD_PAL_60,
ISL7998X_REG_PX_DEC_SDT_STANDARD_PAL_60,
&supported_modes[1] },
{ V4L2_STD_NTSC,
ISL7998X_REG_PX_DEC_SDT_STANDARD_NTSC_M,
&supported_modes[1] },
{ V4L2_STD_PAL,
ISL7998X_REG_PX_DEC_SDT_STANDARD_PAL,
&supported_modes[0] },
{ V4L2_STD_SECAM,
ISL7998X_REG_PX_DEC_SDT_STANDARD_SECAM,
&supported_modes[0] },
{ V4L2_STD_UNKNOWN,
ISL7998X_REG_PX_DEC_SDT_STANDARD_UNKNOWN,
&supported_modes[1] },
};
struct isl7998x {
struct v4l2_subdev subdev;
struct regmap *regmap;
struct gpio_desc *pd_gpio;
struct gpio_desc *rstb_gpio;
unsigned int nr_mipi_lanes;
u32 nr_inputs;
const struct isl7998x_datafmt *fmt;
v4l2_std_id norm;
struct media_pad pads[ISL7998X_NUM_PADS];
int enabled;
/* protect fmt, norm, enabled */
struct mutex lock;
struct v4l2_ctrl_handler ctrl_handler;
/* protect ctrl_handler */
struct mutex ctrl_mutex;
/* V4L2 Controls */
struct v4l2_ctrl *link_freq;
u8 test_pattern;
u8 test_pattern_bars;
u8 test_pattern_chans;
u8 test_pattern_color;
};
static struct isl7998x *sd_to_isl7998x(struct v4l2_subdev *sd)
{
return container_of(sd, struct isl7998x, subdev);
}
static struct isl7998x *i2c_to_isl7998x(const struct i2c_client *client)
{
return sd_to_isl7998x(i2c_get_clientdata(client));
}
static unsigned int isl7998x_norm_to_val(v4l2_std_id norm)
{
unsigned int i;
for (i = 0; i < ARRAY_SIZE(isl7998x_std_res); i++)
if (isl7998x_std_res[i].norm & norm)
break;
if (i == ARRAY_SIZE(isl7998x_std_res))
return ISL7998X_REG_PX_DEC_SDT_STANDARD_UNKNOWN;
return isl7998x_std_res[i].id;
}
static const struct isl7998x_mode *isl7998x_norm_to_mode(v4l2_std_id norm)
{
unsigned int i;
for (i = 0; i < ARRAY_SIZE(isl7998x_std_res); i++)
if (isl7998x_std_res[i].norm & norm)
break;
/* Use NTSC default resolution during standard detection */
if (i == ARRAY_SIZE(isl7998x_std_res))
return &supported_modes[1];
return isl7998x_std_res[i].mode;
}
static int isl7998x_get_nr_inputs(struct device_node *of_node)
{
struct device_node *port;
unsigned int inputs = 0;
unsigned int i;
if (of_graph_get_endpoint_count(of_node) > ISL7998X_NUM_PADS)
return -EINVAL;
/*
* The driver does not provide means to remap the input ports. It
* always configures input ports to start from VID1. Ensure that the
* device tree is correct.
*/
for (i = ISL7998X_PAD_VIN1; i <= ISL7998X_PAD_VIN4; i++) {
port = of_graph_get_port_by_id(of_node, i);
if (!port)
continue;
inputs |= BIT(i);
of_node_put(port);
}
switch (inputs) {
case BIT(ISL7998X_PAD_VIN1):
return 1;
case BIT(ISL7998X_PAD_VIN1) | BIT(ISL7998X_PAD_VIN2):
return 2;
case BIT(ISL7998X_PAD_VIN1) | BIT(ISL7998X_PAD_VIN2) |
BIT(ISL7998X_PAD_VIN3) | BIT(ISL7998X_PAD_VIN4):
return 4;
default:
return -EINVAL;
}
}
static int isl7998x_wait_power_on(struct isl7998x *isl7998x)
{
struct device *dev = isl7998x->subdev.dev;
u32 chip_id;
int ret;
int err;
ret = read_poll_timeout(regmap_read, err, !err, 2000, 20000, false,
isl7998x->regmap,
ISL7998X_REG_P0_PRODUCT_ID_CODE, &chip_id);
if (ret) {
dev_err(dev, "timeout while waiting for ISL7998X\n");
return ret;
}
dev_dbg(dev, "Found ISL799%x\n", chip_id);
return ret;
}
static int isl7998x_set_standard(struct isl7998x *isl7998x, v4l2_std_id norm)
{
const struct isl7998x_mode *mode = isl7998x_norm_to_mode(norm);
unsigned int val = isl7998x_norm_to_val(norm);
unsigned int width = mode->width;
unsigned int i;
int ret;
for (i = 0; i < ISL7998X_INPUTS; i++) {
ret = regmap_write_bits(isl7998x->regmap,
ISL7998X_REG_PX_DEC_SDT(i + 1),
ISL7998X_REG_PX_DEC_SDT_STANDARD,
val);
if (ret)
return ret;
}
ret = regmap_write(isl7998x->regmap,
ISL7998X_REG_P5_LI_ENGINE_LINE_CTL,
0x20 | ((width >> 7) & 0x1f));
if (ret)
return ret;
ret = regmap_write(isl7998x->regmap,
ISL7998X_REG_P5_LI_ENGINE_PIC_WIDTH,
(width << 1) & 0xff);
if (ret)
return ret;
return 0;
}
static int isl7998x_init(struct isl7998x *isl7998x)
{
const unsigned int lanes = isl7998x->nr_mipi_lanes;
const u32 isl7998x_video_in_chan_map[] = { 0x00, 0x11, 0x02, 0x02 };
const struct reg_sequence isl7998x_init_seq_custom[] = {
{ ISL7998X_REG_P0_VIDEO_IN_CHAN_CTL,
isl7998x_video_in_chan_map[isl7998x->nr_inputs - 1] },
{ ISL7998X_REG_P0_CLK_CTL_4,
(lanes == 1) ? 0x40 : 0x41 },
{ ISL7998X_REG_P5_LI_ENGINE_CTL,
(lanes == 1) ? 0x01 : 0x02 },
};
struct device *dev = isl7998x->subdev.dev;
struct regmap *regmap = isl7998x->regmap;
int ret;
dev_dbg(dev, "configuring %d lanes for %d inputs (norm %s)\n",
isl7998x->nr_mipi_lanes, isl7998x->nr_inputs,
v4l2_norm_to_name(isl7998x->norm));
ret = regmap_register_patch(regmap, isl7998x_init_seq_1,
ARRAY_SIZE(isl7998x_init_seq_1));
if (ret)
return ret;
mutex_lock(&isl7998x->lock);
ret = isl7998x_set_standard(isl7998x, isl7998x->norm);
mutex_unlock(&isl7998x->lock);
if (ret)
return ret;
ret = regmap_register_patch(regmap, isl7998x_init_seq_custom,
ARRAY_SIZE(isl7998x_init_seq_custom));
if (ret)
return ret;
return regmap_register_patch(regmap, isl7998x_init_seq_2,
ARRAY_SIZE(isl7998x_init_seq_2));
}
static int isl7998x_set_test_pattern(struct isl7998x *isl7998x)
{
const struct reg_sequence isl7998x_init_seq_tpg_off[] = {
{ ISL7998X_REG_P5_LI_ENGINE_TP_GEN_CTL, 0 },
{ ISL7998X_REG_P5_LI_ENGINE_CTL_2, 0 }
};
const struct reg_sequence isl7998x_init_seq_tpg_on[] = {
{ ISL7998X_REG_P5_TP_GEN_BAR_PATTERN,
isl7998x->test_pattern_bars << 6 },
{ ISL7998X_REG_P5_LI_ENGINE_CTL_2,
isl7998x->norm & V4L2_STD_PAL ? BIT(2) : 0 },
{ ISL7998X_REG_P5_LI_ENGINE_TP_GEN_CTL,
(isl7998x->test_pattern_chans << 4) |
(isl7998x->test_pattern_color << 2) }
};
struct device *dev = isl7998x->subdev.dev;
struct regmap *regmap = isl7998x->regmap;
int ret;
if (pm_runtime_get_if_in_use(dev) <= 0)
return 0;
if (isl7998x->test_pattern != 0) {
dev_dbg(dev, "enabling test pattern: channels 0x%x, %s, %s\n",
isl7998x->test_pattern_chans,
isl7998x_test_pattern_bars[isl7998x->test_pattern_bars],
isl7998x_test_pattern_colors[isl7998x->test_pattern_color]);
ret = regmap_register_patch(regmap, isl7998x_init_seq_tpg_on,
ARRAY_SIZE(isl7998x_init_seq_tpg_on));
} else {
ret = regmap_register_patch(regmap, isl7998x_init_seq_tpg_off,
ARRAY_SIZE(isl7998x_init_seq_tpg_off));
}
pm_runtime_put(dev);
return ret;
}
#ifdef CONFIG_VIDEO_ADV_DEBUG
static int isl7998x_g_register(struct v4l2_subdev *sd,
struct v4l2_dbg_register *reg)
{
struct isl7998x *isl7998x = sd_to_isl7998x(sd);
int ret;
u32 val;
ret = regmap_read(isl7998x->regmap, reg->reg, &val);
if (ret)
return ret;
reg->size = 1;
reg->val = val;
return 0;
}
static int isl7998x_s_register(struct v4l2_subdev *sd,
const struct v4l2_dbg_register *reg)
{
struct isl7998x *isl7998x = sd_to_isl7998x(sd);
return regmap_write(isl7998x->regmap, reg->reg, reg->val);
}
#endif
static int isl7998x_g_std(struct v4l2_subdev *sd, v4l2_std_id *norm)
{
struct isl7998x *isl7998x = sd_to_isl7998x(sd);
mutex_lock(&isl7998x->lock);
*norm = isl7998x->norm;
mutex_unlock(&isl7998x->lock);
return 0;
}
static int isl7998x_s_std(struct v4l2_subdev *sd, v4l2_std_id norm)
{
struct isl7998x *isl7998x = sd_to_isl7998x(sd);
struct i2c_client *client = v4l2_get_subdevdata(sd);
struct device *dev = &client->dev;
int ret = 0;
mutex_lock(&isl7998x->lock);
if (isl7998x->enabled) {
ret = -EBUSY;
mutex_unlock(&isl7998x->lock);
return ret;
}
isl7998x->norm = norm;
mutex_unlock(&isl7998x->lock);
if (pm_runtime_get_if_in_use(dev) <= 0)
return ret;
ret = isl7998x_set_standard(isl7998x, norm);
pm_runtime_put(dev);
return ret;
}
static int isl7998x_querystd(struct v4l2_subdev *sd, v4l2_std_id *std)
{
struct isl7998x *isl7998x = sd_to_isl7998x(sd);
struct i2c_client *client = v4l2_get_subdevdata(sd);
struct device *dev = &client->dev;
unsigned int std_id[ISL7998X_INPUTS];
unsigned int i;
int ret;
u32 reg;
ret = pm_runtime_resume_and_get(dev);
if (ret)
return ret;
dev_dbg(dev, "starting video standard detection\n");
mutex_lock(&isl7998x->lock);
if (isl7998x->enabled) {
ret = -EBUSY;
goto out_unlock;
}
ret = isl7998x_set_standard(isl7998x, V4L2_STD_UNKNOWN);
if (ret)
goto out_unlock;
for (i = 0; i < ISL7998X_INPUTS; i++) {
ret = regmap_write(isl7998x->regmap,
ISL7998X_REG_PX_DEC_SDTR(i + 1),
ISL7998X_REG_PX_DEC_SDTR_ATSTART);
if (ret)
goto out_reset_std;
}
for (i = 0; i < ISL7998X_INPUTS; i++) {
ret = regmap_read_poll_timeout(isl7998x->regmap,
ISL7998X_REG_PX_DEC_SDT(i + 1),
reg,
!(reg & ISL7998X_REG_PX_DEC_SDT_DET),
2000, 500 * USEC_PER_MSEC);
if (ret)
goto out_reset_std;
std_id[i] = FIELD_GET(ISL7998X_REG_PX_DEC_SDT_NOW, reg);
}
/*
* According to Renesas FAE, all input cameras must have the
* same standard on this chip.
*/
for (i = 0; i < isl7998x->nr_inputs; i++) {
dev_dbg(dev, "input %d: detected %s\n",
i, v4l2_norm_to_name(isl7998x_std_res[std_id[i]].norm));
if (std_id[0] != std_id[i])
dev_warn(dev,
"incompatible standards: %s on input %d (expected %s)\n",
v4l2_norm_to_name(isl7998x_std_res[std_id[i]].norm), i,
v4l2_norm_to_name(isl7998x_std_res[std_id[0]].norm));
}
*std = isl7998x_std_res[std_id[0]].norm;
out_reset_std:
isl7998x_set_standard(isl7998x, isl7998x->norm);
out_unlock:
mutex_unlock(&isl7998x->lock);
pm_runtime_put(dev);
return ret;
}
static int isl7998x_g_tvnorms(struct v4l2_subdev *sd, v4l2_std_id *std)
{
*std = V4L2_STD_ALL;
return 0;
}
static int isl7998x_g_input_status(struct v4l2_subdev *sd, u32 *status)
{
struct isl7998x *isl7998x = sd_to_isl7998x(sd);
struct i2c_client *client = v4l2_get_subdevdata(sd);
struct device *dev = &client->dev;
unsigned int i;
int ret = 0;
u32 reg;
if (!pm_runtime_active(dev)) {
*status |= V4L2_IN_ST_NO_POWER;
return 0;
}
for (i = 0; i < isl7998x->nr_inputs; i++) {
ret = regmap_read(isl7998x->regmap,
ISL7998X_REG_PX_DEC_STATUS_1(i + 1), &reg);
if (!ret) {
if (reg & ISL7998X_REG_PX_DEC_STATUS_1_VDLOSS)
*status |= V4L2_IN_ST_NO_SIGNAL;
if (!(reg & ISL7998X_REG_PX_DEC_STATUS_1_HLOCK))
*status |= V4L2_IN_ST_NO_H_LOCK;
if (!(reg & ISL7998X_REG_PX_DEC_STATUS_1_VLOCK))
*status |= V4L2_IN_ST_NO_V_LOCK;
}
}
return ret;
}
static int isl7998x_s_stream(struct v4l2_subdev *sd, int enable)
{
struct isl7998x *isl7998x = sd_to_isl7998x(sd);
struct i2c_client *client = v4l2_get_subdevdata(sd);
struct device *dev = &client->dev;
int ret = 0;
u32 reg;
dev_dbg(dev, "stream %s\n", enable ? "ON" : "OFF");
mutex_lock(&isl7998x->lock);
if (isl7998x->enabled == enable)
goto out;
isl7998x->enabled = enable;
if (enable) {
ret = isl7998x_set_test_pattern(isl7998x);
if (ret)
goto out;
}
regmap_read(isl7998x->regmap,
ISL7998X_REG_P5_LI_ENGINE_CTL, &reg);
if (enable)
reg &= ~BIT(7);
else
reg |= BIT(7);
ret = regmap_write(isl7998x->regmap,
ISL7998X_REG_P5_LI_ENGINE_CTL, reg);
out:
mutex_unlock(&isl7998x->lock);
return ret;
}
static int isl7998x_pre_streamon(struct v4l2_subdev *sd, u32 flags)
{
struct i2c_client *client = v4l2_get_subdevdata(sd);
struct device *dev = &client->dev;
return pm_runtime_resume_and_get(dev);
}
static int isl7998x_post_streamoff(struct v4l2_subdev *sd)
{
struct i2c_client *client = v4l2_get_subdevdata(sd);
struct device *dev = &client->dev;
pm_runtime_put(dev);
return 0;
}
static int isl7998x_enum_mbus_code(struct v4l2_subdev *sd,
struct v4l2_subdev_state *sd_state,
struct v4l2_subdev_mbus_code_enum *code)
{
if (code->index >= ARRAY_SIZE(isl7998x_colour_fmts))
return -EINVAL;
code->code = isl7998x_colour_fmts[code->index].code;
return 0;
}
static int isl7998x_enum_frame_size(struct v4l2_subdev *sd,
struct v4l2_subdev_state *sd_state,
struct v4l2_subdev_frame_size_enum *fse)
{
if (fse->index >= ARRAY_SIZE(supported_modes))
return -EINVAL;
if (fse->code != isl7998x_colour_fmts[0].code)
return -EINVAL;
fse->min_width = supported_modes[fse->index].width;
fse->max_width = fse->min_width;
fse->min_height = supported_modes[fse->index].height;
fse->max_height = fse->min_height;
return 0;
}
static int isl7998x_get_fmt(struct v4l2_subdev *sd,
struct v4l2_subdev_state *sd_state,
struct v4l2_subdev_format *format)
{
struct isl7998x *isl7998x = sd_to_isl7998x(sd);
struct v4l2_mbus_framefmt *mf = &format->format;
const struct isl7998x_mode *mode;
mutex_lock(&isl7998x->lock);
if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
format->format = *v4l2_subdev_get_try_format(sd, sd_state,
format->pad);
goto out;
}
mode = isl7998x_norm_to_mode(isl7998x->norm);
mf->width = mode->width;
mf->height = mode->height;
mf->code = isl7998x->fmt->code;
mf->field = mode->field;
mf->colorspace = 0;
out:
mutex_unlock(&isl7998x->lock);
return 0;
}
static int isl7998x_set_fmt(struct v4l2_subdev *sd,
struct v4l2_subdev_state *sd_state,
struct v4l2_subdev_format *format)
{
struct isl7998x *isl7998x = sd_to_isl7998x(sd);
struct v4l2_mbus_framefmt *mf = &format->format;
const struct isl7998x_mode *mode;
mutex_lock(&isl7998x->lock);
mode = isl7998x_norm_to_mode(isl7998x->norm);
mf->width = mode->width;
mf->height = mode->height;
mf->code = isl7998x->fmt->code;
mf->field = mode->field;
if (format->which == V4L2_SUBDEV_FORMAT_TRY)
*v4l2_subdev_get_try_format(sd, sd_state, format->pad) = format->format;
mutex_unlock(&isl7998x->lock);
return 0;
}
static int isl7998x_set_ctrl(struct v4l2_ctrl *ctrl)
{
struct isl7998x *isl7998x = container_of(ctrl->handler,
struct isl7998x, ctrl_handler);
int ret = 0;
switch (ctrl->id) {
case V4L2_CID_TEST_PATTERN_BARS:
mutex_lock(&isl7998x->lock);
isl7998x->test_pattern_bars = ctrl->val & 0x3;
ret = isl7998x_set_test_pattern(isl7998x);
mutex_unlock(&isl7998x->lock);
break;
case V4L2_CID_TEST_PATTERN_CHANNELS:
mutex_lock(&isl7998x->lock);
isl7998x->test_pattern_chans = ctrl->val & 0xf;
ret = isl7998x_set_test_pattern(isl7998x);
mutex_unlock(&isl7998x->lock);
break;
case V4L2_CID_TEST_PATTERN_COLOR:
mutex_lock(&isl7998x->lock);
isl7998x->test_pattern_color = ctrl->val & 0x3;
ret = isl7998x_set_test_pattern(isl7998x);
mutex_unlock(&isl7998x->lock);
break;
case V4L2_CID_TEST_PATTERN:
mutex_lock(&isl7998x->lock);
isl7998x->test_pattern = ctrl->val;
ret = isl7998x_set_test_pattern(isl7998x);
mutex_unlock(&isl7998x->lock);
break;
}
return ret;
}
static const struct v4l2_subdev_core_ops isl7998x_subdev_core_ops = {
#ifdef CONFIG_VIDEO_ADV_DEBUG
.g_register = isl7998x_g_register,
.s_register = isl7998x_s_register,
#endif
};
static const struct v4l2_subdev_video_ops isl7998x_subdev_video_ops = {
.g_std = isl7998x_g_std,
.s_std = isl7998x_s_std,
.querystd = isl7998x_querystd,
.g_tvnorms = isl7998x_g_tvnorms,
.g_input_status = isl7998x_g_input_status,
.s_stream = isl7998x_s_stream,
.pre_streamon = isl7998x_pre_streamon,
.post_streamoff = isl7998x_post_streamoff,
};
static const struct v4l2_subdev_pad_ops isl7998x_subdev_pad_ops = {
.enum_mbus_code = isl7998x_enum_mbus_code,
.enum_frame_size = isl7998x_enum_frame_size,
.get_fmt = isl7998x_get_fmt,
.set_fmt = isl7998x_set_fmt,
};
static const struct v4l2_subdev_ops isl7998x_subdev_ops = {
.core = &isl7998x_subdev_core_ops,
.video = &isl7998x_subdev_video_ops,
.pad = &isl7998x_subdev_pad_ops,
};
static const struct media_entity_operations isl7998x_entity_ops = {
.link_validate = v4l2_subdev_link_validate,
};
static const struct v4l2_ctrl_ops isl7998x_ctrl_ops = {
.s_ctrl = isl7998x_set_ctrl,
};
static const struct v4l2_ctrl_config isl7998x_ctrls[] = {
{
.ops = &isl7998x_ctrl_ops,
.id = V4L2_CID_TEST_PATTERN_BARS,
.type = V4L2_CTRL_TYPE_MENU,
.name = "Test Pattern Bars",
.max = ARRAY_SIZE(isl7998x_test_pattern_bars) - 1,
.def = 0,
.qmenu = isl7998x_test_pattern_bars,
}, {
.ops = &isl7998x_ctrl_ops,
.id = V4L2_CID_TEST_PATTERN_CHANNELS,
.type = V4L2_CTRL_TYPE_INTEGER,
.name = "Test Pattern Channels",
.min = 0,
.max = 0xf,
.step = 1,
.def = 0xf,
.flags = 0,
}, {
.ops = &isl7998x_ctrl_ops,
.id = V4L2_CID_TEST_PATTERN_COLOR,
.type = V4L2_CTRL_TYPE_MENU,
.name = "Test Pattern Color",
.max = ARRAY_SIZE(isl7998x_test_pattern_colors) - 1,
.def = 0,
.qmenu = isl7998x_test_pattern_colors,
},
};
#define ISL7998X_REG_DECODER_ACA_READABLE_RANGE(page) \
/* Decoder range */ \
regmap_reg_range(ISL7998X_REG_PX_DEC_INPUT_FMT(page), \
ISL7998X_REG_PX_DEC_HS_DELAY_CTL(page)), \
regmap_reg_range(ISL7998X_REG_PX_DEC_ANCTL(page), \
ISL7998X_REG_PX_DEC_CSC_CTL(page)), \
regmap_reg_range(ISL7998X_REG_PX_DEC_BRIGHT(page), \
ISL7998X_REG_PX_DEC_HUE(page)), \
regmap_reg_range(ISL7998X_REG_PX_DEC_VERT_PEAK(page), \
ISL7998X_REG_PX_DEC_CORING(page)), \
regmap_reg_range(ISL7998X_REG_PX_DEC_SDT(page), \
ISL7998X_REG_PX_DEC_SDTR(page)), \
regmap_reg_range(ISL7998X_REG_PX_DEC_CLMPG(page), \
ISL7998X_REG_PX_DEC_DATA_CONV(page)), \
regmap_reg_range(ISL7998X_REG_PX_DEC_INTERNAL_TEST(page), \
ISL7998X_REG_PX_DEC_INTERNAL_TEST(page)), \
regmap_reg_range(ISL7998X_REG_PX_DEC_H_DELAY_CTL(page), \
ISL7998X_REG_PX_DEC_H_DELAY_II_LOW(page)), \
/* ACA range */ \
regmap_reg_range(ISL7998X_REG_PX_ACA_CTL_1(page), \
ISL7998X_REG_PX_ACA_HIST_WIN_V_SZ2(page)), \
regmap_reg_range(ISL7998X_REG_PX_ACA_Y_AVG(page), \
ISL7998X_REG_PX_ACA_CTL_4(page)), \
regmap_reg_range(ISL7998X_REG_PX_ACA_FLEX_WIN_HIST(page), \
ISL7998X_REG_PX_ACA_XFER_HIST_HOST(page)), \
regmap_reg_range(ISL7998X_REG_PX_DEC_PAGE(page), \
ISL7998X_REG_PX_DEC_PAGE(page))
#define ISL7998X_REG_DECODER_ACA_WRITEABLE_RANGE(page) \
/* Decoder range */ \
regmap_reg_range(ISL7998X_REG_PX_DEC_INPUT_FMT(page), \
ISL7998X_REG_PX_DEC_INPUT_FMT(page)), \
regmap_reg_range(ISL7998X_REG_PX_DEC_HS_DELAY_CTL(page), \
ISL7998X_REG_PX_DEC_HS_DELAY_CTL(page)), \
regmap_reg_range(ISL7998X_REG_PX_DEC_ANCTL(page), \
ISL7998X_REG_PX_DEC_CSC_CTL(page)), \
regmap_reg_range(ISL7998X_REG_PX_DEC_BRIGHT(page), \
ISL7998X_REG_PX_DEC_HUE(page)), \
regmap_reg_range(ISL7998X_REG_PX_DEC_VERT_PEAK(page), \
ISL7998X_REG_PX_DEC_CORING(page)), \
regmap_reg_range(ISL7998X_REG_PX_DEC_SDT(page), \
ISL7998X_REG_PX_DEC_SDTR(page)), \
regmap_reg_range(ISL7998X_REG_PX_DEC_CLMPG(page), \
ISL7998X_REG_PX_DEC_MISC3(page)), \
regmap_reg_range(ISL7998X_REG_PX_DEC_CLMD(page), \
ISL7998X_REG_PX_DEC_DATA_CONV(page)), \
regmap_reg_range(ISL7998X_REG_PX_DEC_INTERNAL_TEST(page), \
ISL7998X_REG_PX_DEC_INTERNAL_TEST(page)), \
regmap_reg_range(ISL7998X_REG_PX_DEC_H_DELAY_CTL(page), \
ISL7998X_REG_PX_DEC_H_DELAY_II_LOW(page)), \
/* ACA range */ \
regmap_reg_range(ISL7998X_REG_PX_ACA_CTL_1(page), \
ISL7998X_REG_PX_ACA_HIST_WIN_V_SZ2(page)), \
regmap_reg_range(ISL7998X_REG_PX_ACA_CTL_2(page), \
ISL7998X_REG_PX_ACA_CTL_4(page)), \
regmap_reg_range(ISL7998X_REG_PX_ACA_FLEX_WIN_HIST(page), \
ISL7998X_REG_PX_ACA_HIST_DATA_LO(page)), \
regmap_reg_range(ISL7998X_REG_PX_ACA_XFER_HIST_HOST(page), \
ISL7998X_REG_PX_ACA_XFER_HIST_HOST(page)), \
regmap_reg_range(ISL7998X_REG_PX_DEC_PAGE(page), \
ISL7998X_REG_PX_DEC_PAGE(page))
#define ISL7998X_REG_DECODER_ACA_VOLATILE_RANGE(page) \
/* Decoder range */ \
regmap_reg_range(ISL7998X_REG_PX_DEC_STATUS_1(page), \
ISL7998X_REG_PX_DEC_STATUS_1(page)), \
regmap_reg_range(ISL7998X_REG_PX_DEC_SDT(page), \
ISL7998X_REG_PX_DEC_SDT(page)), \
regmap_reg_range(ISL7998X_REG_PX_DEC_MVSN(page), \
ISL7998X_REG_PX_DEC_HFREF(page)), \
/* ACA range */ \
regmap_reg_range(ISL7998X_REG_PX_ACA_Y_AVG(page), \
ISL7998X_REG_PX_ACA_Y_HIGH(page)), \
regmap_reg_range(ISL7998X_REG_PX_ACA_HIST_DATA_LO(page), \
ISL7998X_REG_PX_ACA_FLEX_WIN_CR_CLR(page))
static const struct regmap_range isl7998x_readable_ranges[] = {
regmap_reg_range(ISL7998X_REG_P0_PRODUCT_ID_CODE,
ISL7998X_REG_P0_IRQ_SYNC_CTL),
regmap_reg_range(ISL7998X_REG_P0_INTERRUPT_STATUS,
ISL7998X_REG_P0_CLOCK_DELAY),
regmap_reg_range(ISL7998X_REG_PX_DEC_PAGE(0),
ISL7998X_REG_PX_DEC_PAGE(0)),
ISL7998X_REG_DECODER_ACA_READABLE_RANGE(1),
ISL7998X_REG_DECODER_ACA_READABLE_RANGE(2),
ISL7998X_REG_DECODER_ACA_READABLE_RANGE(3),
ISL7998X_REG_DECODER_ACA_READABLE_RANGE(4),
regmap_reg_range(ISL7998X_REG_P5_LI_ENGINE_CTL,
ISL7998X_REG_P5_MIPI_SP_HS_TRL_CTL),
regmap_reg_range(ISL7998X_REG_P5_FIFO_THRSH_CNT_1,
ISL7998X_REG_P5_PLL_ANA),
regmap_reg_range(ISL7998X_REG_P5_TOTAL_PF_LINE_CNT_1,
ISL7998X_REG_P5_HIST_LINE_CNT_2),
regmap_reg_range(ISL7998X_REG_PX_DEC_PAGE(5),
ISL7998X_REG_PX_DEC_PAGE(5)),
};
static const struct regmap_range isl7998x_writeable_ranges[] = {
regmap_reg_range(ISL7998X_REG_P0_SW_RESET_CTL,
ISL7998X_REG_P0_IRQ_SYNC_CTL),
regmap_reg_range(ISL7998X_REG_P0_CHAN_1_IRQ,
ISL7998X_REG_P0_SHORT_DIAG_IRQ_EN),
regmap_reg_range(ISL7998X_REG_P0_CLOCK_DELAY,
ISL7998X_REG_P0_CLOCK_DELAY),
regmap_reg_range(ISL7998X_REG_PX_DEC_PAGE(0),
ISL7998X_REG_PX_DEC_PAGE(0)),
ISL7998X_REG_DECODER_ACA_WRITEABLE_RANGE(1),
ISL7998X_REG_DECODER_ACA_WRITEABLE_RANGE(2),
ISL7998X_REG_DECODER_ACA_WRITEABLE_RANGE(3),
ISL7998X_REG_DECODER_ACA_WRITEABLE_RANGE(4),
regmap_reg_range(ISL7998X_REG_P5_LI_ENGINE_CTL,
ISL7998X_REG_P5_ESC_MODE_TIME_CTL),
regmap_reg_range(ISL7998X_REG_P5_MIPI_SP_HS_TRL_CTL,
ISL7998X_REG_P5_PLL_ANA),
regmap_reg_range(ISL7998X_REG_P5_TOTAL_PF_LINE_CNT_1,
ISL7998X_REG_P5_HIST_LINE_CNT_2),
regmap_reg_range(ISL7998X_REG_PX_DEC_PAGE(5),
ISL7998X_REG_PX_DEC_PAGE(5)),
ISL7998X_REG_DECODER_ACA_WRITEABLE_RANGE(0xf),
};
static const struct regmap_range isl7998x_volatile_ranges[] = {
/* Product id code register is used to check availability */
regmap_reg_range(ISL7998X_REG_P0_PRODUCT_ID_CODE,
ISL7998X_REG_P0_PRODUCT_ID_CODE),
regmap_reg_range(ISL7998X_REG_P0_MPP1_SYNC_CTL,
ISL7998X_REG_P0_IRQ_SYNC_CTL),
regmap_reg_range(ISL7998X_REG_P0_INTERRUPT_STATUS,
ISL7998X_REG_P0_INTERRUPT_STATUS),
regmap_reg_range(ISL7998X_REG_P0_CHAN_1_STATUS,
ISL7998X_REG_P0_SHORT_DIAG_STATUS),
ISL7998X_REG_DECODER_ACA_VOLATILE_RANGE(1),
ISL7998X_REG_DECODER_ACA_VOLATILE_RANGE(2),
ISL7998X_REG_DECODER_ACA_VOLATILE_RANGE(3),
ISL7998X_REG_DECODER_ACA_VOLATILE_RANGE(4),
regmap_reg_range(ISL7998X_REG_P5_AUTO_TEST_ERR_DET,
ISL7998X_REG_P5_PIC_HEIGHT_LOW),
};
static const struct regmap_access_table isl7998x_readable_table = {
.yes_ranges = isl7998x_readable_ranges,
.n_yes_ranges = ARRAY_SIZE(isl7998x_readable_ranges),
};
static const struct regmap_access_table isl7998x_writeable_table = {
.yes_ranges = isl7998x_writeable_ranges,
.n_yes_ranges = ARRAY_SIZE(isl7998x_writeable_ranges),
};
static const struct regmap_access_table isl7998x_volatile_table = {
.yes_ranges = isl7998x_volatile_ranges,
.n_yes_ranges = ARRAY_SIZE(isl7998x_volatile_ranges),
};
static const struct regmap_range_cfg isl7998x_ranges[] = {
{
.range_min = ISL7998X_REG_PN_BASE(0),
.range_max = ISL7998X_REG_PX_ACA_XFER_HIST_HOST(0xf),
.selector_reg = ISL7998X_REG_PX_DEC_PAGE(0),
.selector_mask = ISL7998X_REG_PX_DEC_PAGE_MASK,
.window_start = 0,
.window_len = 256,
}
};
static const struct regmap_config isl7998x_regmap = {
.reg_bits = 8,
.val_bits = 8,
.max_register = ISL7998X_REG_PX_ACA_XFER_HIST_HOST(0xf),
.ranges = isl7998x_ranges,
.num_ranges = ARRAY_SIZE(isl7998x_ranges),
.rd_table = &isl7998x_readable_table,
.wr_table = &isl7998x_writeable_table,
.volatile_table = &isl7998x_volatile_table,
.cache_type = REGCACHE_RBTREE,
};
static int isl7998x_mc_init(struct isl7998x *isl7998x)
{
unsigned int i;
isl7998x->subdev.entity.ops = &isl7998x_entity_ops;
isl7998x->subdev.entity.function = MEDIA_ENT_F_VID_IF_BRIDGE;
isl7998x->pads[ISL7998X_PAD_OUT].flags = MEDIA_PAD_FL_SOURCE;
for (i = ISL7998X_PAD_VIN1; i < ISL7998X_NUM_PADS; i++)
isl7998x->pads[i].flags = MEDIA_PAD_FL_SINK;
return media_entity_pads_init(&isl7998x->subdev.entity,
ISL7998X_NUM_PADS,
isl7998x->pads);
}
static int get_link_freq_menu_index(unsigned int lanes,
unsigned int inputs)
{
int ret = -EINVAL;
switch (lanes) {
case 1:
if (inputs == 1)
ret = 0;
if (inputs == 2)
ret = 1;
if (inputs == 4)
ret = 2;
break;
case 2:
if (inputs == 2)
ret = 0;
if (inputs == 4)
ret = 1;
break;
default:
break;
}
return ret;
}
static void isl7998x_remove_controls(struct isl7998x *isl7998x)
{
v4l2_ctrl_handler_free(&isl7998x->ctrl_handler);
mutex_destroy(&isl7998x->ctrl_mutex);
}
static int isl7998x_init_controls(struct isl7998x *isl7998x)
{
struct v4l2_subdev *sd = &isl7998x->subdev;
int link_freq_index;
unsigned int i;
int ret;
ret = v4l2_ctrl_handler_init(&isl7998x->ctrl_handler,
2 + ARRAY_SIZE(isl7998x_ctrls));
if (ret)
return ret;
mutex_init(&isl7998x->ctrl_mutex);
isl7998x->ctrl_handler.lock = &isl7998x->ctrl_mutex;
link_freq_index = get_link_freq_menu_index(isl7998x->nr_mipi_lanes,
isl7998x->nr_inputs);
if (link_freq_index < 0 ||
link_freq_index >= ARRAY_SIZE(link_freq_menu_items)) {
dev_err(sd->dev,
"failed to find MIPI link freq: %d lanes, %d inputs\n",
isl7998x->nr_mipi_lanes, isl7998x->nr_inputs);
ret = -EINVAL;
goto err;
}
isl7998x->link_freq = v4l2_ctrl_new_int_menu(&isl7998x->ctrl_handler,
&isl7998x_ctrl_ops,
V4L2_CID_LINK_FREQ,
ARRAY_SIZE(link_freq_menu_items) - 1,
link_freq_index,
link_freq_menu_items);
if (isl7998x->link_freq)
isl7998x->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY;
for (i = 0; i < ARRAY_SIZE(isl7998x_ctrls); i++)
v4l2_ctrl_new_custom(&isl7998x->ctrl_handler,
&isl7998x_ctrls[i], NULL);
v4l2_ctrl_new_std_menu_items(&isl7998x->ctrl_handler,
&isl7998x_ctrl_ops,
V4L2_CID_TEST_PATTERN,
ARRAY_SIZE(isl7998x_test_pattern_menu) - 1,
0, 0, isl7998x_test_pattern_menu);
ret = isl7998x->ctrl_handler.error;
if (ret)
goto err;
isl7998x->subdev.ctrl_handler = &isl7998x->ctrl_handler;
v4l2_ctrl_handler_setup(&isl7998x->ctrl_handler);
return 0;
err:
isl7998x_remove_controls(isl7998x);
return ret;
}
static int isl7998x_probe(struct i2c_client *client)
{
struct device *dev = &client->dev;
struct v4l2_fwnode_endpoint endpoint = {
.bus_type = V4L2_MBUS_CSI2_DPHY,
};
struct fwnode_handle *ep;
struct isl7998x *isl7998x;
struct i2c_adapter *adapter = to_i2c_adapter(client->dev.parent);
int nr_inputs;
int ret;
ret = i2c_check_functionality(adapter, I2C_FUNC_SMBUS_WORD_DATA);
if (!ret) {
dev_warn(&adapter->dev,
"I2C-Adapter doesn't support I2C_FUNC_SMBUS_WORD\n");
return -EIO;
}
isl7998x = devm_kzalloc(dev, sizeof(*isl7998x), GFP_KERNEL);
if (!isl7998x)
return -ENOMEM;
isl7998x->pd_gpio = devm_gpiod_get_optional(dev, "powerdown",
GPIOD_OUT_HIGH);
if (IS_ERR(isl7998x->pd_gpio))
return dev_err_probe(dev, PTR_ERR(isl7998x->pd_gpio),
"Failed to retrieve/request PD GPIO\n");
isl7998x->rstb_gpio = devm_gpiod_get_optional(dev, "reset",
GPIOD_OUT_HIGH);
if (IS_ERR(isl7998x->rstb_gpio))
return dev_err_probe(dev, PTR_ERR(isl7998x->rstb_gpio),
"Failed to retrieve/request RSTB GPIO\n");
isl7998x->regmap = devm_regmap_init_i2c(client, &isl7998x_regmap);
if (IS_ERR(isl7998x->regmap))
return dev_err_probe(dev, PTR_ERR(isl7998x->regmap),
"Failed to allocate register map\n");
ep = fwnode_graph_get_endpoint_by_id(dev_fwnode(dev),
ISL7998X_PAD_OUT, 0, 0);
if (!ep)
return dev_err_probe(dev, -EINVAL, "Missing endpoint node\n");
ret = v4l2_fwnode_endpoint_parse(ep, &endpoint);
fwnode_handle_put(ep);
if (ret)
return dev_err_probe(dev, ret, "Failed to parse endpoint\n");
if (endpoint.bus.mipi_csi2.num_data_lanes == 0 ||
endpoint.bus.mipi_csi2.num_data_lanes > 2)
return dev_err_probe(dev, -EINVAL,
"Invalid number of MIPI lanes\n");
isl7998x->nr_mipi_lanes = endpoint.bus.mipi_csi2.num_data_lanes;
nr_inputs = isl7998x_get_nr_inputs(dev->of_node);
if (nr_inputs < 0)
return dev_err_probe(dev, nr_inputs,
"Invalid number of input ports\n");
isl7998x->nr_inputs = nr_inputs;
v4l2_i2c_subdev_init(&isl7998x->subdev, client, &isl7998x_subdev_ops);
isl7998x->subdev.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
ret = isl7998x_mc_init(isl7998x);
if (ret < 0)
return ret;
isl7998x->fmt = &isl7998x_colour_fmts[0];
isl7998x->norm = V4L2_STD_NTSC;
isl7998x->enabled = 0;
mutex_init(&isl7998x->lock);
ret = isl7998x_init_controls(isl7998x);
if (ret)
goto err_entity_cleanup;
ret = v4l2_async_register_subdev(&isl7998x->subdev);
if (ret < 0)
goto err_controls_cleanup;
pm_runtime_enable(dev);
return 0;
err_controls_cleanup:
isl7998x_remove_controls(isl7998x);
err_entity_cleanup:
media_entity_cleanup(&isl7998x->subdev.entity);
return ret;
}
static int isl7998x_remove(struct i2c_client *client)
{
struct isl7998x *isl7998x = i2c_to_isl7998x(client);
pm_runtime_disable(&client->dev);
v4l2_async_unregister_subdev(&isl7998x->subdev);
isl7998x_remove_controls(isl7998x);
media_entity_cleanup(&isl7998x->subdev.entity);
return 0;
}
static const struct of_device_id isl7998x_of_match[] = {
{ .compatible = "isil,isl79987", },
{ /* sentinel */ },
};
MODULE_DEVICE_TABLE(of, isl7998x_of_match);
static const struct i2c_device_id isl7998x_id[] = {
{ "isl79987", 0 },
{ /* sentinel */ },
};
MODULE_DEVICE_TABLE(i2c, isl7998x_id);
static int __maybe_unused isl7998x_runtime_resume(struct device *dev)
{
struct v4l2_subdev *sd = dev_get_drvdata(dev);
struct isl7998x *isl7998x = sd_to_isl7998x(sd);
int ret;
gpiod_set_value(isl7998x->rstb_gpio, 1);
gpiod_set_value(isl7998x->pd_gpio, 0);
gpiod_set_value(isl7998x->rstb_gpio, 0);
ret = isl7998x_wait_power_on(isl7998x);
if (ret)
goto err;
ret = isl7998x_init(isl7998x);
if (ret)
goto err;
return 0;
err:
gpiod_set_value(isl7998x->pd_gpio, 1);
return ret;
}
static int __maybe_unused isl7998x_runtime_suspend(struct device *dev)
{
struct v4l2_subdev *sd = dev_get_drvdata(dev);
struct isl7998x *isl7998x = sd_to_isl7998x(sd);
gpiod_set_value(isl7998x->pd_gpio, 1);
return 0;
}
static const struct dev_pm_ops isl7998x_pm_ops = {
SET_RUNTIME_PM_OPS(isl7998x_runtime_suspend,
isl7998x_runtime_resume,
NULL)
};
static struct i2c_driver isl7998x_i2c_driver = {
.driver = {
.name = "isl7998x",
.of_match_table = of_match_ptr(isl7998x_of_match),
.pm = &isl7998x_pm_ops,
},
.probe_new = isl7998x_probe,
.remove = isl7998x_remove,
.id_table = isl7998x_id,
};
module_i2c_driver(isl7998x_i2c_driver);
MODULE_DESCRIPTION("Intersil ISL7998x Analog to MIPI CSI-2/BT656 decoder");
MODULE_AUTHOR("Marek Vasut <marex@denx.de>");
MODULE_LICENSE("GPL v2");
drivers/media/i2c/m5mols/m5mols.h
View file @ 12fdba56
......@@ -13,6 +13,7 @@
#define M5MOLS_H
#include <linux/sizes.h>
#include <linux/gpio/consumer.h>
#include <media/v4l2-subdev.h>
#include "m5mols_reg.h"
......@@ -224,6 +225,7 @@ struct m5mols_info {
struct v4l2_ctrl *jpeg_quality;
int (*set_power)(struct device *dev, int on);
struct gpio_desc *reset;
struct mutex lock;
......
drivers/media/i2c/m5mols/m5mols_capture.c
View file @ 12fdba56
......@@ -15,7 +15,6 @@
#include <linux/irq.h>
#include <linux/interrupt.h>
#include <linux/delay.h>
#include <linux/gpio.h>
#include <linux/regulator/consumer.h>
#include <linux/videodev2.h>
#include <media/v4l2-ctrls.h>
......
drivers/media/i2c/m5mols/m5mols_core.c
View file @ 12fdba56
......@@ -14,7 +14,7 @@
#include <linux/irq.h>
#include <linux/interrupt.h>
#include <linux/delay.h>
#include <linux/gpio.h>
#include <linux/gpio/consumer.h>
#include <linux/regulator/consumer.h>
#include <linux/videodev2.h>
#include <linux/module.h>
......@@ -752,7 +752,6 @@ static int m5mols_sensor_power(struct m5mols_info *info, bool enable)
{
struct v4l2_subdev *sd = &info->sd;
struct i2c_client *client = v4l2_get_subdevdata(sd);
const struct m5mols_platform_data *pdata = info->pdata;
int ret;
if (info->power == enable)
......@@ -772,7 +771,7 @@ static int m5mols_sensor_power(struct m5mols_info *info, bool enable)
return ret;
}
gpio_set_value(pdata->gpio_reset, !pdata->reset_polarity);
gpiod_set_value(info->reset, 0);
info->power = 1;
return ret;
......@@ -785,7 +784,7 @@ static int m5mols_sensor_power(struct m5mols_info *info, bool enable)
if (info->set_power)
info->set_power(&client->dev, 0);
gpio_set_value(pdata->gpio_reset, pdata->reset_polarity);
gpiod_set_value(info->reset, 1);
info->isp_ready = 0;
info->power = 0;
......@@ -944,7 +943,6 @@ static int m5mols_probe(struct i2c_client *client,
const struct i2c_device_id *id)
{
const struct m5mols_platform_data *pdata = client->dev.platform_data;
unsigned long gpio_flags;
struct m5mols_info *info;
struct v4l2_subdev *sd;
int ret;
......@@ -954,11 +952,6 @@ static int m5mols_probe(struct i2c_client *client,
return -EINVAL;
}
if (!gpio_is_valid(pdata->gpio_reset)) {
dev_err(&client->dev, "No valid RESET GPIO specified\n");
return -EINVAL;
}
if (!client->irq) {
dev_err(&client->dev, "Interrupt not assigned\n");
return -EINVAL;
......@@ -968,18 +961,16 @@ static int m5mols_probe(struct i2c_client *client,
if (!info)
return -ENOMEM;
/* This asserts reset, descriptor shall have polarity specified */
info->reset = devm_gpiod_get(&client->dev, "reset", GPIOD_OUT_HIGH);
if (IS_ERR(info->reset))
return PTR_ERR(info->reset);
/* Notice: the "N" in M5MOLS_NRST implies active low */
gpiod_set_consumer_name(info->reset, "M5MOLS_NRST");
info->pdata = pdata;
info->set_power = pdata->set_power;
gpio_flags = pdata->reset_polarity
? GPIOF_OUT_INIT_HIGH : GPIOF_OUT_INIT_LOW;
ret = devm_gpio_request_one(&client->dev, pdata->gpio_reset, gpio_flags,
"M5MOLS_NRST");
if (ret) {
dev_err(&client->dev, "Failed to request gpio: %d\n", ret);
return ret;
}
ret = devm_regulator_bulk_get(&client->dev, ARRAY_SIZE(supplies),
supplies);
if (ret) {
......
drivers/media/i2c/mt9m111.c
View file @ 12fdba56
......@@ -9,7 +9,6 @@
#include <linux/slab.h>
#include <linux/i2c.h>
#include <linux/log2.h>
#include <linux/gpio.h>
#include <linux/delay.h>
#include <linux/regulator/consumer.h>
#include <linux/v4l2-mediabus.h>
......
drivers/media/i2c/noon010pc30.c
View file @ 12fdba56
......@@ -10,7 +10,7 @@
*/
#include <linux/delay.h>
#include <linux/gpio.h>
#include <linux/gpio/consumer.h>
#include <linux/i2c.h>
#include <linux/slab.h>
#include <linux/regulator/consumer.h>
......@@ -130,8 +130,8 @@ struct noon010_info {
struct media_pad pad;
struct v4l2_ctrl_handler hdl;
struct regulator_bulk_data supply[NOON010_NUM_SUPPLIES];
u32 gpio_nreset;
u32 gpio_nstby;
struct gpio_desc *reset;
struct gpio_desc *stby;
/* Protects the struct members below */
struct mutex lock;
......@@ -393,29 +393,33 @@ static int power_enable(struct noon010_info *info)
return 0;
}
if (gpio_is_valid(info->gpio_nstby))
gpio_set_value(info->gpio_nstby, 0);
/* Assert standby: line should be flagged active low in descriptor */
if (info->stby)
gpiod_set_value(info->stby, 1);
if (gpio_is_valid(info->gpio_nreset))
gpio_set_value(info->gpio_nreset, 0);
/* Assert reset: line should be flagged active low in descriptor */
if (info->reset)
gpiod_set_value(info->reset, 1);
ret = regulator_bulk_enable(NOON010_NUM_SUPPLIES, info->supply);
if (ret)
return ret;
if (gpio_is_valid(info->gpio_nreset)) {
/* De-assert reset and standby */
if (info->reset) {
msleep(50);
gpio_set_value(info->gpio_nreset, 1);
gpiod_set_value(info->reset, 0);
}
if (gpio_is_valid(info->gpio_nstby)) {
if (info->stby) {
udelay(1000);
gpio_set_value(info->gpio_nstby, 1);
gpiod_set_value(info->stby, 0);
}
if (gpio_is_valid(info->gpio_nreset)) {
/* Cycle reset: assert and deassert */
if (info->reset) {
udelay(1000);
gpio_set_value(info->gpio_nreset, 0);
gpiod_set_value(info->reset, 1);
msleep(100);
gpio_set_value(info->gpio_nreset, 1);
gpiod_set_value(info->reset, 0);
msleep(20);
}
info->power = 1;
......@@ -438,11 +442,12 @@ static int power_disable(struct noon010_info *info)
if (ret)
return ret;
if (gpio_is_valid(info->gpio_nstby))
gpio_set_value(info->gpio_nstby, 0);
/* Assert standby and reset */
if (info->stby)
gpiod_set_value(info->stby, 1);
if (gpio_is_valid(info->gpio_nreset))
gpio_set_value(info->gpio_nreset, 0);
if (info->reset)
gpiod_set_value(info->reset, 1);
info->power = 0;
......@@ -741,34 +746,24 @@ static int noon010_probe(struct i2c_client *client,
goto np_err;
info->i2c_reg_page = -1;
info->gpio_nreset = -EINVAL;
info->gpio_nstby = -EINVAL;
info->curr_fmt = &noon010_formats[0];
info->curr_win = &noon010_sizes[0];
if (gpio_is_valid(pdata->gpio_nreset)) {
ret = devm_gpio_request_one(&client->dev, pdata->gpio_nreset,
GPIOF_OUT_INIT_LOW,
"NOON010PC30 NRST");
if (ret) {
dev_err(&client->dev, "GPIO request error: %d\n", ret);
goto np_err;
}
info->gpio_nreset = pdata->gpio_nreset;
gpio_export(info->gpio_nreset, 0);
/* Request reset asserted so we get put into reset */
info->reset = devm_gpiod_get(&client->dev, "reset", GPIOD_OUT_HIGH);
if (IS_ERR(info->reset)) {
ret = PTR_ERR(info->reset);
goto np_err;
}
gpiod_set_consumer_name(info->reset, "NOON010PC30 NRST");
if (gpio_is_valid(pdata->gpio_nstby)) {
ret = devm_gpio_request_one(&client->dev, pdata->gpio_nstby,
GPIOF_OUT_INIT_LOW,
"NOON010PC30 NSTBY");
if (ret) {
dev_err(&client->dev, "GPIO request error: %d\n", ret);
goto np_err;
}
info->gpio_nstby = pdata->gpio_nstby;
gpio_export(info->gpio_nstby, 0);
/* Request standby asserted so we get put into standby */
info->stby = devm_gpiod_get(&client->dev, "standby", GPIOD_OUT_HIGH);
if (IS_ERR(info->stby)) {
ret = PTR_ERR(info->stby);
goto np_err;
}
gpiod_set_consumer_name(info->reset, "NOON010PC30 STBY");
for (i = 0; i < NOON010_NUM_SUPPLIES; i++)
info->supply[i].supply = noon010_supply_name[i];
......
drivers/media/i2c/og01a1b.c 0 → 100644
View file @ 12fdba56
// SPDX-License-Identifier: GPL-2.0
// Copyright (c) 2022 Intel Corporation.
#include <asm/unaligned.h>
#include <linux/acpi.h>
#include <linux/delay.h>
#include <linux/i2c.h>
#include <linux/module.h>
#include <linux/pm_runtime.h>
#include <media/v4l2-ctrls.h>
#include <media/v4l2-device.h>
#include <media/v4l2-fwnode.h>
#define OG01A1B_REG_VALUE_08BIT 1
#define OG01A1B_REG_VALUE_16BIT 2
#define OG01A1B_REG_VALUE_24BIT 3
#define OG01A1B_LINK_FREQ_500MHZ 500000000ULL
#define OG01A1B_SCLK 120000000LL
#define OG01A1B_MCLK 19200000
#define OG01A1B_DATA_LANES 2
#define OG01A1B_RGB_DEPTH 10
#define OG01A1B_REG_CHIP_ID 0x300a
#define OG01A1B_CHIP_ID 0x470141
#define OG01A1B_REG_MODE_SELECT 0x0100
#define OG01A1B_MODE_STANDBY 0x00
#define OG01A1B_MODE_STREAMING 0x01
/* vertical-timings from sensor */
#define OG01A1B_REG_VTS 0x380e
#define OG01A1B_VTS_120FPS 0x0498
#define OG01A1B_VTS_120FPS_MIN 0x0498
#define OG01A1B_VTS_MAX 0x7fff
/* horizontal-timings from sensor */
#define OG01A1B_REG_HTS 0x380c
/* Exposure controls from sensor */
#define OG01A1B_REG_EXPOSURE 0x3501
#define OG01A1B_EXPOSURE_MIN 1
#define OG01A1B_EXPOSURE_MAX_MARGIN 14
#define OG01A1B_EXPOSURE_STEP 1
/* Analog gain controls from sensor */
#define OG01A1B_REG_ANALOG_GAIN 0x3508
#define OG01A1B_ANAL_GAIN_MIN 16
#define OG01A1B_ANAL_GAIN_MAX 248 /* Max = 15.5x */
#define OG01A1B_ANAL_GAIN_STEP 1
/* Digital gain controls from sensor */
#define OG01A1B_REG_DIG_GAIN 0x350a
#define OG01A1B_DGTL_GAIN_MIN 1024
#define OG01A1B_DGTL_GAIN_MAX 16384 /* Max = 16x */
#define OG01A1B_DGTL_GAIN_STEP 1
#define OG01A1B_DGTL_GAIN_DEFAULT 1024
/* Group Access */
#define OG01A1B_REG_GROUP_ACCESS 0x3208
#define OG01A1B_GROUP_HOLD_START 0x0
#define OG01A1B_GROUP_HOLD_END 0x10
#define OG01A1B_GROUP_HOLD_LAUNCH 0xa0
/* Test Pattern Control */
#define OG01A1B_REG_TEST_PATTERN 0x5100
#define OG01A1B_TEST_PATTERN_ENABLE BIT(7)
#define OG01A1B_TEST_PATTERN_BAR_SHIFT 2
#define to_og01a1b(_sd) container_of(_sd, struct og01a1b, sd)
enum {
OG01A1B_LINK_FREQ_1000MBPS,
};
struct og01a1b_reg {
u16 address;
u8 val;
};
struct og01a1b_reg_list {
u32 num_of_regs;
const struct og01a1b_reg *regs;
};
struct og01a1b_link_freq_config {
const struct og01a1b_reg_list reg_list;
};
struct og01a1b_mode {
/* Frame width in pixels */
u32 width;
/* Frame height in pixels */
u32 height;
/* Horizontal timining size */
u32 hts;
/* Default vertical timining size */
u32 vts_def;
/* Min vertical timining size */
u32 vts_min;
/* Link frequency needed for this resolution */
u32 link_freq_index;
/* Sensor register settings for this resolution */
const struct og01a1b_reg_list reg_list;
};
static const struct og01a1b_reg mipi_data_rate_1000mbps[] = {
{0x0103, 0x01},
{0x0303, 0x02},
{0x0304, 0x00},
{0x0305, 0xd2},
{0x0323, 0x02},
{0x0324, 0x01},
{0x0325, 0x77},
};
static const struct og01a1b_reg mode_1280x1024_regs[] = {
{0x0300, 0x0a},
{0x0301, 0x29},
{0x0302, 0x31},
{0x0303, 0x02},
{0x0304, 0x00},
{0x0305, 0xd2},
{0x0306, 0x00},
{0x0307, 0x01},
{0x0308, 0x02},
{0x0309, 0x00},
{0x0310, 0x00},
{0x0311, 0x00},
{0x0312, 0x07},
{0x0313, 0x00},
{0x0314, 0x00},
{0x0315, 0x00},
{0x0320, 0x02},
{0x0321, 0x01},
{0x0322, 0x01},
{0x0323, 0x02},
{0x0324, 0x01},
{0x0325, 0x77},
{0x0326, 0xce},
{0x0327, 0x04},
{0x0329, 0x02},
{0x032a, 0x04},
{0x032b, 0x04},
{0x032c, 0x02},
{0x032d, 0x01},
{0x032e, 0x00},
{0x300d, 0x02},
{0x300e, 0x04},
{0x3021, 0x08},
{0x301e, 0x03},
{0x3103, 0x00},
{0x3106, 0x08},
{0x3107, 0x40},
{0x3216, 0x01},
{0x3217, 0x00},
{0x3218, 0xc0},
{0x3219, 0x55},
{0x3500, 0x00},
{0x3501, 0x04},
{0x3502, 0x8a},
{0x3506, 0x01},
{0x3507, 0x72},
{0x3508, 0x01},
{0x3509, 0x00},
{0x350a, 0x01},
{0x350b, 0x00},
{0x350c, 0x00},
{0x3541, 0x00},
{0x3542, 0x40},
{0x3605, 0xe0},
{0x3606, 0x41},
{0x3614, 0x20},
{0x3620, 0x0b},
{0x3630, 0x07},
{0x3636, 0xa0},
{0x3637, 0xf9},
{0x3638, 0x09},
{0x3639, 0x38},
{0x363f, 0x09},
{0x3640, 0x17},
{0x3662, 0x04},
{0x3665, 0x80},
{0x3670, 0x68},
{0x3674, 0x00},
{0x3677, 0x3f},
{0x3679, 0x00},
{0x369f, 0x19},
{0x36a0, 0x03},
{0x36a2, 0x19},
{0x36a3, 0x03},
{0x370d, 0x66},
{0x370f, 0x00},
{0x3710, 0x03},
{0x3715, 0x03},
{0x3716, 0x03},
{0x3717, 0x06},
{0x3733, 0x00},
{0x3778, 0x00},
{0x37a8, 0x0f},
{0x37a9, 0x01},
{0x37aa, 0x07},
{0x37bd, 0x1c},
{0x37c1, 0x2f},
{0x37c3, 0x09},
{0x37c8, 0x1d},
{0x37ca, 0x30},
{0x37df, 0x00},
{0x3800, 0x00},
{0x3801, 0x00},
{0x3802, 0x00},
{0x3803, 0x00},
{0x3804, 0x05},
{0x3805, 0x0f},
{0x3806, 0x04},
{0x3807, 0x0f},
{0x3808, 0x05},
{0x3809, 0x00},
{0x380a, 0x04},
{0x380b, 0x00},
{0x380c, 0x03},
{0x380d, 0x50},
{0x380e, 0x04},
{0x380f, 0x98},
{0x3810, 0x00},
{0x3811, 0x08},
{0x3812, 0x00},
{0x3813, 0x08},
{0x3814, 0x11},
{0x3815, 0x11},
{0x3820, 0x40},
{0x3821, 0x04},
{0x3826, 0x00},
{0x3827, 0x00},
{0x382a, 0x08},
{0x382b, 0x52},
{0x382d, 0xba},
{0x383d, 0x14},
{0x384a, 0xa2},
{0x3866, 0x0e},
{0x3867, 0x07},
{0x3884, 0x00},
{0x3885, 0x08},
{0x3893, 0x68},
{0x3894, 0x2a},
{0x3898, 0x00},
{0x3899, 0x31},
{0x389a, 0x04},
{0x389b, 0x00},
{0x389c, 0x0b},
{0x389d, 0xad},
{0x389f, 0x08},
{0x38a0, 0x00},
{0x38a1, 0x00},
{0x38a8, 0x70},
{0x38ac, 0xea},
{0x38b2, 0x00},
{0x38b3, 0x08},
{0x38bc, 0x20},
{0x38c4, 0x0c},
{0x38c5, 0x3a},
{0x38c7, 0x3a},
{0x38e1, 0xc0},
{0x38ec, 0x3c},
{0x38f0, 0x09},
{0x38f1, 0x6f},
{0x38fe, 0x3c},
{0x391e, 0x00},
{0x391f, 0x00},
{0x3920, 0xa5},
{0x3921, 0x00},
{0x3922, 0x00},
{0x3923, 0x00},
{0x3924, 0x05},
{0x3925, 0x00},
{0x3926, 0x00},
{0x3927, 0x00},
{0x3928, 0x1a},
{0x3929, 0x01},
{0x392a, 0xb4},
{0x392b, 0x00},
{0x392c, 0x10},
{0x392f, 0x40},
{0x4000, 0xcf},
{0x4003, 0x40},
{0x4008, 0x00},
{0x4009, 0x07},
{0x400a, 0x02},
{0x400b, 0x54},
{0x400c, 0x00},
{0x400d, 0x07},
{0x4010, 0xc0},
{0x4012, 0x02},
{0x4014, 0x04},
{0x4015, 0x04},
{0x4017, 0x02},
{0x4042, 0x01},
{0x4306, 0x04},
{0x4307, 0x12},
{0x4509, 0x00},
{0x450b, 0x83},
{0x4604, 0x68},
{0x4608, 0x0a},
{0x4700, 0x06},
{0x4800, 0x64},
{0x481b, 0x3c},
{0x4825, 0x32},
{0x4833, 0x18},
{0x4837, 0x0f},
{0x4850, 0x40},
{0x4860, 0x00},
{0x4861, 0xec},
{0x4864, 0x00},
{0x4883, 0x00},
{0x4888, 0x90},
{0x4889, 0x05},
{0x488b, 0x04},
{0x4f00, 0x04},
{0x4f10, 0x04},
{0x4f21, 0x01},
{0x4f22, 0x40},
{0x4f23, 0x44},
{0x4f24, 0x51},
{0x4f25, 0x41},
{0x5000, 0x1f},
{0x500a, 0x00},
{0x5100, 0x00},
{0x5111, 0x20},
{0x3020, 0x20},
{0x3613, 0x03},
{0x38c9, 0x02},
{0x5304, 0x01},
{0x3620, 0x08},
{0x3639, 0x58},
{0x363a, 0x10},
{0x3674, 0x04},
{0x3780, 0xff},
{0x3781, 0xff},
{0x3782, 0x00},
{0x3783, 0x01},
{0x3798, 0xa3},
{0x37aa, 0x10},
{0x38a8, 0xf0},
{0x38c4, 0x09},
{0x38c5, 0xb0},
{0x38df, 0x80},
{0x38ff, 0x05},
{0x4010, 0xf1},
{0x4011, 0x70},
{0x3667, 0x80},
{0x4d00, 0x4a},
{0x4d01, 0x18},
{0x4d02, 0xbb},
{0x4d03, 0xde},
{0x4d04, 0x93},
{0x4d05, 0xff},
{0x4d09, 0x0a},
{0x37aa, 0x16},
{0x3606, 0x42},
{0x3605, 0x00},
{0x36a2, 0x17},
{0x300d, 0x0a},
{0x4d00, 0x4d},
{0x4d01, 0x95},
{0x3d8C, 0x70},
{0x3d8d, 0xE9},
{0x5300, 0x00},
{0x5301, 0x10},
{0x5302, 0x00},
{0x5303, 0xE3},
{0x3d88, 0x00},
{0x3d89, 0x10},
{0x3d8a, 0x00},
{0x3d8b, 0xE3},
{0x4f22, 0x00},
};
static const char * const og01a1b_test_pattern_menu[] = {
"Disabled",
"Standard Color Bar",
"Top-Bottom Darker Color Bar",
"Right-Left Darker Color Bar",
"Bottom-Top Darker Color Bar"
};
static const s64 link_freq_menu_items[] = {
OG01A1B_LINK_FREQ_500MHZ,
};
static const struct og01a1b_link_freq_config link_freq_configs[] = {
[OG01A1B_LINK_FREQ_1000MBPS] = {
.reg_list = {
.num_of_regs = ARRAY_SIZE(mipi_data_rate_1000mbps),
.regs = mipi_data_rate_1000mbps,
}
}
};
static const struct og01a1b_mode supported_modes[] = {
{
.width = 1280,
.height = 1024,
.hts = 848,
.vts_def = OG01A1B_VTS_120FPS,
.vts_min = OG01A1B_VTS_120FPS_MIN,
.reg_list = {
.num_of_regs = ARRAY_SIZE(mode_1280x1024_regs),
.regs = mode_1280x1024_regs,
},
.link_freq_index = OG01A1B_LINK_FREQ_1000MBPS,
},
};
struct og01a1b {
struct v4l2_subdev sd;
struct media_pad pad;
struct v4l2_ctrl_handler ctrl_handler;
/* V4L2 Controls */
struct v4l2_ctrl *link_freq;
struct v4l2_ctrl *pixel_rate;
struct v4l2_ctrl *vblank;
struct v4l2_ctrl *hblank;
struct v4l2_ctrl *exposure;
/* Current mode */
const struct og01a1b_mode *cur_mode;
/* To serialize asynchronus callbacks */
struct mutex mutex;
/* Streaming on/off */
bool streaming;
};
static u64 to_pixel_rate(u32 f_index)
{
u64 pixel_rate = link_freq_menu_items[f_index] * 2 * OG01A1B_DATA_LANES;
do_div(pixel_rate, OG01A1B_RGB_DEPTH);
return pixel_rate;
}
static u64 to_pixels_per_line(u32 hts, u32 f_index)
{
u64 ppl = hts * to_pixel_rate(f_index);
do_div(ppl, OG01A1B_SCLK);
return ppl;
}
static int og01a1b_read_reg(struct og01a1b *og01a1b, u16 reg, u16 len, u32 *val)
{
struct i2c_client *client = v4l2_get_subdevdata(&og01a1b->sd);
struct i2c_msg msgs[2];
u8 addr_buf[2];
u8 data_buf[4] = {0};
int ret;
if (len > 4)
return -EINVAL;
put_unaligned_be16(reg, addr_buf);
msgs[0].addr = client->addr;
msgs[0].flags = 0;
msgs[0].len = sizeof(addr_buf);
msgs[0].buf = addr_buf;
msgs[1].addr = client->addr;
msgs[1].flags = I2C_M_RD;
msgs[1].len = len;
msgs[1].buf = &data_buf[4 - len];
ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
if (ret != ARRAY_SIZE(msgs))
return -EIO;
*val = get_unaligned_be32(data_buf);
return 0;
}
static int og01a1b_write_reg(struct og01a1b *og01a1b, u16 reg, u16 len, u32 val)
{
struct i2c_client *client = v4l2_get_subdevdata(&og01a1b->sd);
u8 buf[6];
if (len > 4)
return -EINVAL;
put_unaligned_be16(reg, buf);
put_unaligned_be32(val << 8 * (4 - len), buf + 2);
if (i2c_master_send(client, buf, len + 2) != len + 2)
return -EIO;
return 0;
}
static int og01a1b_write_reg_list(struct og01a1b *og01a1b,
const struct og01a1b_reg_list *r_list)
{
struct i2c_client *client = v4l2_get_subdevdata(&og01a1b->sd);
unsigned int i;
int ret;
for (i = 0; i < r_list->num_of_regs; i++) {
ret = og01a1b_write_reg(og01a1b, r_list->regs[i].address, 1,
r_list->regs[i].val);
if (ret) {
dev_err_ratelimited(&client->dev,
"failed to write reg 0x%4.4x. error = %d",
r_list->regs[i].address, ret);
return ret;
}
}
return 0;
}
static int og01a1b_test_pattern(struct og01a1b *og01a1b, u32 pattern)
{
if (pattern)
pattern = (pattern - 1) << OG01A1B_TEST_PATTERN_BAR_SHIFT |
OG01A1B_TEST_PATTERN_ENABLE;
return og01a1b_write_reg(og01a1b, OG01A1B_REG_TEST_PATTERN,
OG01A1B_REG_VALUE_08BIT, pattern);
}
static int og01a1b_set_ctrl(struct v4l2_ctrl *ctrl)
{
struct og01a1b *og01a1b = container_of(ctrl->handler,
struct og01a1b, ctrl_handler);
struct i2c_client *client = v4l2_get_subdevdata(&og01a1b->sd);
s64 exposure_max;
int ret = 0;
/* Propagate change of current control to all related controls */
if (ctrl->id == V4L2_CID_VBLANK) {
/* Update max exposure while meeting expected vblanking */
exposure_max = og01a1b->cur_mode->height + ctrl->val -
OG01A1B_EXPOSURE_MAX_MARGIN;
__v4l2_ctrl_modify_range(og01a1b->exposure,
og01a1b->exposure->minimum,
exposure_max, og01a1b->exposure->step,
exposure_max);
}
/* V4L2 controls values will be applied only when power is already up */
if (!pm_runtime_get_if_in_use(&client->dev))
return 0;
switch (ctrl->id) {
case V4L2_CID_ANALOGUE_GAIN:
ret = og01a1b_write_reg(og01a1b, OG01A1B_REG_ANALOG_GAIN,
OG01A1B_REG_VALUE_16BIT,
ctrl->val << 4);
break;
case V4L2_CID_DIGITAL_GAIN:
ret = og01a1b_write_reg(og01a1b, OG01A1B_REG_DIG_GAIN,
OG01A1B_REG_VALUE_24BIT,
ctrl->val << 6);
break;
case V4L2_CID_EXPOSURE:
ret = og01a1b_write_reg(og01a1b, OG01A1B_REG_EXPOSURE,
OG01A1B_REG_VALUE_16BIT, ctrl->val);
break;
case V4L2_CID_VBLANK:
ret = og01a1b_write_reg(og01a1b, OG01A1B_REG_VTS,
OG01A1B_REG_VALUE_16BIT,
og01a1b->cur_mode->height + ctrl->val);
break;
case V4L2_CID_TEST_PATTERN:
ret = og01a1b_test_pattern(og01a1b, ctrl->val);
break;
default:
ret = -EINVAL;
break;
}
pm_runtime_put(&client->dev);
return ret;
}
static const struct v4l2_ctrl_ops og01a1b_ctrl_ops = {
.s_ctrl = og01a1b_set_ctrl,
};
static int og01a1b_init_controls(struct og01a1b *og01a1b)
{
struct v4l2_ctrl_handler *ctrl_hdlr;
s64 exposure_max, h_blank;
int ret;
ctrl_hdlr = &og01a1b->ctrl_handler;
ret = v4l2_ctrl_handler_init(ctrl_hdlr, 8);
if (ret)
return ret;
ctrl_hdlr->lock = &og01a1b->mutex;
og01a1b->link_freq = v4l2_ctrl_new_int_menu(ctrl_hdlr,
&og01a1b_ctrl_ops,
V4L2_CID_LINK_FREQ,
ARRAY_SIZE
(link_freq_menu_items) - 1,
0, link_freq_menu_items);
if (og01a1b->link_freq)
og01a1b->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY;
og01a1b->pixel_rate = v4l2_ctrl_new_std(ctrl_hdlr, &og01a1b_ctrl_ops,
V4L2_CID_PIXEL_RATE, 0,
to_pixel_rate
(OG01A1B_LINK_FREQ_1000MBPS),
1,
to_pixel_rate
(OG01A1B_LINK_FREQ_1000MBPS));
og01a1b->vblank = v4l2_ctrl_new_std(ctrl_hdlr, &og01a1b_ctrl_ops,
V4L2_CID_VBLANK,
og01a1b->cur_mode->vts_min -
og01a1b->cur_mode->height,
OG01A1B_VTS_MAX -
og01a1b->cur_mode->height, 1,
og01a1b->cur_mode->vts_def -
og01a1b->cur_mode->height);
h_blank = to_pixels_per_line(og01a1b->cur_mode->hts,
og01a1b->cur_mode->link_freq_index) -
og01a1b->cur_mode->width;
og01a1b->hblank = v4l2_ctrl_new_std(ctrl_hdlr, &og01a1b_ctrl_ops,
V4L2_CID_HBLANK, h_blank, h_blank,
1, h_blank);
if (og01a1b->hblank)
og01a1b->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
v4l2_ctrl_new_std(ctrl_hdlr, &og01a1b_ctrl_ops, V4L2_CID_ANALOGUE_GAIN,
OG01A1B_ANAL_GAIN_MIN, OG01A1B_ANAL_GAIN_MAX,
OG01A1B_ANAL_GAIN_STEP, OG01A1B_ANAL_GAIN_MIN);
v4l2_ctrl_new_std(ctrl_hdlr, &og01a1b_ctrl_ops, V4L2_CID_DIGITAL_GAIN,
OG01A1B_DGTL_GAIN_MIN, OG01A1B_DGTL_GAIN_MAX,
OG01A1B_DGTL_GAIN_STEP, OG01A1B_DGTL_GAIN_DEFAULT);
exposure_max = (og01a1b->cur_mode->vts_def -
OG01A1B_EXPOSURE_MAX_MARGIN);
og01a1b->exposure = v4l2_ctrl_new_std(ctrl_hdlr, &og01a1b_ctrl_ops,
V4L2_CID_EXPOSURE,
OG01A1B_EXPOSURE_MIN,
exposure_max,
OG01A1B_EXPOSURE_STEP,
exposure_max);
v4l2_ctrl_new_std_menu_items(ctrl_hdlr, &og01a1b_ctrl_ops,
V4L2_CID_TEST_PATTERN,
ARRAY_SIZE(og01a1b_test_pattern_menu) - 1,
0, 0, og01a1b_test_pattern_menu);
if (ctrl_hdlr->error)
return ctrl_hdlr->error;
og01a1b->sd.ctrl_handler = ctrl_hdlr;
return 0;
}
static void og01a1b_update_pad_format(const struct og01a1b_mode *mode,
struct v4l2_mbus_framefmt *fmt)
{
fmt->width = mode->width;
fmt->height = mode->height;
fmt->code = MEDIA_BUS_FMT_SGRBG10_1X10;
fmt->field = V4L2_FIELD_NONE;
}
static int og01a1b_start_streaming(struct og01a1b *og01a1b)
{
struct i2c_client *client = v4l2_get_subdevdata(&og01a1b->sd);
const struct og01a1b_reg_list *reg_list;
int link_freq_index, ret;
link_freq_index = og01a1b->cur_mode->link_freq_index;
reg_list = &link_freq_configs[link_freq_index].reg_list;
ret = og01a1b_write_reg_list(og01a1b, reg_list);
if (ret) {
dev_err(&client->dev, "failed to set plls");
return ret;
}
reg_list = &og01a1b->cur_mode->reg_list;
ret = og01a1b_write_reg_list(og01a1b, reg_list);
if (ret) {
dev_err(&client->dev, "failed to set mode");
return ret;
}
ret = __v4l2_ctrl_handler_setup(og01a1b->sd.ctrl_handler);
if (ret)
return ret;
ret = og01a1b_write_reg(og01a1b, OG01A1B_REG_MODE_SELECT,
OG01A1B_REG_VALUE_08BIT,
OG01A1B_MODE_STREAMING);
if (ret) {
dev_err(&client->dev, "failed to set stream");
return ret;
}
return 0;
}
static void og01a1b_stop_streaming(struct og01a1b *og01a1b)
{
struct i2c_client *client = v4l2_get_subdevdata(&og01a1b->sd);
if (og01a1b_write_reg(og01a1b, OG01A1B_REG_MODE_SELECT,
OG01A1B_REG_VALUE_08BIT, OG01A1B_MODE_STANDBY))
dev_err(&client->dev, "failed to set stream");
}
static int og01a1b_set_stream(struct v4l2_subdev *sd, int enable)
{
struct og01a1b *og01a1b = to_og01a1b(sd);
struct i2c_client *client = v4l2_get_subdevdata(sd);
int ret = 0;
if (og01a1b->streaming == enable)
return 0;
mutex_lock(&og01a1b->mutex);
if (enable) {
ret = pm_runtime_get_sync(&client->dev);
if (ret < 0) {
pm_runtime_put_noidle(&client->dev);
mutex_unlock(&og01a1b->mutex);
return ret;
}
ret = og01a1b_start_streaming(og01a1b);
if (ret) {
enable = 0;
og01a1b_stop_streaming(og01a1b);
pm_runtime_put(&client->dev);
}
} else {
og01a1b_stop_streaming(og01a1b);
pm_runtime_put(&client->dev);
}
og01a1b->streaming = enable;
mutex_unlock(&og01a1b->mutex);
return ret;
}
static int __maybe_unused og01a1b_suspend(struct device *dev)
{
struct i2c_client *client = to_i2c_client(dev);
struct v4l2_subdev *sd = i2c_get_clientdata(client);
struct og01a1b *og01a1b = to_og01a1b(sd);
mutex_lock(&og01a1b->mutex);
if (og01a1b->streaming)
og01a1b_stop_streaming(og01a1b);
mutex_unlock(&og01a1b->mutex);
return 0;
}
static int __maybe_unused og01a1b_resume(struct device *dev)
{
struct i2c_client *client = to_i2c_client(dev);
struct v4l2_subdev *sd = i2c_get_clientdata(client);
struct og01a1b *og01a1b = to_og01a1b(sd);
int ret;
mutex_lock(&og01a1b->mutex);
if (og01a1b->streaming) {
ret = og01a1b_start_streaming(og01a1b);
if (ret) {
og01a1b->streaming = false;
og01a1b_stop_streaming(og01a1b);
mutex_unlock(&og01a1b->mutex);
return ret;
}
}
mutex_unlock(&og01a1b->mutex);
return 0;
}
static int og01a1b_set_format(struct v4l2_subdev *sd,
struct v4l2_subdev_state *sd_state,
struct v4l2_subdev_format *fmt)
{
struct og01a1b *og01a1b = to_og01a1b(sd);
const struct og01a1b_mode *mode;
s32 vblank_def, h_blank;
mode = v4l2_find_nearest_size(supported_modes,
ARRAY_SIZE(supported_modes), width,
height, fmt->format.width,
fmt->format.height);
mutex_lock(&og01a1b->mutex);
og01a1b_update_pad_format(mode, &fmt->format);
if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
*v4l2_subdev_get_try_format(sd, sd_state,
fmt->pad) = fmt->format;
} else {
og01a1b->cur_mode = mode;
__v4l2_ctrl_s_ctrl(og01a1b->link_freq, mode->link_freq_index);
__v4l2_ctrl_s_ctrl_int64(og01a1b->pixel_rate,
to_pixel_rate(mode->link_freq_index));
/* Update limits and set FPS to default */
vblank_def = mode->vts_def - mode->height;
__v4l2_ctrl_modify_range(og01a1b->vblank,
mode->vts_min - mode->height,
OG01A1B_VTS_MAX - mode->height, 1,
vblank_def);
__v4l2_ctrl_s_ctrl(og01a1b->vblank, vblank_def);
h_blank = to_pixels_per_line(mode->hts, mode->link_freq_index) -
mode->width;
__v4l2_ctrl_modify_range(og01a1b->hblank, h_blank, h_blank, 1,
h_blank);
}
mutex_unlock(&og01a1b->mutex);
return 0;
}
static int og01a1b_get_format(struct v4l2_subdev *sd,
struct v4l2_subdev_state *sd_state,
struct v4l2_subdev_format *fmt)
{
struct og01a1b *og01a1b = to_og01a1b(sd);
mutex_lock(&og01a1b->mutex);
if (fmt->which == V4L2_SUBDEV_FORMAT_TRY)
fmt->format = *v4l2_subdev_get_try_format(&og01a1b->sd,
sd_state,
fmt->pad);
else
og01a1b_update_pad_format(og01a1b->cur_mode, &fmt->format);
mutex_unlock(&og01a1b->mutex);
return 0;
}
static int og01a1b_enum_mbus_code(struct v4l2_subdev *sd,
struct v4l2_subdev_state *sd_state,
struct v4l2_subdev_mbus_code_enum *code)
{
if (code->index > 0)
return -EINVAL;
code->code = MEDIA_BUS_FMT_SGRBG10_1X10;
return 0;
}
static int og01a1b_enum_frame_size(struct v4l2_subdev *sd,
struct v4l2_subdev_state *sd_state,
struct v4l2_subdev_frame_size_enum *fse)
{
if (fse->index >= ARRAY_SIZE(supported_modes))
return -EINVAL;
if (fse->code != MEDIA_BUS_FMT_SGRBG10_1X10)
return -EINVAL;
fse->min_width = supported_modes[fse->index].width;
fse->max_width = fse->min_width;
fse->min_height = supported_modes[fse->index].height;
fse->max_height = fse->min_height;
return 0;
}
static int og01a1b_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
{
struct og01a1b *og01a1b = to_og01a1b(sd);
mutex_lock(&og01a1b->mutex);
og01a1b_update_pad_format(&supported_modes[0],
v4l2_subdev_get_try_format(sd, fh->state, 0));
mutex_unlock(&og01a1b->mutex);
return 0;
}
static const struct v4l2_subdev_video_ops og01a1b_video_ops = {
.s_stream = og01a1b_set_stream,
};
static const struct v4l2_subdev_pad_ops og01a1b_pad_ops = {
.set_fmt = og01a1b_set_format,
.get_fmt = og01a1b_get_format,
.enum_mbus_code = og01a1b_enum_mbus_code,
.enum_frame_size = og01a1b_enum_frame_size,
};
static const struct v4l2_subdev_ops og01a1b_subdev_ops = {
.video = &og01a1b_video_ops,
.pad = &og01a1b_pad_ops,
};
static const struct media_entity_operations og01a1b_subdev_entity_ops = {
.link_validate = v4l2_subdev_link_validate,
};
static const struct v4l2_subdev_internal_ops og01a1b_internal_ops = {
.open = og01a1b_open,
};
static int og01a1b_identify_module(struct og01a1b *og01a1b)
{
struct i2c_client *client = v4l2_get_subdevdata(&og01a1b->sd);
int ret;
u32 val;
ret = og01a1b_read_reg(og01a1b, OG01A1B_REG_CHIP_ID,
OG01A1B_REG_VALUE_24BIT, &val);
if (ret)
return ret;
if (val != OG01A1B_CHIP_ID) {
dev_err(&client->dev, "chip id mismatch: %x!=%x",
OG01A1B_CHIP_ID, val);
return -ENXIO;
}
return 0;
}
static int og01a1b_check_hwcfg(struct device *dev)
{
struct fwnode_handle *ep;
struct fwnode_handle *fwnode = dev_fwnode(dev);
struct v4l2_fwnode_endpoint bus_cfg = {
.bus_type = V4L2_MBUS_CSI2_DPHY
};
u32 mclk;
int ret;
unsigned int i, j;
if (!fwnode)
return -ENXIO;
ret = fwnode_property_read_u32(fwnode, "clock-frequency", &mclk);
if (ret) {
dev_err(dev, "can't get clock frequency");
return ret;
}
if (mclk != OG01A1B_MCLK) {
dev_err(dev, "external clock %d is not supported", mclk);
return -EINVAL;
}
ep = fwnode_graph_get_next_endpoint(fwnode, NULL);
if (!ep)
return -ENXIO;
ret = v4l2_fwnode_endpoint_alloc_parse(ep, &bus_cfg);
fwnode_handle_put(ep);
if (ret)
return ret;
if (bus_cfg.bus.mipi_csi2.num_data_lanes != OG01A1B_DATA_LANES) {
dev_err(dev, "number of CSI2 data lanes %d is not supported",
bus_cfg.bus.mipi_csi2.num_data_lanes);
ret = -EINVAL;
goto check_hwcfg_error;
}
if (!bus_cfg.nr_of_link_frequencies) {
dev_err(dev, "no link frequencies defined");
ret = -EINVAL;
goto check_hwcfg_error;
}
for (i = 0; i < ARRAY_SIZE(link_freq_menu_items); i++) {
for (j = 0; j < bus_cfg.nr_of_link_frequencies; j++) {
if (link_freq_menu_items[i] ==
bus_cfg.link_frequencies[j])
break;
}
if (j == bus_cfg.nr_of_link_frequencies) {
dev_err(dev, "no link frequency %lld supported",
link_freq_menu_items[i]);
ret = -EINVAL;
goto check_hwcfg_error;
}
}
check_hwcfg_error:
v4l2_fwnode_endpoint_free(&bus_cfg);
return ret;
}
static int og01a1b_remove(struct i2c_client *client)
{
struct v4l2_subdev *sd = i2c_get_clientdata(client);
struct og01a1b *og01a1b = to_og01a1b(sd);
v4l2_async_unregister_subdev(sd);
media_entity_cleanup(&sd->entity);
v4l2_ctrl_handler_free(sd->ctrl_handler);
pm_runtime_disable(&client->dev);
mutex_destroy(&og01a1b->mutex);
return 0;
}
static int og01a1b_probe(struct i2c_client *client)
{
struct og01a1b *og01a1b;
int ret;
ret = og01a1b_check_hwcfg(&client->dev);
if (ret) {
dev_err(&client->dev, "failed to check HW configuration: %d",
ret);
return ret;
}
og01a1b = devm_kzalloc(&client->dev, sizeof(*og01a1b), GFP_KERNEL);
if (!og01a1b)
return -ENOMEM;
v4l2_i2c_subdev_init(&og01a1b->sd, client, &og01a1b_subdev_ops);
ret = og01a1b_identify_module(og01a1b);
if (ret) {
dev_err(&client->dev, "failed to find sensor: %d", ret);
return ret;
}
mutex_init(&og01a1b->mutex);
og01a1b->cur_mode = &supported_modes[0];
ret = og01a1b_init_controls(og01a1b);
if (ret) {
dev_err(&client->dev, "failed to init controls: %d", ret);
goto probe_error_v4l2_ctrl_handler_free;
}
og01a1b->sd.internal_ops = &og01a1b_internal_ops;
og01a1b->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
og01a1b->sd.entity.ops = &og01a1b_subdev_entity_ops;
og01a1b->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;
og01a1b->pad.flags = MEDIA_PAD_FL_SOURCE;
ret = media_entity_pads_init(&og01a1b->sd.entity, 1, &og01a1b->pad);
if (ret) {
dev_err(&client->dev, "failed to init entity pads: %d", ret);
goto probe_error_v4l2_ctrl_handler_free;
}
ret = v4l2_async_register_subdev_sensor(&og01a1b->sd);
if (ret < 0) {
dev_err(&client->dev, "failed to register V4L2 subdev: %d",
ret);
goto probe_error_media_entity_cleanup;
}
/*
* Device is already turned on by i2c-core with ACPI domain PM.
* Enable runtime PM and turn off the device.
*/
pm_runtime_set_active(&client->dev);
pm_runtime_enable(&client->dev);
pm_runtime_idle(&client->dev);
return 0;
probe_error_media_entity_cleanup:
media_entity_cleanup(&og01a1b->sd.entity);
probe_error_v4l2_ctrl_handler_free:
v4l2_ctrl_handler_free(og01a1b->sd.ctrl_handler);
mutex_destroy(&og01a1b->mutex);
return ret;
}
static const struct dev_pm_ops og01a1b_pm_ops = {
SET_SYSTEM_SLEEP_PM_OPS(og01a1b_suspend, og01a1b_resume)
};
#ifdef CONFIG_ACPI
static const struct acpi_device_id og01a1b_acpi_ids[] = {
{"OVTI01AC"},
{}
};
MODULE_DEVICE_TABLE(acpi, og01a1b_acpi_ids);
#endif
static struct i2c_driver og01a1b_i2c_driver = {
.driver = {
.name = "og01a1b",
.pm = &og01a1b_pm_ops,
.acpi_match_table = ACPI_PTR(og01a1b_acpi_ids),
},
.probe_new = og01a1b_probe,
.remove = og01a1b_remove,
};
module_i2c_driver(og01a1b_i2c_driver);
MODULE_AUTHOR("Shawn Tu <shawnx.tu@intel.com>");
MODULE_DESCRIPTION("OmniVision OG01A1B sensor driver");
MODULE_LICENSE("GPL v2");
drivers/media/i2c/ov5640.c
View file @ 12fdba56
......@@ -2293,7 +2293,6 @@ static int ov5640_set_fmt(struct v4l2_subdev *sd,
struct ov5640_dev *sensor = to_ov5640_dev(sd);
const struct ov5640_mode_info *new_mode;
struct v4l2_mbus_framefmt *mbus_fmt = &format->format;
struct v4l2_mbus_framefmt *fmt;
int ret;
if (format->pad != 0)
......@@ -2311,12 +2310,10 @@ static int ov5640_set_fmt(struct v4l2_subdev *sd,
if (ret)
goto out;
if (format->which == V4L2_SUBDEV_FORMAT_TRY)
fmt = v4l2_subdev_get_try_format(sd, sd_state, 0);
else
fmt = &sensor->fmt;
*fmt = *mbus_fmt;
if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
*v4l2_subdev_get_try_format(sd, sd_state, 0) = *mbus_fmt;
goto out;
}
if (new_mode != sensor->current_mode) {
sensor->current_mode = new_mode;
......@@ -2325,6 +2322,9 @@ static int ov5640_set_fmt(struct v4l2_subdev *sd,
if (mbus_fmt->code != sensor->fmt.code)
sensor->pending_fmt_change = true;
/* update format even if code is unchanged, resolution might change */
sensor->fmt = *mbus_fmt;
__v4l2_ctrl_s_ctrl_int64(sensor->ctrls.pixel_rate,
ov5640_calc_pixel_rate(sensor));
out:
......
drivers/media/i2c/ov5648.c
View file @ 12fdba56
......@@ -1778,8 +1778,14 @@ static int ov5648_state_configure(struct ov5648_sensor *sensor,
static int ov5648_state_init(struct ov5648_sensor *sensor)
{
return ov5648_state_configure(sensor, &ov5648_modes[0],
ov5648_mbus_codes[0]);
int ret;
mutex_lock(&sensor->mutex);
ret = ov5648_state_configure(sensor, &ov5648_modes[0],
ov5648_mbus_codes[0]);
mutex_unlock(&sensor->mutex);
return ret;
}
/* Sensor Base */
......
drivers/media/i2c/ov8865.c
View file @ 12fdba56
......@@ -457,8 +457,8 @@
#define OV8865_NATIVE_WIDTH 3296
#define OV8865_NATIVE_HEIGHT 2528
#define OV8865_ACTIVE_START_TOP 32
#define OV8865_ACTIVE_START_LEFT 80
#define OV8865_ACTIVE_START_LEFT 16
#define OV8865_ACTIVE_START_TOP 40
#define OV8865_ACTIVE_WIDTH 3264
#define OV8865_ACTIVE_HEIGHT 2448
......
drivers/media/mc/mc-entity.c
View file @ 12fdba56
......@@ -396,20 +396,21 @@ __must_check int __media_pipeline_start(struct media_entity *entity,
struct media_link *link;
int ret;
if (!pipe->streaming_count++) {
ret = media_graph_walk_init(&pipe->graph, mdev);
if (ret)
goto error_graph_walk_start;
if (pipe->streaming_count) {
pipe->streaming_count++;
return 0;
}
ret = media_graph_walk_init(&pipe->graph, mdev);
if (ret)
return ret;
media_graph_walk_start(&pipe->graph, entity);
while ((entity = media_graph_walk_next(graph))) {
DECLARE_BITMAP(active, MEDIA_ENTITY_MAX_PADS);
DECLARE_BITMAP(has_no_links, MEDIA_ENTITY_MAX_PADS);
entity->stream_count++;
if (entity->pipe && entity->pipe != pipe) {
pr_err("Pipe active for %s. Can't start for %s\n",
entity->name,
......@@ -418,12 +419,12 @@ __must_check int __media_pipeline_start(struct media_entity *entity,
goto error;
}
entity->pipe = pipe;
/* Already streaming --- no need to check. */
if (entity->stream_count > 1)
if (entity->pipe)
continue;
entity->pipe = pipe;
if (!entity->ops || !entity->ops->link_validate)
continue;
......@@ -479,6 +480,8 @@ __must_check int __media_pipeline_start(struct media_entity *entity,
}
}
pipe->streaming_count++;
return 0;
error:
......@@ -489,24 +492,17 @@ __must_check int __media_pipeline_start(struct media_entity *entity,
media_graph_walk_start(graph, entity_err);
while ((entity_err = media_graph_walk_next(graph))) {
/* Sanity check for negative stream_count */
if (!WARN_ON_ONCE(entity_err->stream_count <= 0)) {
entity_err->stream_count--;
if (entity_err->stream_count == 0)
entity_err->pipe = NULL;
}
entity_err->pipe = NULL;
/*
* We haven't increased stream_count further than this
* so we quit here.
* We haven't started entities further than this so we quit
* here.
*/
if (entity_err == entity)
break;
}
error_graph_walk_start:
if (!--pipe->streaming_count)
media_graph_walk_cleanup(graph);
media_graph_walk_cleanup(graph);
return ret;
}
......@@ -537,19 +533,15 @@ void __media_pipeline_stop(struct media_entity *entity)
if (WARN_ON(!pipe))
return;
if (--pipe->streaming_count)
return;
media_graph_walk_start(graph, entity);
while ((entity = media_graph_walk_next(graph))) {
/* Sanity check for negative stream_count */
if (!WARN_ON_ONCE(entity->stream_count <= 0)) {
entity->stream_count--;
if (entity->stream_count == 0)
entity->pipe = NULL;
}
}
while ((entity = media_graph_walk_next(graph)))
entity->pipe = NULL;
if (!--pipe->streaming_count)
media_graph_walk_cleanup(graph);
media_graph_walk_cleanup(graph);
}
EXPORT_SYMBOL_GPL(__media_pipeline_stop);
......@@ -834,7 +826,8 @@ int __media_entity_setup_link(struct media_link *link, u32 flags)
sink = link->sink->entity;
if (!(link->flags & MEDIA_LNK_FL_DYNAMIC) &&
(source->stream_count || sink->stream_count))
(media_entity_is_streaming(source) ||
media_entity_is_streaming(sink)))
return -EBUSY;
mdev = source->graph_obj.mdev;
......
drivers/media/platform/exynos4-is/common.c
View file @ 12fdba56
......@@ -10,7 +10,10 @@
#include <media/drv-intf/exynos-fimc.h>
#include "common.h"
/* Called with the media graph mutex held or entity->stream_count > 0. */
/*
* Called with the media graph mutex held or media_entity_is_streaming(entity)
* true.
*/
struct v4l2_subdev *fimc_find_remote_sensor(struct media_entity *entity)
{
struct media_pad *pad = &entity->pads[0];
......
drivers/media/platform/exynos4-is/fimc-isp.c
View file @ 12fdba56
......@@ -226,7 +226,7 @@ static int fimc_isp_subdev_set_fmt(struct v4l2_subdev *sd,
}
}
} else {
if (sd->entity.stream_count == 0) {
if (!media_entity_is_streaming(&sd->entity)) {
if (fmt->pad == FIMC_ISP_SD_PAD_SINK) {
struct v4l2_subdev_format format = *fmt;
......
drivers/media/platform/exynos4-is/fimc-lite.c
View file @ 12fdba56
......@@ -1073,7 +1073,7 @@ static int fimc_lite_subdev_set_fmt(struct v4l2_subdev *sd,
mutex_lock(&fimc->lock);
if ((atomic_read(&fimc->out_path) == FIMC_IO_ISP &&
sd->entity.stream_count > 0) ||
media_entity_is_streaming(&sd->entity)) ||
(atomic_read(&fimc->out_path) == FIMC_IO_DMA &&
vb2_is_busy(&fimc->vb_queue))) {
mutex_unlock(&fimc->lock);
......@@ -1197,8 +1197,8 @@ static int fimc_lite_subdev_s_stream(struct v4l2_subdev *sd, int on)
* Find sensor subdev linked to FIMC-LITE directly or through
* MIPI-CSIS. This is required for configuration where FIMC-LITE
* is used as a subdev only and feeds data internally to FIMC-IS.
* The pipeline links are protected through entity.stream_count
* so there is no need to take the media graph mutex here.
* The pipeline links are protected through entity.pipe so there is no
* need to take the media graph mutex here.
*/
fimc->sensor = fimc_find_remote_sensor(&sd->entity);
......
drivers/media/platform/rcar-vin/rcar-core.c
View file @ 12fdba56
......@@ -793,7 +793,7 @@ static int rvin_csi2_link_notify(struct media_link *link, u32 flags,
* running streams.
*/
media_device_for_each_entity(entity, &group->mdev)
if (entity->stream_count)
if (media_entity_is_streaming(entity))
return -EBUSY;
/* Find the master VIN that controls the routes. */
......
drivers/media/v4l2-core/v4l2-fwnode.c
View file @ 12fdba56
......@@ -894,25 +894,8 @@ static int v4l2_fwnode_reference_parse(struct device *dev,
int ret;
for (index = 0;
!(ret = fwnode_property_get_reference_args(dev_fwnode(dev),
prop, NULL, 0,
index, &args));
index++)
fwnode_handle_put(args.fwnode);
if (!index)
return -ENOENT;
/*
* Note that right now both -ENODATA and -ENOENT may signal
* out-of-bounds access. Return the error in cases other than that.
*/
if (ret != -ENOENT && ret != -ENODATA)
return ret;
for (index = 0;
!fwnode_property_get_reference_args(dev_fwnode(dev), prop, NULL,
0, index, &args);
!(ret = fwnode_property_get_reference_args(dev_fwnode(dev), prop,
NULL, 0, index, &args));
index++) {
struct v4l2_async_subdev *asd;
......@@ -928,7 +911,12 @@ static int v4l2_fwnode_reference_parse(struct device *dev,
}
}
return 0;
/* -ENOENT here means successful parsing */
if (ret != -ENOENT)
return ret;
/* Return -ENOENT if no references were found */
return index ? 0 : -ENOENT;
}
/*
......
include/media/i2c/m5mols.h
View file @ 12fdba56
......@@ -14,15 +14,11 @@
/**
* struct m5mols_platform_data - platform data for M-5MOLS driver
* @gpio_reset: GPIO driving the reset pin of M-5MOLS
* @reset_polarity: active state for gpio_reset pin, 0 or 1
* @set_power: an additional callback to the board setup code
* to be called after enabling and before disabling
* the sensor's supply regulators
*/
struct m5mols_platform_data {
int gpio_reset;
u8 reset_polarity;
int (*set_power)(struct device *dev, int on);
};
......
include/media/i2c/noon010pc30.h
View file @ 12fdba56
......@@ -12,14 +12,10 @@
/**
* struct noon010pc30_platform_data - platform data
* @clk_rate: the clock frequency in Hz
* @gpio_nreset: GPIO driving nRESET pin
* @gpio_nstby: GPIO driving nSTBY pin
*/
struct noon010pc30_platform_data {
unsigned long clk_rate;
int gpio_nreset;
int gpio_nstby;
};
#endif /* NOON010PC30_H */
include/media/media-entity.h
View file @ 12fdba56
......@@ -268,7 +268,6 @@ enum media_entity_type {
* @pads: Pads array with the size defined by @num_pads.
* @links: List of data links.
* @ops: Entity operations.
* @stream_count: Stream count for the entity.
* @use_count: Use count for the entity.
* @pipe: Pipeline this entity belongs to.
* @info: Union with devnode information. Kept just for backward
......@@ -283,10 +282,9 @@ enum media_entity_type {
*
* .. note::
*
* @stream_count and @use_count reference counts must never be
* negative, but are signed integers on purpose: a simple ``WARN_ON(<0)``
* check can be used to detect reference count bugs that would make them
* negative.
* The @use_count reference count must never be negative, but is a signed
* integer on purpose: a simple ``WARN_ON(<0)`` check can be used to detect
* reference count bugs that would make it negative.
*/
struct media_entity {
struct media_gobj graph_obj; /* must be first field in struct */
......@@ -305,7 +303,6 @@ struct media_entity {
const struct media_entity_operations *ops;
int stream_count;
int use_count;
struct media_pipeline *pipe;
......@@ -657,6 +654,10 @@ int media_entity_pads_init(struct media_entity *entity, u16 num_pads,
*
* This function must be called during the cleanup phase after unregistering
* the entity (currently, it does nothing).
*
* Calling media_entity_cleanup() on a media_entity whose memory has been
* zeroed but that has not been initialized with media_entity_pad_init() is
* valid and is a no-op.
*/
#if IS_ENABLED(CONFIG_MEDIA_CONTROLLER)
static inline void media_entity_cleanup(struct media_entity *entity) {}
......@@ -858,6 +859,18 @@ struct media_link *media_entity_find_link(struct media_pad *source,
*/
struct media_pad *media_entity_remote_pad(const struct media_pad *pad);
/**
* media_entity_is_streaming - Test if an entity is part of a streaming pipeline
* @entity: The entity
*
* Return: True if the entity is part of a pipeline started with the
* media_pipeline_start() function, false otherwise.
*/
static inline bool media_entity_is_streaming(const struct media_entity *entity)
{
return entity->pipe;
}
/**
* media_entity_get_fwnode_pad - Get pad number from fwnode
*
......
include/uapi/linux/v4l2-controls.h
View file @ 12fdba56
......@@ -219,6 +219,12 @@ enum v4l2_colorfx {
*/
#define V4L2_CID_USER_ALLEGRO_BASE (V4L2_CID_USER_BASE + 0x1170)
/*
* The base for the isl7998x driver controls.
* We reserve 16 controls for this driver.
*/
#define V4L2_CID_USER_ISL7998X_BASE (V4L2_CID_USER_BASE + 0x1180)
/* MPEG-class control IDs */
/* The MPEG controls are applicable to all codec controls
* and the 'MPEG' part of the define is historical */
......
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