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Commit 147455ed authored by Emil Renner Berthing's avatar Emil Renner Berthing Committed by Conor Dooley
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clk: starfive: Rename "jh7100" to "jh71x0" for the common code 

Rename some variables from "jh7100" or "JH7100" to "jh71x0"
or "JH71X0".
Tested-by: default avatarTommaso Merciai <tomm.merciai@gmail.com>
Reviewed-by: default avatarConor Dooley <conor.dooley@microchip.com>
Reviewed-by: default avatarEmil Renner Berthing <emil.renner.berthing@canonical.com>
Signed-off-by: default avatarEmil Renner Berthing <kernel@esmil.dk>
Signed-off-by: default avatarHal Feng <hal.feng@starfivetech.com>
Signed-off-by: default avatarConor Dooley <conor.dooley@microchip.com>
parent e19aa786
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Showing with 418 additions and 406 deletions
drivers/clk/starfive/clk-starfive-jh7100-audio.c
View file @ 147455ed
...@@ -28,66 +28,66 @@ ...@@ -28,66 +28,66 @@
#define JH7100_AUDCLK_I2SDAC_LRCLK_IOPAD (JH7100_AUDCLK_END + 6) #define JH7100_AUDCLK_I2SDAC_LRCLK_IOPAD (JH7100_AUDCLK_END + 6)
#define JH7100_AUDCLK_VAD_INTMEM (JH7100_AUDCLK_END + 7) #define JH7100_AUDCLK_VAD_INTMEM (JH7100_AUDCLK_END + 7)
static const struct jh7100_clk_data jh7100_audclk_data[] = { static const struct jh71x0_clk_data jh7100_audclk_data[] = {
JH7100__GMD(JH7100_AUDCLK_ADC_MCLK, "adc_mclk", 0, 15, 2, JH71X0__GMD(JH7100_AUDCLK_ADC_MCLK, "adc_mclk", 0, 15, 2,
JH7100_AUDCLK_AUDIO_SRC, JH7100_AUDCLK_AUDIO_SRC,
JH7100_AUDCLK_AUDIO_12288), JH7100_AUDCLK_AUDIO_12288),
JH7100__GMD(JH7100_AUDCLK_I2S1_MCLK, "i2s1_mclk", 0, 15, 2, JH71X0__GMD(JH7100_AUDCLK_I2S1_MCLK, "i2s1_mclk", 0, 15, 2,
JH7100_AUDCLK_AUDIO_SRC, JH7100_AUDCLK_AUDIO_SRC,
JH7100_AUDCLK_AUDIO_12288), JH7100_AUDCLK_AUDIO_12288),
JH7100_GATE(JH7100_AUDCLK_I2SADC_APB, "i2sadc_apb", 0, JH7100_AUDCLK_APB0_BUS), JH71X0_GATE(JH7100_AUDCLK_I2SADC_APB, "i2sadc_apb", 0, JH7100_AUDCLK_APB0_BUS),
JH7100_MDIV(JH7100_AUDCLK_I2SADC_BCLK, "i2sadc_bclk", 31, 2, JH71X0_MDIV(JH7100_AUDCLK_I2SADC_BCLK, "i2sadc_bclk", 31, 2,
JH7100_AUDCLK_ADC_MCLK, JH7100_AUDCLK_ADC_MCLK,
JH7100_AUDCLK_I2SADC_BCLK_IOPAD), JH7100_AUDCLK_I2SADC_BCLK_IOPAD),
JH7100__INV(JH7100_AUDCLK_I2SADC_BCLK_N, "i2sadc_bclk_n", JH7100_AUDCLK_I2SADC_BCLK), JH71X0__INV(JH7100_AUDCLK_I2SADC_BCLK_N, "i2sadc_bclk_n", JH7100_AUDCLK_I2SADC_BCLK),
JH7100_MDIV(JH7100_AUDCLK_I2SADC_LRCLK, "i2sadc_lrclk", 63, 3, JH71X0_MDIV(JH7100_AUDCLK_I2SADC_LRCLK, "i2sadc_lrclk", 63, 3,
JH7100_AUDCLK_I2SADC_BCLK_N, JH7100_AUDCLK_I2SADC_BCLK_N,
JH7100_AUDCLK_I2SADC_LRCLK_IOPAD, JH7100_AUDCLK_I2SADC_LRCLK_IOPAD,
JH7100_AUDCLK_I2SADC_BCLK), JH7100_AUDCLK_I2SADC_BCLK),
JH7100_GATE(JH7100_AUDCLK_PDM_APB, "pdm_apb", 0, JH7100_AUDCLK_APB0_BUS), JH71X0_GATE(JH7100_AUDCLK_PDM_APB, "pdm_apb", 0, JH7100_AUDCLK_APB0_BUS),
JH7100__GMD(JH7100_AUDCLK_PDM_MCLK, "pdm_mclk", 0, 15, 2, JH71X0__GMD(JH7100_AUDCLK_PDM_MCLK, "pdm_mclk", 0, 15, 2,
JH7100_AUDCLK_AUDIO_SRC, JH7100_AUDCLK_AUDIO_SRC,
JH7100_AUDCLK_AUDIO_12288), JH7100_AUDCLK_AUDIO_12288),
JH7100_GATE(JH7100_AUDCLK_I2SVAD_APB, "i2svad_apb", 0, JH7100_AUDCLK_APB0_BUS), JH71X0_GATE(JH7100_AUDCLK_I2SVAD_APB, "i2svad_apb", 0, JH7100_AUDCLK_APB0_BUS),
JH7100__GMD(JH7100_AUDCLK_SPDIF, "spdif", 0, 15, 2, JH71X0__GMD(JH7100_AUDCLK_SPDIF, "spdif", 0, 15, 2,
JH7100_AUDCLK_AUDIO_SRC, JH7100_AUDCLK_AUDIO_SRC,
JH7100_AUDCLK_AUDIO_12288), JH7100_AUDCLK_AUDIO_12288),
JH7100_GATE(JH7100_AUDCLK_SPDIF_APB, "spdif_apb", 0, JH7100_AUDCLK_APB0_BUS), JH71X0_GATE(JH7100_AUDCLK_SPDIF_APB, "spdif_apb", 0, JH7100_AUDCLK_APB0_BUS),
JH7100_GATE(JH7100_AUDCLK_PWMDAC_APB, "pwmdac_apb", 0, JH7100_AUDCLK_APB0_BUS), JH71X0_GATE(JH7100_AUDCLK_PWMDAC_APB, "pwmdac_apb", 0, JH7100_AUDCLK_APB0_BUS),
JH7100__GMD(JH7100_AUDCLK_DAC_MCLK, "dac_mclk", 0, 15, 2, JH71X0__GMD(JH7100_AUDCLK_DAC_MCLK, "dac_mclk", 0, 15, 2,
JH7100_AUDCLK_AUDIO_SRC, JH7100_AUDCLK_AUDIO_SRC,
JH7100_AUDCLK_AUDIO_12288), JH7100_AUDCLK_AUDIO_12288),
JH7100_GATE(JH7100_AUDCLK_I2SDAC_APB, "i2sdac_apb", 0, JH7100_AUDCLK_APB0_BUS), JH71X0_GATE(JH7100_AUDCLK_I2SDAC_APB, "i2sdac_apb", 0, JH7100_AUDCLK_APB0_BUS),
JH7100_MDIV(JH7100_AUDCLK_I2SDAC_BCLK, "i2sdac_bclk", 31, 2, JH71X0_MDIV(JH7100_AUDCLK_I2SDAC_BCLK, "i2sdac_bclk", 31, 2,
JH7100_AUDCLK_DAC_MCLK, JH7100_AUDCLK_DAC_MCLK,
JH7100_AUDCLK_I2SDAC_BCLK_IOPAD), JH7100_AUDCLK_I2SDAC_BCLK_IOPAD),
JH7100__INV(JH7100_AUDCLK_I2SDAC_BCLK_N, "i2sdac_bclk_n", JH7100_AUDCLK_I2SDAC_BCLK), JH71X0__INV(JH7100_AUDCLK_I2SDAC_BCLK_N, "i2sdac_bclk_n", JH7100_AUDCLK_I2SDAC_BCLK),
JH7100_MDIV(JH7100_AUDCLK_I2SDAC_LRCLK, "i2sdac_lrclk", 31, 2, JH71X0_MDIV(JH7100_AUDCLK_I2SDAC_LRCLK, "i2sdac_lrclk", 31, 2,
JH7100_AUDCLK_I2S1_MCLK, JH7100_AUDCLK_I2S1_MCLK,
JH7100_AUDCLK_I2SDAC_BCLK_IOPAD), JH7100_AUDCLK_I2SDAC_BCLK_IOPAD),
JH7100_GATE(JH7100_AUDCLK_I2S1_APB, "i2s1_apb", 0, JH7100_AUDCLK_APB0_BUS), JH71X0_GATE(JH7100_AUDCLK_I2S1_APB, "i2s1_apb", 0, JH7100_AUDCLK_APB0_BUS),
JH7100_MDIV(JH7100_AUDCLK_I2S1_BCLK, "i2s1_bclk", 31, 2, JH71X0_MDIV(JH7100_AUDCLK_I2S1_BCLK, "i2s1_bclk", 31, 2,
JH7100_AUDCLK_I2S1_MCLK, JH7100_AUDCLK_I2S1_MCLK,
JH7100_AUDCLK_I2SDAC_BCLK_IOPAD), JH7100_AUDCLK_I2SDAC_BCLK_IOPAD),
JH7100__INV(JH7100_AUDCLK_I2S1_BCLK_N, "i2s1_bclk_n", JH7100_AUDCLK_I2S1_BCLK), JH71X0__INV(JH7100_AUDCLK_I2S1_BCLK_N, "i2s1_bclk_n", JH7100_AUDCLK_I2S1_BCLK),
JH7100_MDIV(JH7100_AUDCLK_I2S1_LRCLK, "i2s1_lrclk", 63, 3, JH71X0_MDIV(JH7100_AUDCLK_I2S1_LRCLK, "i2s1_lrclk", 63, 3,
JH7100_AUDCLK_I2S1_BCLK_N, JH7100_AUDCLK_I2S1_BCLK_N,
JH7100_AUDCLK_I2SDAC_LRCLK_IOPAD), JH7100_AUDCLK_I2SDAC_LRCLK_IOPAD),
JH7100_GATE(JH7100_AUDCLK_I2SDAC16K_APB, "i2s1dac16k_apb", 0, JH7100_AUDCLK_APB0_BUS), JH71X0_GATE(JH7100_AUDCLK_I2SDAC16K_APB, "i2s1dac16k_apb", 0, JH7100_AUDCLK_APB0_BUS),
JH7100__DIV(JH7100_AUDCLK_APB0_BUS, "apb0_bus", 8, JH7100_AUDCLK_DOM7AHB_BUS), JH71X0__DIV(JH7100_AUDCLK_APB0_BUS, "apb0_bus", 8, JH7100_AUDCLK_DOM7AHB_BUS),
JH7100_GATE(JH7100_AUDCLK_DMA1P_AHB, "dma1p_ahb", 0, JH7100_AUDCLK_DOM7AHB_BUS), JH71X0_GATE(JH7100_AUDCLK_DMA1P_AHB, "dma1p_ahb", 0, JH7100_AUDCLK_DOM7AHB_BUS),
JH7100_GATE(JH7100_AUDCLK_USB_APB, "usb_apb", CLK_IGNORE_UNUSED, JH7100_AUDCLK_APB_EN), JH71X0_GATE(JH7100_AUDCLK_USB_APB, "usb_apb", CLK_IGNORE_UNUSED, JH7100_AUDCLK_APB_EN),
JH7100_GDIV(JH7100_AUDCLK_USB_LPM, "usb_lpm", CLK_IGNORE_UNUSED, 4, JH7100_AUDCLK_USB_APB), JH71X0_GDIV(JH7100_AUDCLK_USB_LPM, "usb_lpm", CLK_IGNORE_UNUSED, 4, JH7100_AUDCLK_USB_APB),
JH7100_GDIV(JH7100_AUDCLK_USB_STB, "usb_stb", CLK_IGNORE_UNUSED, 3, JH7100_AUDCLK_USB_APB), JH71X0_GDIV(JH7100_AUDCLK_USB_STB, "usb_stb", CLK_IGNORE_UNUSED, 3, JH7100_AUDCLK_USB_APB),
JH7100__DIV(JH7100_AUDCLK_APB_EN, "apb_en", 8, JH7100_AUDCLK_DOM7AHB_BUS), JH71X0__DIV(JH7100_AUDCLK_APB_EN, "apb_en", 8, JH7100_AUDCLK_DOM7AHB_BUS),
JH7100__MUX(JH7100_AUDCLK_VAD_MEM, "vad_mem", 2, JH71X0__MUX(JH7100_AUDCLK_VAD_MEM, "vad_mem", 2,
JH7100_AUDCLK_VAD_INTMEM, JH7100_AUDCLK_VAD_INTMEM,
JH7100_AUDCLK_AUDIO_12288), JH7100_AUDCLK_AUDIO_12288),
}; };
static struct clk_hw *jh7100_audclk_get(struct of_phandle_args *clkspec, void *data) static struct clk_hw *jh7100_audclk_get(struct of_phandle_args *clkspec, void *data)
{ {
struct jh7100_clk_priv *priv = data; struct jh71x0_clk_priv *priv = data;
unsigned int idx = clkspec->args[0]; unsigned int idx = clkspec->args[0];
if (idx < JH7100_AUDCLK_END) if (idx < JH7100_AUDCLK_END)
...@@ -98,7 +98,7 @@ static struct clk_hw *jh7100_audclk_get(struct of_phandle_args *clkspec, void *d ...@@ -98,7 +98,7 @@ static struct clk_hw *jh7100_audclk_get(struct of_phandle_args *clkspec, void *d
static int jh7100_audclk_probe(struct platform_device *pdev) static int jh7100_audclk_probe(struct platform_device *pdev)
{ {
struct jh7100_clk_priv *priv; struct jh71x0_clk_priv *priv;
unsigned int idx; unsigned int idx;
int ret; int ret;
...@@ -117,12 +117,12 @@ static int jh7100_audclk_probe(struct platform_device *pdev) ...@@ -117,12 +117,12 @@ static int jh7100_audclk_probe(struct platform_device *pdev)
struct clk_parent_data parents[4] = {}; struct clk_parent_data parents[4] = {};
struct clk_init_data init = { struct clk_init_data init = {
.name = jh7100_audclk_data[idx].name, .name = jh7100_audclk_data[idx].name,
.ops = starfive_jh7100_clk_ops(max), .ops = starfive_jh71x0_clk_ops(max),
.parent_data = parents, .parent_data = parents,
.num_parents = ((max & JH7100_CLK_MUX_MASK) >> JH7100_CLK_MUX_SHIFT) + 1, .num_parents = ((max & JH71X0_CLK_MUX_MASK) >> JH71X0_CLK_MUX_SHIFT) + 1,
.flags = jh7100_audclk_data[idx].flags, .flags = jh7100_audclk_data[idx].flags,
}; };
struct jh7100_clk *clk = &priv->reg[idx]; struct jh71x0_clk *clk = &priv->reg[idx];
unsigned int i; unsigned int i;
for (i = 0; i < init.num_parents; i++) { for (i = 0; i < init.num_parents; i++) {
...@@ -140,7 +140,7 @@ static int jh7100_audclk_probe(struct platform_device *pdev) ...@@ -140,7 +140,7 @@ static int jh7100_audclk_probe(struct platform_device *pdev)
clk->hw.init = &init; clk->hw.init = &init;
clk->idx = idx; clk->idx = idx;
clk->max_div = max & JH7100_CLK_DIV_MASK; clk->max_div = max & JH71X0_CLK_DIV_MASK;
ret = devm_clk_hw_register(priv->dev, &clk->hw); ret = devm_clk_hw_register(priv->dev, &clk->hw);
if (ret) if (ret)
......
drivers/clk/starfive/clk-starfive-jh7100.c
View file @ 147455ed
This diff is collapsed.
drivers/clk/starfive/clk-starfive-jh71x0.c
View file @ 147455ed
This diff is collapsed.
drivers/clk/starfive/clk-starfive-jh71x0.h
View file @ 147455ed
/* SPDX-License-Identifier: GPL-2.0 */ /* SPDX-License-Identifier: GPL-2.0 */
#ifndef __CLK_STARFIVE_JH7100_H #ifndef __CLK_STARFIVE_JH71X0_H
#define __CLK_STARFIVE_JH7100_H #define __CLK_STARFIVE_JH71X0_H
#include <linux/bits.h> #include <linux/bits.h>
#include <linux/clk-provider.h> #include <linux/clk-provider.h>
...@@ -8,107 +8,116 @@ ...@@ -8,107 +8,116 @@
#include <linux/spinlock.h> #include <linux/spinlock.h>
/* register fields */ /* register fields */
#define JH7100_CLK_ENABLE BIT(31) #define JH71X0_CLK_ENABLE BIT(31)
#define JH7100_CLK_INVERT BIT(30) #define JH71X0_CLK_INVERT BIT(30)
#define JH7100_CLK_MUX_MASK GENMASK(27, 24) #define JH71X0_CLK_MUX_MASK GENMASK(27, 24)
#define JH7100_CLK_MUX_SHIFT 24 #define JH71X0_CLK_MUX_SHIFT 24
#define JH7100_CLK_DIV_MASK GENMASK(23, 0) #define JH71X0_CLK_DIV_MASK GENMASK(23, 0)
#define JH7100_CLK_FRAC_MASK GENMASK(15, 8) #define JH71X0_CLK_FRAC_MASK GENMASK(15, 8)
#define JH7100_CLK_FRAC_SHIFT 8 #define JH71X0_CLK_FRAC_SHIFT 8
#define JH7100_CLK_INT_MASK GENMASK(7, 0) #define JH71X0_CLK_INT_MASK GENMASK(7, 0)
/* fractional divider min/max */ /* fractional divider min/max */
#define JH7100_CLK_FRAC_MIN 100UL #define JH71X0_CLK_FRAC_MIN 100UL
#define JH7100_CLK_FRAC_MAX 25599UL #define JH71X0_CLK_FRAC_MAX 25599UL
/* clock data */ /* clock data */
struct jh7100_clk_data { struct jh71x0_clk_data {
const char *name; const char *name;
unsigned long flags; unsigned long flags;
u32 max; u32 max;
u8 parents[4]; u8 parents[4];
}; };
#define JH7100_GATE(_idx, _name, _flags, _parent) [_idx] = { \ #define JH71X0_GATE(_idx, _name, _flags, _parent) \
[_idx] = { \
.name = _name, \ .name = _name, \
.flags = CLK_SET_RATE_PARENT | (_flags), \ .flags = CLK_SET_RATE_PARENT | (_flags), \
.max = JH7100_CLK_ENABLE, \ .max = JH71X0_CLK_ENABLE, \
.parents = { [0] = _parent }, \ .parents = { [0] = _parent }, \
} }
#define JH7100__DIV(_idx, _name, _max, _parent) [_idx] = { \ #define JH71X0__DIV(_idx, _name, _max, _parent) \
[_idx] = { \
.name = _name, \ .name = _name, \
.flags = 0, \ .flags = 0, \
.max = _max, \ .max = _max, \
.parents = { [0] = _parent }, \ .parents = { [0] = _parent }, \
} }
#define JH7100_GDIV(_idx, _name, _flags, _max, _parent) [_idx] = { \ #define JH71X0_GDIV(_idx, _name, _flags, _max, _parent) \
[_idx] = { \
.name = _name, \ .name = _name, \
.flags = _flags, \ .flags = _flags, \
.max = JH7100_CLK_ENABLE | (_max), \ .max = JH71X0_CLK_ENABLE | (_max), \
.parents = { [0] = _parent }, \ .parents = { [0] = _parent }, \
} }
#define JH7100_FDIV(_idx, _name, _parent) [_idx] = { \ #define JH71X0_FDIV(_idx, _name, _parent) \
[_idx] = { \
.name = _name, \ .name = _name, \
.flags = 0, \ .flags = 0, \
.max = JH7100_CLK_FRAC_MAX, \ .max = JH71X0_CLK_FRAC_MAX, \
.parents = { [0] = _parent }, \ .parents = { [0] = _parent }, \
} }
#define JH7100__MUX(_idx, _name, _nparents, ...) [_idx] = { \ #define JH71X0__MUX(_idx, _name, _nparents, ...) \
[_idx] = { \
.name = _name, \ .name = _name, \
.flags = 0, \ .flags = 0, \
.max = ((_nparents) - 1) << JH7100_CLK_MUX_SHIFT, \ .max = ((_nparents) - 1) << JH71X0_CLK_MUX_SHIFT, \
.parents = { __VA_ARGS__ }, \ .parents = { __VA_ARGS__ }, \
} }
#define JH7100_GMUX(_idx, _name, _flags, _nparents, ...) [_idx] = { \ #define JH71X0_GMUX(_idx, _name, _flags, _nparents, ...) \
[_idx] = { \
.name = _name, \ .name = _name, \
.flags = _flags, \ .flags = _flags, \
.max = JH7100_CLK_ENABLE | \ .max = JH71X0_CLK_ENABLE | \
(((_nparents) - 1) << JH7100_CLK_MUX_SHIFT), \ (((_nparents) - 1) << JH71X0_CLK_MUX_SHIFT), \
.parents = { __VA_ARGS__ }, \ .parents = { __VA_ARGS__ }, \
} }
#define JH7100_MDIV(_idx, _name, _max, _nparents, ...) [_idx] = { \ #define JH71X0_MDIV(_idx, _name, _max, _nparents, ...) \
[_idx] = { \
.name = _name, \ .name = _name, \
.flags = 0, \ .flags = 0, \
.max = (((_nparents) - 1) << JH7100_CLK_MUX_SHIFT) | (_max), \ .max = (((_nparents) - 1) << JH71X0_CLK_MUX_SHIFT) | (_max), \
.parents = { __VA_ARGS__ }, \ .parents = { __VA_ARGS__ }, \
} }
#define JH7100__GMD(_idx, _name, _flags, _max, _nparents, ...) [_idx] = { \ #define JH71X0__GMD(_idx, _name, _flags, _max, _nparents, ...) \
[_idx] = { \
.name = _name, \ .name = _name, \
.flags = _flags, \ .flags = _flags, \
.max = JH7100_CLK_ENABLE | \ .max = JH71X0_CLK_ENABLE | \
(((_nparents) - 1) << JH7100_CLK_MUX_SHIFT) | (_max), \ (((_nparents) - 1) << JH71X0_CLK_MUX_SHIFT) | (_max), \
.parents = { __VA_ARGS__ }, \ .parents = { __VA_ARGS__ }, \
} }
#define JH7100__INV(_idx, _name, _parent) [_idx] = { \ #define JH71X0__INV(_idx, _name, _parent) \
[_idx] = { \
.name = _name, \ .name = _name, \
.flags = CLK_SET_RATE_PARENT, \ .flags = CLK_SET_RATE_PARENT, \
.max = JH7100_CLK_INVERT, \ .max = JH71X0_CLK_INVERT, \
.parents = { [0] = _parent }, \ .parents = { [0] = _parent }, \
} }
struct jh7100_clk { struct jh71x0_clk {
struct clk_hw hw; struct clk_hw hw;
unsigned int idx; unsigned int idx;
unsigned int max_div; unsigned int max_div;
}; };
struct jh7100_clk_priv { struct jh71x0_clk_priv {
/* protect clk enable and set rate/parent from happening at the same time */ /* protect clk enable and set rate/parent from happening at the same time */
spinlock_t rmw_lock; spinlock_t rmw_lock;
struct device *dev; struct device *dev;
void __iomem *base; void __iomem *base;
struct clk_hw *pll[3]; struct clk_hw *pll[3];
struct jh7100_clk reg[]; struct jh71x0_clk reg[];
}; };
const struct clk_ops *starfive_jh7100_clk_ops(u32 max); const struct clk_ops *starfive_jh71x0_clk_ops(u32 max);
#endif #endif
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