Commit 14af7fd1 authored by Jiri Pirko's avatar Jiri Pirko Committed by David S. Miller

ethtool: Add support for 400Gbps (50Gbps per lane) link modes

Add support for 400Gbps speed, link modes of 50Gbps per lane
Signed-off-by: default avatarJiri Pirko <jiri@mellanox.com>
Signed-off-by: default avatarIdo Schimmel <idosch@mellanox.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 14f2cf60
...@@ -8,7 +8,7 @@ ...@@ -8,7 +8,7 @@
const char *phy_speed_to_str(int speed) const char *phy_speed_to_str(int speed)
{ {
BUILD_BUG_ON_MSG(__ETHTOOL_LINK_MODE_MASK_NBITS != 69, BUILD_BUG_ON_MSG(__ETHTOOL_LINK_MODE_MASK_NBITS != 74,
"Enum ethtool_link_mode_bit_indices and phylib are out of sync. " "Enum ethtool_link_mode_bit_indices and phylib are out of sync. "
"If a speed or mode has been added please update phy_speed_to_str " "If a speed or mode has been added please update phy_speed_to_str "
"and the PHY settings array.\n"); "and the PHY settings array.\n");
...@@ -42,6 +42,8 @@ const char *phy_speed_to_str(int speed) ...@@ -42,6 +42,8 @@ const char *phy_speed_to_str(int speed)
return "100Gbps"; return "100Gbps";
case SPEED_200000: case SPEED_200000:
return "200Gbps"; return "200Gbps";
case SPEED_400000:
return "400Gbps";
case SPEED_UNKNOWN: case SPEED_UNKNOWN:
return "Unknown"; return "Unknown";
default: default:
...@@ -70,6 +72,12 @@ EXPORT_SYMBOL_GPL(phy_duplex_to_str); ...@@ -70,6 +72,12 @@ EXPORT_SYMBOL_GPL(phy_duplex_to_str);
.bit = ETHTOOL_LINK_MODE_ ## b ## _BIT} .bit = ETHTOOL_LINK_MODE_ ## b ## _BIT}
static const struct phy_setting settings[] = { static const struct phy_setting settings[] = {
/* 400G */
PHY_SETTING( 400000, FULL, 400000baseCR8_Full ),
PHY_SETTING( 400000, FULL, 400000baseKR8_Full ),
PHY_SETTING( 400000, FULL, 400000baseLR8_ER8_FR8_Full ),
PHY_SETTING( 400000, FULL, 400000baseDR8_Full ),
PHY_SETTING( 400000, FULL, 400000baseSR8_Full ),
/* 200G */ /* 200G */
PHY_SETTING( 200000, FULL, 200000baseCR4_Full ), PHY_SETTING( 200000, FULL, 200000baseCR4_Full ),
PHY_SETTING( 200000, FULL, 200000baseKR4_Full ), PHY_SETTING( 200000, FULL, 200000baseKR4_Full ),
......
...@@ -1507,6 +1507,11 @@ enum ethtool_link_mode_bit_indices { ...@@ -1507,6 +1507,11 @@ enum ethtool_link_mode_bit_indices {
ETHTOOL_LINK_MODE_200000baseCR4_Full_BIT = 66, ETHTOOL_LINK_MODE_200000baseCR4_Full_BIT = 66,
ETHTOOL_LINK_MODE_100baseT1_Full_BIT = 67, ETHTOOL_LINK_MODE_100baseT1_Full_BIT = 67,
ETHTOOL_LINK_MODE_1000baseT1_Full_BIT = 68, ETHTOOL_LINK_MODE_1000baseT1_Full_BIT = 68,
ETHTOOL_LINK_MODE_400000baseKR8_Full_BIT = 69,
ETHTOOL_LINK_MODE_400000baseSR8_Full_BIT = 70,
ETHTOOL_LINK_MODE_400000baseLR8_ER8_FR8_Full_BIT = 71,
ETHTOOL_LINK_MODE_400000baseDR8_Full_BIT = 72,
ETHTOOL_LINK_MODE_400000baseCR8_Full_BIT = 73,
/* must be last entry */ /* must be last entry */
__ETHTOOL_LINK_MODE_MASK_NBITS __ETHTOOL_LINK_MODE_MASK_NBITS
...@@ -1618,6 +1623,7 @@ enum ethtool_link_mode_bit_indices { ...@@ -1618,6 +1623,7 @@ enum ethtool_link_mode_bit_indices {
#define SPEED_56000 56000 #define SPEED_56000 56000
#define SPEED_100000 100000 #define SPEED_100000 100000
#define SPEED_200000 200000 #define SPEED_200000 200000
#define SPEED_400000 400000
#define SPEED_UNKNOWN -1 #define SPEED_UNKNOWN -1
......
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